tree 26400e408063ff814436e566cafba6423c7e879d
parent 7c8e79c9a0ce79d2f3892be70218ea9239d1a449
author Jolly Shah <jollys@xilinx.com> 1546465553 -0800
committer Jolly Shah <jollys@xilinx.com> 1546631946 -0800

zynqmp: pm: Fix model of ACPU clocks

In the existing model for ACPU clock the mux, divider, and gate were
represented as one clock and ACPU_HALF was modelled as child of
ACPU clock. This is not correct. ACPU clock model contains only
mux and the divider, and it has 2 children: ACPU_FULL and ACPU_HALF
clocks which have only gates. The models of ACPU and ACPU_HALF clocks
are fixed and ACPU_FULL clock is added.

Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>