diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_clock.c b/plat/xilinx/zynqmp/pm_service/pm_api_clock.c
index 8c15792..d91f4e4 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_api_clock.c
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_clock.c
@@ -330,18 +330,6 @@
 		.mult = NA_MULT,
 		.div = NA_DIV,
 	},
-	{
-		.type = TYPE_GATE,
-		.offset = PERIPH_GATE_SHIFT,
-		.width = PERIPH_GATE_WIDTH,
-		.clkflags = CLK_SET_RATE_PARENT |
-			    CLK_IGNORE_UNUSED |
-			    CLK_IS_BASIC |
-			    CLK_IS_CRITICAL,
-		.typeflags = NA_TYPE_FLAGS,
-		.mult = NA_MULT,
-		.div = NA_DIV,
-	},
 };
 
 static struct pm_clock_node generic_mux_div_nodes[] = {
@@ -476,6 +464,20 @@
 	},
 };
 
+static struct pm_clock_node acpu_full_nodes[] = {
+	{
+		.type = TYPE_GATE,
+		.offset = 24,
+		.width = PERIPH_GATE_WIDTH,
+		.clkflags = CLK_IGNORE_UNUSED |
+			    CLK_SET_RATE_PARENT |
+			    CLK_IS_BASIC,
+		.typeflags = NA_TYPE_FLAGS,
+		.mult = NA_MULT,
+		.div = NA_DIV,
+	},
+};
+
 static struct pm_clock_node wdt_nodes[] = {
 	{
 		.type = TYPE_MUX,
@@ -1205,6 +1207,17 @@
 		.nodes = &acpu_nodes,
 		.num_nodes = ARRAY_SIZE(acpu_nodes),
 	},
+	[CLK_ACPU_FULL] = {
+		.name = "acpu_full",
+		.control_reg = CRF_APB_ACPU_CTRL,
+		.status_reg = 0,
+		.parents = &((int32_t []) {
+			CLK_ACPU | PARENT_CLK_NODE2 << CLK_PARENTS_ID_LEN,
+			CLK_NA_PARENT
+		}),
+		.nodes = &acpu_full_nodes,
+		.num_nodes = ARRAY_SIZE(acpu_full_nodes),
+	},
 	[CLK_DBG_TRACE] = {
 		.name = "dbg_trace",
 		.control_reg = CRF_APB_DBG_TRACE_CTRL,
diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_clock.h b/plat/xilinx/zynqmp/pm_service/pm_api_clock.h
index 671c29f..8d5e967 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_api_clock.h
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_clock.h
@@ -159,6 +159,7 @@
 	CLK_VPLL_POST_SRC,
 	CLK_CAN0_MIO,
 	CLK_CAN1_MIO,
+	CLK_ACPU_FULL,
 	END_OF_OUTPUT_CLKS,
 };