| commit | 3c2e37a9545c07905a4cb4d4f099e2e8fc727daf | [log] [tgz] |
|---|---|---|
| author | Jagdish Gediya <jagdish.gediya@arm.com> | Fri Jun 28 11:22:37 2024 +0000 |
| committer | Icen.Zeyada <Icen.Zeyada2@arm.com> | Thu Jan 09 10:17:18 2025 +0000 |
| tree | b21e4c578bc6e1d8f341bdadbf34077ecca69a11 | |
| parent | 6fde27f3afe0391c7817c3fd7b8a42360c75c32a [diff] |
feat(tc): configure UART for TC4 FPGA TC4 FPGA have a UART clock of 4000000 so modify the value of TC_UARTCLK for TC4. Change-Id: I8de84d58bce8b7277bf356136a5185c008ab4c28 Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com> Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>