fix(cpus): workaround for Cortex-A725 erratum 3699564
Cortex-A725 erratum 3699564 that applies to r0p0, r0p1 and is
fixed in r0p2.
The workaround is for EL3 software that performs context save/restore
on a change of Security state to use a value of SCR_EL3.NS when
accessing ICH_VMCR_EL2 that reflects the Security state that owns the
data being saved or restored.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-2832921/latest
Change-Id: Ifad1f6c3f5b74060273f897eb5e4b79dd9f088f7
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index 5b439c9..57875da 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -992,6 +992,12 @@
to Cortex-A715_AE CPU. This needs to be enabled for revisions r0p0.
It is still open.
+For Cortex-A725, the following errata build flags are defined :
+
+- ``ERRATA_A725_3699564``: This applies errata 3699564 workaround to
+ Cortex-A725 CPU. This needs to be enabled for revisions r0p0 and r0p1.
+ It is fixed in r0p2.
+
DSU Errata Workarounds
----------------------