fix(cpus): workaround for Cortex-A725 erratum 3699564
Cortex-A725 erratum 3699564 that applies to r0p0, r0p1 and is
fixed in r0p2.
The workaround is for EL3 software that performs context save/restore
on a change of Security state to use a value of SCR_EL3.NS when
accessing ICH_VMCR_EL2 that reflects the Security state that owns the
data being saved or restored.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-2832921/latest
Change-Id: Ifad1f6c3f5b74060273f897eb5e4b79dd9f088f7
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index 5b439c9..57875da 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -992,6 +992,12 @@
to Cortex-A715_AE CPU. This needs to be enabled for revisions r0p0.
It is still open.
+For Cortex-A725, the following errata build flags are defined :
+
+- ``ERRATA_A725_3699564``: This applies errata 3699564 workaround to
+ Cortex-A725 CPU. This needs to be enabled for revisions r0p0 and r0p1.
+ It is fixed in r0p2.
+
DSU Errata Workarounds
----------------------
diff --git a/include/lib/cpus/aarch64/cortex_a725.h b/include/lib/cpus/aarch64/cortex_a725.h
index cb1c099..20488dd 100644
--- a/include/lib/cpus/aarch64/cortex_a725.h
+++ b/include/lib/cpus/aarch64/cortex_a725.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2023-2024, Arm Limited. All rights reserved.
+ * Copyright (c) 2023-2025, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -21,4 +21,8 @@
#define CORTEX_A725_CPUPWRCTLR_EL1 S3_0_C15_C2_7
#define CORTEX_A725_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
+#ifndef __ASSEMBLER__
+long check_erratum_cortex_a725_3699564(long cpu_rev);
+#endif /* __ASSEMBLER__ */
+
#endif /* CORTEX_A725_H */
diff --git a/lib/cpus/aarch64/cortex_a725.S b/lib/cpus/aarch64/cortex_a725.S
index af98d14..c4d6034 100644
--- a/lib/cpus/aarch64/cortex_a725.S
+++ b/lib/cpus/aarch64/cortex_a725.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2023-2024, Arm Limited. All rights reserved.
+ * Copyright (c) 2023-2025, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -21,6 +21,12 @@
#error "Cortex-A725 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif
+.global check_erratum_cortex_a725_3699564
+
+add_erratum_entry cortex_a725, ERRATUM(3699564), ERRATA_A725_3699564, NO_APPLY_AT_RESET
+
+check_erratum_ls cortex_a725, ERRATUM(3699564), CPU_REV(0, 1)
+
cpu_reset_func_start cortex_a725
/* Disable speculative loads */
msr SSBS, xzr
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index 75d5ad2..747edf4 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -1020,6 +1020,11 @@
# cpu and is still open.
CPU_FLAG_LIST += ERRATA_A720_AE_3699562
+# Flag to apply erratum 3699564 workaround during context save/restore of
+# ICH_VMCR_EL2 reg. This erratum applies to revisions r0p0, r0p1 of
+# the Cortex-A725 cpu and is fixed in r0p2
+CPU_FLAG_LIST += ERRATA_A725_3699564
+
# Flag to apply DSU erratum 798953. This erratum applies to DSUs revision r0p0.
# Applying the workaround results in higher DSU power consumption on idle.
CPU_FLAG_LIST += ERRATA_DSU_798953
diff --git a/lib/cpus/errata_common.c b/lib/cpus/errata_common.c
index a6be68a..d9f8339 100644
--- a/lib/cpus/errata_common.c
+++ b/lib/cpus/errata_common.c
@@ -14,6 +14,7 @@
#include <cortex_a715.h>
#include <cortex_a720.h>
#include <cortex_a720_ae.h>
+#include <cortex_a725.h>
#include <cortex_x4.h>
#include <lib/cpus/cpu_ops.h>
#include <lib/cpus/errata.h>
@@ -76,6 +77,12 @@
break;
#endif /* ERRATA_A720_AE_3699562 */
+#if ERRATA_A725_3699564
+ case EXTRACT_PARTNUM(CORTEX_A725_MIDR):
+ if (check_erratum_cortex_a725_3699564(cpu_get_rev_var()) == ERRATA_APPLIES)
+ return true;
+ break;
+#endif /* ERRATA_A725_3699564 */
default:
break;
}