Tegra186: mce: remove unused type conversions
This patch removes unused type conversions as all the relevant macros
now use U()/ULL(), making these explicit typecasts unnecessary.
Change-Id: I01fb534649db2aaf186406b1aef6897662b44fe3
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
diff --git a/plat/nvidia/tegra/soc/t186/drivers/mce/ari.c b/plat/nvidia/tegra/soc/t186/drivers/mce/ari.c
index 3769599..599e46e 100644
--- a/plat/nvidia/tegra/soc/t186/drivers/mce/ari.c
+++ b/plat/nvidia/tegra/soc/t186/drivers/mce/ari.c
@@ -99,9 +99,9 @@
ret = 0;
} else {
/* For shutdown/reboot commands, we dont have to check for timeouts */
- if ((req == (uint32_t)TEGRA_ARI_MISC_CCPLEX) &&
- ((lo == (uint32_t)TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF) ||
- (lo == (uint32_t)TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_REBOOT))) {
+ if ((req == TEGRA_ARI_MISC_CCPLEX) &&
+ ((lo == TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF) ||
+ (lo == TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_REBOOT))) {
ret = 0;
} else {
/*
@@ -161,38 +161,38 @@
uint32_t system, uint8_t sys_state_force, uint32_t wake_mask,
uint8_t update_wake_mask)
{
- uint32_t val = 0U;
+ uint64_t val = 0U;
/* clean the previous response state */
ari_clobber_response(ari_base);
/* update CLUSTER_CSTATE? */
if (cluster != 0U) {
- val |= (cluster & (uint32_t)CLUSTER_CSTATE_MASK) |
- (uint32_t)CLUSTER_CSTATE_UPDATE_BIT;
+ val |= (cluster & CLUSTER_CSTATE_MASK) |
+ CLUSTER_CSTATE_UPDATE_BIT;
}
/* update CCPLEX_CSTATE? */
if (ccplex != 0U) {
- val |= ((ccplex & (uint32_t)CCPLEX_CSTATE_MASK) << (uint32_t)CCPLEX_CSTATE_SHIFT) |
- (uint32_t)CCPLEX_CSTATE_UPDATE_BIT;
+ val |= ((ccplex & CCPLEX_CSTATE_MASK) << CCPLEX_CSTATE_SHIFT) |
+ CCPLEX_CSTATE_UPDATE_BIT;
}
/* update SYSTEM_CSTATE? */
if (system != 0U) {
- val |= ((system & (uint32_t)SYSTEM_CSTATE_MASK) << (uint32_t)SYSTEM_CSTATE_SHIFT) |
- (((uint32_t)sys_state_force << SYSTEM_CSTATE_FORCE_UPDATE_SHIFT) |
- (uint32_t)SYSTEM_CSTATE_UPDATE_BIT);
+ val |= ((system & SYSTEM_CSTATE_MASK) << SYSTEM_CSTATE_SHIFT) |
+ (((uint64_t)sys_state_force << SYSTEM_CSTATE_FORCE_UPDATE_SHIFT) |
+ SYSTEM_CSTATE_UPDATE_BIT);
}
/* update wake mask value? */
if (update_wake_mask != 0U) {
- val |= (uint32_t)CSTATE_WAKE_MASK_UPDATE_BIT;
+ val |= CSTATE_WAKE_MASK_UPDATE_BIT;
}
/* set the updated cstate info */
- return ari_request_wait(ari_base, 0U, TEGRA_ARI_UPDATE_CSTATE_INFO, val,
- wake_mask);
+ return ari_request_wait(ari_base, 0U, TEGRA_ARI_UPDATE_CSTATE_INFO,
+ (uint32_t)val, wake_mask);
}
int32_t ari_update_crossover_time(uint32_t ari_base, uint32_t type, uint32_t time)
@@ -299,10 +299,8 @@
int32_t ret, result;
/* check for allowed power state */
- if ((state != TEGRA_ARI_CORE_C0) &&
- (state != TEGRA_ARI_CORE_C1) &&
- (state != TEGRA_ARI_CORE_C6) &&
- (state != TEGRA_ARI_CORE_C7)) {
+ if ((state != TEGRA_ARI_CORE_C0) && (state != TEGRA_ARI_CORE_C1) &&
+ (state != TEGRA_ARI_CORE_C6) && (state != TEGRA_ARI_CORE_C7)) {
ERROR("%s: unknown cstate (%d)\n", __func__, state);
result = EINVAL;
} else {
@@ -325,12 +323,10 @@
int32_t ari_online_core(uint32_t ari_base, uint32_t core)
{
- uint64_t cpu = read_mpidr() & (uint64_t)(MPIDR_CPU_MASK);
- uint64_t cluster = (read_mpidr() & ((uint64_t)(MPIDR_AFFLVL_MASK) <<
- (uint64_t)(MPIDR_AFFINITY_BITS))) >>
- (uint64_t)(MPIDR_AFFINITY_BITS);
- uint64_t impl = (read_midr() >> (uint64_t)MIDR_IMPL_SHIFT) &
- (uint64_t)MIDR_IMPL_MASK;
+ uint64_t cpu = read_mpidr() & (MPIDR_CPU_MASK);
+ uint64_t cluster = (read_mpidr() & (MPIDR_CLUSTER_MASK)) >>
+ (MPIDR_AFFINITY_BITS);
+ uint64_t impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK;
int32_t ret;
/* construct the current CPU # */
@@ -344,8 +340,7 @@
/*
* The Denver cluster has 2 CPUs only - 0, 1.
*/
- if ((impl == (uint32_t)DENVER_IMPL) &&
- ((core == 2U) || (core == 3U))) {
+ if ((impl == DENVER_IMPL) && ((core == 2U) || (core == 3U))) {
ERROR("%s: unknown core id (%d)\n", __func__, core);
ret = EINVAL;
} else {
@@ -467,7 +462,7 @@
{
int32_t ret = 0;
/* sanity check GSC ID */
- if (gsc_idx > (uint32_t)TEGRA_ARI_GSC_VPR_IDX) {
+ if (gsc_idx > TEGRA_ARI_GSC_VPR_IDX) {
ret = EINVAL;
} else {
/* clean the previous response state */
diff --git a/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c b/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c
index 8cbb0b8..e948e99 100644
--- a/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c
+++ b/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c
@@ -111,8 +111,8 @@
static uint32_t mce_get_curr_cpu_ari_base(void)
{
uint64_t mpidr = read_mpidr();
- uint64_t cpuid = mpidr & (uint64_t)MPIDR_CPU_MASK;
- uint64_t impl = (read_midr() >> (uint64_t)MIDR_IMPL_SHIFT) & (uint64_t)MIDR_IMPL_MASK;
+ uint64_t cpuid = mpidr & MPIDR_CPU_MASK;
+ uint64_t impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK;
/*
* T186 has 2 CPU clusters, one with Denver CPUs and the other with
@@ -131,9 +131,9 @@
static arch_mce_ops_t *mce_get_curr_cpu_ops(void)
{
uint64_t mpidr = read_mpidr();
- uint64_t cpuid = mpidr & (uint64_t)MPIDR_CPU_MASK;
- uint64_t impl = (read_midr() >> (uint64_t)MIDR_IMPL_SHIFT) &
- (uint64_t)MIDR_IMPL_MASK;
+ uint64_t cpuid = mpidr & MPIDR_CPU_MASK;
+ uint64_t impl = (read_midr() >> MIDR_IMPL_SHIFT) &
+ MIDR_IMPL_MASK;
/*
* T186 has 2 CPU clusters, one with Denver CPUs and the other with
@@ -180,17 +180,17 @@
* get the parameters required for the update cstate info
* command
*/
- arg3 = read_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X4));
- arg4 = read_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X5));
- arg5 = read_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X6));
+ arg3 = read_ctx_reg(gp_regs, CTX_GPREG_X4);
+ arg4 = read_ctx_reg(gp_regs, CTX_GPREG_X5);
+ arg5 = read_ctx_reg(gp_regs, CTX_GPREG_X6);
ret = ops->update_cstate_info(cpu_ari_base, (uint32_t)arg0,
(uint32_t)arg1, (uint32_t)arg2, (uint8_t)arg3,
(uint32_t)arg4, (uint8_t)arg5);
- write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X4), (0));
- write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X5), (0));
- write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X6), (0));
+ write_ctx_reg(gp_regs, CTX_GPREG_X4, (0ULL));
+ write_ctx_reg(gp_regs, CTX_GPREG_X5, (0ULL));
+ write_ctx_reg(gp_regs, CTX_GPREG_X6, (0ULL));
break;
@@ -203,8 +203,8 @@
ret64 = ops->read_cstate_stats(cpu_ari_base, arg0);
/* update context to return cstate stats value */
- write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X1), (ret64));
- write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X2), (ret64));
+ write_ctx_reg(gp_regs, CTX_GPREG_X1, (ret64));
+ write_ctx_reg(gp_regs, CTX_GPREG_X2, (ret64));
break;
@@ -217,8 +217,7 @@
ret = ops->is_ccx_allowed(cpu_ari_base, arg0, arg1);
/* update context to return CCx status value */
- write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X1),
- (uint64_t)(ret));
+ write_ctx_reg(gp_regs, CTX_GPREG_X1, (uint64_t)(ret));
break;
@@ -226,10 +225,8 @@
ret = ops->is_sc7_allowed(cpu_ari_base, arg0, arg1);
/* update context to return SC7 status value */
- write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X1),
- (uint64_t)(ret));
- write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X3),
- (uint64_t)(ret));
+ write_ctx_reg(gp_regs, CTX_GPREG_X1, (uint64_t)(ret));
+ write_ctx_reg(gp_regs, CTX_GPREG_X3, (uint64_t)(ret));
break;
@@ -248,10 +245,10 @@
arg0);
/* update context to return if echo'd data matched source */
- write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X1),
- ((ret64 == arg0) ? 1ULL : 0ULL));
- write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X2),
- ((ret64 == arg0) ? 1ULL : 0ULL));
+ write_ctx_reg(gp_regs, CTX_GPREG_X1, ((ret64 == arg0) ?
+ 1ULL : 0ULL));
+ write_ctx_reg(gp_regs, CTX_GPREG_X2, ((ret64 == arg0) ?
+ 1ULL : 0ULL));
break;
@@ -263,10 +260,8 @@
* version = minor(63:32) | major(31:0). Update context
* to return major and minor version number.
*/
- write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X1),
- (ret64));
- write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X2),
- (ret64 >> 32ULL));
+ write_ctx_reg(gp_regs, CTX_GPREG_X1, (ret64));
+ write_ctx_reg(gp_regs, CTX_GPREG_X2, (ret64 >> 32ULL));
break;
@@ -275,7 +270,7 @@
TEGRA_ARI_MISC_FEATURE_LEAF_0, arg0);
/* update context to return features value */
- write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X1), (ret64));
+ write_ctx_reg(gp_regs, CTX_GPREG_X1, (ret64));
break;
@@ -298,9 +293,9 @@
ret64 = ops->read_write_mca(cpu_ari_base, arg0, &arg1);
/* update context to return MCA data/error */
- write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X1), (ret64));
- write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X2), (arg1));
- write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X3), (ret64));
+ write_ctx_reg(gp_regs, CTX_GPREG_X1, (ret64));
+ write_ctx_reg(gp_regs, CTX_GPREG_X2, (arg1));
+ write_ctx_reg(gp_regs, CTX_GPREG_X3, (ret64));
break;
@@ -308,8 +303,8 @@
ret64 = ops->read_write_mca(cpu_ari_base, arg0, &arg1);
/* update context to return MCA error */
- write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X1), (ret64));
- write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X3), (ret64));
+ write_ctx_reg(gp_regs, CTX_GPREG_X1, (ret64));
+ write_ctx_reg(gp_regs, CTX_GPREG_X3, (ret64));
break;
@@ -336,7 +331,7 @@
ret = ops->read_write_uncore_perfmon(cpu_ari_base, arg0, &arg1);
/* update context to return data */
- write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X1), (arg1));
+ write_ctx_reg(gp_regs, CTX_GPREG_X1, (arg1));
break;
case MCE_CMD_MISC_CCPLEX:
diff --git a/plat/nvidia/tegra/soc/t186/drivers/mce/nvg.c b/plat/nvidia/tegra/soc/t186/drivers/mce/nvg.c
index 1ac3710..44ee8fb 100644
--- a/plat/nvidia/tegra/soc/t186/drivers/mce/nvg.c
+++ b/plat/nvidia/tegra/soc/t186/drivers/mce/nvg.c
@@ -200,15 +200,14 @@
int32_t nvg_online_core(uint32_t ari_base, uint32_t core)
{
- uint64_t cpu = read_mpidr() & (uint64_t)MPIDR_CPU_MASK;
- uint64_t impl = (read_midr() >> (uint64_t)MIDR_IMPL_SHIFT) &
- (uint64_t)MIDR_IMPL_MASK;
+ uint64_t cpu = read_mpidr() & MPIDR_CPU_MASK;
+ uint64_t impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK;
int32_t ret = 0;
(void)ari_base;
/* sanity check code id */
- if ((core >= (uint32_t)MCE_CORE_ID_MAX) || (cpu == core)) {
+ if ((core >= MCE_CORE_ID_MAX) || (cpu == core)) {
ERROR("%s: unsupported core id (%d)\n", __func__, core);
ret = EINVAL;
} else {