intel: Modify non secure access function
Combine both peripheral and bridge non-secure access code
into a single callable function
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I38d335ed8d1e9f55d337b63cca121a473897ef70
diff --git a/plat/intel/soc/agilex/bl2_plat_setup.c b/plat/intel/soc/agilex/bl2_plat_setup.c
index 86b7ab8..0366f50 100644
--- a/plat/intel/soc/agilex/bl2_plat_setup.c
+++ b/plat/intel/soc/agilex/bl2_plat_setup.c
@@ -74,7 +74,6 @@
socfpga_delay_timer_init();
init_ncore_ccu();
init_hard_memory_controller();
- enable_ns_bridge_access();
}
diff --git a/plat/intel/soc/agilex/include/agilex_system_manager.h b/plat/intel/soc/agilex/include/agilex_system_manager.h
index be29536..65ab9f9 100644
--- a/plat/intel/soc/agilex/include/agilex_system_manager.h
+++ b/plat/intel/soc/agilex/include/agilex_system_manager.h
@@ -66,6 +66,7 @@
#define AGX_CCU_NOC_IOM_RAMSPACE0_0 0xf7018628
#define AGX_SYSMGR_CORE(x) (0xffd12000 + (x))
+
#define SYSMGR_BOOT_SCRATCH_COLD_0 0x200
#define SYSMGR_BOOT_SCRATCH_COLD_1 0x204
#define SYSMGR_BOOT_SCRATCH_COLD_2 0x208
@@ -73,6 +74,8 @@
#define DISABLE_BRIDGE_FIREWALL 0x0ffe0101
#define DISABLE_L4_FIREWALL (BIT(0) | BIT(16) | BIT(24))
+void enable_nonsecure_access(void);
+void enable_ns_peripheral_access(void);
void enable_ns_bridge_access(void);
#endif
diff --git a/plat/intel/soc/agilex/soc/agilex_system_manager.c b/plat/intel/soc/agilex/soc/agilex_system_manager.c
index 88e895d..2232365 100644
--- a/plat/intel/soc/agilex/soc/agilex_system_manager.c
+++ b/plat/intel/soc/agilex/soc/agilex_system_manager.c
@@ -11,6 +11,12 @@
void enable_nonsecure_access(void)
{
+ enable_ns_peripheral_access();
+ enable_ns_bridge_access();
+}
+
+void enable_ns_peripheral_access(void)
+{
mmio_write_32(AGX_NOC_FW_L4_PER_SCR_NAND_REGISTER, DISABLE_L4_FIREWALL);
mmio_write_32(AGX_NOC_FW_L4_PER_SCR_NAND_DATA, DISABLE_L4_FIREWALL);
diff --git a/plat/intel/soc/stratix10/include/s10_system_manager.h b/plat/intel/soc/stratix10/include/s10_system_manager.h
index 4abfedb..8c51181 100644
--- a/plat/intel/soc/stratix10/include/s10_system_manager.h
+++ b/plat/intel/soc/stratix10/include/s10_system_manager.h
@@ -4,6 +4,10 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
+#define S10_FIREWALL_SOC2FPGA 0xffd21200
+#define S10_FIREWALL_LWSOC2FPGA 0xffd21300
+
+/* L3 Interconnect Register Map */
#define S10_NOC_FW_L4_PER_SCR_NAND_REGISTER 0xffd21000
#define S10_NOC_FW_L4_PER_SCR_NAND_DATA 0xffd21004
#define S10_NOC_FW_L4_PER_SCR_USB0_REGISTER 0xffd2100c
@@ -59,13 +63,19 @@
#define S10_CCU_NOC_CPU0_RAMSPACE0_0 0xf7004688
#define S10_CCU_NOC_IOM_RAMSPACE0_0 0xf7018628
+/* System Manager Register Map */
#define S10_SYSMGR_CORE(x) (0xffd12000 + (x))
+
#define SYSMGR_MMC 0x28
#define SYSMGR_MMC_DRVSEL(x) (((x) & 0x7) << 0)
+
#define SYSMGR_BOOT_SCRATCH_COLD_0 0x200
#define SYSMGR_BOOT_SCRATCH_COLD_1 0x204
#define SYSMGR_BOOT_SCRATCH_COLD_2 0x208
-
+#define DISABLE_BRIDGE_FIREWALL 0x0ffe0101
#define DISABLE_L4_FIREWALL (BIT(0) | BIT(16) | BIT(24))
+void enable_nonsecure_access(void);
+void enable_ns_peripheral_access(void);
+void enable_ns_bridge_access(void);
diff --git a/plat/intel/soc/stratix10/soc/s10_system_manager.c b/plat/intel/soc/stratix10/soc/s10_system_manager.c
index a2ed5a3..6963e7d 100644
--- a/plat/intel/soc/stratix10/soc/s10_system_manager.c
+++ b/plat/intel/soc/stratix10/soc/s10_system_manager.c
@@ -10,6 +10,12 @@
void enable_nonsecure_access(void)
{
+ enable_ns_peripheral_access();
+ enable_ns_bridge_access();
+}
+
+void enable_ns_peripheral_access(void)
+{
mmio_write_32(S10_NOC_FW_L4_PER_SCR_NAND_REGISTER, DISABLE_L4_FIREWALL);
mmio_write_32(S10_NOC_FW_L4_PER_SCR_NAND_DATA, DISABLE_L4_FIREWALL);
@@ -91,3 +97,8 @@
}
+void enable_ns_bridge_access(void)
+{
+ mmio_write_32(S10_FIREWALL_SOC2FPGA, DISABLE_BRIDGE_FIREWALL);
+ mmio_write_32(S10_FIREWALL_LWSOC2FPGA, DISABLE_BRIDGE_FIREWALL);
+}