Merge "fix(zynqmp): fix prepare_dtb() memory description" into integration
diff --git a/.versionrc.js b/.versionrc.js
index 4e9c71f..3a21ded 100644
--- a/.versionrc.js
+++ b/.versionrc.js
@@ -101,6 +101,25 @@
"type": "json"
},
{
+ "filename": "docs/conf.py",
+ "updater": {
+ "readVersion": function (contents) {
+ const _ver = contents.match(/version\s=.*"(\d)\.(\d)\.(\d)/);
+
+ return `${_ver[1]}.${_ver[2]}.${_ver[2]}`;
+ },
+
+ "writeVersion": function (contents, version) {
+ const _ver = 'version = "' + version + '"'
+ const _rel = 'release = "' + version + '"'
+
+ contents = contents.replace(/^(version\s=\s")((\d).?)*$/m, _ver)
+ contents = contents.replace(/^(release\s=\s")((\d).?)*$/m, _rel)
+ return contents
+ }
+ },
+ },
+ {
"filename": "tools/conventional-changelog-tf-a/package.json",
"type": "json"
},
diff --git a/Makefile b/Makefile
index 3dbf28e..3ac31a5 100644
--- a/Makefile
+++ b/Makefile
@@ -646,6 +646,11 @@
ifeq ($(SPMC_AT_EL3),1)
$(error SPMC_AT_EL3 and ENABLE_RME cannot both be enabled.)
endif
+ifneq (${SPD}, none)
+ifneq (${SPD}, spmd)
+ $(error ENABLE_RME is incompatible with SPD=${SPD}. Use SPD=spmd)
+endif
+endif
include services/std_svc/rmmd/rmmd.mk
$(warning "RME is an experimental feature")
endif
diff --git a/bl1/aarch64/bl1_arch_setup.c b/bl1/aarch64/bl1_arch_setup.c
index 0a1cb30..f3de536 100644
--- a/bl1/aarch64/bl1_arch_setup.c
+++ b/bl1/aarch64/bl1_arch_setup.c
@@ -17,19 +17,3 @@
/* Set the next EL to be AArch64 */
write_scr_el3(read_scr_el3() | SCR_RW_BIT);
}
-
-/*******************************************************************************
- * Set the Secure EL1 required architectural state
- ******************************************************************************/
-void bl1_arch_next_el_setup(void)
-{
- u_register_t next_sctlr;
-
- /* Use the same endianness than the current BL */
- next_sctlr = (read_sctlr_el3() & SCTLR_EE_BIT);
-
- /* Set SCTLR Secure EL1 */
- next_sctlr |= SCTLR_EL1_RES1;
-
- write_sctlr_el1(next_sctlr);
-}
diff --git a/bl1/bl1.ld.S b/bl1/bl1.ld.S
index a2527e6..49dda85 100644
--- a/bl1/bl1.ld.S
+++ b/bl1/bl1.ld.S
@@ -41,6 +41,7 @@
*bl1_entrypoint.o(.text*)
*(SORT_BY_ALIGNMENT(.text*))
*(.vectors)
+ __TEXT_END_UNALIGNED__ = .;
. = ALIGN(PAGE_SIZE);
@@ -72,6 +73,7 @@
* aligned and lld does not align the LMA to the alignment specified
* on the .data section.
*/
+ __RODATA_END_UNALIGNED__ = .;
__RODATA_END__ = .;
. = ALIGN(16);
diff --git a/bl1/bl1_private.h b/bl1/bl1_private.h
index e119ba7..61fb5be 100644
--- a/bl1/bl1_private.h
+++ b/bl1/bl1_private.h
@@ -17,7 +17,6 @@
* Function prototypes
*****************************************/
void bl1_arch_setup(void);
-void bl1_arch_next_el_setup(void);
void bl1_prepare_next_image(unsigned int image_id);
void bl1_run_bl2_in_root(void);
diff --git a/bl2/aarch64/bl2_run_next_image.S b/bl2/aarch64/bl2_run_next_image.S
index f0a8be8..1431a5f 100644
--- a/bl2/aarch64/bl2_run_next_image.S
+++ b/bl2/aarch64/bl2_run_next_image.S
@@ -24,15 +24,6 @@
tlbi alle3
bl bl2_el3_plat_prepare_exit
-#if ENABLE_PAUTH
- /* ---------------------------------------------
- * Disable pointer authentication before jumping
- * to next boot image.
- * ---------------------------------------------
- */
- bl pauth_disable_el3
-#endif /* ENABLE_PAUTH */
-
ldp x0, x1, [x20, #ENTRY_POINT_INFO_PC_OFFSET]
msr elr_el3, x0
msr spsr_el3, x1
diff --git a/bl2/bl2.ld.S b/bl2/bl2.ld.S
index 5f689d5..db83a0c 100644
--- a/bl2/bl2.ld.S
+++ b/bl2/bl2.ld.S
@@ -35,6 +35,7 @@
*(SORT_BY_ALIGNMENT(.text*))
*(.vectors)
+ __TEXT_END_UNALIGNED__ = .;
. = ALIGN(PAGE_SIZE);
@@ -57,6 +58,7 @@
RODATA_COMMON
+ __RODATA_END_UNALIGNED__ = .;
. = ALIGN(PAGE_SIZE);
__RODATA_END__ = .;
diff --git a/bl2/bl2_el3.ld.S b/bl2/bl2_el3.ld.S
index 5da631c..4aa5cb0 100644
--- a/bl2/bl2_el3.ld.S
+++ b/bl2/bl2_el3.ld.S
@@ -65,6 +65,7 @@
*(SORT_BY_ALIGNMENT(.text*))
*(.vectors)
+ __TEXT_END_UNALIGNED__ = .;
. = ALIGN(PAGE_SIZE);
@@ -78,6 +79,7 @@
RODATA_COMMON
+ __RODATA_END_UNALIGNED__ = .;
. = ALIGN(PAGE_SIZE);
__RODATA_END__ = .;
diff --git a/bl2u/bl2u.ld.S b/bl2u/bl2u.ld.S
index 21c91b4..7b1a101 100644
--- a/bl2u/bl2u.ld.S
+++ b/bl2u/bl2u.ld.S
@@ -32,6 +32,7 @@
*bl2u_entrypoint.o(.text*)
*(SORT_BY_ALIGNMENT(.text*))
*(.vectors)
+ __TEXT_END_UNALIGNED__ = .;
. = ALIGN(PAGE_SIZE);
@@ -53,6 +54,7 @@
RODATA_COMMON
+ __RODATA_END_UNALIGNED__ = .;
. = ALIGN(PAGE_SIZE);
__RODATA_END__ = .;
} >RAM
diff --git a/bl31/bl31.ld.S b/bl31/bl31.ld.S
index abcae0c..7a8c41a 100644
--- a/bl31/bl31.ld.S
+++ b/bl31/bl31.ld.S
@@ -42,6 +42,7 @@
*bl31_entrypoint.o(.text*)
*(SORT_BY_ALIGNMENT(SORT(.text*)))
*(.vectors)
+ __TEXT_END_UNALIGNED__ = .;
. = ALIGN(PAGE_SIZE);
@@ -62,6 +63,7 @@
. = ALIGN(8);
# include <lib/el3_runtime/pubsub_events.h>
+ __RODATA_END_UNALIGNED__ = .;
. = ALIGN(PAGE_SIZE);
diff --git a/bl32/sp_min/sp_min.ld.S b/bl32/sp_min/sp_min.ld.S
index 0a2bad0..dd81973 100644
--- a/bl32/sp_min/sp_min.ld.S
+++ b/bl32/sp_min/sp_min.ld.S
@@ -34,6 +34,7 @@
*entrypoint.o(.text*)
*(SORT_BY_ALIGNMENT(.text*))
*(.vectors)
+ __TEXT_END_UNALIGNED__ = .;
. = ALIGN(PAGE_SIZE);
@@ -58,6 +59,7 @@
. = ALIGN(8);
# include <lib/el3_runtime/pubsub_events.h>
+ __RODATA_END_UNALIGNED__ = .;
. = ALIGN(PAGE_SIZE);
diff --git a/bl32/tsp/tsp.ld.S b/bl32/tsp/tsp.ld.S
index b735f45..22bf11d 100644
--- a/bl32/tsp/tsp.ld.S
+++ b/bl32/tsp/tsp.ld.S
@@ -30,6 +30,7 @@
*tsp_entrypoint.o(.text*)
*(.text*)
*(.vectors)
+ __TEXT_END_UNALIGNED__ = .;
. = ALIGN(PAGE_SIZE);
@@ -43,6 +44,7 @@
RODATA_COMMON
+ __RODATA_END_UNALIGNED__ = .;
. = ALIGN(PAGE_SIZE);
__RODATA_END__ = .;
diff --git a/changelog.yaml b/changelog.yaml
index 0c4644d..4703979 100644
--- a/changelog.yaml
+++ b/changelog.yaml
@@ -1301,6 +1301,9 @@
- title: Certificate Creation Tool
scope: cert-create
+ - title: Memory Mapping Tool
+ scope: memmap
+
deprecated:
- cert_create
diff --git a/docs/components/ffa-manifest-binding.rst b/docs/components/ffa-manifest-binding.rst
index 1061ca0..ee322ac 100644
--- a/docs/components/ffa-manifest-binding.rst
+++ b/docs/components/ffa-manifest-binding.rst
@@ -91,7 +91,7 @@
- 0x2: 64k
- boot-order
- - value type: <u32>
+ - value type: <u16>
- A unique number amongst all partitions that specifies if this partition
must be booted before others. The partition with the smaller number will be
booted first.
diff --git a/docs/conf.py b/docs/conf.py
index 371632a..345f53b 100644
--- a/docs/conf.py
+++ b/docs/conf.py
@@ -1,6 +1,6 @@
# -*- coding: utf-8 -*-
#
-# Copyright (c) 2019-2021, Arm Limited. All rights reserved.
+# Copyright (c) 2019-2023, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -9,27 +9,34 @@
#
# See the options documentation at http://www.sphinx-doc.org/en/master/config
-import os
# -- Project information -----------------------------------------------------
-project = 'Trusted Firmware-A'
+project = "Trusted Firmware-A"
+author = "Trusted Firmware-A contributors"
+version = "2.9.0"
+release = "2.9.0"
# -- General configuration ---------------------------------------------------
# Add any Sphinx extension module names here, as strings. They can be
# extensions coming with Sphinx (named 'sphinx.ext.*') or your custom
# ones.
-extensions = ['myst_parser', 'sphinx.ext.autosectionlabel', 'sphinxcontrib.plantuml']
+extensions = [
+ "myst_parser",
+ "sphinx.ext.autosectionlabel",
+ "sphinxcontrib.plantuml",
+ "sphinxcontrib.inkscapeconverter",
+]
# Add any paths that contain templates here, relative to this directory.
-templates_path = ['_templates']
+templates_path = ["_templates"]
# The suffix(es) of source filenames.
-source_suffix = ['.md', '.rst']
+source_suffix = [".md", ".rst"]
# The master toctree document.
-master_doc = 'index'
+master_doc = "index"
# The language for content autogenerated by Sphinx. Refer to documentation
# for a list of supported languages.
@@ -45,15 +52,16 @@
exclude_patterns = [".env", "env", ".venv", "venv"]
# The name of the Pygments (syntax highlighting) style to use.
-pygments_style = 'sphinx'
+pygments_style = "sphinx"
# Load the contents of the global substitutions file into the 'rst_prolog'
-# variable. This ensures that the substitutions are all inserted into each page.
-with open('global_substitutions.txt', 'r') as subs:
- rst_prolog = subs.read()
+# variable. This ensures that the substitutions are all inserted into each
+# page.
+with open("global_substitutions.txt", "r") as subs:
+ rst_prolog = subs.read()
# Minimum version of sphinx required
-needs_sphinx = '2.0'
+needs_sphinx = "2.0"
# -- Options for HTML output -------------------------------------------------
@@ -68,21 +76,21 @@
html_theme = "sphinx_rtd_theme"
# The logo to display in the sidebar
-html_logo = 'resources/TrustedFirmware-Logo_standard-white.png'
+html_logo = "resources/TrustedFirmware-Logo_standard-white.png"
# Options for the "sphinx-rtd-theme" theme
html_theme_options = {
- 'collapse_navigation': False, # Can expand and collapse sidebar entries
- 'prev_next_buttons_location': 'both', # Top and bottom of the page
- 'style_external_links': True # Display an icon next to external links
+ "collapse_navigation": False, # Can expand and collapse sidebar entries
+ "prev_next_buttons_location": "both", # Top and bottom of the page
+ "style_external_links": True, # Display an icon next to external links
}
# Path to _static directory
-html_static_path = ['_static']
+html_static_path = ["_static"]
# Path to css file relative to html_static_path
html_css_files = [
- 'css/custom.css',
+ "css/custom.css",
]
# -- Options for autosectionlabel --------------------------------------------
@@ -92,4 +100,12 @@
# -- Options for plantuml ----------------------------------------------------
+plantuml_output_format = "svg_img"
+
-plantuml_output_format = 'svg_img'
+# -- Options for latexmk ----------------------------------------------------
+
+latex_engine = "xelatex"
+latex_elements = {
+ "maxlistdepth": "10",
+ "pointsize": "11pt",
+}
diff --git a/docs/design/firmware-design.rst b/docs/design/firmware-design.rst
index 8ac1c3e..50839bd 100644
--- a/docs/design/firmware-design.rst
+++ b/docs/design/firmware-design.rst
@@ -245,63 +245,6 @@
specific reset handler function (see the section: "CPU specific operations
framework").
-- Control register setup (for AArch64)
-
- - ``SCTLR_EL3``. Instruction cache is enabled by setting the ``SCTLR_EL3.I``
- bit. Alignment and stack alignment checking is enabled by setting the
- ``SCTLR_EL3.A`` and ``SCTLR_EL3.SA`` bits. Exception endianness is set to
- little-endian by clearing the ``SCTLR_EL3.EE`` bit.
-
- - ``SCR_EL3``. The register width of the next lower exception level is set
- to AArch64 by setting the ``SCR.RW`` bit. The ``SCR.EA`` bit is set to trap
- both External Aborts and SError Interrupts in EL3. The ``SCR.SIF`` bit is
- also set to disable instruction fetches from Non-secure memory when in
- secure state.
-
- - ``CPTR_EL3``. Accesses to the ``CPACR_EL1`` register from EL1 or EL2, or the
- ``CPTR_EL2`` register from EL2 are configured to not trap to EL3 by
- clearing the ``CPTR_EL3.TCPAC`` bit. Access to the trace functionality is
- configured not to trap to EL3 by clearing the ``CPTR_EL3.TTA`` bit.
- Instructions that access the registers associated with Floating Point
- and Advanced SIMD execution are configured to not trap to EL3 by
- clearing the ``CPTR_EL3.TFP`` bit.
-
- - ``DAIF``. The SError interrupt is enabled by clearing the SError interrupt
- mask bit.
-
- - ``MDCR_EL3``. The trap controls, ``MDCR_EL3.TDOSA``, ``MDCR_EL3.TDA`` and
- ``MDCR_EL3.TPM``, are set so that accesses to the registers they control
- do not trap to EL3. AArch64 Secure self-hosted debug is disabled by
- setting the ``MDCR_EL3.SDD`` bit. Also ``MDCR_EL3.SPD32`` is set to
- disable AArch32 Secure self-hosted privileged debug from S-EL1.
-
-- Control register setup (for AArch32)
-
- - ``SCTLR``. Instruction cache is enabled by setting the ``SCTLR.I`` bit.
- Alignment checking is enabled by setting the ``SCTLR.A`` bit.
- Exception endianness is set to little-endian by clearing the
- ``SCTLR.EE`` bit.
-
- - ``SCR``. The ``SCR.SIF`` bit is set to disable instruction fetches from
- Non-secure memory when in secure state.
-
- - ``CPACR``. Allow execution of Advanced SIMD instructions at PL0 and PL1,
- by clearing the ``CPACR.ASEDIS`` bit. Access to the trace functionality
- is configured not to trap to undefined mode by clearing the
- ``CPACR.TRCDIS`` bit.
-
- - ``NSACR``. Enable non-secure access to Advanced SIMD functionality and
- system register access to implemented trace registers.
-
- - ``FPEXC``. Enable access to the Advanced SIMD and floating-point
- functionality from all Exception levels.
-
- - ``CPSR.A``. The Asynchronous data abort interrupt is enabled by clearing
- the Asynchronous data abort interrupt mask bit.
-
- - ``SDCR``. The ``SDCR.SPD`` field is set to disable AArch32 Secure
- self-hosted privileged debug.
-
Platform initialization
^^^^^^^^^^^^^^^^^^^^^^^
@@ -1616,8 +1559,10 @@
- ``__RO_START__``
- ``__RO_END__``
- ``__TEXT_START__``
+- ``__TEXT_END_UNALIGNED__``
- ``__TEXT_END__``
- ``__RODATA_START__``
+- ``__RODATA_END_UNALIGNED__``
- ``__RODATA_END__``
BL1's linker symbols
diff --git a/docs/design_documents/psci_osi_mode.rst b/docs/design_documents/psci_osi_mode.rst
index 3296e27..a6e1bdf 100644
--- a/docs/design_documents/psci_osi_mode.rst
+++ b/docs/design_documents/psci_osi_mode.rst
@@ -4,7 +4,7 @@
:Author: Maulik Shah & Wing Li
:Organization: Qualcomm Innovation Center, Inc. & Google LLC
:Contact: Maulik Shah <quic_mkshah@quicinc.com> & Wing Li <wingers@google.com>
-:Status: RFC
+:Status: Accepted
.. contents:: Table of Contents
@@ -367,9 +367,11 @@
``psci_validate_state_coordination``. If validation fails, propagate the
error up the call stack.
-* Update the return type of the platform specific ``pwr_domain_suspend``
- handler from ``void`` to ``int``, to allow the platform to optionally perform
- validations based on hardware states.
+* Add a new optional member ``pwr_domain_validate_suspend`` to
+ ``plat_psci_ops_t`` to allow the platform to optionally perform validations
+ based on hardware states.
+
+* The platform specific ``pwr_domain_suspend`` handler remains unchanged.
.. image:: ../resources/diagrams/psci-osi-mode.png
diff --git a/docs/porting-guide.rst b/docs/porting-guide.rst
index 1250071..8182f91 100644
--- a/docs/porting-guide.rst
+++ b/docs/porting-guide.rst
@@ -2818,6 +2818,17 @@
for the higher power domain levels depending on the result of state
coordination. The generic code expects the handler to succeed.
+plat_psci_ops.pwr_domain_validate_suspend() [optional]
+......................................................
+
+This is an optional function that is only compiled into the build if the build
+option ``PSCI_OS_INIT_MODE`` is enabled.
+
+If implemented, this function allows the platform to perform platform specific
+validations based on hardware states. The generic code expects this function to
+return PSCI_E_SUCCESS on success, or either PSCI_E_DENIED or
+PSCI_E_INVALID_PARAMS as appropriate for any invalid requests.
+
plat_psci_ops.pwr_domain_suspend_pwrdown_early() [optional]
...........................................................
@@ -2876,10 +2887,6 @@
data, for example in DRAM. The Distributor can then be powered down using an
implementation-defined sequence.
-If the build option ``PSCI_OS_INIT_MODE`` is enabled, the generic code expects
-the platform to return PSCI_E_SUCCESS on success, or either PSCI_E_DENIED or
-PSCI_E_INVALID_PARAMS as appropriate for any invalid requests.
-
plat_psci_ops.pwr_domain_pwr_down_wfi()
.......................................
diff --git a/docs/process/coding-guidelines.rst b/docs/process/coding-guidelines.rst
index 13fb7cb..9730390 100644
--- a/docs/process/coding-guidelines.rst
+++ b/docs/process/coding-guidelines.rst
@@ -449,17 +449,20 @@
portable, harder to understand, maintain and audit security wise. Also, static
analysis tools generally don't analyze assembly code.
-There are, however, legitimate uses of assembly language. These include:
+If specific system-level instructions must be used (like cache maintenance
+operations), please consider using inline assembly. The ``arch_helpers.h`` files
+already define inline functions for a lot of these.
- - Early boot code executed before the C runtime environment is setup.
-
- - Exception handling code.
-
- - Low-level code where the exact sequence of instructions executed on the CPU
- matters, such as CPU reset sequences.
+There are, however, legitimate uses of assembly language. These are usually
+early boot (eg. cpu reset sequences) and exception handling code before the C
+runtime environment is set up.
- - Low-level code where specific system-level instructions must be used, such
- as cache maintenance operations.
+When writing assembly please note that a wide variety of common instruction
+sequences have helper macros in ``asm_macros.S`` which are preferred over
+writing them directly. This is especially important for debugging purposes as
+debug symbols must manually be included. Please use the ``func_prologue`` and
+``func_epilogue`` macros if you need to use the stack. Also, obeying the
+Procedure Call Standard (PCS) is generally recommended.
Do not use weak functions
-------------------------
diff --git a/docs/resources/diagrams/plantuml/fconf_bl1_load_config.puml b/docs/resources/diagrams/plantuml/fconf_bl1_load_config.puml
index e513ed4..9b693c8 100644
--- a/docs/resources/diagrams/plantuml/fconf_bl1_load_config.puml
+++ b/docs/resources/diagrams/plantuml/fconf_bl1_load_config.puml
@@ -21,7 +21,7 @@
fvp_bl1_setup -> arm_bl1_setup : arm_bl1_platform_setup()
arm_bl1_setup -> arm_io_storage : plat_arm_io_setup()
note over arm_io_storage : register and setup fip
-arm_bl1_setup -> fconf : set_fw_config_info(fw_config_base, max_size)
+arm_bl1_setup -> fconf : set_config_info(fw_config_base, max_size, FW_CONFIG_ID)
note over fconf
set fw_config information
(address, size, image_id)
diff --git a/docs/resources/diagrams/psci-osi-mode.png b/docs/resources/diagrams/psci-osi-mode.png
index d322953..09175e5 100644
--- a/docs/resources/diagrams/psci-osi-mode.png
+++ b/docs/resources/diagrams/psci-osi-mode.png
Binary files differ
diff --git a/docs/tools/memory-layout-tool.rst b/docs/tools/memory-layout-tool.rst
index ce14dab..8874bd7 100644
--- a/docs/tools/memory-layout-tool.rst
+++ b/docs/tools/memory-layout-tool.rst
@@ -113,6 +113,122 @@
poetry run memory --help
+Memory Footprint
+~~~~~~~~~~~~~~~~
+
+The tool enables users to view static memory consumption. When the options
+``-f``, or ``--footprint`` are provided, the script analyses the ELF binaries in
+the build path to generate a table (per memory type), showing memory allocation
+and usage. This is the default output generated by the tool.
+
+.. code:: shell
+
+ $ poetry run memory -f
+ build-path: build/fvp/release
+ +----------------------------------------------------------------------------+
+ | Memory Usage (bytes) [RAM] |
+ +-----------+------------+------------+------------+------------+------------+
+ | Component | Start | Limit | Size | Free | Total |
+ +-----------+------------+------------+------------+------------+------------+
+ | BL1 | 4034000 | 4040000 | 7000 | 5000 | c000 |
+ | BL2 | 4021000 | 4034000 | d000 | 6000 | 13000 |
+ | BL2U | 4021000 | 4034000 | a000 | 9000 | 13000 |
+ | BL31 | 4003000 | 4040000 | 1e000 | 1f000 | 3d000 |
+ +-----------+------------+------------+------------+------------+------------+
+
+ +----------------------------------------------------------------------------+
+ | Memory Usage (bytes) [ROM] |
+ +-----------+------------+------------+------------+------------+------------+
+ | Component | Start | Limit | Size | Free | Total |
+ +-----------+------------+------------+------------+------------+------------+
+ | BL1 | 0 | 4000000 | 5df0 | 3ffa210 | 4000000 |
+ +-----------+------------+------------+------------+------------+------------+
+
+The script relies on symbols in the symbol table to determine the start, end,
+and limit addresses of each bootloader stage.
+
+Memory Tree
+~~~~~~~~~~~
+
+A hierarchical view of the memory layout can be produced by passing the option
+``-t`` or ``--tree`` to the tool. This gives the start, end, and size of each
+module, their ELF segments as well as sections.
+
+.. code:: shell
+
+ $ poetry run memory -t
+ build-path: build/fvp/release
+ name start end size
+ bl1 0 400c000 400c000
+ ├── 00 0 5de0 5de0
+ │ ├── .text 0 5000 5000
+ │ └── .rodata 5000 5de0 de0
+ ├── 01 4034000 40344c5 4c5
+ │ └── .data 4034000 40344c5 4c5
+ ├── 02 4034500 4034a00 500
+ │ └── .stacks 4034500 4034a00 500
+ ├── 04 4034a00 4035600 c00
+ │ └── .bss 4034a00 4035600 c00
+ └── 03 4036000 403b000 5000
+ └── .xlat_table 4036000 403b000 5000
+ bl2 4021000 4034000 13000
+ ├── 00 4021000 4027000 6000
+ │ ├── .text 4021000 4026000 5000
+ │ └── .rodata 4026000 4027000 1000
+ └── 01 4027000 402e000 7000
+ ├── .data 4027000 4027809 809
+ ├── .stacks 4027840 4027e40 600
+ ├── .bss 4028000 4028800 800
+ └── .xlat_table 4029000 402e000 5000
+ bl2u 4021000 4034000 13000
+ ├── 00 4021000 4025000 4000
+ │ ├── .text 4021000 4024000 3000
+ │ └── .rodata 4024000 4025000 1000
+ └── 01 4025000 402b000 6000
+ ├── .data 4025000 4025065 65
+ ├── .stacks 4025080 4025480 400
+ ├── .bss 4025600 4025c00 600
+ └── .xlat_table 4026000 402b000 5000
+ bl31 4003000 4040000 3d000
+ ├── 02 ffe00000 ffe03000 3000
+ │ └── .el3_tzc_dram ffe00000 ffe03000 3000
+ ├── 00 4003000 4010000 d000
+ │ └── .text 4003000 4010000 d000
+ └── 01 4010000 4021000 11000
+ ├── .rodata 4010000 4012000 2000
+ ├── .data 4012000 401219d 19d
+ ├── .stacks 40121c0 40161c0 4000
+ ├── .bss 4016200 4018c00 2a00
+ ├── .xlat_table 4019000 4020000 7000
+ └── .coherent_ram 4020000 4021000 1000
+
+
+The granularity of this view can be modified with the ``--depth`` option. For
+instance, if you only require the tree up to the level showing segment data,
+you can specify the depth with:
+
+.. code::
+
+ $ poetry run memory -t --depth 2
+ build-path: build/fvp/release
+ name start end size
+ bl1 0 400c000 400c000
+ ├── 00 0 5df0 5df0
+ ├── 01 4034000 40344c5 4c5
+ ├── 02 4034500 4034a00 500
+ ├── 04 4034a00 4035600 c00
+ └── 03 4036000 403b000 5000
+ bl2 4021000 4034000 13000
+ ├── 00 4021000 4027000 6000
+ └── 01 4027000 402e000 7000
+ bl2u 4021000 4034000 13000
+ ├── 00 4021000 4025000 4000
+ └── 01 4025000 402b000 6000
+ bl31 4003000 4040000 3d000
+ ├── 02 ffe00000 ffe03000 3000
+ ├── 00 4003000 4010000 d000
+ └── 01 4010000 4021000 11000
+
--------------
*Copyright (c) 2023, Arm Limited. All rights reserved.*
diff --git a/drivers/auth/cca/cot.c b/drivers/auth/cca/cot.c
index e8f4d9c..2a03604 100644
--- a/drivers/auth/cca/cot.c
+++ b/drivers/auth/cca/cot.c
@@ -42,8 +42,8 @@
/*
* Parameter type descriptors.
*/
-static auth_param_type_desc_t trusted_nv_ctr = AUTH_PARAM_TYPE_DESC(
- AUTH_PARAM_NV_CTR, TRUSTED_FW_NVCOUNTER_OID);
+static auth_param_type_desc_t cca_nv_ctr = AUTH_PARAM_TYPE_DESC(
+ AUTH_PARAM_NV_CTR, CCA_FW_NVCOUNTER_OID);
static auth_param_type_desc_t subject_pk = AUTH_PARAM_TYPE_DESC(
AUTH_PARAM_PUB_KEY, 0);
static auth_param_type_desc_t sig = AUTH_PARAM_TYPE_DESC(
@@ -69,6 +69,8 @@
AUTH_PARAM_HASH, RMM_HASH_OID);
#ifdef IMAGE_BL2
+static auth_param_type_desc_t trusted_nv_ctr = AUTH_PARAM_TYPE_DESC(
+ AUTH_PARAM_NV_CTR, TRUSTED_FW_NVCOUNTER_OID);
static auth_param_type_desc_t non_trusted_nv_ctr = AUTH_PARAM_TYPE_DESC(
AUTH_PARAM_NV_CTR, NON_TRUSTED_FW_NVCOUNTER_OID);
@@ -127,8 +129,8 @@
[1] = {
.type = AUTH_METHOD_NV_CTR,
.param.nv_ctr = {
- .cert_nv_ctr = &trusted_nv_ctr,
- .plat_nv_ctr = &trusted_nv_ctr
+ .cert_nv_ctr = &cca_nv_ctr,
+ .plat_nv_ctr = &cca_nv_ctr
}
}
},
diff --git a/drivers/mtd/nand/spi_nand.c b/drivers/mtd/nand/spi_nand.c
index 542b614..744383a 100644
--- a/drivers/mtd/nand/spi_nand.c
+++ b/drivers/mtd/nand/spi_nand.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2022, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2019-2023, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -17,7 +17,6 @@
#define SPI_NAND_MAX_ID_LEN 4U
#define DELAY_US_400MS 400000U
-#define MACRONIX_ID 0xC2U
static struct spinand_device spinand_dev;
@@ -91,7 +90,7 @@
{
bool enable = false;
- if (manufacturer_id != MACRONIX_ID) {
+ if ((spinand_dev.flags & SPI_NAND_HAS_QE_BIT) == 0U) {
return 0;
}
diff --git a/drivers/st/clk/clk-stm32mp13.c b/drivers/st/clk/clk-stm32mp13.c
index db427ad..01d1764 100644
--- a/drivers/st/clk/clk-stm32mp13.c
+++ b/drivers/st/clk/clk-stm32mp13.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2022, STMicroelectronics - All Rights Reserved
+ * Copyright (C) 2022-2023, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
*/
@@ -1216,7 +1216,7 @@
* => deactivate CKPER only after switching clock
*/
if (ckper_disabled) {
- ret = stm32_clk_configure_mux(priv, CLK_CKPER_DISABLED & CMD_MASK);
+ ret = stm32_clk_configure_mux(priv, CLK_CKPER_DISABLED);
if (ret != 0) {
return ret;
}
diff --git a/drivers/st/uart/aarch32/stm32_console.S b/drivers/st/uart/aarch32/stm32_console.S
index e3e0e67..d64a6cd 100644
--- a/drivers/st/uart/aarch32/stm32_console.S
+++ b/drivers/st/uart/aarch32/stm32_console.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -234,11 +234,16 @@
cmp r0, #0
ASM_ASSERT(ne)
#endif /* ENABLE_ASSERTIONS */
+ /* Skip flush if UART is not enabled */
+ ldr r1, [r0, #USART_CR1]
+ ands r1, r1, #USART_CR1_UE
+ beq 1f
/* Check Transmit Data Register Empty */
txe_loop_3:
ldr r1, [r0, #USART_ISR]
tst r1, #USART_ISR_TXE
beq txe_loop_3
+1:
bx lr
endfunc console_stm32_core_flush
diff --git a/fdts/stm32mp13-bl2.dtsi b/fdts/stm32mp13-bl2.dtsi
index 06db796..2b23daf 100644
--- a/fdts/stm32mp13-bl2.dtsi
+++ b/fdts/stm32mp13-bl2.dtsi
@@ -3,6 +3,15 @@
* Copyright (c) 2022-2023, STMicroelectronics - All Rights Reserved
*/
+/omit-if-no-ref/ &i2c4_pins_a;
+/omit-if-no-ref/ &sdmmc1_b4_pins_a;
+/omit-if-no-ref/ &sdmmc1_clk_pins_a;
+/omit-if-no-ref/ &sdmmc2_b4_pins_a;
+/omit-if-no-ref/ &sdmmc2_clk_pins_a;
+/omit-if-no-ref/ &uart4_pins_a;
+/omit-if-no-ref/ &uart8_pins_a;
+/omit-if-no-ref/ &usart1_pins_a;
+
/ {
aliases {
#if !STM32MP_EMMC && !STM32MP_SDMMC
diff --git a/fdts/stm32mp13-pinctrl.dtsi b/fdts/stm32mp13-pinctrl.dtsi
index 0129372..323d5ba 100644
--- a/fdts/stm32mp13-pinctrl.dtsi
+++ b/fdts/stm32mp13-pinctrl.dtsi
@@ -6,7 +6,7 @@
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
&pinctrl {
- /omit-if-no-ref/ i2c4_pins_a: i2c4-0 {
+ i2c4_pins_a: i2c4-0 {
pins {
pinmux = <STM32_PINMUX('E', 15, AF6)>, /* I2C4_SCL */
<STM32_PINMUX('B', 9, AF6)>; /* I2C4_SDA */
@@ -16,7 +16,7 @@
};
};
- /omit-if-no-ref/ sdmmc1_b4_pins_a: sdmmc1-b4-0 {
+ sdmmc1_b4_pins_a: sdmmc1-b4-0 {
pins {
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
@@ -29,7 +29,7 @@
};
};
- /omit-if-no-ref/ sdmmc1_clk_pins_a: sdmmc1-clk-0 {
+ sdmmc1_clk_pins_a: sdmmc1-clk-0 {
pins {
pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
slew-rate = <1>;
@@ -38,7 +38,7 @@
};
};
- /omit-if-no-ref/ sdmmc2_b4_pins_a: sdmmc2-b4-0 {
+ sdmmc2_b4_pins_a: sdmmc2-b4-0 {
pins {
pinmux = <STM32_PINMUX('B', 14, AF10)>, /* SDMMC2_D0 */
<STM32_PINMUX('B', 15, AF10)>, /* SDMMC2_D1 */
@@ -51,7 +51,7 @@
};
};
- /omit-if-no-ref/ sdmmc2_clk_pins_a: sdmmc2-clk-0 {
+ sdmmc2_clk_pins_a: sdmmc2-clk-0 {
pins {
pinmux = <STM32_PINMUX('E', 3, AF10)>; /* SDMMC2_CK */
slew-rate = <1>;
@@ -60,7 +60,7 @@
};
};
- /omit-if-no-ref/ uart4_pins_a: uart4-0 {
+ uart4_pins_a: uart4-0 {
pins1 {
pinmux = <STM32_PINMUX('D', 6, AF8)>; /* UART4_TX */
bias-disable;
@@ -73,7 +73,7 @@
};
};
- /omit-if-no-ref/ usart1_pins_a: usart1-0 {
+ usart1_pins_a: usart1-0 {
pins1 {
pinmux = <STM32_PINMUX('C', 0, AF7)>, /* USART1_TX */
<STM32_PINMUX('C', 2, AF7)>; /* USART1_RTS */
@@ -88,7 +88,7 @@
};
};
- /omit-if-no-ref/ uart8_pins_a: uart8-0 {
+ uart8_pins_a: uart8-0 {
pins1 {
pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */
bias-disable;
diff --git a/fdts/stm32mp131.dtsi b/fdts/stm32mp131.dtsi
index 543afa5..2be39af 100644
--- a/fdts/stm32mp131.dtsi
+++ b/fdts/stm32mp131.dtsi
@@ -416,7 +416,7 @@
};
bsec: efuse@5c005000 {
- compatible = "st,stm32mp15-bsec";
+ compatible = "st,stm32mp13-bsec";
reg = <0x5c005000 0x400>;
#address-cells = <1>;
#size-cells = <1>;
diff --git a/fdts/stm32mp15-bl2.dtsi b/fdts/stm32mp15-bl2.dtsi
index 18a4ba9..53aeec5 100644
--- a/fdts/stm32mp15-bl2.dtsi
+++ b/fdts/stm32mp15-bl2.dtsi
@@ -3,8 +3,37 @@
* Copyright (c) 2020-2023, STMicroelectronics - All Rights Reserved
*/
+/omit-if-no-ref/ &fmc_pins_a;
+/omit-if-no-ref/ &i2c2_pins_a;
+/omit-if-no-ref/ &i2c4_pins_a;
/omit-if-no-ref/ &i2c6;
+/omit-if-no-ref/ &qspi_bk1_pins_a;
+/omit-if-no-ref/ &qspi_bk2_pins_a;
+/omit-if-no-ref/ &qspi_clk_pins_a;
+/omit-if-no-ref/ &sdmmc1_b4_pins_a;
+/omit-if-no-ref/ &sdmmc1_dir_pins_a;
+/omit-if-no-ref/ &sdmmc1_dir_pins_b;
+/omit-if-no-ref/ &sdmmc2_b4_pins_a;
+/omit-if-no-ref/ &sdmmc2_b4_pins_b;
+/omit-if-no-ref/ &sdmmc2_d47_pins_a;
+/omit-if-no-ref/ &sdmmc2_d47_pins_b;
+/omit-if-no-ref/ &sdmmc2_d47_pins_c;
+/omit-if-no-ref/ &sdmmc2_d47_pins_d;
/omit-if-no-ref/ &spi6;
+/omit-if-no-ref/ &uart4_pins_a;
+/omit-if-no-ref/ &uart4_pins_b;
+/omit-if-no-ref/ &uart7_pins_a;
+/omit-if-no-ref/ &uart7_pins_b;
+/omit-if-no-ref/ &uart7_pins_c;
+/omit-if-no-ref/ &uart8_pins_a;
+/omit-if-no-ref/ &usart2_pins_a;
+/omit-if-no-ref/ &usart2_pins_b;
+/omit-if-no-ref/ &usart2_pins_c;
+/omit-if-no-ref/ &usart3_pins_a;
+/omit-if-no-ref/ &usart3_pins_b;
+/omit-if-no-ref/ &usart3_pins_c;
+/omit-if-no-ref/ &usbotg_fs_dp_dm_pins_a;
+/omit-if-no-ref/ &usbotg_hs_pins_a;
/ {
#if !STM32MP_EMMC && !STM32MP_SDMMC
diff --git a/fdts/stm32mp15-bl32.dtsi b/fdts/stm32mp15-bl32.dtsi
index 6882224..7b63f1b 100644
--- a/fdts/stm32mp15-bl32.dtsi
+++ b/fdts/stm32mp15-bl32.dtsi
@@ -3,8 +3,37 @@
* Copyright (c) 2020-2023, STMicroelectronics - All Rights Reserved
*/
+/omit-if-no-ref/ &fmc_pins_a;
+/omit-if-no-ref/ &i2c2_pins_a;
+/omit-if-no-ref/ &i2c4_pins_a;
/omit-if-no-ref/ &i2c6;
+/omit-if-no-ref/ &qspi_bk1_pins_a;
+/omit-if-no-ref/ &qspi_bk2_pins_a;
+/omit-if-no-ref/ &qspi_clk_pins_a;
+/omit-if-no-ref/ &sdmmc1_b4_pins_a;
+/omit-if-no-ref/ &sdmmc1_dir_pins_a;
+/omit-if-no-ref/ &sdmmc1_dir_pins_b;
+/omit-if-no-ref/ &sdmmc2_b4_pins_a;
+/omit-if-no-ref/ &sdmmc2_b4_pins_b;
+/omit-if-no-ref/ &sdmmc2_d47_pins_a;
+/omit-if-no-ref/ &sdmmc2_d47_pins_b;
+/omit-if-no-ref/ &sdmmc2_d47_pins_c;
+/omit-if-no-ref/ &sdmmc2_d47_pins_d;
/omit-if-no-ref/ &spi6;
+/omit-if-no-ref/ &uart4_pins_a;
+/omit-if-no-ref/ &uart4_pins_b;
+/omit-if-no-ref/ &uart7_pins_a;
+/omit-if-no-ref/ &uart7_pins_b;
+/omit-if-no-ref/ &uart7_pins_c;
+/omit-if-no-ref/ &uart8_pins_a;
+/omit-if-no-ref/ &usart2_pins_a;
+/omit-if-no-ref/ &usart2_pins_b;
+/omit-if-no-ref/ &usart2_pins_c;
+/omit-if-no-ref/ &usart3_pins_a;
+/omit-if-no-ref/ &usart3_pins_b;
+/omit-if-no-ref/ &usart3_pins_c;
+/omit-if-no-ref/ &usbotg_fs_dp_dm_pins_a;
+/omit-if-no-ref/ &usbotg_hs_pins_a;
/ {
aliases {
diff --git a/fdts/stm32mp15-pinctrl.dtsi b/fdts/stm32mp15-pinctrl.dtsi
index 8dc00fe..a1be447 100644
--- a/fdts/stm32mp15-pinctrl.dtsi
+++ b/fdts/stm32mp15-pinctrl.dtsi
@@ -6,7 +6,7 @@
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
&pinctrl {
- /omit-if-no-ref/ fmc_pins_a: fmc-0 {
+ fmc_pins_a: fmc-0 {
pins1 {
pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
<STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */
@@ -31,7 +31,7 @@
};
};
- /omit-if-no-ref/ i2c2_pins_a: i2c2-0 {
+ i2c2_pins_a: i2c2-0 {
pins {
pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */
<STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
@@ -41,7 +41,7 @@
};
};
- /omit-if-no-ref/ qspi_clk_pins_a: qspi-clk-0 {
+ qspi_clk_pins_a: qspi-clk-0 {
pins {
pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
bias-disable;
@@ -50,7 +50,7 @@
};
};
- /omit-if-no-ref/ qspi_bk1_pins_a: qspi-bk1-0 {
+ qspi_bk1_pins_a: qspi-bk1-0 {
pins1 {
pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
<STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
@@ -68,7 +68,7 @@
};
};
- /omit-if-no-ref/ qspi_bk2_pins_a: qspi-bk2-0 {
+ qspi_bk2_pins_a: qspi-bk2-0 {
pins1 {
pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */
<STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */
@@ -86,7 +86,7 @@
};
};
- /omit-if-no-ref/ sdmmc1_b4_pins_a: sdmmc1-b4-0 {
+ sdmmc1_b4_pins_a: sdmmc1-b4-0 {
pins1 {
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
@@ -105,7 +105,7 @@
};
};
- /omit-if-no-ref/ sdmmc1_dir_pins_a: sdmmc1-dir-0 {
+ sdmmc1_dir_pins_a: sdmmc1-dir-0 {
pins1 {
pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
<STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
@@ -120,7 +120,7 @@
};
};
- /omit-if-no-ref/ sdmmc1_dir_pins_b: sdmmc1-dir-1 {
+ sdmmc1_dir_pins_b: sdmmc1-dir-1 {
pins1 {
pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
<STM32_PINMUX('E', 14, AF11)>, /* SDMMC1_D123DIR */
@@ -135,7 +135,7 @@
};
};
- /omit-if-no-ref/ sdmmc2_b4_pins_a: sdmmc2-b4-0 {
+ sdmmc2_b4_pins_a: sdmmc2-b4-0 {
pins1 {
pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
<STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
@@ -154,7 +154,7 @@
};
};
- /omit-if-no-ref/ sdmmc2_b4_pins_b: sdmmc2-b4-1 {
+ sdmmc2_b4_pins_b: sdmmc2-b4-1 {
pins1 {
pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
<STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
@@ -173,7 +173,7 @@
};
};
- /omit-if-no-ref/ sdmmc2_d47_pins_a: sdmmc2-d47-0 {
+ sdmmc2_d47_pins_a: sdmmc2-d47-0 {
pins {
pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
<STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
@@ -185,7 +185,7 @@
};
};
- /omit-if-no-ref/ sdmmc2_d47_pins_b: sdmmc2-d47-1 {
+ sdmmc2_d47_pins_b: sdmmc2-d47-1 {
pins {
pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
<STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
@@ -197,7 +197,7 @@
};
};
- /omit-if-no-ref/ sdmmc2_d47_pins_c: sdmmc2-d47-2 {
+ sdmmc2_d47_pins_c: sdmmc2-d47-2 {
pins {
pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
<STM32_PINMUX('A', 15, AF9)>, /* SDMMC2_D5 */
@@ -209,7 +209,7 @@
};
};
- /omit-if-no-ref/ sdmmc2_d47_pins_d: sdmmc2-d47-3 {
+ sdmmc2_d47_pins_d: sdmmc2-d47-3 {
pins {
pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
<STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
@@ -218,7 +218,7 @@
};
};
- /omit-if-no-ref/ uart4_pins_a: uart4-0 {
+ uart4_pins_a: uart4-0 {
pins1 {
pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
bias-disable;
@@ -231,7 +231,7 @@
};
};
- /omit-if-no-ref/ uart4_pins_b: uart4-1 {
+ uart4_pins_b: uart4-1 {
pins1 {
pinmux = <STM32_PINMUX('D', 1, AF8)>; /* UART4_TX */
bias-disable;
@@ -244,7 +244,7 @@
};
};
- /omit-if-no-ref/ uart7_pins_a: uart7-0 {
+ uart7_pins_a: uart7-0 {
pins1 {
pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART7_TX */
bias-disable;
@@ -259,7 +259,7 @@
};
};
- /omit-if-no-ref/ uart7_pins_b: uart7-1 {
+ uart7_pins_b: uart7-1 {
pins1 {
pinmux = <STM32_PINMUX('F', 7, AF7)>; /* UART7_TX */
bias-disable;
@@ -272,7 +272,7 @@
};
};
- /omit-if-no-ref/ uart7_pins_c: uart7-2 {
+ uart7_pins_c: uart7-2 {
pins1 {
pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART7_TX */
bias-disable;
@@ -285,7 +285,7 @@
};
};
- /omit-if-no-ref/ uart8_pins_a: uart8-0 {
+ uart8_pins_a: uart8-0 {
pins1 {
pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */
bias-disable;
@@ -298,7 +298,7 @@
};
};
- /omit-if-no-ref/ usart2_pins_a: usart2-0 {
+ usart2_pins_a: usart2-0 {
pins1 {
pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */
<STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */
@@ -313,7 +313,7 @@
};
};
- /omit-if-no-ref/ usart2_pins_b: usart2-1 {
+ usart2_pins_b: usart2-1 {
pins1 {
pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */
<STM32_PINMUX('A', 1, AF7)>; /* USART2_RTS */
@@ -328,7 +328,7 @@
};
};
- /omit-if-no-ref/ usart2_pins_c: usart2-2 {
+ usart2_pins_c: usart2-2 {
pins1 {
pinmux = <STM32_PINMUX('D', 5, AF7)>, /* USART2_TX */
<STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */
@@ -343,7 +343,7 @@
};
};
- /omit-if-no-ref/ usart3_pins_a: usart3-0 {
+ usart3_pins_a: usart3-0 {
pins1 {
pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */
bias-disable;
@@ -356,7 +356,7 @@
};
};
- /omit-if-no-ref/ usart3_pins_b: usart3-1 {
+ usart3_pins_b: usart3-1 {
pins1 {
pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
<STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
@@ -371,7 +371,7 @@
};
};
- /omit-if-no-ref/ usart3_pins_c: usart3-2 {
+ usart3_pins_c: usart3-2 {
pins1 {
pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
<STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
@@ -386,13 +386,13 @@
};
};
- /omit-if-no-ref/ usbotg_hs_pins_a: usbotg-hs-0 {
+ usbotg_hs_pins_a: usbotg-hs-0 {
pins {
pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */
};
};
- /omit-if-no-ref/ usbotg_fs_dp_dm_pins_a: usbotg-fs-dp-dm-0 {
+ usbotg_fs_dp_dm_pins_a: usbotg-fs-dp-dm-0 {
pins {
pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* OTG_FS_DM */
<STM32_PINMUX('A', 12, ANALOG)>; /* OTG_FS_DP */
@@ -401,7 +401,7 @@
};
&pinctrl_z {
- /omit-if-no-ref/ i2c4_pins_a: i2c4-0 {
+ i2c4_pins_a: i2c4-0 {
pins {
pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
<STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */
diff --git a/include/arch/aarch32/arch.h b/include/arch/aarch32/arch.h
index 227f058..c8a6334 100644
--- a/include/arch/aarch32/arch.h
+++ b/include/arch/aarch32/arch.h
@@ -119,6 +119,10 @@
#define ID_DFR1_MTPMU_MASK U(0xf)
#define ID_DFR1_MTPMU_SUPPORTED U(1)
+/* ID_MMFR3 definitions */
+#define ID_MMFR3_PAN_SHIFT U(16)
+#define ID_MMFR3_PAN_MASK U(0xf)
+
/* ID_MMFR4 definitions */
#define ID_MMFR4_CNP_SHIFT U(12)
#define ID_MMFR4_CNP_LENGTH U(4)
@@ -533,6 +537,7 @@
#define DCISW p15, 0, c7, c6, 2
#define CTR p15, 0, c0, c0, 1
#define CNTFRQ p15, 0, c14, c0, 0
+#define ID_MMFR3 p15, 0, c0, c1, 7
#define ID_MMFR4 p15, 0, c0, c2, 6
#define ID_DFR0 p15, 0, c0, c1, 2
#define ID_DFR1 p15, 0, c0, c3, 5
diff --git a/include/arch/aarch32/arch_features.h b/include/arch/aarch32/arch_features.h
index 62a512b..99e3fd0 100644
--- a/include/arch/aarch32/arch_features.h
+++ b/include/arch/aarch32/arch_features.h
@@ -110,10 +110,56 @@
return read_feat_dit_id_field() != 0U;
}
-static inline bool is_feat_spe_supported(void)
+static inline unsigned int read_feat_pan_id_field(void)
{
- /* FEAT_SPE is AArch64 only */
- return false;
+ return ISOLATE_FIELD(read_id_mmfr3(), ID_MMFR3_PAN);
+}
+
+static inline bool is_feat_pan_supported(void)
+{
+ if (ENABLE_FEAT_PAN == FEAT_STATE_DISABLED) {
+ return false;
+ }
+
+ if (ENABLE_FEAT_PAN == FEAT_STATE_ALWAYS) {
+ return true;
+ }
+
+ return read_feat_pan_id_field() != 0U;
}
+/*
+ * TWED, ECV, CSV2, RAS are only used by the AArch64 EL2 context switch
+ * code. In fact, EL2 context switching is only needed for AArch64 (since
+ * there is no secure AArch32 EL2), so just disable these features here.
+ */
+static inline bool is_feat_twed_supported(void) { return false; }
+static inline bool is_feat_ecv_supported(void) { return false; }
+static inline bool is_feat_ecv_v2_supported(void) { return false; }
+static inline bool is_feat_csv2_2_supported(void) { return false; }
+static inline bool is_feat_ras_supported(void) { return false; }
+
+/* The following features are supported in AArch64 only. */
+static inline bool is_feat_vhe_supported(void) { return false; }
+static inline bool is_feat_sel2_supported(void) { return false; }
+static inline bool is_feat_fgt_supported(void) { return false; }
+static inline bool is_feat_tcr2_supported(void) { return false; }
+static inline bool is_feat_spe_supported(void) { return false; }
+static inline bool is_feat_rng_supported(void) { return false; }
+static inline bool is_feat_gcs_supported(void) { return false; }
+static inline bool is_feat_mpam_supported(void) { return false; }
+static inline bool is_feat_hcx_supported(void) { return false; }
+static inline bool is_feat_sve_supported(void) { return false; }
+static inline bool is_feat_brbe_supported(void) { return false; }
+static inline bool is_feat_trbe_supported(void) { return false; }
+static inline bool is_feat_nv2_supported(void) { return false; }
+static inline bool is_feat_sme_supported(void) { return false; }
+static inline bool is_feat_sme2_supported(void) { return false; }
+static inline bool is_feat_s2poe_supported(void) { return false; }
+static inline bool is_feat_s1poe_supported(void) { return false; }
+static inline bool is_feat_sxpoe_supported(void) { return false; }
+static inline bool is_feat_s2pie_supported(void) { return false; }
+static inline bool is_feat_s1pie_supported(void) { return false; }
+static inline bool is_feat_sxpie_supported(void) { return false; }
+
#endif /* ARCH_FEATURES_H */
diff --git a/include/arch/aarch32/arch_helpers.h b/include/arch/aarch32/arch_helpers.h
index 95d056f..ca5a44b 100644
--- a/include/arch/aarch32/arch_helpers.h
+++ b/include/arch/aarch32/arch_helpers.h
@@ -8,6 +8,7 @@
#ifndef ARCH_HELPERS_H
#define ARCH_HELPERS_H
+#include <assert.h>
#include <cdefs.h>
#include <stdbool.h>
#include <stdint.h>
@@ -217,6 +218,7 @@
******************************************************************************/
DEFINE_COPROCR_READ_FUNC(mpidr, MPIDR)
DEFINE_COPROCR_READ_FUNC(midr, MIDR)
+DEFINE_COPROCR_READ_FUNC(id_mmfr3, ID_MMFR3)
DEFINE_COPROCR_READ_FUNC(id_mmfr4, ID_MMFR4)
DEFINE_COPROCR_READ_FUNC(id_dfr0, ID_DFR0)
DEFINE_COPROCR_READ_FUNC(id_pfr0, ID_PFR0)
@@ -351,6 +353,17 @@
*/
DEFINE_COPROCR_RW_FUNCS(clusterpwrdn, CLUSTERPWRDN)
+/*
+ * RNDR is AArch64 only, so just provide a placeholder here to make the
+ * linker happy.
+ */
+static inline u_register_t read_rndr(void)
+{
+ assert(1);
+
+ return 0;
+}
+
/* Previously defined accessor functions with incomplete register names */
#define dsb() dsbsy()
#define dmb() dmbsy()
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h
index 0038893..f3bccc4 100644
--- a/include/arch/aarch64/arch.h
+++ b/include/arch/aarch64/arch.h
@@ -300,6 +300,7 @@
#define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28)
#define ID_AA64MMFR0_EL1_TGRAN4_MASK ULL(0xf)
#define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED ULL(0x0)
+#define ID_AA64MMFR0_EL1_TGRAN4_52B_SUPPORTED ULL(0x1)
#define ID_AA64MMFR0_EL1_TGRAN4_NOT_SUPPORTED ULL(0xf)
#define ID_AA64MMFR0_EL1_TGRAN64_SHIFT U(24)
@@ -311,6 +312,7 @@
#define ID_AA64MMFR0_EL1_TGRAN16_MASK ULL(0xf)
#define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED ULL(0x1)
#define ID_AA64MMFR0_EL1_TGRAN16_NOT_SUPPORTED ULL(0x0)
+#define ID_AA64MMFR0_EL1_TGRAN16_52B_SUPPORTED ULL(0x2)
/* ID_AA64MMFR1_EL1 definitions */
#define ID_AA64MMFR1_EL1_TWED_SHIFT U(32)
diff --git a/include/arch/aarch64/arch_features.h b/include/arch/aarch64/arch_features.h
index d6f12f3..609a95b 100644
--- a/include/arch/aarch64/arch_features.h
+++ b/include/arch/aarch64/arch_features.h
@@ -678,4 +678,25 @@
return read_feat_sme_id_field() >= ID_AA64PFR1_EL1_SME2_SUPPORTED;
}
+/*******************************************************************************
+ * Function to get hardware granularity support
+ ******************************************************************************/
+
+static inline unsigned int read_id_aa64mmfr0_el0_tgran4_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64mmfr0_el1(), ID_AA64MMFR0_EL1_TGRAN4);
+}
+
+static inline unsigned int read_id_aa64mmfr0_el0_tgran16_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64mmfr0_el1(),
+ ID_AA64MMFR0_EL1_TGRAN16);
+}
+
+static inline unsigned int read_id_aa64mmfr0_el0_tgran64_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64mmfr0_el1(),
+ ID_AA64MMFR0_EL1_TGRAN64);
+}
+
#endif /* ARCH_FEATURES_H */
diff --git a/include/arch/aarch64/asm_macros.S b/include/arch/aarch64/asm_macros.S
index 7d1407a..6091f62 100644
--- a/include/arch/aarch64/asm_macros.S
+++ b/include/arch/aarch64/asm_macros.S
@@ -25,12 +25,50 @@
#endif
- .macro func_prologue
+ /*
+ * Create a stack frame at the start of an assembly function. Will also
+ * add all necessary call frame information (cfi) directives for a
+ * pretty stack trace. This is necessary as there is quite a bit of
+ * flexibility within a stack frame and the stack pointer can move
+ * around throughout the function. If the debugger isn't told where to
+ * find things, it gets lost, gives up and displays nothing. So inform
+ * the debugger of what's where. Anchor the Canonical Frame Address
+ * (CFA; the thing used to track what's where) to the frame pointer as
+ * that's not expected to change in the function body and no extra
+ * bookkeeping will be necessary, allowing free movement of the sp
+ *
+ * _frame_size: requested space for caller to use. Must be a mutliple
+ * of 16 for stack pointer alignment
+ */
+ .macro func_prologue _frame_size=0
+ .if \_frame_size & 0xf
+ .error "frame_size must have stack pointer alignment (multiple of 16)"
+ .endif
+
+ /* put frame record at top of frame */
stp x29, x30, [sp, #-0x10]!
mov x29,sp
+ .if \_frame_size
+ sub sp, sp, #\_frame_size
+ .endif
+
+ /* point CFA to start of frame record, i.e. x29 + 0x10 */
+ .cfi_def_cfa x29, 0x10
+ /* inform it about x29, x30 locations */
+ .cfi_offset x30, -0x8
+ .cfi_offset x29, -0x10
.endm
- .macro func_epilogue
+ /*
+ * Clear stack frame at the end of an assembly function.
+ *
+ * _frame_size: the value passed to func_prologue
+ */
+ .macro func_epilogue _frame_size=0
+ /* remove requested space */
+ .if \_frame_size
+ add sp, sp, #\_frame_size
+ .endif
ldp x29, x30, [sp], #0x10
.endm
diff --git a/include/drivers/spi_nand.h b/include/drivers/spi_nand.h
index 40e2063..869a0c6 100644
--- a/include/drivers/spi_nand.h
+++ b/include/drivers/spi_nand.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2019-2023, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -29,9 +29,13 @@
#define SPI_NAND_STATUS_BUSY BIT(0)
#define SPI_NAND_STATUS_ECC_UNCOR BIT(5)
+/* Flags for specific configuration */
+#define SPI_NAND_HAS_QE_BIT BIT(0)
+
struct spinand_device {
struct nand_device *nand_dev;
struct spi_mem_op spi_read_cache_op;
+ uint32_t flags;
uint8_t cfg_cache; /* Cached value of SPI NAND device register CFG */
};
diff --git a/include/lib/cpus/aarch64/cortex_a715.h b/include/lib/cpus/aarch64/cortex_a715.h
new file mode 100644
index 0000000..950d02f
--- /dev/null
+++ b/include/lib/cpus/aarch64/cortex_a715.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CORTEX_A715_H
+#define CORTEX_A715_H
+
+#define CORTEX_A715_MIDR U(0x410FD4D0)
+
+/* Cortex-A715 loop count for CVE-2022-23960 mitigation */
+#define CORTEX_A715_BHB_LOOP_COUNT U(38)
+
+/*******************************************************************************
+ * CPU Extended Control register specific definitions
+ ******************************************************************************/
+#define CORTEX_A715_CPUECTLR_EL1 S3_0_C15_C1_4
+
+/*******************************************************************************
+ * CPU Power Control register specific definitions
+ ******************************************************************************/
+#define CORTEX_A715_CPUPWRCTLR_EL1 S3_0_C15_C2_7
+#define CORTEX_A715_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
+
+#endif /* CORTEX_A715_H */
diff --git a/include/lib/cpus/aarch64/cortex_makalu.h b/include/lib/cpus/aarch64/cortex_makalu.h
deleted file mode 100644
index ee59657..0000000
--- a/include/lib/cpus/aarch64/cortex_makalu.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * Copyright (c) 2021-2022, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef CORTEX_MAKALU_H
-#define CORTEX_MAKALU_H
-
-#define CORTEX_MAKALU_MIDR U(0x410FD4D0)
-
-/* Cortex Makalu loop count for CVE-2022-23960 mitigation */
-#define CORTEX_MAKALU_BHB_LOOP_COUNT U(38)
-
-/*******************************************************************************
- * CPU Extended Control register specific definitions
- ******************************************************************************/
-#define CORTEX_MAKALU_CPUECTLR_EL1 S3_0_C15_C1_4
-
-/*******************************************************************************
- * CPU Power Control register specific definitions
- ******************************************************************************/
-#define CORTEX_MAKALU_CPUPWRCTLR_EL1 S3_0_C15_C2_7
-#define CORTEX_MAKALU_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
-
-#endif /* CORTEX_MAKALU_H */
diff --git a/include/lib/psa/measured_boot.h b/include/lib/psa/measured_boot.h
index 231da2c..af624a6 100644
--- a/include/lib/psa/measured_boot.h
+++ b/include/lib/psa/measured_boot.h
@@ -36,10 +36,10 @@
* signer_id Pointer to signer_id buffer.
* signer_id_size Size of the signer_id in bytes.
* version Pointer to version buffer.
- * version_size Size of the version string in bytes (with \0).
+ * version_size Size of the version string in bytes.
* measurement_algo Algorithm identifier used for measurement.
* sw_type Pointer to sw_type buffer.
- * sw_type_size Size of the sw_type string in bytes (with \0).
+ * sw_type_size Size of the sw_type string in bytes.
* measurement_value Pointer to measurement_value buffer.
* measurement_value_size Size of the measurement_value in bytes.
* lock_measurement Boolean flag requesting whether the measurement
diff --git a/include/lib/psci/psci.h b/include/lib/psci/psci.h
index 4d7e58e..01dc3cb 100644
--- a/include/lib/psci/psci.h
+++ b/include/lib/psci/psci.h
@@ -319,13 +319,13 @@
int (*pwr_domain_on)(u_register_t mpidr);
void (*pwr_domain_off)(const psci_power_state_t *target_state);
int (*pwr_domain_off_early)(const psci_power_state_t *target_state);
+#if PSCI_OS_INIT_MODE
+ int (*pwr_domain_validate_suspend)(
+ const psci_power_state_t *target_state);
+#endif
void (*pwr_domain_suspend_pwrdown_early)(
const psci_power_state_t *target_state);
-#if PSCI_OS_INIT_MODE
- int (*pwr_domain_suspend)(const psci_power_state_t *target_state);
-#else
void (*pwr_domain_suspend)(const psci_power_state_t *target_state);
-#endif
void (*pwr_domain_on_finish)(const psci_power_state_t *target_state);
void (*pwr_domain_on_finish_late)(
const psci_power_state_t *target_state);
diff --git a/include/services/el3_spmc_logical_sp.h b/include/services/el3_spmc_logical_sp.h
index 5ce33ed..dccd362 100644
--- a/include/services/el3_spmc_logical_sp.h
+++ b/include/services/el3_spmc_logical_sp.h
@@ -49,8 +49,7 @@
* Function & variable prototypes.
******************************************************************************/
int el3_sp_desc_validate(void);
-uintptr_t handle_el3_sp(uint32_t smc_fid, void *cookie, void *handle,
- unsigned int flags);
+
IMPORT_SYM(uintptr_t, __EL3_LP_DESCS_START__, EL3_LP_DESCS_START);
IMPORT_SYM(uintptr_t, __EL3_LP_DESCS_END__, EL3_LP_DESCS_END);
diff --git a/include/tools_share/cca_oid.h b/include/tools_share/cca_oid.h
index e586b8c..2ca12c9 100644
--- a/include/tools_share/cca_oid.h
+++ b/include/tools_share/cca_oid.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2022-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -25,4 +25,7 @@
/* Realm Monitor Manager (RMM) Hash */
#define RMM_HASH_OID "1.3.6.1.4.1.4128.2100.1106"
+/* CCAFirmwareNVCounter - Non-volatile counter extension */
+#define CCA_FW_NVCOUNTER_OID "1.3.6.1.4.1.4128.2100.3"
+
#endif /* CCA_OID_H */
diff --git a/lib/cpus/aarch64/cortex_a715.S b/lib/cpus/aarch64/cortex_a715.S
index 7603210..12d969f 100644
--- a/lib/cpus/aarch64/cortex_a715.S
+++ b/lib/cpus/aarch64/cortex_a715.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,23 +7,23 @@
#include <arch.h>
#include <asm_macros.S>
#include <common/bl_common.h>
-#include <cortex_makalu.h>
+#include <cortex_a715.h>
#include <cpu_macros.S>
#include <plat_macros.S>
#include "wa_cve_2022_23960_bhb_vector.S"
/* Hardware handled coherency */
#if HW_ASSISTED_COHERENCY == 0
-#error "Cortex Makalu must be compiled with HW_ASSISTED_COHERENCY enabled"
+#error "Cortex-A715 must be compiled with HW_ASSISTED_COHERENCY enabled"
#endif
/* 64-bit only core */
#if CTX_INCLUDE_AARCH32_REGS == 1
-#error "Cortex Makalu supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
+#error "Cortex-A715 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif
#if WORKAROUND_CVE_2022_23960
- wa_cve_2022_23960_bhb_vector_table CORTEX_MAKALU_BHB_LOOP_COUNT, cortex_makalu
+ wa_cve_2022_23960_bhb_vector_table CORTEX_A715_BHB_LOOP_COUNT, cortex_a715
#endif /* WORKAROUND_CVE_2022_23960 */
func check_errata_cve_2022_23960
@@ -35,44 +35,44 @@
ret
endfunc check_errata_cve_2022_23960
-func cortex_makalu_reset_func
+func cortex_a715_reset_func
/* Disable speculative loads */
msr SSBS, xzr
#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
/*
- * The Cortex Makalu generic vectors are overridden to apply errata
+ * The Cortex-A715 generic vectors are overridden to apply errata
* mitigation on exception entry from lower ELs.
*/
- adr x0, wa_cve_vbar_cortex_makalu
+ adr x0, wa_cve_vbar_cortex_a715
msr vbar_el3, x0
#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
isb
ret
-endfunc cortex_makalu_reset_func
+endfunc cortex_a715_reset_func
/* ----------------------------------------------------
* HW will do the cache maintenance while powering down
* ----------------------------------------------------
*/
-func cortex_makalu_core_pwr_dwn
+func cortex_a715_core_pwr_dwn
/* ---------------------------------------------------
* Enable CPU power down bit in power control register
* ---------------------------------------------------
*/
- mrs x0, CORTEX_MAKALU_CPUPWRCTLR_EL1
- orr x0, x0, #CORTEX_MAKALU_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
- msr CORTEX_MAKALU_CPUPWRCTLR_EL1, x0
+ mrs x0, CORTEX_A715_CPUPWRCTLR_EL1
+ orr x0, x0, #CORTEX_A715_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+ msr CORTEX_A715_CPUPWRCTLR_EL1, x0
isb
ret
-endfunc cortex_makalu_core_pwr_dwn
+endfunc cortex_a715_core_pwr_dwn
#if REPORT_ERRATA
/*
- * Errata printing function for Cortex Makalu. Must follow AAPCS.
+ * Errata printing function for Cortex-A715. Must follow AAPCS.
*/
-func cortex_makalu_errata_report
+func cortex_a715_errata_report
stp x8, x30, [sp, #-16]!
bl cpu_get_rev_var
@@ -82,15 +82,15 @@
* Report all errata. The revision-variant information is passed to
* checking functions of each errata.
*/
- report_errata WORKAROUND_CVE_2022_23960, cortex_makalu, cve_2022_23960
+ report_errata WORKAROUND_CVE_2022_23960, cortex_a715, cve_2022_23960
ldp x8, x30, [sp], #16
ret
-endfunc cortex_makalu_errata_report
+endfunc cortex_a715_errata_report
#endif
/* ---------------------------------------------
- * This function provides Cortex Makalu-specific
+ * This function provides Cortex-A715 specific
* register information for crash reporting.
* It needs to return with x6 pointing to
* a list of register names in ascii and
@@ -98,16 +98,16 @@
* reported.
* ---------------------------------------------
*/
-.section .rodata.cortex_makalu_regs, "aS"
-cortex_makalu_regs: /* The ascii list of register names to be reported */
+.section .rodata.cortex_a715_regs, "aS"
+cortex_a715_regs: /* The ascii list of register names to be reported */
.asciz "cpuectlr_el1", ""
-func cortex_makalu_cpu_reg_dump
- adr x6, cortex_makalu_regs
- mrs x8, CORTEX_MAKALU_CPUECTLR_EL1
+func cortex_a715_cpu_reg_dump
+ adr x6, cortex_a715_regs
+ mrs x8, CORTEX_A715_CPUECTLR_EL1
ret
-endfunc cortex_makalu_cpu_reg_dump
+endfunc cortex_a715_cpu_reg_dump
-declare_cpu_ops cortex_makalu, CORTEX_MAKALU_MIDR, \
- cortex_makalu_reset_func, \
- cortex_makalu_core_pwr_dwn
+declare_cpu_ops cortex_a715, CORTEX_A715_MIDR, \
+ cortex_a715_reset_func, \
+ cortex_a715_core_pwr_dwn
diff --git a/lib/extensions/pauth/pauth_helpers.S b/lib/extensions/pauth/pauth_helpers.S
index d483c7df..fb5fa97 100644
--- a/lib/extensions/pauth/pauth_helpers.S
+++ b/lib/extensions/pauth/pauth_helpers.S
@@ -45,7 +45,7 @@
endfunc pauth_init_enable_el1
/* -------------------------------------------------------------
- * Disable pointer authentication in EL3
+ * Disable pointer authentication in EL1
* -------------------------------------------------------------
*/
func pauth_disable_el1
diff --git a/lib/fconf/fconf_dyn_cfg_getter.c b/lib/fconf/fconf_dyn_cfg_getter.c
index 13081b0..58956d6 100644
--- a/lib/fconf/fconf_dyn_cfg_getter.c
+++ b/lib/fconf/fconf_dyn_cfg_getter.c
@@ -83,7 +83,7 @@
/*
* In case of BL1, fw_config dtb information is already
- * populated in global dtb_infos array by 'set_fw_config_info'
+ * populated in global dtb_infos array by 'set_config_info'
* function, Below check is present to avoid re-population of
* fw_config information.
*
diff --git a/lib/psa/measured_boot.c b/lib/psa/measured_boot.c
index 10c43f1..c359e9f 100644
--- a/lib/psa/measured_boot.c
+++ b/lib/psa/measured_boot.c
@@ -80,16 +80,23 @@
.lock_measurement = lock_measurement,
.measurement_algo = measurement_algo,
.sw_type = {0},
- /* Removing \0 */
- .sw_type_size = (sw_type_size > 0) ? (sw_type_size - 1) : 0,
+ .sw_type_size = sw_type_size,
};
+ if (version_size > VERSION_MAX_SIZE) {
+ return PSA_ERROR_INVALID_ARGUMENT;
+ }
+
+
+ if (version_size > 0 && version[version_size - 1] == '\0') {
+ version_size--;
+ }
+
psa_invec in_vec[] = {
{.base = &extend_iov,
.len = sizeof(struct measured_boot_extend_iovec_t)},
{.base = signer_id, .len = signer_id_size},
- {.base = version,
- .len = (version_size > 0) ? (version_size - 1) : 0},
+ {.base = version, .len = version_size },
{.base = measurement_value, .len = measurement_value_size}
};
@@ -97,6 +104,9 @@
if (extend_iov.sw_type_size > SW_TYPE_MAX_SIZE) {
return PSA_ERROR_INVALID_ARGUMENT;
}
+ if (sw_type_size > 0 && sw_type[sw_type_size - 1] == '\0') {
+ extend_iov.sw_type_size--;
+ }
memcpy(extend_iov.sw_type, sw_type, extend_iov.sw_type_size);
}
diff --git a/lib/psci/psci_common.c b/lib/psci/psci_common.c
index c893476..bfc09cc 100644
--- a/lib/psci/psci_common.c
+++ b/lib/psci/psci_common.c
@@ -451,8 +451,8 @@
* enter. This function will be called after coordination of requested power
* states has been done for each power level.
*****************************************************************************/
-static void psci_set_target_local_pwr_states(unsigned int end_pwrlvl,
- const psci_power_state_t *target_state)
+void psci_set_target_local_pwr_states(unsigned int end_pwrlvl,
+ const psci_power_state_t *target_state)
{
unsigned int parent_idx, lvl;
const plat_local_state_t *pd_state = target_state->pwr_domain_state;
@@ -474,7 +474,6 @@
}
}
-
/*******************************************************************************
* PSCI helper function to get the parent nodes corresponding to a cpu_index.
******************************************************************************/
@@ -595,9 +594,6 @@
state_info->pwr_domain_state[lvl] = PSCI_LOCAL_STATE_RUN;
}
-
- /* Update the target state in the power domain nodes */
- psci_set_target_local_pwr_states(end_pwrlvl, state_info);
}
#if PSCI_OS_INIT_MODE
@@ -684,9 +680,6 @@
return rc;
}
- /* Update the target state in the power domain nodes */
- psci_set_target_local_pwr_states(end_pwrlvl, state_info);
-
return rc;
}
#endif
diff --git a/lib/psci/psci_off.c b/lib/psci/psci_off.c
index 9f36ac7..f83753f 100644
--- a/lib/psci/psci_off.c
+++ b/lib/psci/psci_off.c
@@ -104,6 +104,9 @@
*/
psci_do_state_coordination(end_pwrlvl, &state_info);
+ /* Update the target state in the power domain nodes */
+ psci_set_target_local_pwr_states(end_pwrlvl, &state_info);
+
#if ENABLE_PSCI_STAT
/* Update the last cpu for each level till end_pwrlvl */
psci_stats_update_pwr_down(end_pwrlvl, &state_info);
diff --git a/lib/psci/psci_private.h b/lib/psci/psci_private.h
index b9987fe..04f93bd 100644
--- a/lib/psci/psci_private.h
+++ b/lib/psci/psci_private.h
@@ -298,6 +298,8 @@
#endif
void psci_get_target_local_pwr_states(unsigned int end_pwrlvl,
psci_power_state_t *target_state);
+void psci_set_target_local_pwr_states(unsigned int end_pwrlvl,
+ const psci_power_state_t *target_state);
int psci_validate_entry_point(entry_point_info_t *ep,
uintptr_t entrypoint, u_register_t context_id);
void psci_get_parent_pwr_domain_nodes(unsigned int cpu_idx,
diff --git a/lib/psci/psci_suspend.c b/lib/psci/psci_suspend.c
index 861b875..d93e60d 100644
--- a/lib/psci/psci_suspend.c
+++ b/lib/psci/psci_suspend.c
@@ -219,6 +219,19 @@
}
#endif
+#if PSCI_OS_INIT_MODE
+ if (psci_plat_pm_ops->pwr_domain_validate_suspend != NULL) {
+ rc = psci_plat_pm_ops->pwr_domain_validate_suspend(state_info);
+ if (rc != PSCI_E_SUCCESS) {
+ skip_wfi = true;
+ goto exit;
+ }
+ }
+#endif
+
+ /* Update the target state in the power domain nodes */
+ psci_set_target_local_pwr_states(end_pwrlvl, state_info);
+
#if ENABLE_PSCI_STAT
/* Update the last cpu for each level till end_pwrlvl */
psci_stats_update_pwr_down(end_pwrlvl, state_info);
@@ -234,15 +247,7 @@
* program the power controller etc.
*/
-#if PSCI_OS_INIT_MODE
- rc = psci_plat_pm_ops->pwr_domain_suspend(state_info);
- if (rc != PSCI_E_SUCCESS) {
- skip_wfi = true;
- goto exit;
- }
-#else
psci_plat_pm_ops->pwr_domain_suspend(state_info);
-#endif
#if ENABLE_PSCI_STAT
plat_psci_stat_accounting_start(state_info);
diff --git a/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c b/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c
index 719110a..c847a9e 100644
--- a/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c
+++ b/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -22,22 +22,23 @@
*/
bool xlat_arch_is_granule_size_supported(size_t size)
{
- u_register_t id_aa64mmfr0_el1 = read_id_aa64mmfr0_el1();
+ unsigned int tgranx;
if (size == PAGE_SIZE_4KB) {
- return ((id_aa64mmfr0_el1 >> ID_AA64MMFR0_EL1_TGRAN4_SHIFT) &
- ID_AA64MMFR0_EL1_TGRAN4_MASK) ==
- ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED;
+ tgranx = read_id_aa64mmfr0_el0_tgran4_field();
+ /* MSB of TGRAN4 field will be '1' for unsupported feature */
+ return ((tgranx >= ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED) &&
+ (tgranx < 8U));
} else if (size == PAGE_SIZE_16KB) {
- return ((id_aa64mmfr0_el1 >> ID_AA64MMFR0_EL1_TGRAN16_SHIFT) &
- ID_AA64MMFR0_EL1_TGRAN16_MASK) ==
- ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED;
+ tgranx = read_id_aa64mmfr0_el0_tgran16_field();
+ return (tgranx >= ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED);
} else if (size == PAGE_SIZE_64KB) {
- return ((id_aa64mmfr0_el1 >> ID_AA64MMFR0_EL1_TGRAN64_SHIFT) &
- ID_AA64MMFR0_EL1_TGRAN64_MASK) ==
- ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED;
+ tgranx = read_id_aa64mmfr0_el0_tgran64_field();
+ /* MSB of TGRAN64 field will be '1' for unsupported feature */
+ return ((tgranx >= ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED) &&
+ (tgranx < 8U));
} else {
- return 0;
+ return false;
}
}
diff --git a/make_helpers/tbbr/tbbr_tools.mk b/make_helpers/tbbr/tbbr_tools.mk
index 8605bae..a3351eb 100644
--- a/make_helpers/tbbr/tbbr_tools.mk
+++ b/make_helpers/tbbr/tbbr_tools.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -43,10 +43,14 @@
# Default non-volatile counter values (overridable by the platform)
TFW_NVCTR_VAL ?= 0
NTFW_NVCTR_VAL ?= 0
+CCAFW_NVCTR_VAL ?= 0
# Pass the non-volatile counters to the cert_create tool
$(eval $(call CERT_ADD_CMD_OPT,${TFW_NVCTR_VAL},--tfw-nvctr))
$(eval $(call CERT_ADD_CMD_OPT,${NTFW_NVCTR_VAL},--ntfw-nvctr))
+ifeq (${COT},cca)
+$(eval $(call CERT_ADD_CMD_OPT,${CCAFW_NVCTR_VAL},--ccafw-nvctr))
+endif
# Add Trusted Key certificate to the fiptool and cert_create command line options
ifneq (${COT},cca)
diff --git a/plat/arm/board/common/board_common.mk b/plat/arm/board/common/board_common.mk
index d73c2e3..777784d 100644
--- a/plat/arm/board/common/board_common.mk
+++ b/plat/arm/board/common/board_common.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -67,11 +67,16 @@
# ARM development platforms
TFW_NVCTR_VAL ?= 31
NTFW_NVCTR_VAL ?= 223
+# The CCA Non-Volatile Counter only exists on some Arm development platforms.
+# On others, we mock it by aliasing it to the Trusted Firmware Non-Volatile counter,
+# hence we set both counters to the same default value.
+CCAFW_NVCTR_VAL ?= 31
else
# Certificate NV-Counters when CryptoCell is integrated. For development
# platforms we set the counter to first valid value.
TFW_NVCTR_VAL ?= 0
NTFW_NVCTR_VAL ?= 0
+CCAFW_NVCTR_VAL ?= 0
endif
BL1_SOURCES += plat/arm/board/common/board_arm_trusted_boot.c \
${ARM_ROTPK_S}
diff --git a/plat/arm/board/fvp/fvp_pm.c b/plat/arm/board/fvp/fvp_pm.c
index a3289b6..b8c97f8 100644
--- a/plat/arm/board/fvp/fvp_pm.c
+++ b/plat/arm/board/fvp/fvp_pm.c
@@ -228,11 +228,7 @@
* FVP handler called when a power domain is about to be suspended. The
* target_state encodes the power state that each level should transition to.
******************************************************************************/
-#if PSCI_OS_INIT_MODE
-static int fvp_pwr_domain_suspend(const psci_power_state_t *target_state)
-#else
static void fvp_pwr_domain_suspend(const psci_power_state_t *target_state)
-#endif
{
unsigned long mpidr;
@@ -242,11 +238,7 @@
*/
if (target_state->pwr_domain_state[ARM_PWR_LVL0] ==
ARM_LOCAL_STATE_RET)
-#if PSCI_OS_INIT_MODE
- return PSCI_E_SUCCESS;
-#else
return;
-#endif
assert(target_state->pwr_domain_state[ARM_PWR_LVL0] ==
ARM_LOCAL_STATE_OFF);
@@ -279,11 +271,7 @@
/* Program the power controller to power off this cpu. */
fvp_pwrc_write_ppoffr(read_mpidr_el1());
-#if PSCI_OS_INIT_MODE
- return PSCI_E_SUCCESS;
-#else
return;
-#endif
}
/*******************************************************************************
diff --git a/plat/arm/board/fvp/fvp_trusted_boot.c b/plat/arm/board/fvp/fvp_trusted_boot.c
index 1ea37f7..4c3201e 100644
--- a/plat/arm/board/fvp/fvp_trusted_boot.c
+++ b/plat/arm/board/fvp/fvp_trusted_boot.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -14,7 +14,7 @@
#include <plat/arm/common/fconf_nv_cntr_getter.h>
#include <plat/common/platform.h>
#include <platform_def.h>
-#include <tools_share/tbbr_oid.h>
+#include <tools_share/cca_oid.h>
/*
* Return the ROTPK hash in the following ASN.1 structure in DER format:
@@ -36,6 +36,33 @@
}
/*
+ * Return the non-volatile counter address stored in the platform. The cookie
+ * will contain the OID of the counter in the certificate.
+ *
+ * Return: 0 = success, Otherwise = error
+ */
+static int plat_get_nv_ctr_addr(void *cookie, uintptr_t *nv_ctr_addr)
+{
+ const char *oid = (const char *)cookie;
+
+ if (strcmp(oid, TRUSTED_FW_NVCOUNTER_OID) == 0) {
+ *nv_ctr_addr = FCONF_GET_PROPERTY(cot, nv_cntr_addr,
+ TRUSTED_NV_CTR_ID);
+ } else if (strcmp(oid, NON_TRUSTED_FW_NVCOUNTER_OID) == 0) {
+ *nv_ctr_addr = FCONF_GET_PROPERTY(cot, nv_cntr_addr,
+ NON_TRUSTED_NV_CTR_ID);
+ } else if (strcmp(oid, CCA_FW_NVCOUNTER_OID) == 0) {
+ /* FVP does not support the CCA NV Counter so use the Trusted NV */
+ *nv_ctr_addr = FCONF_GET_PROPERTY(cot, nv_cntr_addr,
+ TRUSTED_NV_CTR_ID);
+ } else {
+ return 1;
+ }
+
+ return 0;
+}
+
+/*
* Store a new non-volatile counter value.
*
* On some FVP versions, the non-volatile counters are read-only so this
@@ -45,20 +72,14 @@
*/
int plat_set_nv_ctr(void *cookie, unsigned int nv_ctr)
{
- const char *oid;
uintptr_t nv_ctr_addr;
+ int rc;
assert(cookie != NULL);
- oid = (const char *)cookie;
- if (strcmp(oid, TRUSTED_FW_NVCOUNTER_OID) == 0) {
- nv_ctr_addr = FCONF_GET_PROPERTY(cot, nv_cntr_addr,
- TRUSTED_NV_CTR_ID);
- } else if (strcmp(oid, NON_TRUSTED_FW_NVCOUNTER_OID) == 0) {
- nv_ctr_addr = FCONF_GET_PROPERTY(cot, nv_cntr_addr,
- NON_TRUSTED_NV_CTR_ID);
- } else {
- return 1;
+ rc = plat_get_nv_ctr_addr(cookie, &nv_ctr_addr);
+ if (rc != 0) {
+ return rc;
}
mmio_write_32(nv_ctr_addr, nv_ctr);
@@ -69,3 +90,27 @@
*/
return (mmio_read_32(nv_ctr_addr) == nv_ctr) ? 0 : 1;
}
+
+/*
+ * Return the non-volatile counter value stored in the platform. The cookie
+ * will contain the OID of the counter in the certificate.
+ *
+ * Return: 0 = success, Otherwise = error
+ */
+int plat_get_nv_ctr(void *cookie, unsigned int *nv_ctr)
+{
+ uintptr_t nv_ctr_addr;
+ int rc;
+
+ assert(cookie != NULL);
+ assert(nv_ctr != NULL);
+
+ rc = plat_get_nv_ctr_addr(cookie, &nv_ctr_addr);
+ if (rc != 0) {
+ return rc;
+ }
+
+ *nv_ctr = *((unsigned int *)nv_ctr_addr);
+
+ return 0;
+}
diff --git a/plat/arm/board/fvp_r/fvp_r_bl1_arch_setup.c b/plat/arm/board/fvp_r/fvp_r_bl1_arch_setup.c
index ae6af6c..820470b 100644
--- a/plat/arm/board/fvp_r/fvp_r_bl1_arch_setup.c
+++ b/plat/arm/board/fvp_r/fvp_r_bl1_arch_setup.c
@@ -17,19 +17,3 @@
{
/* v8-R64 does not include SCRs. */
}
-
-/*******************************************************************************
- * Set the Secure EL1 required architectural state
- ******************************************************************************/
-void bl1_arch_next_el_setup(void)
-{
- u_register_t next_sctlr;
-
- /* Use the same endianness than the current BL */
- next_sctlr = (read_sctlr_el2() & SCTLR_EE_BIT);
-
- /* Set SCTLR Secure EL1 */
- next_sctlr |= SCTLR_EL1_RES1;
-
- write_sctlr_el1(next_sctlr);
-}
diff --git a/plat/mediatek/drivers/apusys/apusys.c b/plat/mediatek/drivers/apusys/apusys.c
index c82b3a7..dfe1dcf 100644
--- a/plat/mediatek/drivers/apusys/apusys.c
+++ b/plat/mediatek/drivers/apusys/apusys.c
@@ -9,7 +9,10 @@
/* Vendor header */
#include "apusys.h"
+#include "apusys_devapc.h"
#include "apusys_power.h"
+#include "apusys_rv.h"
+#include "apusys_security_ctrl_plat.h"
#include <lib/mtk_init/mtk_init.h>
#include <mtk_sip_svc.h>
@@ -32,6 +35,39 @@
case MTK_APUSYS_KERNEL_OP_APUSYS_PWR_TOP_OFF:
ret = apusys_kernel_apusys_pwr_top_off();
break;
+ case MTK_APUSYS_KERNEL_OP_APUSYS_RV_SETUP_REVISER:
+ ret = apusys_kernel_apusys_rv_setup_reviser();
+ break;
+ case MTK_APUSYS_KERNEL_OP_APUSYS_RV_RESET_MP:
+ ret = apusys_kernel_apusys_rv_reset_mp();
+ break;
+ case MTK_APUSYS_KERNEL_OP_APUSYS_RV_SETUP_BOOT:
+ ret = apusys_kernel_apusys_rv_setup_boot();
+ break;
+ case MTK_APUSYS_KERNEL_OP_APUSYS_RV_START_MP:
+ ret = apusys_kernel_apusys_rv_start_mp();
+ break;
+ case MTK_APUSYS_KERNEL_OP_APUSYS_RV_STOP_MP:
+ ret = apusys_kernel_apusys_rv_stop_mp();
+ break;
+ case MTK_APUSYS_KERNEL_OP_DEVAPC_INIT_RCX:
+ ret = apusys_devapc_rcx_init();
+ break;
+ case MTK_APUSYS_KERNEL_OP_APUSYS_RV_SETUP_SEC_MEM:
+ ret = apusys_kernel_apusys_rv_setup_sec_mem();
+ break;
+ case MTK_APUSYS_KERNEL_OP_APUSYS_RV_DISABLE_WDT_ISR:
+ ret = apusys_kernel_apusys_rv_disable_wdt_isr();
+ break;
+ case MTK_APUSYS_KERNEL_OP_APUSYS_RV_CLEAR_WDT_ISR:
+ ret = apusys_kernel_apusys_rv_clear_wdt_isr();
+ break;
+ case MTK_APUSYS_KERNEL_OP_APUSYS_RV_CG_GATING:
+ ret = apusys_kernel_apusys_rv_cg_gating();
+ break;
+ case MTK_APUSYS_KERNEL_OP_APUSYS_RV_CG_UNGATING:
+ ret = apusys_kernel_apusys_rv_cg_ungating();
+ break;
default:
ERROR(MODULE_TAG "%s unknown request_ops = %x\n", MODULE_TAG, request_ops);
break;
@@ -43,7 +79,17 @@
int apusys_init(void)
{
- apusys_power_init();
+ if (apusys_power_init() != 0) {
+ return -1;
+ }
+
+ if (apusys_devapc_ao_init() != 0) {
+ return -1;
+ }
+
+ apusys_security_ctrl_init();
+ apusys_rv_mbox_mpu_init();
+
return 0;
}
MTK_PLAT_SETUP_1_INIT(apusys_init);
diff --git a/plat/mediatek/drivers/apusys/apusys.h b/plat/mediatek/drivers/apusys/apusys.h
index 1592cff..ed4e195 100644
--- a/plat/mediatek/drivers/apusys/apusys.h
+++ b/plat/mediatek/drivers/apusys/apusys.h
@@ -10,8 +10,19 @@
#define MODULE_TAG "[APUSYS]"
enum MTK_APUSYS_KERNEL_OP {
- MTK_APUSYS_KERNEL_OP_APUSYS_PWR_TOP_ON, /* 0 */
- MTK_APUSYS_KERNEL_OP_APUSYS_PWR_TOP_OFF,/* 1 */
+ MTK_APUSYS_KERNEL_OP_APUSYS_PWR_TOP_ON, /* 0 */
+ MTK_APUSYS_KERNEL_OP_APUSYS_PWR_TOP_OFF, /* 1 */
+ MTK_APUSYS_KERNEL_OP_APUSYS_RV_SETUP_REVISER, /* 2 */
+ MTK_APUSYS_KERNEL_OP_APUSYS_RV_RESET_MP, /* 3 */
+ MTK_APUSYS_KERNEL_OP_APUSYS_RV_SETUP_BOOT, /* 4 */
+ MTK_APUSYS_KERNEL_OP_APUSYS_RV_START_MP, /* 5 */
+ MTK_APUSYS_KERNEL_OP_APUSYS_RV_STOP_MP, /* 6 */
+ MTK_APUSYS_KERNEL_OP_DEVAPC_INIT_RCX, /* 7 */
+ MTK_APUSYS_KERNEL_OP_APUSYS_RV_SETUP_SEC_MEM, /* 8 */
+ MTK_APUSYS_KERNEL_OP_APUSYS_RV_DISABLE_WDT_ISR, /* 9 */
+ MTK_APUSYS_KERNEL_OP_APUSYS_RV_CLEAR_WDT_ISR, /* 10 */
+ MTK_APUSYS_KERNEL_OP_APUSYS_RV_CG_GATING, /* 11 */
+ MTK_APUSYS_KERNEL_OP_APUSYS_RV_CG_UNGATING, /* 12 */
MTK_APUSYS_KERNEL_OP_NUM,
};
diff --git a/plat/mediatek/drivers/apusys/apusys_rv/2.0/apusys_rv.c b/plat/mediatek/drivers/apusys/apusys_rv/2.0/apusys_rv.c
new file mode 100644
index 0000000..c1b3de0
--- /dev/null
+++ b/plat/mediatek/drivers/apusys/apusys_rv/2.0/apusys_rv.c
@@ -0,0 +1,257 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* TF-A system header */
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <lib/mmio.h>
+#include <lib/spinlock.h>
+
+/* Vendor header */
+#include "apusys.h"
+#include "apusys_rv.h"
+#include "apusys_rv_mbox_mpu.h"
+#include "emi_mpu.h"
+
+static spinlock_t apusys_rv_lock;
+
+void apusys_rv_mbox_mpu_init(void)
+{
+ int i;
+
+ for (i = 0; i < APU_MBOX_NUM; i++) {
+ mmio_write_32(APU_MBOX_FUNC_CFG(i),
+ (MBOX_CTRL_LOCK |
+ (mbox_mpu_setting_tab[i].no_mpu << MBOX_NO_MPU_SHIFT)));
+ mmio_write_32(APU_MBOX_DOMAIN_CFG(i),
+ (MBOX_CTRL_LOCK |
+ (mbox_mpu_setting_tab[i].rx_ns << MBOX_RX_NS_SHIFT) |
+ (mbox_mpu_setting_tab[i].rx_domain << MBOX_RX_DOMAIN_SHIFT) |
+ (mbox_mpu_setting_tab[i].tx_ns << MBOX_TX_NS_SHIFT) |
+ (mbox_mpu_setting_tab[i].tx_domain << MBOX_TX_DOMAIN_SHIFT)));
+ }
+}
+
+int apusys_kernel_apusys_rv_setup_reviser(void)
+{
+ static bool apusys_rv_setup_reviser_called;
+
+ spin_lock(&apusys_rv_lock);
+
+ if (apusys_rv_setup_reviser_called) {
+ WARN(MODULE_TAG "%s: already initialized\n", __func__);
+ spin_unlock(&apusys_rv_lock);
+ return -1;
+ }
+
+ apusys_rv_setup_reviser_called = true;
+
+ mmio_write_32(USERFW_CTXT, CFG_4GB_SEL_EN | CFG_4GB_SEL);
+ mmio_write_32(SECUREFW_CTXT, CFG_4GB_SEL_EN | CFG_4GB_SEL);
+
+ mmio_write_32(UP_IOMMU_CTRL, MMU_CTRL_LOCK | MMU_CTRL | MMU_EN);
+
+ mmio_write_32(UP_NORMAL_DOMAIN_NS,
+ (UP_NORMAL_DOMAIN << UP_DOMAIN_SHIFT) | (UP_NORMAL_NS << UP_NS_SHIFT));
+ mmio_write_32(UP_PRI_DOMAIN_NS,
+ (UP_PRI_DOMAIN << UP_DOMAIN_SHIFT) | (UP_PRI_NS << UP_NS_SHIFT));
+
+ mmio_write_32(UP_CORE0_VABASE0,
+ VLD | PARTIAL_ENABLE | (THREAD_NUM_PRI << THREAD_NUM_SHIFT));
+ mmio_write_32(UP_CORE0_MVABASE0, VASIZE_1MB | (APU_SEC_FW_IOVA >> MVA_34BIT_SHIFT));
+
+ mmio_write_32(UP_CORE0_VABASE1,
+ VLD | PARTIAL_ENABLE | (THREAD_NUM_NORMAL << THREAD_NUM_SHIFT));
+ mmio_write_32(UP_CORE0_MVABASE1, VASIZE_1MB | (APU_SEC_FW_IOVA >> MVA_34BIT_SHIFT));
+
+ spin_unlock(&apusys_rv_lock);
+
+ return 0;
+}
+
+int apusys_kernel_apusys_rv_reset_mp(void)
+{
+ static bool apusys_rv_reset_mp_called;
+
+ spin_lock(&apusys_rv_lock);
+
+ if (apusys_rv_reset_mp_called) {
+ WARN(MODULE_TAG "%s: already initialized\n", __func__);
+ spin_unlock(&apusys_rv_lock);
+ return -1;
+ }
+
+ apusys_rv_reset_mp_called = true;
+
+ mmio_write_32(MD32_SYS_CTRL, MD32_SYS_CTRL_RST);
+
+ udelay(RESET_DEALY_US);
+
+ mmio_write_32(MD32_SYS_CTRL, MD32_G2B_CG_EN | MD32_DBG_EN | MD32_DM_AWUSER_IOMMU_EN |
+ MD32_DM_ARUSER_IOMMU_EN | MD32_PM_AWUSER_IOMMU_EN | MD32_PM_ARUSER_IOMMU_EN |
+ MD32_SOFT_RSTN);
+
+ mmio_write_32(MD32_CLK_CTRL, MD32_CLK_EN);
+ mmio_write_32(UP_WAKE_HOST_MASK0, WDT_IRQ_EN);
+ mmio_write_32(UP_WAKE_HOST_MASK1, MBOX0_IRQ_EN | MBOX1_IRQ_EN | MBOX2_IRQ_EN);
+
+ spin_unlock(&apusys_rv_lock);
+
+ return 0;
+}
+
+int apusys_kernel_apusys_rv_setup_boot(void)
+{
+ static bool apusys_rv_setup_boot_called;
+
+ spin_lock(&apusys_rv_lock);
+
+ if (apusys_rv_setup_boot_called) {
+ WARN(MODULE_TAG "%s: already initialized\n", __func__);
+ spin_unlock(&apusys_rv_lock);
+ return -1;
+ }
+
+ apusys_rv_setup_boot_called = true;
+
+ mmio_write_32(MD32_BOOT_CTRL, APU_SEC_FW_IOVA);
+
+ mmio_write_32(MD32_PRE_DEFINE, (PREDEFINE_CACHE_TCM << PREDEF_1G_OFS) |
+ (PREDEFINE_CACHE << PREDEF_2G_OFS) | (PREDEFINE_CACHE << PREDEF_3G_OFS) |
+ (PREDEFINE_CACHE << PREDEF_4G_OFS));
+
+ spin_unlock(&apusys_rv_lock);
+ return 0;
+}
+
+int apusys_kernel_apusys_rv_start_mp(void)
+{
+ static bool apusys_rv_start_mp_called;
+
+ spin_lock(&apusys_rv_lock);
+
+ if (apusys_rv_start_mp_called) {
+ WARN(MODULE_TAG "%s: already initialized\n", __func__);
+ spin_unlock(&apusys_rv_lock);
+ return -1;
+ }
+
+ apusys_rv_start_mp_called = true;
+
+ mmio_write_32(MD32_RUNSTALL, MD32_RUN);
+
+ spin_unlock(&apusys_rv_lock);
+
+ return 0;
+}
+
+static bool watch_dog_is_timeout(void)
+{
+ if (mmio_read_32(WDT_INT) != WDT_INT_W1C) {
+ ERROR(MODULE_TAG "%s: WDT does not timeout\n", __func__);
+ return false;
+ }
+ return true;
+}
+
+int apusys_kernel_apusys_rv_stop_mp(void)
+{
+ static bool apusys_rv_stop_mp_called;
+
+ spin_lock(&apusys_rv_lock);
+
+ if (apusys_rv_stop_mp_called) {
+ WARN(MODULE_TAG "%s: already initialized\n", __func__);
+ spin_unlock(&apusys_rv_lock);
+ return -1;
+ }
+
+ if (watch_dog_is_timeout() == false) {
+ spin_unlock(&apusys_rv_lock);
+ return -1;
+ }
+
+ apusys_rv_stop_mp_called = true;
+
+ mmio_write_32(MD32_RUNSTALL, MD32_STALL);
+
+ spin_unlock(&apusys_rv_lock);
+
+ return 0;
+}
+
+int apusys_kernel_apusys_rv_setup_sec_mem(void)
+{
+ static bool apusys_rv_setup_sec_mem_called;
+ int ret;
+
+ spin_lock(&apusys_rv_lock);
+
+ if (apusys_rv_setup_sec_mem_called) {
+ WARN(MODULE_TAG "%s: already initialized\n", __func__);
+ spin_unlock(&apusys_rv_lock);
+ return -1;
+ }
+
+ apusys_rv_setup_sec_mem_called = true;
+
+ ret = set_apu_emi_mpu_region();
+ if (ret != 0) {
+ ERROR(MODULE_TAG "%s: set emimpu protection failed\n", __func__);
+ }
+
+ spin_unlock(&apusys_rv_lock);
+ return ret;
+}
+
+int apusys_kernel_apusys_rv_disable_wdt_isr(void)
+{
+ spin_lock(&apusys_rv_lock);
+ mmio_clrbits_32(WDT_CTRL0, WDT_EN);
+ spin_unlock(&apusys_rv_lock);
+
+ return 0;
+}
+
+int apusys_kernel_apusys_rv_clear_wdt_isr(void)
+{
+ spin_lock(&apusys_rv_lock);
+ mmio_clrbits_32(UP_INT_EN2, DBG_APB_EN);
+ mmio_write_32(WDT_INT, WDT_INT_W1C);
+ spin_unlock(&apusys_rv_lock);
+
+ return 0;
+}
+
+int apusys_kernel_apusys_rv_cg_gating(void)
+{
+ spin_lock(&apusys_rv_lock);
+
+ if (watch_dog_is_timeout() == false) {
+ spin_unlock(&apusys_rv_lock);
+ return -1;
+ }
+
+ mmio_write_32(MD32_CLK_CTRL, MD32_CLK_DIS);
+ spin_unlock(&apusys_rv_lock);
+
+ return 0;
+}
+
+int apusys_kernel_apusys_rv_cg_ungating(void)
+{
+ spin_lock(&apusys_rv_lock);
+
+ if (watch_dog_is_timeout() == false) {
+ spin_unlock(&apusys_rv_lock);
+ return -1;
+ }
+
+ mmio_write_32(MD32_CLK_CTRL, MD32_CLK_EN);
+ spin_unlock(&apusys_rv_lock);
+
+ return 0;
+}
diff --git a/plat/mediatek/drivers/apusys/apusys_rv/2.0/apusys_rv.h b/plat/mediatek/drivers/apusys/apusys_rv/2.0/apusys_rv.h
new file mode 100644
index 0000000..8a43890
--- /dev/null
+++ b/plat/mediatek/drivers/apusys/apusys_rv/2.0/apusys_rv.h
@@ -0,0 +1,120 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef APUSYS_RV_H
+#define APUSYS_RV_H
+
+#include <platform_def.h>
+
+#define APU_SEC_FW_IOVA (0x200000UL)
+
+/* APU_SCTRL_REVISER */
+#define UP_NORMAL_DOMAIN_NS (APU_REVISER + 0x0000)
+#define UP_PRI_DOMAIN_NS (APU_REVISER + 0x0004)
+#define UP_IOMMU_CTRL (APU_REVISER + 0x0008)
+#define UP_CORE0_VABASE0 (APU_REVISER + 0x000c)
+#define UP_CORE0_MVABASE0 (APU_REVISER + 0x0010)
+#define UP_CORE0_VABASE1 (APU_REVISER + 0x0014)
+#define UP_CORE0_MVABASE1 (APU_REVISER + 0x0018)
+#define UP_CORE0_VABASE2 (APU_REVISER + 0x001c)
+#define UP_CORE0_MVABASE2 (APU_REVISER + 0x0020)
+#define UP_CORE0_VABASE3 (APU_REVISER + 0x0024)
+#define UP_CORE0_MVABASE3 (APU_REVISER + 0x0028)
+#define USERFW_CTXT (APU_REVISER + 0x1000)
+#define SECUREFW_CTXT (APU_REVISER + 0x1004)
+#define UP_NORMAL_DOMAIN (7)
+#define UP_NORMAL_NS (1)
+#define UP_PRI_DOMAIN (5)
+#define UP_PRI_NS (1)
+#define UP_DOMAIN_SHIFT (0)
+#define UP_NS_SHIFT (4)
+#define MMU_EN BIT(0)
+#define MMU_CTRL BIT(1)
+#define MMU_CTRL_LOCK BIT(2)
+#define VLD BIT(0)
+#define PARTIAL_ENABLE BIT(1)
+#define THREAD_NUM_PRI (1)
+#define THREAD_NUM_NORMAL (0)
+#define THREAD_NUM_SHIFT (2)
+#define VASIZE_1MB BIT(0)
+#define CFG_4GB_SEL_EN BIT(2)
+#define CFG_4GB_SEL (0)
+#define MVA_34BIT_SHIFT (2)
+
+/* APU_MD32_SYSCTRL */
+#define MD32_SYS_CTRL (APU_MD32_SYSCTRL + 0x0000)
+#define UP_INT_EN2 (APU_MD32_SYSCTRL + 0x000c)
+#define MD32_CLK_CTRL (APU_MD32_SYSCTRL + 0x00b8)
+#define UP_WAKE_HOST_MASK0 (APU_MD32_SYSCTRL + 0x00bc)
+#define UP_WAKE_HOST_MASK1 (APU_MD32_SYSCTRL + 0x00c0)
+#define MD32_SYS_CTRL_RST (0)
+#define MD32_G2B_CG_EN BIT(11)
+#define MD32_DBG_EN BIT(10)
+#define MD32_DM_AWUSER_IOMMU_EN BIT(9)
+#define MD32_DM_ARUSER_IOMMU_EN BIT(7)
+#define MD32_PM_AWUSER_IOMMU_EN BIT(5)
+#define MD32_PM_ARUSER_IOMMU_EN BIT(3)
+#define MD32_SOFT_RSTN BIT(0)
+#define MD32_CLK_EN (1)
+#define MD32_CLK_DIS (0)
+#define WDT_IRQ_EN BIT(0)
+#define MBOX0_IRQ_EN BIT(21)
+#define MBOX1_IRQ_EN BIT(22)
+#define MBOX2_IRQ_EN BIT(23)
+#define RESET_DEALY_US (10)
+#define DBG_APB_EN BIT(31)
+
+/* APU_AO_CTRL */
+#define MD32_PRE_DEFINE (APU_AO_CTRL + 0x0000)
+#define MD32_BOOT_CTRL (APU_AO_CTRL + 0x0004)
+#define MD32_RUNSTALL (APU_AO_CTRL + 0x0008)
+#define PREDEFINE_NON_CACHE (0)
+#define PREDEFINE_TCM (1)
+#define PREDEFINE_CACHE (2)
+#define PREDEFINE_CACHE_TCM (3)
+#define PREDEF_1G_OFS (0)
+#define PREDEF_2G_OFS (2)
+#define PREDEF_3G_OFS (4)
+#define PREDEF_4G_OFS (6)
+#define MD32_RUN (0)
+#define MD32_STALL (1)
+
+/* APU_MD32_WDT */
+#define WDT_INT (APU_MD32_WDT + 0x0)
+#define WDT_CTRL0 (APU_MD32_WDT + 0x4)
+#define WDT_INT_W1C (1)
+#define WDT_EN BIT(31)
+
+/* APU MBOX */
+#define MBOX_FUNC_CFG (0xb0)
+#define MBOX_DOMAIN_CFG (0xe0)
+#define MBOX_CTRL_LOCK BIT(0)
+#define MBOX_NO_MPU_SHIFT (16)
+#define MBOX_RX_NS_SHIFT (16)
+#define MBOX_RX_DOMAIN_SHIFT (17)
+#define MBOX_TX_NS_SHIFT (24)
+#define MBOX_TX_DOMAIN_SHIFT (25)
+#define MBOX_SIZE (0x100)
+#define MBOX_NUM (8)
+
+#define APU_MBOX(i) (((i) < MBOX_NUM) ? (APU_MBOX0 + MBOX_SIZE * (i)) : \
+ (APU_MBOX1 + MBOX_SIZE * ((i) - MBOX_NUM)))
+#define APU_MBOX_FUNC_CFG(i) (APU_MBOX(i) + MBOX_FUNC_CFG)
+#define APU_MBOX_DOMAIN_CFG(i) (APU_MBOX(i) + MBOX_DOMAIN_CFG)
+
+void apusys_rv_mbox_mpu_init(void);
+int apusys_kernel_apusys_rv_setup_reviser(void);
+int apusys_kernel_apusys_rv_reset_mp(void);
+int apusys_kernel_apusys_rv_setup_boot(void);
+int apusys_kernel_apusys_rv_start_mp(void);
+int apusys_kernel_apusys_rv_stop_mp(void);
+int apusys_kernel_apusys_rv_setup_sec_mem(void);
+int apusys_kernel_apusys_rv_disable_wdt_isr(void);
+int apusys_kernel_apusys_rv_clear_wdt_isr(void);
+int apusys_kernel_apusys_rv_cg_gating(void);
+int apusys_kernel_apusys_rv_cg_ungating(void);
+
+#endif /* APUSYS_RV_H */
diff --git a/plat/mediatek/drivers/apusys/apusys_rv/2.0/apusys_rv_mbox_mpu.h b/plat/mediatek/drivers/apusys/apusys_rv/2.0/apusys_rv_mbox_mpu.h
new file mode 100644
index 0000000..0ee4878
--- /dev/null
+++ b/plat/mediatek/drivers/apusys/apusys_rv/2.0/apusys_rv_mbox_mpu.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef APUSYS_RV_MBOX_MPU_H
+#define APUSYS_RV_MBOX_MPU_H
+
+#define MPU_EN (0)
+#define MPU_DIS (1)
+#define MBOX0_TX_DOMAIN (0)
+#define MBOX0_TX_NS (1)
+#define MBOX4_RX_DOMAIN (0)
+#define MBOX4_RX_NS (0)
+#define MBOX5_TX_DOMAIN (3)
+#define MBOX5_TX_NS (0)
+#define MBOXN_RX_DOMAIN (5)
+#define MBOXN_RX_NS (1)
+#define MBOXN_TX_DOMAIN (0)
+#define MBOXN_TX_NS (0)
+
+struct mbox_mpu_setting {
+ uint32_t no_mpu;
+ uint32_t rx_ns;
+ uint32_t rx_domain;
+ uint32_t tx_ns;
+ uint32_t tx_domain;
+};
+
+static const struct mbox_mpu_setting mbox_mpu_setting_tab[] = {
+ { MPU_EN, MBOXN_RX_NS, MBOXN_RX_DOMAIN, MBOX0_TX_NS, MBOX0_TX_DOMAIN },
+ { MPU_EN, MBOXN_RX_NS, MBOXN_RX_DOMAIN, MBOXN_TX_NS, MBOXN_TX_DOMAIN },
+ { MPU_EN, MBOXN_RX_NS, MBOXN_RX_DOMAIN, MBOXN_TX_NS, MBOXN_TX_DOMAIN },
+ { MPU_EN, MBOXN_RX_NS, MBOXN_RX_DOMAIN, MBOXN_TX_NS, MBOXN_TX_DOMAIN },
+ { MPU_DIS, MBOX4_RX_NS, MBOX4_RX_DOMAIN, MBOXN_TX_NS, MBOXN_TX_DOMAIN },
+ { MPU_EN, MBOXN_RX_NS, MBOXN_RX_DOMAIN, MBOX5_TX_NS, MBOX5_TX_DOMAIN },
+ { MPU_EN, MBOXN_RX_NS, MBOXN_RX_DOMAIN, MBOXN_TX_NS, MBOXN_TX_DOMAIN },
+ { MPU_EN, MBOXN_RX_NS, MBOXN_RX_DOMAIN, MBOXN_TX_NS, MBOXN_TX_DOMAIN },
+ { MPU_EN, MBOXN_RX_NS, MBOXN_RX_DOMAIN, MBOXN_TX_NS, MBOXN_TX_DOMAIN },
+ { MPU_EN, MBOXN_RX_NS, MBOXN_RX_DOMAIN, MBOXN_TX_NS, MBOXN_TX_DOMAIN },
+};
+
+#define APU_MBOX_NUM ARRAY_SIZE(mbox_mpu_setting_tab)
+
+#endif /* APUSYS_RV_MBOX_MPU_H */
diff --git a/plat/mediatek/drivers/apusys/apusys_rv/2.0/rules.mk b/plat/mediatek/drivers/apusys/apusys_rv/2.0/rules.mk
new file mode 100644
index 0000000..031264d
--- /dev/null
+++ b/plat/mediatek/drivers/apusys/apusys_rv/2.0/rules.mk
@@ -0,0 +1,15 @@
+#
+# Copyright (c) 2023, MediaTek Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+LOCAL_DIR := $(call GET_LOCAL_DIR)
+
+MODULE := apusys_rv_${MTK_SOC}
+
+PLAT_INCLUDES += -I${MTK_PLAT}/drivers/apusys/${MTK_SOC}
+
+LOCAL_SRCS-y := ${LOCAL_DIR}/apusys_rv.c
+
+$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))
diff --git a/plat/mediatek/drivers/apusys/devapc/apusys_dapc_v1.c b/plat/mediatek/drivers/apusys/devapc/apusys_dapc_v1.c
new file mode 100644
index 0000000..4bd4272
--- /dev/null
+++ b/plat/mediatek/drivers/apusys/devapc/apusys_dapc_v1.c
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* TF-A system header */
+#include <common/debug.h>
+#include <lib/utils_def.h>
+
+/* Vendor header */
+#include "apusys.h"
+#include "apusys_dapc_v1.h"
+#include <platform_def.h>
+
+enum apusys_apc_err_status set_apusys_dapc_v1(const struct apc_dom_16 *dapc,
+ uint32_t size, dapc_cfg_func cfg)
+{
+ enum apusys_apc_err_status ret = APUSYS_APC_OK;
+ uint32_t i;
+
+ if ((dapc == NULL) || (cfg == NULL)) {
+ return APUSYS_APC_ERR_GENERIC;
+ }
+
+ for (i = 0; i < size; i++) {
+ ret += cfg(i, DOMAIN_0, dapc[i].d0_permission);
+ ret += cfg(i, DOMAIN_1, dapc[i].d1_permission);
+ ret += cfg(i, DOMAIN_2, dapc[i].d2_permission);
+ ret += cfg(i, DOMAIN_3, dapc[i].d3_permission);
+ ret += cfg(i, DOMAIN_4, dapc[i].d4_permission);
+ ret += cfg(i, DOMAIN_5, dapc[i].d5_permission);
+ ret += cfg(i, DOMAIN_6, dapc[i].d6_permission);
+ ret += cfg(i, DOMAIN_7, dapc[i].d7_permission);
+ ret += cfg(i, DOMAIN_8, dapc[i].d8_permission);
+ ret += cfg(i, DOMAIN_9, dapc[i].d9_permission);
+ ret += cfg(i, DOMAIN_10, dapc[i].d10_permission);
+ ret += cfg(i, DOMAIN_11, dapc[i].d11_permission);
+ ret += cfg(i, DOMAIN_12, dapc[i].d12_permission);
+ ret += cfg(i, DOMAIN_13, dapc[i].d13_permission);
+ ret += cfg(i, DOMAIN_14, dapc[i].d14_permission);
+ ret += cfg(i, DOMAIN_15, dapc[i].d15_permission);
+ }
+
+ if (ret != APUSYS_APC_OK) {
+ ret = APUSYS_APC_ERR_GENERIC;
+ }
+
+ return ret;
+}
+
+void dump_apusys_dapc_v1(const char *name, uintptr_t base, uint32_t reg_num, uint32_t dom_num)
+{
+ uint32_t d, i;
+
+ if ((name == NULL) || (base == 0)) {
+ return;
+ }
+
+ for (d = 0; d < dom_num; d++) {
+ for (i = 0; i <= reg_num; i++) {
+ INFO(MODULE_TAG "[%s] D%d_APC_%d: 0x%x\n", name, d, i,
+ mmio_read_32(base + d * DEVAPC_DOM_SIZE + i * DEVAPC_REG_SIZE));
+ }
+ }
+
+ INFO(MODULE_TAG "[%s] APC_CON: 0x%x\n", name, mmio_read_32(APUSYS_DAPC_CON(base)));
+}
diff --git a/plat/mediatek/drivers/apusys/devapc/apusys_dapc_v1.h b/plat/mediatek/drivers/apusys/devapc/apusys_dapc_v1.h
new file mode 100644
index 0000000..2f5d47b
--- /dev/null
+++ b/plat/mediatek/drivers/apusys/devapc/apusys_dapc_v1.h
@@ -0,0 +1,173 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef APUSYS_DAPC_V1_H
+#define APUSYS_DAPC_V1_H
+
+#include <lib/mmio.h>
+
+/******************************************************************************
+ * STRUCTURE DEFINITION
+ ******************************************************************************/
+enum apusys_apc_err_status {
+ APUSYS_APC_OK = 0x0,
+ APUSYS_APC_ERR_GENERIC = 0x1,
+};
+
+enum apusys_apc_perm_type {
+ NO_PROTECTION = 0,
+ SEC_RW_ONLY = 1,
+ SEC_RW_NS_R = 2,
+ FORBIDDEN = 3,
+ PERM_NUM = 4,
+};
+
+enum apusys_apc_domain_id {
+ DOMAIN_0 = 0,
+ DOMAIN_1 = 1,
+ DOMAIN_2 = 2,
+ DOMAIN_3 = 3,
+ DOMAIN_4 = 4,
+ DOMAIN_5 = 5,
+ DOMAIN_6 = 6,
+ DOMAIN_7 = 7,
+ DOMAIN_8 = 8,
+ DOMAIN_9 = 9,
+ DOMAIN_10 = 10,
+ DOMAIN_11 = 11,
+ DOMAIN_12 = 12,
+ DOMAIN_13 = 13,
+ DOMAIN_14 = 14,
+ DOMAIN_15 = 15,
+};
+
+struct apc_dom_16 {
+ unsigned char d0_permission;
+ unsigned char d1_permission;
+ unsigned char d2_permission;
+ unsigned char d3_permission;
+ unsigned char d4_permission;
+ unsigned char d5_permission;
+ unsigned char d6_permission;
+ unsigned char d7_permission;
+ unsigned char d8_permission;
+ unsigned char d9_permission;
+ unsigned char d10_permission;
+ unsigned char d11_permission;
+ unsigned char d12_permission;
+ unsigned char d13_permission;
+ unsigned char d14_permission;
+ unsigned char d15_permission;
+};
+
+#define APUSYS_APC_AO_ATTR(DEV_NAME, \
+ PERM_ATTR0, PERM_ATTR1, PERM_ATTR2, PERM_ATTR3, \
+ PERM_ATTR4, PERM_ATTR5, PERM_ATTR6, PERM_ATTR7, \
+ PERM_ATTR8, PERM_ATTR9, PERM_ATTR10, PERM_ATTR11, \
+ PERM_ATTR12, PERM_ATTR13, PERM_ATTR14, PERM_ATTR15) \
+ {(unsigned char)PERM_ATTR0, (unsigned char)PERM_ATTR1, \
+ (unsigned char)PERM_ATTR2, (unsigned char)PERM_ATTR3, \
+ (unsigned char)PERM_ATTR4, (unsigned char)PERM_ATTR5, \
+ (unsigned char)PERM_ATTR6, (unsigned char)PERM_ATTR7, \
+ (unsigned char)PERM_ATTR8, (unsigned char)PERM_ATTR9, \
+ (unsigned char)PERM_ATTR10, (unsigned char)PERM_ATTR11, \
+ (unsigned char)PERM_ATTR12, (unsigned char)PERM_ATTR13, \
+ (unsigned char)PERM_ATTR14, (unsigned char)PERM_ATTR15}
+
+typedef enum apusys_apc_err_status (*dapc_cfg_func)(uint32_t slave,
+ enum apusys_apc_domain_id domain_id,
+ enum apusys_apc_perm_type perm);
+
+/* Register */
+#define DEVAPC_DOM_SIZE (0x40)
+#define DEVAPC_REG_SIZE (4)
+
+/* APUSYS APC offsets */
+#define APUSYS_DAPC_CON_VIO_MASK (0x80000000)
+#define APUSYS_DAPC_CON(base) ((base) + 0x00f00)
+
+/******************************************************************************
+ * DAPC Common Function
+ ******************************************************************************/
+#define SET_APUSYS_DAPC_V1(dapc, cfg) \
+ set_apusys_dapc_v1(dapc, ARRAY_SIZE(dapc), cfg)
+
+#define DUMP_APUSYS_DAPC_V1(apc) \
+ dump_apusys_dapc_v1(#apc, apc##_BASE, \
+ (apc##_SLAVE_NUM / apc##_SLAVE_NUM_IN_1_DOM), apc##_DOM_NUM)
+
+enum apusys_apc_err_status set_apusys_dapc_v1(const struct apc_dom_16 *dapc,
+ uint32_t size, dapc_cfg_func cfg);
+
+void dump_apusys_dapc_v1(const char *name, uintptr_t base, uint32_t reg_num, uint32_t dom_num);
+
+/******************************************************************************
+ * DAPC Permission Policy
+ ******************************************************************************/
+#define SLAVE_FORBID_EXCEPT_D0_SEC_RW(domain) \
+ APUSYS_APC_AO_ATTR(domain, \
+ SEC_RW_ONLY, FORBIDDEN, FORBIDDEN, FORBIDDEN, \
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN)
+
+#define SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT(domain) \
+ APUSYS_APC_AO_ATTR(domain, \
+ SEC_RW_ONLY, FORBIDDEN, FORBIDDEN, FORBIDDEN, \
+ FORBIDDEN, NO_PROTECTION, FORBIDDEN, FORBIDDEN, \
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN)
+
+#define SLAVE_FORBID_EXCEPT_D5_NO_PROTECT(domain) \
+ APUSYS_APC_AO_ATTR(domain, \
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \
+ FORBIDDEN, NO_PROTECTION, FORBIDDEN, FORBIDDEN, \
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN)
+
+#define SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_NO_PROTECT(domain) \
+ APUSYS_APC_AO_ATTR(domain, \
+ SEC_RW_NS_R, FORBIDDEN, FORBIDDEN, FORBIDDEN, \
+ FORBIDDEN, NO_PROTECTION, FORBIDDEN, FORBIDDEN, \
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN)
+
+#define SLAVE_FORBID_EXCEPT_D7_NO_PROTECT(domain) \
+ APUSYS_APC_AO_ATTR(domain, \
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, NO_PROTECTION, \
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN)
+
+#define SLAVE_FORBID_EXCEPT_D5_D7_NO_PROTECT(domain) \
+ APUSYS_APC_AO_ATTR(domain, \
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \
+ FORBIDDEN, NO_PROTECTION, FORBIDDEN, NO_PROTECTION, \
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN)
+
+#define SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT(domain) \
+ APUSYS_APC_AO_ATTR(domain, \
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, \
+ FORBIDDEN, NO_PROTECTION, FORBIDDEN, FORBIDDEN, \
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN)
+
+#define SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT_D3_SEC_RW(domain) \
+ APUSYS_APC_AO_ATTR(domain, \
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, SEC_RW_ONLY, \
+ FORBIDDEN, NO_PROTECTION, FORBIDDEN, FORBIDDEN, \
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN)
+
+#define SLAVE_FORBID_EXCEPT_D0_D3_SEC_RW_D5_NO_PROTECT(domain) \
+ APUSYS_APC_AO_ATTR(domain, \
+ SEC_RW_ONLY, FORBIDDEN, FORBIDDEN, SEC_RW_ONLY, \
+ FORBIDDEN, NO_PROTECTION, FORBIDDEN, FORBIDDEN, \
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN)
+
+#endif /* APUSYS_DAPC_V1_H */
diff --git a/plat/mediatek/drivers/apusys/devapc/rules.mk b/plat/mediatek/drivers/apusys/devapc/rules.mk
new file mode 100644
index 0000000..6153b31
--- /dev/null
+++ b/plat/mediatek/drivers/apusys/devapc/rules.mk
@@ -0,0 +1,13 @@
+#
+# Copyright (c) 2023, MediaTek Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+LOCAL_DIR := $(call GET_LOCAL_DIR)
+
+MODULE := apusys_devapc
+
+LOCAL_SRCS-y := ${LOCAL_DIR}/apusys_dapc_v1.c
+
+$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))
diff --git a/plat/mediatek/drivers/apusys/mt8188/apusys_devapc.c b/plat/mediatek/drivers/apusys/mt8188/apusys_devapc.c
new file mode 100644
index 0000000..da5242a
--- /dev/null
+++ b/plat/mediatek/drivers/apusys/mt8188/apusys_devapc.c
@@ -0,0 +1,307 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* TF-A system header */
+#include <common/debug.h>
+#include <lib/utils_def.h>
+
+/* Vendor header */
+#include "apusys.h"
+#include "apusys_devapc.h"
+#include "apusys_devapc_def.h"
+#include <platform_def.h>
+
+#define DUMP_APUSYS_DAPC (0)
+
+static const struct apc_dom_16 APU_NOC_DAPC_RCX[] = {
+ /* ctrl index = 0 */
+ SLAVE_MD32_SRAM("slv16-0"),
+ SLAVE_MD32_SRAM("slv16-1"),
+ SLAVE_MD32_SRAM("slv16-2"),
+ SLAVE_MD32_SRAM("slv16-3"),
+ SLAVE_MD32_SRAM("slv16-4"),
+};
+
+static const struct apc_dom_16 APU_CTRL_DAPC_AO[] = {
+ /* ctrl index = 0 */
+ SLAVE_VCORE("apu_ao_ctl_o-0"),
+ SLAVE_RPC("apu_ao_ctl_o-2"),
+ SLAVE_PCU("apu_ao_ctl_o-3"),
+ SLAVE_AO_CTRL("apu_ao_ctl_o-4"),
+ SLAVE_PLL("apu_ao_ctl_o-5"),
+ SLAVE_ACC("apu_ao_ctl_o-6"),
+ SLAVE_SEC("apu_ao_ctl_o-7"),
+ SLAVE_ARE0("apu_ao_ctl_o-8"),
+ SLAVE_ARE1("apu_ao_ctl_o-9"),
+ SLAVE_ARE2("apu_ao_ctl_o-10"),
+
+ /* ctrl index = 10 */
+ SLAVE_UNKNOWN("apu_ao_ctl_o-11"),
+ SLAVE_AO_BCRM("apu_ao_ctl_o-12"),
+ SLAVE_AO_DAPC_WRAP("apu_ao_ctl_o-13"),
+ SLAVE_AO_DAPC_CON("apu_ao_ctl_o-14"),
+ SLAVE_RCX_ACX_BULK("apu_ao_ctl_o-15"),
+ SLAVE_UNKNOWN("apu_ao_ctl_o-16"),
+ SLAVE_UNKNOWN("apu_ao_ctl_o-17"),
+ SLAVE_APU_BULK("apu_ao_ctl_o-18"),
+ SLAVE_ACX0_BCRM("apu_ao_ctl_o-20"),
+ SLAVE_RPCTOP_LITE_ACX0("apu_ao_ctl_o-21"),
+
+ /* ctrl index = 20 */
+ SLAVE_ACX1_BCRM("apu_ao_ctl_o-22"),
+ SLAVE_RPCTOP_LITE_ACX1("apu_ao_ctl_o-23"),
+ SLAVE_RCX_TO_ACX0_0("apu_rcx2acx0_o-0"),
+ SLAVE_RCX_TO_ACX0_1("apu_rcx2acx0_o-1"),
+ SLAVE_SAE_TO_ACX0_0("apu_sae2acx0_o-0"),
+ SLAVE_SAE_TO_ACX0_1("apu_sae2acx0_o-1"),
+ SLAVE_RCX_TO_ACX1_0("apu_rcx2acx1_o-0"),
+ SLAVE_RCX_TO_ACX1_1("apu_rcx2acx1_o-1"),
+ SLAVE_SAE_TO_ACX1_0("apu_sae2acx1_o-0"),
+ SLAVE_SAE_TO_ACX1_1("apu_sae2acx1_o-1"),
+};
+
+static const struct apc_dom_16 APU_CTRL_DAPC_RCX[] = {
+ /* ctrl index = 0 */
+ SLAVE_MD32_SYSCTRL0("md32_apb_s-0"),
+ SLAVE_MD32_SYSCTRL1("md32_apb_s-1"),
+ SLAVE_MD32_WDT("md32_apb_s-2"),
+ SLAVE_MD32_CACHE("md32_apb_s-3"),
+ SLAVE_RPC("apusys_ao-0"),
+ SLAVE_PCU("apusys_ao-1"),
+ SLAVE_AO_CTRL("apusys_ao-2"),
+ SLAVE_PLL("apusys_ao-3"),
+ SLAVE_ACC("apusys_ao-4"),
+ SLAVE_SEC("apusys_ao-5"),
+
+ /* ctrl index = 10 */
+ SLAVE_ARE0("apusys_ao-6"),
+ SLAVE_ARE1("apusys_ao-7"),
+ SLAVE_ARE2("apusys_ao-8"),
+ SLAVE_UNKNOWN("apusys_ao-9"),
+ SLAVE_AO_BCRM("apusys_ao-10"),
+ SLAVE_AO_DAPC_WRAP("apusys_ao-11"),
+ SLAVE_AO_DAPC_CON("apusys_ao-12"),
+ SLAVE_VCORE("apusys_ao-13"),
+ SLAVE_ACX0_BCRM("apusys_ao-15"),
+ SLAVE_ACX1_BCRM("apusys_ao-16"),
+
+ /* ctrl index = 20 */
+ SLAVE_NOC_AXI("noc_axi"),
+ SLAVE_MD32_DBG("md32_dbg"),
+ SLAVE_DBG_CRTL("apb_infra_dbg"),
+ SLAVE_IOMMU0_BANK0("apu_n_mmu_r0"),
+ SLAVE_IOMMU0_BANK1("apu_n_mmu_r1"),
+ SLAVE_IOMMU0_BANK2("apu_n_mmu_r2"),
+ SLAVE_IOMMU0_BANK3("apu_n_mmu_r3"),
+ SLAVE_IOMMU0_BANK4("apu_n_mmu_r4"),
+ SLAVE_IOMMU1_BANK0("apu_s_mmu_r0"),
+ SLAVE_IOMMU1_BANK1("apu_s_mmu_r1"),
+
+ /* ctrl index = 30 */
+ SLAVE_IOMMU1_BANK2("apu_s_mmu_r2"),
+ SLAVE_IOMMU1_BANK3("apu_s_mmu_r3"),
+ SLAVE_IOMMU1_BANK4("apu_s_mmu_r4"),
+ SLAVE_S0_SSC("apu_s0_ssc_cfg"),
+ SLAVE_N0_SSC("apu_n0_ssc_cfg"),
+ SLAVE_ACP_SSC("apu_acp_ssc_cfg"),
+ SLAVE_S1_SSC("apu_s1_ssc_cfg"),
+ SLAVE_N1_SSC("apu_n1_ssc_cfg"),
+ SLAVE_CFG("apu_rcx_cfg"),
+ SLAVE_SEMA_STIMER("apu_sema_stimer"),
+
+ /* ctrl index = 40 */
+ SLAVE_EMI_CFG("apu_emi_cfg"),
+ SLAVE_LOG("apu_logtop"),
+ SLAVE_CPE_SENSOR("apu_cpe_sensor"),
+ SLAVE_CPE_COEF("apu_cpe_coef"),
+ SLAVE_CPE_CTRL("apu_cpe_ctrl"),
+ SLAVE_UNKNOWN("apu_xpu_rsi"),
+ SLAVE_DFD_REG_SOC("apu_dfd"),
+ SLAVE_SENSOR_WRAP_ACX0_DLA0("apu_sen_ac0_dla0"),
+ SLAVE_SENSOR_WRAP_ACX0_DLA1("apu_sen_ac0_dla1"),
+ SLAVE_SENSOR_WRAP_ACX0_VPU0("apu_sen_ac0_vpu"),
+
+ /* ctrl index = 50 */
+ SLAVE_SENSOR_WRAP_ACX1_DLA0("apu_sen_ac1_dla0"),
+ SLAVE_SENSOR_WRAP_ACX1_DLA1("apu_sen_ac1_dla1"),
+ SLAVE_SENSOR_WRAP_ACX1_VPU0("apu_sen_ac1_vpu"),
+ SLAVE_REVISER("noc_cfg-0"),
+ SLAVE_NOC("noc_cfg-1"),
+ SLAVE_BCRM("infra_bcrm"),
+ SLAVE_DAPC_WRAP("infra_dapc_wrap"),
+ SLAVE_DAPC_CON("infra_dapc_con"),
+ SLAVE_NOC_DAPC_WRAP("noc_dapc_wrap"),
+ SLAVE_NOC_DAPC_CON("noc_dapc_con"),
+
+ /* ctrl index = 60 */
+ SLAVE_NOC_BCRM("noc_bcrm"),
+ SLAVE_ACS("apu_rcx_acs"),
+ SLAVE_HSE("apu_hse"),
+};
+
+static enum apusys_apc_err_status set_slave_ao_ctrl_apc(uint32_t slave,
+ enum apusys_apc_domain_id domain_id,
+ enum apusys_apc_perm_type perm)
+{
+ uint32_t apc_register_index;
+ uint32_t apc_set_index;
+ uint32_t base;
+ uint32_t clr_bit;
+ uint32_t set_bit;
+
+ if ((perm < 0) || (perm >= PERM_NUM)) {
+ ERROR(MODULE_TAG "%s: permission type:0x%x is not supported!\n", __func__, perm);
+ return APUSYS_APC_ERR_GENERIC;
+ }
+
+ if ((slave >= APU_CTRL_DAPC_AO_SLAVE_NUM) ||
+ ((domain_id < 0) || (domain_id >= APU_CTRL_DAPC_AO_DOM_NUM))) {
+ ERROR(MODULE_TAG "%s: out of boundary, slave:0x%x, domain_id:0x%x\n",
+ __func__, slave, domain_id);
+ return APUSYS_APC_ERR_GENERIC;
+ }
+
+ apc_register_index = slave / APU_CTRL_DAPC_AO_SLAVE_NUM_IN_1_DOM;
+ apc_set_index = slave % APU_CTRL_DAPC_AO_SLAVE_NUM_IN_1_DOM;
+
+ clr_bit = (DEVAPC_MASK << (apc_set_index * DEVAPC_DOM_SHIFT));
+ set_bit = (uint32_t)perm << (apc_set_index * DEVAPC_DOM_SHIFT);
+
+ base = (APU_CTRL_DAPC_AO_BASE + domain_id * DEVAPC_DOM_SIZE +
+ apc_register_index * DEVAPC_REG_SIZE);
+
+ mmio_clrsetbits_32(base, clr_bit, set_bit);
+ return APUSYS_APC_OK;
+}
+
+static enum apusys_apc_err_status set_slave_noc_dapc_rcx(uint32_t slave,
+ enum apusys_apc_domain_id domain_id,
+ enum apusys_apc_perm_type perm)
+{
+ uint32_t apc_register_index;
+ uint32_t apc_set_index;
+ uint32_t base;
+ uint32_t clr_bit;
+ uint32_t set_bit;
+
+ if ((perm >= PERM_NUM) || (perm < 0)) {
+ ERROR(MODULE_TAG "%s: permission type:0x%x is not supported!\n", __func__, perm);
+ return APUSYS_APC_ERR_GENERIC;
+ }
+
+ if ((slave >= APU_NOC_DAPC_RCX_SLAVE_NUM) ||
+ ((domain_id < 0) || (domain_id >= APU_NOC_DAPC_RCX_DOM_NUM))) {
+ ERROR(MODULE_TAG "%s: out of boundary, slave:0x%x, domain_id:0x%x\n",
+ __func__, slave, domain_id);
+ return APUSYS_APC_ERR_GENERIC;
+ }
+
+ apc_register_index = slave / APU_NOC_DAPC_RCX_SLAVE_NUM_IN_1_DOM;
+ apc_set_index = slave % APU_NOC_DAPC_RCX_SLAVE_NUM_IN_1_DOM;
+
+ clr_bit = (DEVAPC_MASK << (apc_set_index * DEVAPC_DOM_SHIFT));
+ set_bit = ((uint32_t)perm) << (apc_set_index * DEVAPC_DOM_SHIFT);
+ base = (APU_NOC_DAPC_RCX_BASE + domain_id * DEVAPC_DOM_SIZE +
+ apc_register_index * DEVAPC_REG_SIZE);
+
+ mmio_clrsetbits_32(base, clr_bit, set_bit);
+ return APUSYS_APC_OK;
+}
+
+static enum apusys_apc_err_status set_slave_rcx_ctrl_apc(uint32_t slave,
+ enum apusys_apc_domain_id domain_id,
+ enum apusys_apc_perm_type perm)
+{
+ uint32_t apc_register_index;
+ uint32_t apc_set_index;
+ uint32_t base;
+ uint32_t clr_bit;
+ uint32_t set_bit;
+
+ if ((perm < 0) || (perm >= PERM_NUM)) {
+ ERROR(MODULE_TAG "%s: permission type:0x%x is not supported!\n", __func__, perm);
+ return APUSYS_APC_ERR_GENERIC;
+ }
+
+ if ((slave >= APU_CTRL_DAPC_RCX_SLAVE_NUM) ||
+ ((domain_id < 0) || (domain_id >= APU_CTRL_DAPC_RCX_DOM_NUM))) {
+ ERROR(MODULE_TAG "%s: out of boundary, slave:0x%x, domain_id:0x%x\n",
+ __func__, slave, domain_id);
+ return APUSYS_APC_ERR_GENERIC;
+ }
+
+ apc_register_index = slave / APU_CTRL_DAPC_RCX_SLAVE_NUM_IN_1_DOM;
+ apc_set_index = slave % APU_CTRL_DAPC_RCX_SLAVE_NUM_IN_1_DOM;
+
+ clr_bit = (DEVAPC_MASK << (apc_set_index * DEVAPC_DOM_SHIFT));
+ set_bit = (uint32_t)perm << (apc_set_index * DEVAPC_DOM_SHIFT);
+ base = (APU_CTRL_DAPC_RCX_BASE + domain_id * DEVAPC_DOM_SIZE +
+ apc_register_index * DEVAPC_REG_SIZE);
+
+ mmio_clrsetbits_32(base, clr_bit, set_bit);
+ return APUSYS_APC_OK;
+}
+
+static void apusys_devapc_init(const char *name, uint32_t base)
+{
+ mmio_write_32(APUSYS_DAPC_CON(base), APUSYS_DAPC_CON_VIO_MASK);
+}
+
+int apusys_devapc_ao_init(void)
+{
+ enum apusys_apc_err_status ret;
+
+ apusys_devapc_init("APUAPC_CTRL_AO", APU_CTRL_DAPC_AO_BASE);
+
+ ret = SET_APUSYS_DAPC_V1(APU_CTRL_DAPC_AO, set_slave_ao_ctrl_apc);
+ if (ret != APUSYS_APC_OK) {
+ ERROR(MODULE_TAG "%s: set_apusys_ao_ctrl_dap FAILED!\n", __func__);
+ return -1;
+ }
+
+#if DUMP_APUSYS_DAPC
+ DUMP_APUSYS_DAPC_V1(APU_CTRL_DAPC_AO);
+#endif
+
+ return 0;
+}
+
+int apusys_devapc_rcx_init(void)
+{
+ static bool apusys_devapc_rcx_init_called;
+ enum apusys_apc_err_status ret;
+
+ if (apusys_devapc_rcx_init_called == true) {
+ INFO(MODULE_TAG "%s: init more than once!\n", __func__);
+ return -1;
+ }
+ apusys_devapc_rcx_init_called = true;
+
+ apusys_devapc_init("APUAPC_CTRL_RCX", APU_CTRL_DAPC_RCX_BASE);
+ apusys_devapc_init("APUAPC_NOC_RCX", APU_NOC_DAPC_RCX_BASE);
+
+ ret = SET_APUSYS_DAPC_V1(APU_CTRL_DAPC_RCX, set_slave_rcx_ctrl_apc);
+ if (ret != APUSYS_APC_OK) {
+ ERROR(MODULE_TAG "%s: set_slave_rcx_ctrl_apc FAILED!\n", __func__);
+ return -1;
+ }
+
+#if DUMP_APUSYS_DAPC
+ DUMP_APUSYS_DAPC_V1(APU_CTRL_DAPC_RCX);
+#endif
+
+ ret = SET_APUSYS_DAPC_V1(APU_NOC_DAPC_RCX, set_slave_noc_dapc_rcx);
+ if (ret != APUSYS_APC_OK) {
+ ERROR(MODULE_TAG "%s: set_slave_noc_dapc_rcx FAILED\n", __func__);
+ return -1;
+ }
+
+#if DUMP_APUSYS_DAPC
+ DUMP_APUSYS_DAPC_V1(APU_NOC_DAPC_RCX);
+#endif
+
+ return 0;
+}
diff --git a/plat/mediatek/drivers/apusys/mt8188/apusys_devapc.h b/plat/mediatek/drivers/apusys/mt8188/apusys_devapc.h
new file mode 100644
index 0000000..de76459
--- /dev/null
+++ b/plat/mediatek/drivers/apusys/mt8188/apusys_devapc.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef APUSYS_DEVAPC_H
+#define APUSYS_DEVAPC_H
+
+int apusys_devapc_ao_init(void);
+int apusys_devapc_rcx_init(void);
+
+#endif /* APUSYS_DEVAPC_H */
diff --git a/plat/mediatek/drivers/apusys/mt8188/apusys_devapc_def.h b/plat/mediatek/drivers/apusys/mt8188/apusys_devapc_def.h
new file mode 100644
index 0000000..e74b022
--- /dev/null
+++ b/plat/mediatek/drivers/apusys/mt8188/apusys_devapc_def.h
@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef APUSYS_DEVAPC_DEF_H
+#define APUSYS_DEVAPC_DEF_H
+
+#include <lib/mmio.h>
+#include "../devapc/apusys_dapc_v1.h"
+
+/* NoC */
+#define SLAVE_MD32_SRAM SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+
+/* Control */
+#define SLAVE_VCORE SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_RPC SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_NO_PROTECT
+#define SLAVE_PCU SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_AO_CTRL SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_PLL SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_NO_PROTECT
+#define SLAVE_ACC SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_SEC SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_ARE0 SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_ARE1 SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_ARE2 SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_UNKNOWN SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
+#define SLAVE_APU_BULK SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_AO_BCRM SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
+#define SLAVE_AO_DAPC_WRAP SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
+#define SLAVE_AO_DAPC_CON SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_RCX_ACX_BULK SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT_D3_SEC_RW
+#define SLAVE_ACX0_BCRM SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT_D3_SEC_RW
+#define SLAVE_RPCTOP_LITE_ACX0 SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
+#define SLAVE_ACX1_BCRM SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT_D3_SEC_RW
+#define SLAVE_RPCTOP_LITE_ACX1 SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
+#define SLAVE_RCX_TO_ACX0_0 SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT_D3_SEC_RW
+#define SLAVE_RCX_TO_ACX0_1 SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
+#define SLAVE_SAE_TO_ACX0_0 SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT_D3_SEC_RW
+#define SLAVE_SAE_TO_ACX0_1 SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
+#define SLAVE_RCX_TO_ACX1_0 SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
+#define SLAVE_RCX_TO_ACX1_1 SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
+#define SLAVE_SAE_TO_ACX1_0 SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
+#define SLAVE_SAE_TO_ACX1_1 SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
+#define SLAVE_MD32_SYSCTRL0 SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_MD32_SYSCTRL1 SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_NO_PROTECT
+#define SLAVE_MD32_WDT SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_MD32_CACHE SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_NOC_AXI SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
+#define SLAVE_MD32_DBG SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
+#define SLAVE_DBG_CRTL SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_IOMMU0_BANK0 SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
+#define SLAVE_IOMMU0_BANK1 SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_IOMMU0_BANK2 SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_IOMMU0_BANK3 SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_IOMMU0_BANK4 SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_IOMMU1_BANK0 SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
+#define SLAVE_IOMMU1_BANK1 SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_IOMMU1_BANK2 SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_IOMMU1_BANK3 SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_IOMMU1_BANK4 SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_S0_SSC SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
+#define SLAVE_N0_SSC SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
+#define SLAVE_ACP_SSC SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
+#define SLAVE_S1_SSC SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
+#define SLAVE_N1_SSC SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
+#define SLAVE_CFG SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_NO_PROTECT
+#define SLAVE_SEMA_STIMER SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
+#define SLAVE_EMI_CFG SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
+#define SLAVE_LOG SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_NO_PROTECT
+#define SLAVE_CPE_SENSOR SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
+#define SLAVE_CPE_COEF SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
+#define SLAVE_CPE_CTRL SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
+#define SLAVE_DFD_REG_SOC SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
+#define SLAVE_SENSOR_WRAP_ACX0_DLA0 SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
+#define SLAVE_SENSOR_WRAP_ACX0_DLA1 SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
+#define SLAVE_SENSOR_WRAP_ACX0_VPU0 SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
+#define SLAVE_SENSOR_WRAP_ACX1_DLA0 SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
+#define SLAVE_SENSOR_WRAP_ACX1_DLA1 SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
+#define SLAVE_SENSOR_WRAP_ACX1_VPU0 SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
+#define SLAVE_REVISER SLAVE_FORBID_EXCEPT_D0_SEC_RW
+#define SLAVE_NOC SLAVE_FORBID_EXCEPT_D0_D3_SEC_RW_D5_NO_PROTECT
+#define SLAVE_BCRM SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
+#define SLAVE_DAPC_WRAP SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
+#define SLAVE_DAPC_CON SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_NOC_DAPC_WRAP SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
+#define SLAVE_NOC_DAPC_CON SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_NOC_BCRM SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
+#define SLAVE_ACS SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_HSE SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
+
+
+/* Power Domain: AO */
+#define APU_CTRL_DAPC_AO_SLAVE_NUM_IN_1_DOM (16)
+#define APU_CTRL_DAPC_AO_DOM_NUM (16)
+#define APU_CTRL_DAPC_AO_SLAVE_NUM (30)
+#define DEVAPC_MASK (0x3U)
+#define DEVAPC_DOM_SHIFT (2)
+
+/* Power Domain: RCX */
+#define APU_CTRL_DAPC_RCX_SLAVE_NUM_IN_1_DOM (16)
+#define APU_CTRL_DAPC_RCX_DOM_NUM (16)
+#define APU_CTRL_DAPC_RCX_SLAVE_NUM (63)
+
+#define APU_NOC_DAPC_RCX_SLAVE_NUM_IN_1_DOM (16)
+#define APU_NOC_DAPC_RCX_DOM_NUM (16)
+#define APU_NOC_DAPC_RCX_SLAVE_NUM (5)
+
+#endif /* APUSYS_DEVAPC_DEF_H */
diff --git a/plat/mediatek/drivers/apusys/mt8188/apusys_power.c b/plat/mediatek/drivers/apusys/mt8188/apusys_power.c
index ac62f2f..cdfc133 100644
--- a/plat/mediatek/drivers/apusys/mt8188/apusys_power.c
+++ b/plat/mediatek/drivers/apusys/mt8188/apusys_power.c
@@ -17,6 +17,7 @@
/* Vendor header */
#include "apusys.h"
#include "apusys_power.h"
+#include "apusys_rv.h"
#include <mtk_mmap_pool.h>
static spinlock_t apu_lock;
@@ -47,6 +48,43 @@
return -1;
}
+static void apu_backup_restore(enum APU_BACKUP_RESTORE_CTRL ctrl)
+{
+ int i;
+ static struct apu_restore_data apu_restore_data[] = {
+ { UP_NORMAL_DOMAIN_NS, 0 },
+ { UP_PRI_DOMAIN_NS, 0 },
+ { UP_IOMMU_CTRL, 0 },
+ { UP_CORE0_VABASE0, 0 },
+ { UP_CORE0_MVABASE0, 0 },
+ { UP_CORE0_VABASE1, 0 },
+ { UP_CORE0_MVABASE1, 0 },
+ { UP_CORE0_VABASE2, 0 },
+ { UP_CORE0_MVABASE2, 0 },
+ { UP_CORE0_VABASE3, 0 },
+ { UP_CORE0_MVABASE3, 0 },
+ { MD32_SYS_CTRL, 0 },
+ { MD32_CLK_CTRL, 0 },
+ { UP_WAKE_HOST_MASK0, 0 }
+ };
+
+ switch (ctrl) {
+ case APU_CTRL_BACKUP:
+ for (i = 0; i < ARRAY_SIZE(apu_restore_data); i++) {
+ apu_restore_data[i].data = mmio_read_32(apu_restore_data[i].reg);
+ }
+ break;
+ case APU_CTRL_RESTORE:
+ for (i = 0; i < ARRAY_SIZE(apu_restore_data); i++) {
+ mmio_write_32(apu_restore_data[i].reg, apu_restore_data[i].data);
+ }
+ break;
+ default:
+ ERROR(MODULE_TAG "%s invalid op: %d\n", __func__, ctrl);
+ break;
+ }
+}
+
static void apu_xpu2apusys_d4_slv_en(enum APU_D4_SLV_CTRL en)
{
switch (en) {
@@ -120,6 +158,8 @@
apu_xpu2apusys_d4_slv_en(D4_SLV_OFF);
+ apu_backup_restore(APU_CTRL_RESTORE);
+
apusys_top_on = true;
spin_unlock(&apu_lock);
@@ -153,6 +193,8 @@
return 0;
}
+ apu_backup_restore(APU_CTRL_BACKUP);
+
apu_xpu2apusys_d4_slv_en(D4_SLV_ON);
if (mmio_read_32(APU_MBOX0_BASE + PWR_FLOW_SYNC_REG) == 0) {
diff --git a/plat/mediatek/drivers/apusys/mt8188/apusys_power.h b/plat/mediatek/drivers/apusys/mt8188/apusys_power.h
index b4968d6..460cc50 100644
--- a/plat/mediatek/drivers/apusys/mt8188/apusys_power.h
+++ b/plat/mediatek/drivers/apusys/mt8188/apusys_power.h
@@ -29,6 +29,16 @@
D4_SLV_ON,
};
+enum APU_BACKUP_RESTORE_CTRL {
+ APU_CTRL_BACKUP = 0,
+ APU_CTRL_RESTORE = 1,
+};
+
+struct apu_restore_data {
+ uint32_t reg;
+ uint32_t data;
+};
+
#define APU_POLL_STEP_US (5)
#define OUT_CLK_FREQ_MIN (1500)
diff --git a/plat/mediatek/drivers/apusys/mt8188/apusys_security_ctrl_plat.c b/plat/mediatek/drivers/apusys/mt8188/apusys_security_ctrl_plat.c
new file mode 100644
index 0000000..86bebe5
--- /dev/null
+++ b/plat/mediatek/drivers/apusys/mt8188/apusys_security_ctrl_plat.c
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* TF-A system header */
+#include <common/debug.h>
+#include <lib/mmio.h>
+
+/* Vendor header */
+#include "apusys_security_ctrl_plat.h"
+
+static void apusys_domain_remap_init(void)
+{
+ const uint32_t remap_domains[] = {
+ D0_REMAP_DOMAIN, D1_REMAP_DOMAIN, D2_REMAP_DOMAIN, D3_REMAP_DOMAIN,
+ D4_REMAP_DOMAIN, D5_REMAP_DOMAIN, D6_REMAP_DOMAIN, D7_REMAP_DOMAIN,
+ D8_REMAP_DOMAIN, D9_REMAP_DOMAIN, D10_REMAP_DOMAIN, D11_REMAP_DOMAIN,
+ D12_REMAP_DOMAIN, D13_REMAP_DOMAIN, D14_REMAP_DOMAIN, D15_REMAP_DOMAIN
+ };
+ uint32_t lower_domain = 0;
+ uint32_t higher_domain = 0;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(remap_domains); i++) {
+ if (i < REG_DOMAIN_NUM) {
+ lower_domain |= (remap_domains[i] << (i * REG_DOMAIN_BITS));
+ } else {
+ higher_domain |= (remap_domains[i] <<
+ ((i - REG_DOMAIN_NUM) * REG_DOMAIN_BITS));
+ }
+ }
+
+ mmio_write_32(SOC2APU_SET1_0, lower_domain);
+ mmio_write_32(SOC2APU_SET1_1, higher_domain);
+ mmio_setbits_32(APU_SEC_CON, DOMAIN_REMAP_SEL);
+}
+
+void apusys_security_ctrl_init(void)
+{
+ apusys_domain_remap_init();
+}
diff --git a/plat/mediatek/drivers/apusys/mt8188/apusys_security_ctrl_plat.h b/plat/mediatek/drivers/apusys/mt8188/apusys_security_ctrl_plat.h
new file mode 100644
index 0000000..f9181ae
--- /dev/null
+++ b/plat/mediatek/drivers/apusys/mt8188/apusys_security_ctrl_plat.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef APUSYS_SECURITY_CTRL_PLAT_H
+#define APUSYS_SECURITY_CTRL_PLAT_H
+
+#include <platform_def.h>
+
+#define SOC2APU_SET1_0 (APU_SEC_CON + 0x0c)
+#define SOC2APU_SET1_1 (APU_SEC_CON + 0x10)
+
+#define REG_DOMAIN_NUM (8)
+#define REG_DOMAIN_BITS (4)
+#define DOMAIN_REMAP_SEL BIT(6)
+
+#define D0_REMAP_DOMAIN (0)
+#define D1_REMAP_DOMAIN (1)
+#define D2_REMAP_DOMAIN (2)
+#define D3_REMAP_DOMAIN (3)
+#define D4_REMAP_DOMAIN (4)
+#define D5_REMAP_DOMAIN (14)
+#define D6_REMAP_DOMAIN (6)
+#define D7_REMAP_DOMAIN (14)
+#define D8_REMAP_DOMAIN (8)
+#define D9_REMAP_DOMAIN (9)
+#define D10_REMAP_DOMAIN (10)
+#define D11_REMAP_DOMAIN (11)
+#define D12_REMAP_DOMAIN (12)
+#define D13_REMAP_DOMAIN (13)
+#define D14_REMAP_DOMAIN (14)
+#define D15_REMAP_DOMAIN (15)
+
+void apusys_security_ctrl_init(void);
+
+#endif /* APUSYS_SECURITY_CTRL_PLAT_H */
diff --git a/plat/mediatek/drivers/apusys/mt8188/rules.mk b/plat/mediatek/drivers/apusys/mt8188/rules.mk
index f676b6e..c358067 100644
--- a/plat/mediatek/drivers/apusys/mt8188/rules.mk
+++ b/plat/mediatek/drivers/apusys/mt8188/rules.mk
@@ -8,6 +8,8 @@
MODULE := apusys_${MTK_SOC}
-LOCAL_SRCS-y := ${LOCAL_DIR}/apusys_power.c
+LOCAL_SRCS-y := ${LOCAL_DIR}/apusys_devapc.c
+LOCAL_SRCS-y += ${LOCAL_DIR}/apusys_power.c
+LOCAL_SRCS-y += ${LOCAL_DIR}/apusys_security_ctrl_plat.c
$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))
diff --git a/plat/mediatek/drivers/apusys/rules.mk b/plat/mediatek/drivers/apusys/rules.mk
index 1aa67bc..498925c 100644
--- a/plat/mediatek/drivers/apusys/rules.mk
+++ b/plat/mediatek/drivers/apusys/rules.mk
@@ -10,10 +10,12 @@
LOCAL_SRCS-y:= ${LOCAL_DIR}/apusys.c
-PLAT_INCLUDES += -I${LOCAL_DIR} -I${LOCAL_DIR}/${MTK_SOC}
+PLAT_INCLUDES += -I${LOCAL_DIR} -I${LOCAL_DIR}/${MTK_SOC} -I${LOCAL_DIR}/apusys_rv/2.0
$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))
SUB_RULES-y := ${LOCAL_DIR}/${MTK_SOC}
+SUB_RULES-y += ${LOCAL_DIR}/devapc
+SUB_RULES-y += ${LOCAL_DIR}/apusys_rv/2.0
$(eval $(call INCLUDE_MAKEFILE,$(SUB_RULES-y)))
diff --git a/plat/mediatek/drivers/emi_mpu/emi_mpu.h b/plat/mediatek/drivers/emi_mpu/emi_mpu.h
index 66a369e..9c1ebb5 100644
--- a/plat/mediatek/drivers/emi_mpu/emi_mpu.h
+++ b/plat/mediatek/drivers/emi_mpu/emi_mpu.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2022-2023, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -60,5 +60,6 @@
int emi_mpu_init(void);
int emi_mpu_set_protection(struct emi_region_info_t *region_info);
void set_emi_mpu_regions(void);
+int set_apu_emi_mpu_region(void);
#endif
diff --git a/plat/mediatek/drivers/emi_mpu/mt8188/emi_mpu.c b/plat/mediatek/drivers/emi_mpu/mt8188/emi_mpu.c
index 558533d..59ab315 100644
--- a/plat/mediatek/drivers/emi_mpu/mt8188/emi_mpu.c
+++ b/plat/mediatek/drivers/emi_mpu/mt8188/emi_mpu.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2022-2023, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -12,3 +12,20 @@
/* TODO: set emi mpu region */
INFO("%s, emi mpu is not setting currently\n", __func__);
}
+
+int set_apu_emi_mpu_region(void)
+{
+ struct emi_region_info_t region_info;
+
+ region_info.start = (unsigned long long)APUSYS_SEC_BUF_PA;
+ region_info.end = (unsigned long long)(APUSYS_SEC_BUF_PA + APUSYS_SEC_BUF_SZ) - 1;
+ region_info.region = APUSYS_SEC_BUF_EMI_REGION;
+
+ SET_ACCESS_PERMISSION(region_info.apc, UNLOCK,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, SEC_RW);
+
+ return emi_mpu_set_protection(®ion_info);
+}
diff --git a/plat/mediatek/drivers/emi_mpu/mt8188/emi_mpu_priv.h b/plat/mediatek/drivers/emi_mpu/mt8188/emi_mpu_priv.h
index 1ee7397..cc7f7f1 100644
--- a/plat/mediatek/drivers/emi_mpu/mt8188/emi_mpu_priv.h
+++ b/plat/mediatek/drivers/emi_mpu/mt8188/emi_mpu_priv.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2022-2023, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -42,4 +42,9 @@
#define EMI_MPU_DGROUP_NUM (EMI_MPU_DOMAIN_NUM / 8)
+/* APU EMI MPU Setting */
+#define APUSYS_SEC_BUF_EMI_REGION (21)
+#define APUSYS_SEC_BUF_PA (0x55000000)
+#define APUSYS_SEC_BUF_SZ (0x100000)
+
#endif
diff --git a/plat/mediatek/mt8188/include/platform_def.h b/plat/mediatek/mt8188/include/platform_def.h
index fc9725e..0a7ae6d 100644
--- a/plat/mediatek/mt8188/include/platform_def.h
+++ b/plat/mediatek/mt8188/include/platform_def.h
@@ -28,17 +28,25 @@
* APUSYS related constants
******************************************************************************/
#define BCRM_FMEM_PDN_BASE (IO_PHYS + 0x00276000)
+#define APU_MD32_SYSCTRL (IO_PHYS + 0x09001000)
+#define APU_MD32_WDT (IO_PHYS + 0x09002000)
#define APU_RCX_CONFIG (IO_PHYS + 0x09020000)
+#define APU_CTRL_DAPC_RCX_BASE (IO_PHYS + 0x09034000)
+#define APU_NOC_DAPC_RCX_BASE (IO_PHYS + 0x09038000)
+#define APU_REVISER (IO_PHYS + 0x0903c000)
#define APU_RCX_VCORE_CONFIG (IO_PHYS + 0x090e0000)
#define APU_MBOX0 (IO_PHYS + 0x090e1000)
+#define APU_MBOX1 (IO_PHYS + 0x090e2000)
#define APU_RPCTOP (IO_PHYS + 0x090f0000)
#define APU_PCUTOP (IO_PHYS + 0x090f1000)
#define APU_AO_CTRL (IO_PHYS + 0x090f2000)
#define APU_PLL (IO_PHYS + 0x090f3000)
#define APU_ACC (IO_PHYS + 0x090f4000)
+#define APU_SEC_CON (IO_PHYS + 0x090f5000)
#define APU_ARETOP_ARE0 (IO_PHYS + 0x090f6000)
#define APU_ARETOP_ARE1 (IO_PHYS + 0x090f7000)
#define APU_ARETOP_ARE2 (IO_PHYS + 0x090f8000)
+#define APU_CTRL_DAPC_AO_BASE (IO_PHYS + 0x090fc000)
#define APU_ACX0_RPC_LITE (IO_PHYS + 0x09140000)
#define BCRM_FMEM_PDN_SIZE (0x1000)
@@ -193,7 +201,7 @@
* Platform memory map related constants
******************************************************************************/
#define TZRAM_BASE (0x54600000)
-#define TZRAM_SIZE (0x00030000)
+#define TZRAM_SIZE (0x00040000)
/*******************************************************************************
* BL31 specific defines.
diff --git a/plat/qemu/common/qemu_bl31_setup.c b/plat/qemu/common/qemu_bl31_setup.c
index 0b84e96..f309efd 100644
--- a/plat/qemu/common/qemu_bl31_setup.c
+++ b/plat/qemu/common/qemu_bl31_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -55,6 +55,11 @@
/* Initialize the console to provide early debug support */
qemu_console_init();
+/* Platform names have to be lowercase. */
+#ifdef PLAT_qemu_sbsa
+ sip_svc_init();
+#endif
+
/*
* Check params passed from BL2
*/
diff --git a/plat/qemu/common/qemu_private.h b/plat/qemu/common/qemu_private.h
index 199ca01..e80a88d 100644
--- a/plat/qemu/common/qemu_private.h
+++ b/plat/qemu/common/qemu_private.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -18,6 +18,9 @@
const mmap_region_t *plat_qemu_get_mmap(void);
void qemu_console_init(void);
+#ifdef PLAT_qemu_sbsa
+void sip_svc_init(void);
+#endif
void plat_qemu_gic_init(void);
void qemu_pwr_gic_on_finish(void);
diff --git a/plat/qemu/qemu_sbsa/include/platform_def.h b/plat/qemu/qemu_sbsa/include/platform_def.h
index 85fbb4d..deaf16e 100644
--- a/plat/qemu/qemu_sbsa/include/platform_def.h
+++ b/plat/qemu/qemu_sbsa/include/platform_def.h
@@ -215,6 +215,8 @@
/*
* GIC related constants
* We use GICv3 where CPU Interface registers are not memory mapped
+ *
+ * Legacy values - on platform version 0.1+ they are read from DT
*/
#define GICD_BASE 0x40060000
#define GICR_BASE 0x40080000
diff --git a/plat/qemu/qemu_sbsa/platform.mk b/plat/qemu/qemu_sbsa/platform.mk
index 8b8d76b..60d6b7e 100644
--- a/plat/qemu/qemu_sbsa/platform.mk
+++ b/plat/qemu/qemu_sbsa/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2019-2021, Linaro Limited and Contributors. All rights reserved.
+# Copyright (c) 2019-2023, Linaro Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -89,14 +89,15 @@
include drivers/arm/gic/v3/gicv3.mk
QEMU_GIC_SOURCES := ${GICV3_SOURCES} \
- plat/common/plat_gicv3.c \
- ${PLAT_QEMU_COMMON_PATH}/qemu_gicv3.c
+ plat/common/plat_gicv3.c
BL31_SOURCES += ${QEMU_CPU_LIBS} \
lib/semihosting/semihosting.c \
lib/semihosting/${ARCH}/semihosting_call.S \
plat/common/plat_psci_common.c \
+ ${PLAT_QEMU_PATH}/sbsa_gic.c \
${PLAT_QEMU_PATH}/sbsa_pm.c \
+ ${PLAT_QEMU_PATH}/sbsa_sip_svc.c \
${PLAT_QEMU_PATH}/sbsa_topology.c \
${PLAT_QEMU_COMMON_PATH}/aarch64/plat_helpers.S \
${PLAT_QEMU_COMMON_PATH}/qemu_bl31_setup.c \
diff --git a/plat/qemu/qemu_sbsa/sbsa_gic.c b/plat/qemu/qemu_sbsa/sbsa_gic.c
new file mode 100644
index 0000000..962dbb3
--- /dev/null
+++ b/plat/qemu/qemu_sbsa/sbsa_gic.c
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2023, Linaro Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <drivers/arm/gicv3.h>
+#include <plat/common/platform.h>
+
+static const interrupt_prop_t qemu_interrupt_props[] = {
+ PLATFORM_G1S_PROPS(INTR_GROUP1S),
+ PLATFORM_G0_PROPS(INTR_GROUP0)
+};
+
+static uintptr_t qemu_rdistif_base_addrs[PLATFORM_CORE_COUNT];
+
+static unsigned int qemu_mpidr_to_core_pos(unsigned long mpidr)
+{
+ return plat_core_pos_by_mpidr(mpidr);
+}
+
+static gicv3_driver_data_t sbsa_gic_driver_data = {
+ /* we set those two values for compatibility with older QEMU */
+ .gicd_base = GICD_BASE,
+ .gicr_base = GICR_BASE,
+ .interrupt_props = qemu_interrupt_props,
+ .interrupt_props_num = ARRAY_SIZE(qemu_interrupt_props),
+ .rdistif_num = PLATFORM_CORE_COUNT,
+ .rdistif_base_addrs = qemu_rdistif_base_addrs,
+ .mpidr_to_core_pos = qemu_mpidr_to_core_pos
+};
+
+void sbsa_set_gic_bases(const uintptr_t gicd_base, const uintptr_t gicr_base)
+{
+ sbsa_gic_driver_data.gicd_base = gicd_base;
+ sbsa_gic_driver_data.gicr_base = gicr_base;
+}
+
+uintptr_t sbsa_get_gicd(void)
+{
+ return sbsa_gic_driver_data.gicd_base;
+}
+
+uintptr_t sbsa_get_gicr(void)
+{
+ return sbsa_gic_driver_data.gicr_base;
+}
+
+void plat_qemu_gic_init(void)
+{
+ gicv3_driver_init(&sbsa_gic_driver_data);
+ gicv3_distif_init();
+ gicv3_rdistif_init(plat_my_core_pos());
+ gicv3_cpuif_enable(plat_my_core_pos());
+}
+
+void qemu_pwr_gic_on_finish(void)
+{
+ gicv3_rdistif_init(plat_my_core_pos());
+ gicv3_cpuif_enable(plat_my_core_pos());
+}
+
+void qemu_pwr_gic_off(void)
+{
+ gicv3_cpuif_disable(plat_my_core_pos());
+ gicv3_rdistif_off(plat_my_core_pos());
+}
diff --git a/plat/qemu/qemu_sbsa/sbsa_sip_svc.c b/plat/qemu/qemu_sbsa/sbsa_sip_svc.c
new file mode 100644
index 0000000..37460d7
--- /dev/null
+++ b/plat/qemu/qemu_sbsa/sbsa_sip_svc.c
@@ -0,0 +1,166 @@
+/*
+ * Copyright (c) 2023, Linaro Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+
+#include <common/fdt_wrappers.h>
+#include <common/runtime_svc.h>
+#include <libfdt.h>
+#include <smccc_helpers.h>
+
+/* default platform version is 0.0 */
+static int platform_version_major;
+static int platform_version_minor;
+
+#define SMC_FASTCALL 0x80000000
+#define SMC64_FUNCTION (SMC_FASTCALL | 0x40000000)
+#define SIP_FUNCTION (SMC64_FUNCTION | 0x02000000)
+#define SIP_FUNCTION_ID(n) (SIP_FUNCTION | (n))
+
+/*
+ * We do not use SMCCC_ARCH_SOC_ID here because qemu_sbsa is virtual platform
+ * which uses SoC present in QEMU. And they can change on their own while we
+ * need version of whole 'virtual hardware platform'.
+ */
+#define SIP_SVC_VERSION SIP_FUNCTION_ID(1)
+
+#define SIP_SVC_GET_GIC SIP_FUNCTION_ID(100)
+
+void sbsa_set_gic_bases(const uintptr_t gicd_base, const uintptr_t gicr_base);
+uintptr_t sbsa_get_gicd(void);
+uintptr_t sbsa_get_gicr(void);
+
+void read_platform_config_from_dt(void *dtb)
+{
+ int node;
+ const fdt64_t *data;
+ int err;
+ uintptr_t gicd_base;
+ uintptr_t gicr_base;
+
+ /*
+ * QEMU gives us this DeviceTree node:
+ *
+ * intc {
+ reg = < 0x00 0x40060000 0x00 0x10000
+ 0x00 0x40080000 0x00 0x4000000>;
+ };
+ */
+ node = fdt_path_offset(dtb, "/intc");
+ if (node < 0) {
+ return;
+ }
+
+ data = fdt_getprop(dtb, node, "reg", NULL);
+ if (data == NULL) {
+ return;
+ }
+
+ err = fdt_get_reg_props_by_index(dtb, node, 0, &gicd_base, NULL);
+ if (err < 0) {
+ ERROR("Failed to read GICD reg property of GIC node\n");
+ return;
+ }
+ INFO("GICD base = 0x%lx\n", gicd_base);
+
+ err = fdt_get_reg_props_by_index(dtb, node, 1, &gicr_base, NULL);
+ if (err < 0) {
+ ERROR("Failed to read GICR reg property of GIC node\n");
+ return;
+ }
+ INFO("GICR base = 0x%lx\n", gicr_base);
+
+ sbsa_set_gic_bases(gicd_base, gicr_base);
+}
+
+void read_platform_version(void *dtb)
+{
+ int node;
+
+ node = fdt_path_offset(dtb, "/");
+ if (node >= 0) {
+ platform_version_major = fdt32_ld(fdt_getprop(dtb, node,
+ "machine-version-major", NULL));
+ platform_version_minor = fdt32_ld(fdt_getprop(dtb, node,
+ "machine-version-minor", NULL));
+ }
+}
+
+void sip_svc_init(void)
+{
+ /* Read DeviceTree data before MMU is enabled */
+
+ void *dtb = (void *)(uintptr_t)ARM_PRELOADED_DTB_BASE;
+ int err;
+
+ err = fdt_open_into(dtb, dtb, PLAT_QEMU_DT_MAX_SIZE);
+ if (err < 0) {
+ ERROR("Invalid Device Tree at %p: error %d\n", dtb, err);
+ return;
+ }
+
+ err = fdt_check_header(dtb);
+ if (err < 0) {
+ ERROR("Invalid DTB file passed\n");
+ return;
+ }
+
+ read_platform_version(dtb);
+ INFO("Platform version: %d.%d\n", platform_version_major, platform_version_minor);
+
+ read_platform_config_from_dt(dtb);
+}
+
+/*
+ * This function is responsible for handling all SiP calls from the NS world
+ */
+uintptr_t sbsa_sip_smc_handler(uint32_t smc_fid,
+ u_register_t x1,
+ u_register_t x2,
+ u_register_t x3,
+ u_register_t x4,
+ void *cookie,
+ void *handle,
+ u_register_t flags)
+{
+ uint32_t ns;
+
+ /* Determine which security state this SMC originated from */
+ ns = is_caller_non_secure(flags);
+ if (!ns) {
+ ERROR("%s: wrong world SMC (0x%x)\n", __func__, smc_fid);
+ SMC_RET1(handle, SMC_UNK);
+ }
+
+ switch (smc_fid) {
+ case SIP_SVC_VERSION:
+ INFO("Platform version requested\n");
+ SMC_RET3(handle, NULL, platform_version_major, platform_version_minor);
+
+ case SIP_SVC_GET_GIC:
+ SMC_RET3(handle, NULL, sbsa_get_gicd(), sbsa_get_gicr());
+
+ default:
+ ERROR("%s: unhandled SMC (0x%x) (function id: %d)\n", __func__, smc_fid,
+ smc_fid - SIP_FUNCTION);
+ SMC_RET1(handle, SMC_UNK);
+ }
+}
+
+int sbsa_sip_smc_setup(void)
+{
+ return 0;
+}
+
+/* Define a runtime service descriptor for fast SMC calls */
+DECLARE_RT_SVC(
+ sbsa_sip_svc,
+ OEN_SIP_START,
+ OEN_SIP_END,
+ SMC_TYPE_FAST,
+ sbsa_sip_smc_setup,
+ sbsa_sip_smc_handler
+);
diff --git a/plat/qti/common/src/qti_pm.c b/plat/qti/common/src/qti_pm.c
index 1405ca6..487a56e 100644
--- a/plat/qti/common/src/qti_pm.c
+++ b/plat/qti/common/src/qti_pm.c
@@ -191,18 +191,6 @@
}
}
-#if PSCI_OS_INIT_MODE
-static int qti_node_suspend(const psci_power_state_t *target_state)
-{
- qtiseclib_psci_node_suspend((const uint8_t *)target_state->
- pwr_domain_state);
- if (is_cpu_off(target_state)) {
- plat_qti_gic_cpuif_disable();
- qti_set_cpupwrctlr_val();
- }
- return PSCI_E_SUCCESS;
-}
-#else
static void qti_node_suspend(const psci_power_state_t *target_state)
{
qtiseclib_psci_node_suspend((const uint8_t *)target_state->
@@ -212,7 +200,6 @@
qti_set_cpupwrctlr_val();
}
}
-#endif
static void qti_node_suspend_finish(const psci_power_state_t *target_state)
{
diff --git a/plat/st/common/stm32cubeprogrammer_uart.c b/plat/st/common/stm32cubeprogrammer_uart.c
index d004dcf..e4a5338 100644
--- a/plat/st/common/stm32cubeprogrammer_uart.c
+++ b/plat/st/common/stm32cubeprogrammer_uart.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2022, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2021-2023, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -481,6 +481,8 @@
}
}
+ stm32_uart_flush(&handle.uart);
+
return 0;
}
diff --git a/plat/st/stm32mp1/stm32mp1_def.h b/plat/st/stm32mp1/stm32mp1_def.h
index 8cac4b5..df5593a 100644
--- a/plat/st/stm32mp1/stm32mp1_def.h
+++ b/plat/st/stm32mp1/stm32mp1_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -647,11 +647,12 @@
/*******************************************************************************
* Device Tree defines
******************************************************************************/
-#define DT_BSEC_COMPAT "st,stm32mp15-bsec"
#if STM32MP13
+#define DT_BSEC_COMPAT "st,stm32mp13-bsec"
#define DT_DDR_COMPAT "st,stm32mp13-ddr"
#endif
#if STM32MP15
+#define DT_BSEC_COMPAT "st,stm32mp15-bsec"
#define DT_DDR_COMPAT "st,stm32mp1-ddr"
#endif
#define DT_IWDG_COMPAT "st,stm32mp1-iwdg"
diff --git a/plat/st/stm32mp1/stm32mp1_pm.c b/plat/st/stm32mp1/stm32mp1_pm.c
index 8e1c1cf..ff2218f 100644
--- a/plat/st/stm32mp1/stm32mp1_pm.c
+++ b/plat/st/stm32mp1/stm32mp1_pm.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -161,17 +161,15 @@
static int stm32_validate_power_state(unsigned int power_state,
psci_power_state_t *req_state)
{
- int pstate = psci_get_pstate_type(power_state);
-
- if (pstate != 0) {
+ if (psci_get_pstate_type(power_state) != 0U) {
return PSCI_E_INVALID_PARAMS;
}
- if (psci_get_pstate_pwrlvl(power_state)) {
+ if (psci_get_pstate_pwrlvl(power_state) != 0U) {
return PSCI_E_INVALID_PARAMS;
}
- if (psci_get_pstate_id(power_state)) {
+ if (psci_get_pstate_id(power_state) != 0U) {
return PSCI_E_INVALID_PARAMS;
}
diff --git a/plat/xilinx/common/include/plat_startup.h b/plat/xilinx/common/include/plat_startup.h
index ed3946f..d1c5303 100644
--- a/plat/xilinx/common/include/plat_startup.h
+++ b/plat/xilinx/common/include/plat_startup.h
@@ -26,18 +26,18 @@
uint64_t flags;
};
-/* Structure for handoff parameters to ARM Trusted Firmware (ATF) */
-struct xfsbl_atf_handoff_params {
+/* Structure for handoff parameters to TrustedFirmware-A (TF-A) */
+struct xfsbl_tfa_handoff_params {
uint8_t magic[4];
uint32_t num_entries;
struct xfsbl_partition partition[FSBL_MAX_PARTITIONS];
};
-#define ATF_HANDOFF_PARAMS_MAX_SIZE sizeof(struct xfsbl_atf_handoff_params)
+#define TFA_HANDOFF_PARAMS_MAX_SIZE sizeof(struct xfsbl_tfa_handoff_params)
-enum fsbl_handoff fsbl_atf_handover(entry_point_info_t *bl32,
+enum fsbl_handoff fsbl_tfa_handover(entry_point_info_t *bl32,
entry_point_info_t *bl33,
- uint64_t atf_handoff_addr);
+ uint64_t tfa_handoff_addr);
/* JEDEC Standard Manufacturer's Identification Code and Bank ID JEP106 */
#define JEDEC_XILINX_MFID U(0x49)
diff --git a/plat/xilinx/common/plat_startup.c b/plat/xilinx/common/plat_startup.c
index 539aba2..007c045 100644
--- a/plat/xilinx/common/plat_startup.c
+++ b/plat/xilinx/common/plat_startup.c
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2014-2020, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2023, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -14,7 +15,7 @@
/*
- * ATFHandoffParams
+ * TFAHandoffParams
* Parameter bitfield encoding
* -----------------------------------------------------------------------------
* Exec State 0 0 -> Aarch64, 1-> Aarch32
@@ -133,7 +134,7 @@
* Populates the bl32 and bl33 image info structures
* @bl32: BL32 image info structure
* @bl33: BL33 image info structure
- * atf_handoff_addr: ATF handoff address
+ * tfa_handoff_addr: TF-A handoff address
*
* Process the handoff parameters from the FSBL and populate the BL32 and BL33
* image info structures accordingly.
@@ -141,31 +142,31 @@
* Return: Return the status of the handoff. The value will be from the
* fsbl_handoff enum.
*/
-enum fsbl_handoff fsbl_atf_handover(entry_point_info_t *bl32,
+enum fsbl_handoff fsbl_tfa_handover(entry_point_info_t *bl32,
entry_point_info_t *bl33,
- uint64_t atf_handoff_addr)
+ uint64_t tfa_handoff_addr)
{
- const struct xfsbl_atf_handoff_params *ATFHandoffParams;
- if (!atf_handoff_addr) {
- WARN("BL31: No ATF handoff structure passed\n");
+ const struct xfsbl_tfa_handoff_params *TFAHandoffParams;
+ if (!tfa_handoff_addr) {
+ WARN("BL31: No TFA handoff structure passed\n");
return FSBL_HANDOFF_NO_STRUCT;
}
- ATFHandoffParams = (struct xfsbl_atf_handoff_params *)atf_handoff_addr;
- if ((ATFHandoffParams->magic[0] != 'X') ||
- (ATFHandoffParams->magic[1] != 'L') ||
- (ATFHandoffParams->magic[2] != 'N') ||
- (ATFHandoffParams->magic[3] != 'X')) {
- ERROR("BL31: invalid ATF handoff structure at %" PRIx64 "\n",
- atf_handoff_addr);
+ TFAHandoffParams = (struct xfsbl_tfa_handoff_params *)tfa_handoff_addr;
+ if ((TFAHandoffParams->magic[0] != 'X') ||
+ (TFAHandoffParams->magic[1] != 'L') ||
+ (TFAHandoffParams->magic[2] != 'N') ||
+ (TFAHandoffParams->magic[3] != 'X')) {
+ ERROR("BL31: invalid TF-A handoff structure at %" PRIx64 "\n",
+ tfa_handoff_addr);
return FSBL_HANDOFF_INVAL_STRUCT;
}
- VERBOSE("BL31: ATF handoff params at:0x%" PRIx64 ", entries:%u\n",
- atf_handoff_addr, ATFHandoffParams->num_entries);
- if (ATFHandoffParams->num_entries > FSBL_MAX_PARTITIONS) {
- ERROR("BL31: ATF handoff params: too many partitions (%u/%u)\n",
- ATFHandoffParams->num_entries, FSBL_MAX_PARTITIONS);
+ VERBOSE("BL31: TF-A handoff params at:0x%" PRIx64 ", entries:%u\n",
+ tfa_handoff_addr, TFAHandoffParams->num_entries);
+ if (TFAHandoffParams->num_entries > FSBL_MAX_PARTITIONS) {
+ ERROR("BL31: TF-A handoff params: too many partitions (%u/%u)\n",
+ TFAHandoffParams->num_entries, FSBL_MAX_PARTITIONS);
return FSBL_HANDOFF_TOO_MANY_PARTS;
}
@@ -174,29 +175,29 @@
* (bl32, bl33). I.e. the last applicable images in the handoff
* structure will be used for the hand off
*/
- for (size_t i = 0; i < ATFHandoffParams->num_entries; i++) {
+ for (size_t i = 0; i < TFAHandoffParams->num_entries; i++) {
entry_point_info_t *image;
int32_t target_estate, target_secure, target_cpu;
uint32_t target_endianness, target_el;
VERBOSE("BL31: %zd: entry:0x%" PRIx64 ", flags:0x%" PRIx64 "\n", i,
- ATFHandoffParams->partition[i].entry_point,
- ATFHandoffParams->partition[i].flags);
+ TFAHandoffParams->partition[i].entry_point,
+ TFAHandoffParams->partition[i].flags);
- target_cpu = get_fsbl_cpu(&ATFHandoffParams->partition[i]);
+ target_cpu = get_fsbl_cpu(&TFAHandoffParams->partition[i]);
if (target_cpu != FSBL_FLAGS_A53_0) {
WARN("BL31: invalid target CPU (%i)\n", target_cpu);
continue;
}
- target_el = get_fsbl_el(&ATFHandoffParams->partition[i]);
+ target_el = get_fsbl_el(&TFAHandoffParams->partition[i]);
if ((target_el == FSBL_FLAGS_EL3) ||
(target_el == FSBL_FLAGS_EL0)) {
WARN("BL31: invalid exception level (%i)\n", target_el);
continue;
}
- target_secure = get_fsbl_ss(&ATFHandoffParams->partition[i]);
+ target_secure = get_fsbl_ss(&TFAHandoffParams->partition[i]);
if (target_secure == FSBL_FLAGS_SECURE &&
target_el == FSBL_FLAGS_EL2) {
WARN("BL31: invalid security state (%i) for exception level (%i)\n",
@@ -204,8 +205,8 @@
continue;
}
- target_estate = get_fsbl_estate(&ATFHandoffParams->partition[i]);
- target_endianness = get_fsbl_endian(&ATFHandoffParams->partition[i]);
+ target_estate = get_fsbl_estate(&TFAHandoffParams->partition[i]);
+ target_endianness = get_fsbl_endian(&TFAHandoffParams->partition[i]);
if (target_secure == FSBL_FLAGS_SECURE) {
image = bl32;
@@ -245,9 +246,9 @@
VERBOSE("Setting up %s entry point to:%" PRIx64 ", el:%x\n",
target_secure == FSBL_FLAGS_SECURE ? "BL32" : "BL33",
- ATFHandoffParams->partition[i].entry_point,
+ TFAHandoffParams->partition[i].entry_point,
target_el);
- image->pc = ATFHandoffParams->partition[i].entry_point;
+ image->pc = TFAHandoffParams->partition[i].entry_point;
if (target_endianness == SPSR_E_BIG) {
EP_SET_EE(image->h.attr, EP_EE_BIG);
diff --git a/plat/xilinx/common/pm_service/pm_api_sys.c b/plat/xilinx/common/pm_service/pm_api_sys.c
index 2f47cca..dcdd2dc 100644
--- a/plat/xilinx/common/pm_service/pm_api_sys.c
+++ b/plat/xilinx/common/pm_service/pm_api_sys.c
@@ -572,7 +572,7 @@
uint32_t payload[PAYLOAD_ARG_CNT];
uint32_t module_id;
- /* Return version of API which are implemented in ATF only */
+ /* Return version of API which are implemented in TF-A only */
switch (api_id) {
case PM_GET_CALLBACK_DATA:
case PM_GET_TRUSTZONE_VERSION:
diff --git a/plat/xilinx/versal/bl31_versal_setup.c b/plat/xilinx/versal/bl31_versal_setup.c
index 54ebc22..e5e095a 100644
--- a/plat/xilinx/versal/bl31_versal_setup.c
+++ b/plat/xilinx/versal/bl31_versal_setup.c
@@ -67,10 +67,10 @@
void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
- uint64_t atf_handoff_addr;
- uint32_t payload[PAYLOAD_ARG_CNT], max_size = ATF_HANDOFF_PARAMS_MAX_SIZE;
+ uint64_t tfa_handoff_addr;
+ uint32_t payload[PAYLOAD_ARG_CNT], max_size = TFA_HANDOFF_PARAMS_MAX_SIZE;
enum pm_ret_status ret_status;
- uint64_t addr[ATF_HANDOFF_PARAMS_MAX_SIZE];
+ uint64_t addr[TFA_HANDOFF_PARAMS_MAX_SIZE];
if (VERSAL_CONSOLE_IS(pl011) || (VERSAL_CONSOLE_IS(pl011_1))) {
static console_t versal_runtime_console;
@@ -119,15 +119,15 @@
ret_status = pm_ipi_send_sync(primary_proc, payload, NULL, 0);
if (ret_status == PM_RET_SUCCESS) {
INFO("BL31: GET_HANDOFF_PARAMS call success=%d\n", ret_status);
- atf_handoff_addr = (uintptr_t)&addr;
+ tfa_handoff_addr = (uintptr_t)&addr;
} else {
- ERROR("BL31: GET_HANDOFF_PARAMS Failed, read atf_handoff_addr from reg\n");
- atf_handoff_addr = mmio_read_32(PMC_GLOBAL_GLOB_GEN_STORAGE4);
+ ERROR("BL31: GET_HANDOFF_PARAMS Failed, read tfa_handoff_addr from reg\n");
+ tfa_handoff_addr = mmio_read_32(PMC_GLOBAL_GLOB_GEN_STORAGE4);
}
- enum fsbl_handoff ret = fsbl_atf_handover(&bl32_image_ep_info,
+ enum fsbl_handoff ret = fsbl_tfa_handover(&bl32_image_ep_info,
&bl33_image_ep_info,
- atf_handoff_addr);
+ tfa_handoff_addr);
if (ret == FSBL_HANDOFF_NO_STRUCT || ret == FSBL_HANDOFF_INVAL_STRUCT) {
bl31_set_default_config();
} else if (ret == FSBL_HANDOFF_TOO_MANY_PARTS) {
diff --git a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
index 3598b53..b00513e 100644
--- a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
+++ b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
@@ -71,7 +71,7 @@
void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
- uint64_t atf_handoff_addr;
+ uint64_t tfa_handoff_addr;
if (ZYNQMP_CONSOLE_IS(cadence) || (ZYNQMP_CONSOLE_IS(cadence1))) {
/* Register the console to provide early debug support */
@@ -107,15 +107,15 @@
SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0);
SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
- atf_handoff_addr = mmio_read_32(PMU_GLOBAL_GEN_STORAGE6);
+ tfa_handoff_addr = mmio_read_32(PMU_GLOBAL_GEN_STORAGE6);
if (zynqmp_get_bootmode() == ZYNQMP_BOOTMODE_JTAG) {
bl31_set_default_config();
} else {
/* use parameters from FSBL */
- enum fsbl_handoff ret = fsbl_atf_handover(&bl32_image_ep_info,
+ enum fsbl_handoff ret = fsbl_tfa_handover(&bl32_image_ep_info,
&bl33_image_ep_info,
- atf_handoff_addr);
+ tfa_handoff_addr);
if (ret != FSBL_HANDOFF_SUCCESS) {
panic();
}
diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c b/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c
index 54b1f7a..afd664e 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c
@@ -727,7 +727,7 @@
* pm_update_ioctl_bitmask() - API to get supported IOCTL ID mask
* @bit_mask Returned bit mask of supported IOCTL IDs
*/
-enum pm_ret_status atf_ioctl_bitmask(uint32_t *bit_mask)
+enum pm_ret_status tfa_ioctl_bitmask(uint32_t *bit_mask)
{
uint8_t supported_ids[] = {
IOCTL_GET_RPU_OPER_MODE,
diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.h b/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.h
index 27056ba..6b094db 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.h
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.h
@@ -55,5 +55,5 @@
uint32_t arg1,
uint32_t arg2,
uint32_t *value);
-enum pm_ret_status atf_ioctl_bitmask(uint32_t *bit_mask);
+enum pm_ret_status tfa_ioctl_bitmask(uint32_t *bit_mask);
#endif /* PM_API_IOCTL_H */
diff --git a/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.c b/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.c
index 85e1464..75cb54f 100644
--- a/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.c
+++ b/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.c
@@ -38,7 +38,7 @@
/**
* struct eemi_api_dependency - Dependent EEMI APIs which are implemented
- * on both the ATF and firmware
+ * on both the TF-A and firmware
*
* @id: EEMI API id or IOCTL id to be checked
* @api_id: Dependent EEMI API
@@ -48,7 +48,7 @@
uint8_t api_id;
} eemi_api_dependency;
-/* Dependent APIs for ATF to check their version from firmware */
+/* Dependent APIs for TF-A to check their version from firmware */
static const eemi_api_dependency api_dep_table[] = {
{
.id = PM_SELF_SUSPEND,
@@ -216,8 +216,8 @@
},
};
-/* Expected firmware API version to ATF */
-static const uint8_t atf_expected_ver_id[] = {
+/* Expected firmware API version to TF-A */
+static const uint8_t tfa_expected_ver_id[] = {
[PM_SELF_SUSPEND] = FW_API_BASE_VERSION,
[PM_REQ_WAKEUP] = FW_API_BASE_VERSION,
[PM_ABORT_SUSPEND] = FW_API_BASE_VERSION,
@@ -764,8 +764,8 @@
return ret;
}
- /* Check if fw version matches ATF expected version */
- if (version != atf_expected_ver_id[api_dep_table[i].api_id]) {
+ /* Check if fw version matches TF-A expected version */
+ if (version != tfa_expected_ver_id[api_dep_table[i].api_id]) {
return PM_RET_ERROR_NOTSUPPORTED;
}
}
@@ -775,13 +775,13 @@
}
/**
- * feature_check_atf() - These are API's completely implemented in ATF
+ * feature_check_tfa() - These are API's completely implemented in TF-A
* @api_id API ID to check
* @version Returned supported API version
*
* @return Returns status, either success or error+reason
*/
-static enum pm_ret_status feature_check_atf(uint32_t api_id, uint32_t *version,
+static enum pm_ret_status feature_check_tfa(uint32_t api_id, uint32_t *version,
uint32_t *bit_mask)
{
switch (api_id) {
@@ -793,7 +793,7 @@
case PM_GET_CALLBACK_DATA:
case PM_GET_TRUSTZONE_VERSION:
case PM_SET_SUSPEND_MODE:
- *version = ATF_API_BASE_VERSION;
+ *version = TFA_API_BASE_VERSION;
return PM_RET_SUCCESS;
default:
return PM_RET_ERROR_NO_FEATURE;
@@ -801,14 +801,14 @@
}
/**
- * get_atf_version_for_partial_apis() - Return ATF version for partially
+ * get_tfa_version_for_partial_apis() - Return TF-A version for partially
* implemented APIs
* @api_id API ID to check
* @version Returned supported API version
*
* @return Returns status, either success or error+reason
*/
-static enum pm_ret_status get_atf_version_for_partial_apis(uint32_t api_id,
+static enum pm_ret_status get_tfa_version_for_partial_apis(uint32_t api_id,
uint32_t *version)
{
switch (api_id) {
@@ -830,7 +830,7 @@
case PM_PLL_SET_MODE:
case PM_PLL_GET_MODE:
case PM_REGISTER_ACCESS:
- *version = ATF_API_BASE_VERSION;
+ *version = TFA_API_BASE_VERSION;
return PM_RET_SUCCESS;
case PM_FEATURE_CHECK:
*version = FW_API_VERSION_2;
@@ -842,7 +842,7 @@
/**
* feature_check_partial() - These are API's partially implemented in
- * ATF and firmware both
+ * TF-A and firmware both
* @api_id API ID to check
* @version Returned supported API version
*
@@ -877,7 +877,7 @@
if (status != PM_RET_SUCCESS) {
return status;
}
- return get_atf_version_for_partial_apis(api_id, version);
+ return get_tfa_version_for_partial_apis(api_id, version);
default:
return PM_RET_ERROR_NO_FEATURE;
}
@@ -898,13 +898,13 @@
uint32_t ret_payload[PAYLOAD_ARG_CNT] = {0U};
uint32_t status;
- /* Get API version implemented in ATF */
- status = feature_check_atf(api_id, version, bit_mask);
+ /* Get API version implemented in TF-A */
+ status = feature_check_tfa(api_id, version, bit_mask);
if (status != PM_RET_ERROR_NO_FEATURE) {
return status;
}
- /* Get API version implemented by firmware and ATF both */
+ /* Get API version implemented by firmware and TF-A both */
status = feature_check_partial(api_id, version);
if (status != PM_RET_ERROR_NO_FEATURE) {
return status;
@@ -913,7 +913,7 @@
/* Get API version implemented by firmware */
status = fw_api_version(api_id, ret_payload, 3);
/* IOCTL call may return failure whose ID is not implemented in
- * firmware but implemented in ATF
+ * firmware but implemented in TF-A
*/
if ((api_id != PM_IOCTL) && (status != PM_RET_SUCCESS)) {
return status;
@@ -921,7 +921,7 @@
*version = ret_payload[0];
- /* Update IOCTL bit mask which are implemented in ATF */
+ /* Update IOCTL bit mask which are implemented in TF-A */
if ((api_id == PM_IOCTL) || (api_id == PM_GET_OP_CHARACTERISTIC)) {
if (len < 2) {
return PM_RET_ERROR_ARGS;
@@ -929,8 +929,8 @@
bit_mask[0] = ret_payload[1];
bit_mask[1] = ret_payload[2];
if (api_id == PM_IOCTL) {
- /* Get IOCTL's implemented by ATF */
- status = atf_ioctl_bitmask(bit_mask);
+ /* Get IOCTL's implemented by TF-A */
+ status = tfa_ioctl_bitmask(bit_mask);
}
} else {
/* Requires for MISRA */
diff --git a/plat/xilinx/zynqmp/pm_service/zynqmp_pm_defs.h b/plat/xilinx/zynqmp/pm_service/zynqmp_pm_defs.h
index 658e9eb..6dff07e 100644
--- a/plat/xilinx/zynqmp/pm_service/zynqmp_pm_defs.h
+++ b/plat/xilinx/zynqmp/pm_service/zynqmp_pm_defs.h
@@ -30,8 +30,8 @@
#define FW_API_BASE_VERSION (1U)
/* Expected version of firmware API for feature check */
#define FW_API_VERSION_2 (2U)
-/* Version of APIs implemented in ATF */
-#define ATF_API_BASE_VERSION (1U)
+/* Version of APIs implemented in TF-A */
+#define TFA_API_BASE_VERSION (1U)
/* Updating the QUERY_DATA API versioning as the bitmask functionality
* support is added in the v2.*/
#define TFA_API_QUERY_DATA_VERSION (2U)
diff --git a/plat/xilinx/zynqmp/pm_service/zynqmp_pm_svc_main.c b/plat/xilinx/zynqmp/pm_service/zynqmp_pm_svc_main.c
index 7b15443..54b0007 100644
--- a/plat/xilinx/zynqmp/pm_service/zynqmp_pm_svc_main.c
+++ b/plat/xilinx/zynqmp/pm_service/zynqmp_pm_svc_main.c
@@ -95,7 +95,7 @@
*
* When WDT event is received in PMU, PMU needs to notify master to do cleanup
* if required. PMU sets up timer and starts timer to overflow in zero time upon
- * WDT event. ATF handles this timer event and takes necessary action required
+ * WDT event. TF-A handles this timer event and takes necessary action required
* for warm restart.
*
* In presence of non-secure software layers (EL1/2) sets the interrupt
@@ -131,7 +131,7 @@
*
* Function registered as INTR_TYPE_EL3 interrupt handler
*
- * On receiving WDT event from PMU, ATF generates SGI7 to all running CPUs.
+ * On receiving WDT event from PMU, TF-A generates SGI7 to all running CPUs.
* In response to SGI7 interrupt, each CPUs do clean up if required and last
* running CPU calls system restart.
*/
diff --git a/plat/xilinx/zynqmp/zynqmp_sdei.c b/plat/xilinx/zynqmp/zynqmp_sdei.c
index 8a6d894..984252e 100644
--- a/plat/xilinx/zynqmp/zynqmp_sdei.c
+++ b/plat/xilinx/zynqmp/zynqmp_sdei.c
@@ -16,7 +16,10 @@
int arm_validate_ns_entrypoint(uintptr_t entrypoint)
{
- return (entrypoint < BL31_BASE || entrypoint > BL31_LIMIT) ? 0 : -1;
+ uint64_t base = BL31_BASE;
+ uint64_t limit = BL31_LIMIT;
+
+ return (entrypoint < base || entrypoint > limit) ? 0 : -1;
}
/* Private event mappings */
diff --git a/poetry.lock b/poetry.lock
index 92b38da..07cd572 100644
--- a/poetry.lock
+++ b/poetry.lock
@@ -1,10 +1,9 @@
-# This file is automatically @generated by Poetry and should not be changed by hand.
+# This file is automatically @generated by Poetry 1.5.0 and should not be changed by hand.
[[package]]
name = "alabaster"
version = "0.7.13"
description = "A configurable sidebar-enabled Sphinx theme"
-category = "dev"
optional = false
python-versions = ">=3.6"
files = [
@@ -16,7 +15,6 @@
name = "anytree"
version = "2.8.0"
description = "Powerful and Lightweight Python Tree Data Structure.."
-category = "dev"
optional = false
python-versions = "*"
files = [
@@ -35,7 +33,6 @@
name = "babel"
version = "2.12.1"
description = "Internationalization utilities"
-category = "dev"
optional = false
python-versions = ">=3.7"
files = [
@@ -50,7 +47,6 @@
name = "build"
version = "0.10.0"
description = "A simple, correct Python build frontend"
-category = "dev"
optional = false
python-versions = ">= 3.7"
files = [
@@ -74,7 +70,6 @@
name = "certifi"
version = "2022.12.7"
description = "Python package for providing Mozilla's CA Bundle."
-category = "dev"
optional = false
python-versions = ">=3.6"
files = [
@@ -86,7 +81,6 @@
name = "charset-normalizer"
version = "3.1.0"
description = "The Real First Universal Charset Detector. Open, modern and actively maintained alternative to Chardet."
-category = "dev"
optional = false
python-versions = ">=3.7.0"
files = [
@@ -171,7 +165,6 @@
name = "click"
version = "8.1.3"
description = "Composable command line interface toolkit"
-category = "dev"
optional = false
python-versions = ">=3.7"
files = [
@@ -186,7 +179,6 @@
name = "colorama"
version = "0.4.6"
description = "Cross-platform colored terminal text."
-category = "dev"
optional = false
python-versions = "!=3.0.*,!=3.1.*,!=3.2.*,!=3.3.*,!=3.4.*,!=3.5.*,!=3.6.*,>=2.7"
files = [
@@ -198,7 +190,6 @@
name = "docutils"
version = "0.18.1"
description = "Docutils -- Python Documentation Utilities"
-category = "dev"
optional = false
python-versions = ">=2.7, !=3.0.*, !=3.1.*, !=3.2.*, !=3.3.*, !=3.4.*"
files = [
@@ -210,7 +201,6 @@
name = "idna"
version = "3.4"
description = "Internationalized Domain Names in Applications (IDNA)"
-category = "dev"
optional = false
python-versions = ">=3.5"
files = [
@@ -222,7 +212,6 @@
name = "imagesize"
version = "1.4.1"
description = "Getting image size from png/jpeg/jpeg2000/gif file"
-category = "dev"
optional = false
python-versions = ">=2.7, !=3.0.*, !=3.1.*, !=3.2.*, !=3.3.*"
files = [
@@ -234,7 +223,6 @@
name = "importlib-metadata"
version = "6.6.0"
description = "Read metadata from Python packages"
-category = "dev"
optional = false
python-versions = ">=3.7"
files = [
@@ -254,7 +242,6 @@
name = "jinja2"
version = "3.1.2"
description = "A very fast and expressive template engine."
-category = "dev"
optional = false
python-versions = ">=3.7"
files = [
@@ -272,7 +259,6 @@
name = "markdown-it-py"
version = "2.2.0"
description = "Python port of markdown-it. Markdown parsing, done right!"
-category = "dev"
optional = false
python-versions = ">=3.7"
files = [
@@ -297,7 +283,6 @@
name = "markupsafe"
version = "2.1.2"
description = "Safely add untrusted strings to HTML/XML markup."
-category = "dev"
optional = false
python-versions = ">=3.7"
files = [
@@ -357,7 +342,6 @@
name = "mdit-py-plugins"
version = "0.3.5"
description = "Collection of plugins for markdown-it-py"
-category = "dev"
optional = false
python-versions = ">=3.7"
files = [
@@ -377,7 +361,6 @@
name = "mdurl"
version = "0.1.2"
description = "Markdown URL utilities"
-category = "dev"
optional = false
python-versions = ">=3.7"
files = [
@@ -389,7 +372,6 @@
name = "myst-parser"
version = "0.18.1"
description = "An extended commonmark compliant parser, with bridges to docutils & sphinx."
-category = "dev"
optional = false
python-versions = ">=3.7"
files = [
@@ -416,7 +398,6 @@
name = "packaging"
version = "23.1"
description = "Core utilities for Python packages"
-category = "dev"
optional = false
python-versions = ">=3.7"
files = [
@@ -428,7 +409,6 @@
name = "pip"
version = "23.1.2"
description = "The PyPA recommended tool for installing Python packages."
-category = "dev"
optional = false
python-versions = ">=3.7"
files = [
@@ -440,7 +420,6 @@
name = "pip-tools"
version = "6.13.0"
description = "pip-tools keeps your pinned dependencies fresh."
-category = "dev"
optional = false
python-versions = ">=3.7"
files = [
@@ -463,7 +442,6 @@
name = "prettytable"
version = "3.7.0"
description = "A simple Python library for easily displaying tabular data in a visually appealing ASCII table format"
-category = "dev"
optional = false
python-versions = ">=3.7"
files = [
@@ -481,7 +459,6 @@
name = "pyelftools"
version = "0.29"
description = "Library for analyzing ELF files and DWARF debugging information"
-category = "dev"
optional = false
python-versions = "*"
files = [
@@ -493,7 +470,6 @@
name = "pygments"
version = "2.15.1"
description = "Pygments is a syntax highlighting package written in Python."
-category = "dev"
optional = false
python-versions = ">=3.7"
files = [
@@ -508,7 +484,6 @@
name = "pyproject-hooks"
version = "1.0.0"
description = "Wrappers to call pyproject.toml-based build backend hooks."
-category = "dev"
optional = false
python-versions = ">=3.7"
files = [
@@ -523,7 +498,6 @@
name = "pytz"
version = "2023.3"
description = "World timezone definitions, modern and historical"
-category = "dev"
optional = false
python-versions = "*"
files = [
@@ -535,7 +509,6 @@
name = "pyyaml"
version = "6.0"
description = "YAML parser and emitter for Python"
-category = "dev"
optional = false
python-versions = ">=3.6"
files = [
@@ -585,7 +558,6 @@
name = "requests"
version = "2.30.0"
description = "Python HTTP for Humans."
-category = "dev"
optional = false
python-versions = ">=3.7"
files = [
@@ -607,7 +579,6 @@
name = "setuptools"
version = "67.7.2"
description = "Easily download, build, install, upgrade, and uninstall Python packages"
-category = "dev"
optional = false
python-versions = ">=3.7"
files = [
@@ -624,7 +595,6 @@
name = "six"
version = "1.16.0"
description = "Python 2 and 3 compatibility utilities"
-category = "dev"
optional = false
python-versions = ">=2.7, !=3.0.*, !=3.1.*, !=3.2.*"
files = [
@@ -636,7 +606,6 @@
name = "snowballstemmer"
version = "2.2.0"
description = "This package provides 29 stemmers for 28 languages generated from Snowball algorithms."
-category = "dev"
optional = false
python-versions = "*"
files = [
@@ -648,7 +617,6 @@
name = "sphinx"
version = "5.3.0"
description = "Python documentation generator"
-category = "dev"
optional = false
python-versions = ">=3.6"
files = [
@@ -684,7 +652,6 @@
name = "sphinx-rtd-theme"
version = "1.2.0"
description = "Read the Docs theme for Sphinx"
-category = "dev"
optional = false
python-versions = "!=3.0.*,!=3.1.*,!=3.2.*,!=3.3.*,!=3.4.*,!=3.5.*,>=2.7"
files = [
@@ -704,7 +671,6 @@
name = "sphinxcontrib-applehelp"
version = "1.0.4"
description = "sphinxcontrib-applehelp is a Sphinx extension which outputs Apple help books"
-category = "dev"
optional = false
python-versions = ">=3.8"
files = [
@@ -720,7 +686,6 @@
name = "sphinxcontrib-devhelp"
version = "1.0.2"
description = "sphinxcontrib-devhelp is a sphinx extension which outputs Devhelp document."
-category = "dev"
optional = false
python-versions = ">=3.5"
files = [
@@ -736,7 +701,6 @@
name = "sphinxcontrib-htmlhelp"
version = "2.0.1"
description = "sphinxcontrib-htmlhelp is a sphinx extension which renders HTML help files"
-category = "dev"
optional = false
python-versions = ">=3.8"
files = [
@@ -752,7 +716,6 @@
name = "sphinxcontrib-jquery"
version = "4.1"
description = "Extension to include jQuery on newer Sphinx releases"
-category = "dev"
optional = false
python-versions = ">=2.7"
files = [
@@ -767,7 +730,6 @@
name = "sphinxcontrib-jsmath"
version = "1.0.1"
description = "A sphinx extension which renders display math in HTML via JavaScript"
-category = "dev"
optional = false
python-versions = ">=3.5"
files = [
@@ -782,7 +744,6 @@
name = "sphinxcontrib-plantuml"
version = "0.24.1"
description = "Sphinx \"plantuml\" extension"
-category = "dev"
optional = false
python-versions = "*"
files = [
@@ -799,7 +760,6 @@
name = "sphinxcontrib-qthelp"
version = "1.0.3"
description = "sphinxcontrib-qthelp is a sphinx extension which outputs QtHelp document."
-category = "dev"
optional = false
python-versions = ">=3.5"
files = [
@@ -815,7 +775,6 @@
name = "sphinxcontrib-serializinghtml"
version = "1.1.5"
description = "sphinxcontrib-serializinghtml is a sphinx extension which outputs \"serialized\" HTML files (json and pickle)."
-category = "dev"
optional = false
python-versions = ">=3.5"
files = [
@@ -828,10 +787,26 @@
test = ["pytest"]
[[package]]
+name = "sphinxcontrib-svg2pdfconverter"
+version = "1.2.2"
+description = "Sphinx SVG to PDF converter extension"
+optional = false
+python-versions = "~=3.4"
+files = [
+ {file = "sphinxcontrib-svg2pdfconverter-1.2.2.tar.gz", hash = "sha256:80a55ca61f70eae93efc65f3814f2f177c86ba55934a9f6c5022f1778b62146b"},
+ {file = "sphinxcontrib_svg2pdfconverter-1.2.2-py3-none-any.whl", hash = "sha256:04ec767b55780a6b18d89cc1a8ada6d900c6efde9d1683abdb98a49b144465ca"},
+]
+
+[package.dependencies]
+Sphinx = ">=1.6.3"
+
+[package.extras]
+cairosvg = ["cairosvg (>=1.0)"]
+
+[[package]]
name = "tomli"
version = "2.0.1"
description = "A lil' TOML parser"
-category = "dev"
optional = false
python-versions = ">=3.7"
files = [
@@ -843,7 +818,6 @@
name = "typing-extensions"
version = "4.5.0"
description = "Backported and Experimental Type Hints for Python 3.7+"
-category = "dev"
optional = false
python-versions = ">=3.7"
files = [
@@ -855,7 +829,6 @@
name = "urllib3"
version = "2.0.2"
description = "HTTP library with thread-safe connection pooling, file post, and more."
-category = "dev"
optional = false
python-versions = ">=3.7"
files = [
@@ -873,7 +846,6 @@
name = "wcwidth"
version = "0.2.6"
description = "Measures the displayed width of unicode strings in a terminal"
-category = "dev"
optional = false
python-versions = "*"
files = [
@@ -885,7 +857,6 @@
name = "wheel"
version = "0.40.0"
description = "A built-package format for Python"
-category = "dev"
optional = false
python-versions = ">=3.7"
files = [
@@ -900,7 +871,6 @@
name = "zipp"
version = "3.15.0"
description = "Backport of pathlib-compatible object wrapper for zip files"
-category = "dev"
optional = false
python-versions = ">=3.7"
files = [
@@ -915,4 +885,4 @@
[metadata]
lock-version = "2.0"
python-versions = "^3.8"
-content-hash = "9c25ef33612d10c7caafa551a3cf6a12753167c6400f49cc261fddd18c7eaf6e"
+content-hash = "62d9ce9ca1c9f4669c7b40724acfc93968cde31c0460d1d7515d289739dc9464"
diff --git a/pyproject.toml b/pyproject.toml
index 44e78d3..19ba4d8 100644
--- a/pyproject.toml
+++ b/pyproject.toml
@@ -21,6 +21,7 @@
sphinxcontrib-plantuml = "^0.24.1"
sphinx-rtd-theme = "^1.1.1"
pip-tools = "^6.4.0"
+sphinxcontrib-svg2pdfconverter = "^1.2.2"
[tool.poetry.group.ci.dependencies]
click = "^8.1.3"
diff --git a/services/std_svc/errata_abi/cpu_errata_info.h b/services/std_svc/errata_abi/cpu_errata_info.h
index 671a694..00a3b73 100644
--- a/services/std_svc/errata_abi/cpu_errata_info.h
+++ b/services/std_svc/errata_abi/cpu_errata_info.h
@@ -25,7 +25,7 @@
#include <cortex_a78.h>
#include <cortex_a78_ae.h>
#include <cortex_a78c.h>
-#include <cortex_makalu.h>
+#include <cortex_a715.h>
#include <cortex_x1.h>
#include <cortex_x2.h>
#include <neoverse_n1.h>
diff --git a/services/std_svc/errata_abi/errata_abi_main.c b/services/std_svc/errata_abi/errata_abi_main.c
index bf9409d..bc176c6 100644
--- a/services/std_svc/errata_abi/errata_abi_main.c
+++ b/services/std_svc/errata_abi/errata_abi_main.c
@@ -406,7 +406,7 @@
#if CORTEX_A715_H_INC
{
- .cpu_partnumber = CORTEX_MAKALU_MIDR,
+ .cpu_partnumber = CORTEX_A715_MIDR,
.cpu_errata_list = {
[0] = {2701951, 0x00, 0x11, ERRATA_A715_2701951, \
ERRATA_NON_ARM_INTERCONNECT},
diff --git a/services/std_svc/spm/el3_spmc/spmc_shared_mem.c b/services/std_svc/spm/el3_spmc/spmc_shared_mem.c
index 1f8e7ff..8183a0a 100644
--- a/services/std_svc/spm/el3_spmc/spmc_shared_mem.c
+++ b/services/std_svc/spm/el3_spmc/spmc_shared_mem.c
@@ -80,6 +80,13 @@
return NULL;
}
+ /* Ensure that descriptor size is aligned */
+ if (!is_aligned(desc_size, 16)) {
+ WARN("%s(0x%zx) desc_size not 16-byte aligned\n",
+ __func__, desc_size);
+ return NULL;
+ }
+
obj_size = spmc_shmem_obj_size(desc_size);
/* Ensure the obj size has not overflowed. */
@@ -248,25 +255,6 @@
}
/**
- * spmc_shmem_obj_ffa_constituent_size - Calculate variable size part of obj.
- * @obj: Object containing ffa_memory_region_descriptor.
- *
- * Return: Size of ffa_constituent_memory_region_descriptors in @obj.
- */
-static size_t
-spmc_shmem_obj_ffa_constituent_size(struct spmc_shmem_obj *obj,
- uint32_t ffa_version)
-{
- struct ffa_comp_mrd *comp_mrd;
-
- comp_mrd = spmc_shmem_obj_get_comp_mrd(obj, ffa_version);
- if (comp_mrd == NULL) {
- return 0;
- }
- return comp_mrd->address_range_count * sizeof(struct ffa_cons_mrd);
-}
-
-/**
* spmc_shmem_obj_validate_id - Validate a partition ID is participating in
* a given memory transaction.
* @sp_id: Partition ID to validate.
@@ -371,10 +359,10 @@
*
* Return: the size required to store the descriptor store in the v1.1 format.
*/
-static size_t
+static uint64_t
spmc_shm_get_v1_1_descriptor_size(struct ffa_mtd_v1_0 *orig, size_t desc_size)
{
- size_t size = 0;
+ uint64_t size = 0;
struct ffa_comp_mrd *mrd;
struct ffa_emad_v1_0 *emad_array = orig->emad;
@@ -391,11 +379,7 @@
mrd = (struct ffa_comp_mrd *) ((uint8_t *) orig +
emad_array[0].comp_mrd_offset);
- /* Check the calculated address is within the memory descriptor. */
- if (((uintptr_t) mrd + sizeof(struct ffa_comp_mrd)) >
- (uintptr_t)((uint8_t *) orig + desc_size)) {
- return 0;
- }
+ /* Add the size of the memory region descriptors. */
size += mrd->address_range_count * sizeof(struct ffa_cons_mrd);
return size;
@@ -776,51 +760,75 @@
return 0;
}
+static inline const struct ffa_emad_v1_0 *
+emad_advance(const struct ffa_emad_v1_0 *emad, size_t offset)
+{
+ return (const struct ffa_emad_v1_0 *)((const uint8_t *)emad + offset);
+}
+
/**
* spmc_shmem_check_obj - Check that counts in descriptor match overall size.
* @obj: Object containing ffa_memory_region_descriptor.
* @ffa_version: FF-A version of the provided descriptor.
*
- * Return: 0 if object is valid, -EINVAL if constituent_memory_region_descriptor
- * offset or count is invalid.
+ * Return: 0 if object is valid, FFA_ERROR_INVALID_PARAMETER if
+ * constituent_memory_region_descriptor offset or count is invalid.
*/
static int spmc_shmem_check_obj(struct spmc_shmem_obj *obj,
uint32_t ffa_version)
{
+ const struct ffa_emad_v1_0 *first_emad;
+ const struct ffa_emad_v1_0 *end_emad;
+ size_t emad_size;
uint32_t comp_mrd_offset = 0;
- if (obj->desc.emad_count == 0U) {
- WARN("%s: unsupported attribute desc count %u.\n",
- __func__, obj->desc.emad_count);
- return -EINVAL;
+ if (obj->desc_filled != obj->desc_size) {
+ ERROR("BUG: %s called on incomplete object (%zu != %zu)\n",
+ __func__, obj->desc_filled, obj->desc_size);
+ panic();
}
- for (size_t emad_num = 0; emad_num < obj->desc.emad_count; emad_num++) {
+ if (spmc_validate_mtd_start(&obj->desc, ffa_version,
+ obj->desc_filled, obj->desc_size)) {
+ ERROR("BUG: %s called on object with corrupt memory region descriptor\n",
+ __func__);
+ panic();
+ }
+
+ first_emad = spmc_shmem_obj_get_emad(&obj->desc, 0,
+ ffa_version, &emad_size);
+ end_emad = emad_advance(first_emad, obj->desc.emad_count * emad_size);
+
+ /* Loop through the endpoint descriptors, validating each of them. */
+ for (const struct ffa_emad_v1_0 *emad = first_emad;
+ emad < end_emad;
+ emad = emad_advance(emad, emad_size)) {
size_t size;
size_t count;
size_t expected_size;
- size_t total_page_count;
- size_t emad_size;
+ uint64_t total_page_count;
size_t header_emad_size;
uint32_t offset;
struct ffa_comp_mrd *comp;
- struct ffa_emad_v1_0 *emad;
+ ffa_endpoint_id16_t ep_id;
- emad = spmc_shmem_obj_get_emad(&obj->desc, emad_num,
- ffa_version, &emad_size);
+ offset = emad->comp_mrd_offset;
/*
- * Validate the calculated emad address resides within the
- * descriptor.
+ * If a partition ID resides in the secure world validate that
+ * the partition ID is for a known partition. Ignore any
+ * partition ID belonging to the normal world as it is assumed
+ * the Hypervisor will have validated these.
*/
- if ((uintptr_t) emad >=
- (uintptr_t)((uint8_t *) &obj->desc + obj->desc_size)) {
- WARN("Invalid emad access.\n");
- return -EINVAL;
+ ep_id = emad->mapd.endpoint_id;
+ if (ffa_is_secure_world_id(ep_id)) {
+ if (spmc_get_sp_ctx(ep_id) == NULL) {
+ WARN("%s: Invalid receiver id 0x%x\n",
+ __func__, ep_id);
+ return FFA_ERROR_INVALID_PARAMETER;
+ }
}
- offset = emad->comp_mrd_offset;
-
/*
* The offset provided to the composite memory region descriptor
* should be consistent across endpoint descriptors. Store the
@@ -832,7 +840,7 @@
if (comp_mrd_offset != offset) {
ERROR("%s: mismatching offsets provided, %u != %u\n",
__func__, offset, comp_mrd_offset);
- return -EINVAL;
+ return FFA_ERROR_INVALID_PARAMETER;
}
continue; /* Remainder only executed on first iteration. */
}
@@ -843,7 +851,7 @@
if (offset < header_emad_size) {
WARN("%s: invalid object, offset %u < header + emad %zu\n",
__func__, offset, header_emad_size);
- return -EINVAL;
+ return FFA_ERROR_INVALID_PARAMETER;
}
size = obj->desc_size;
@@ -851,14 +859,14 @@
if (offset > size) {
WARN("%s: invalid object, offset %u > total size %zu\n",
__func__, offset, obj->desc_size);
- return -EINVAL;
+ return FFA_ERROR_INVALID_PARAMETER;
}
size -= offset;
if (size < sizeof(struct ffa_comp_mrd)) {
WARN("%s: invalid object, offset %u, total size %zu, no header space.\n",
__func__, offset, obj->desc_size);
- return -EINVAL;
+ return FFA_ERROR_INVALID_PARAMETER;
}
size -= sizeof(struct ffa_comp_mrd);
@@ -868,23 +876,22 @@
if (comp == NULL) {
WARN("%s: invalid comp_mrd offset\n", __func__);
- return -EINVAL;
+ return FFA_ERROR_INVALID_PARAMETER;
}
if (comp->address_range_count != count) {
WARN("%s: invalid object, desc count %u != %zu\n",
__func__, comp->address_range_count, count);
- return -EINVAL;
+ return FFA_ERROR_INVALID_PARAMETER;
}
expected_size = offset + sizeof(*comp) +
- spmc_shmem_obj_ffa_constituent_size(obj,
- ffa_version);
+ count * sizeof(struct ffa_cons_mrd);
if (expected_size != obj->desc_size) {
WARN("%s: invalid object, computed size %zu != size %zu\n",
__func__, expected_size, obj->desc_size);
- return -EINVAL;
+ return FFA_ERROR_INVALID_PARAMETER;
}
total_page_count = 0;
@@ -894,10 +901,10 @@
comp->address_range_array[i].page_count;
}
if (comp->total_page_count != total_page_count) {
- WARN("%s: invalid object, desc total_page_count %u != %zu\n",
+ WARN("%s: invalid object, desc total_page_count %u != %" PRIu64 "\n",
__func__, comp->total_page_count,
total_page_count);
- return -EINVAL;
+ return FFA_ERROR_INVALID_PARAMETER;
}
}
return 0;
@@ -910,7 +917,8 @@
* the memory is not in a valid state for lending.
* @obj: Object containing ffa_memory_region_descriptor.
*
- * Return: 0 if object is valid, -EINVAL if invalid memory state.
+ * Return: 0 if object is valid, FFA_ERROR_INVALID_PARAMETER if invalid memory
+ * state.
*/
static int spmc_shmem_check_state_obj(struct spmc_shmem_obj *obj,
uint32_t ffa_version)
@@ -923,7 +931,7 @@
ffa_version);
if (requested_mrd == NULL) {
- return -EINVAL;
+ return FFA_ERROR_INVALID_PARAMETER;
}
inflight_obj = spmc_shmem_obj_get_next(&spmc_shmem_obj_state,
@@ -939,11 +947,11 @@
other_mrd = spmc_shmem_obj_get_comp_mrd(inflight_obj,
FFA_VERSION_COMPILED);
if (other_mrd == NULL) {
- return -EINVAL;
+ return FFA_ERROR_INVALID_PARAMETER;
}
if (overlapping_memory_regions(requested_mrd,
other_mrd)) {
- return -EINVAL;
+ return FFA_ERROR_INVALID_PARAMETER;
}
}
@@ -973,9 +981,10 @@
goto err_arg;
}
- if (fragment_length > mbox->rxtx_page_count * PAGE_SIZE_4KB) {
- WARN("%s: bad fragment size %u > %u buffer size\n", __func__,
- fragment_length, mbox->rxtx_page_count * PAGE_SIZE_4KB);
+ CASSERT(sizeof(mbox->rxtx_page_count) == 4, assert_bogus_page_count);
+ if (fragment_length > (uint64_t)mbox->rxtx_page_count * PAGE_SIZE_4KB) {
+ WARN("%s: bad fragment size %u > %" PRIu64 " buffer size\n", __func__,
+ fragment_length, (uint64_t)mbox->rxtx_page_count * PAGE_SIZE_4KB);
ret = FFA_ERROR_INVALID_PARAMETER;
goto err_arg;
}
@@ -1044,32 +1053,9 @@
ret = spmc_shmem_check_obj(obj, ffa_version);
if (ret != 0) {
- ret = FFA_ERROR_INVALID_PARAMETER;
goto err_bad_desc;
}
- /*
- * If a partition ID resides in the secure world validate that the
- * partition ID is for a known partition. Ignore any partition ID
- * belonging to the normal world as it is assumed the Hypervisor will
- * have validated these.
- */
- for (size_t i = 0; i < obj->desc.emad_count; i++) {
- emad = spmc_shmem_obj_get_emad(&obj->desc, i, ffa_version,
- &emad_size);
-
- ffa_endpoint_id16_t ep_id = emad->mapd.endpoint_id;
-
- if (ffa_is_secure_world_id(ep_id)) {
- if (spmc_get_sp_ctx(ep_id) == NULL) {
- WARN("%s: Invalid receiver id 0x%x\n",
- __func__, ep_id);
- ret = FFA_ERROR_INVALID_PARAMETER;
- goto err_bad_desc;
- }
- }
- }
-
/* Ensure partition IDs are not duplicated. */
for (size_t i = 0; i < obj->desc.emad_count; i++) {
emad = spmc_shmem_obj_get_emad(&obj->desc, i, ffa_version,
@@ -1093,7 +1079,6 @@
ret = spmc_shmem_check_state_obj(obj, ffa_version);
if (ret) {
ERROR("%s: invalid memory region descriptor.\n", __func__);
- ret = FFA_ERROR_INVALID_PARAMETER;
goto err_bad_desc;
}
@@ -1106,19 +1091,18 @@
uint64_t mem_handle;
/* Calculate the size that the v1.1 descriptor will required. */
- size_t v1_1_desc_size =
+ uint64_t v1_1_desc_size =
spmc_shm_get_v1_1_descriptor_size((void *) &obj->desc,
obj->desc_size);
- if (v1_1_desc_size == 0U) {
- ERROR("%s: cannot determine size of descriptor.\n",
- __func__);
+ if (v1_1_desc_size > UINT32_MAX) {
+ ret = FFA_ERROR_NO_MEMORY;
goto err_arg;
}
/* Get a new obj to store the v1.1 descriptor. */
v1_1_obj =
- spmc_shmem_obj_alloc(&spmc_shmem_obj_state, v1_1_desc_size);
+ spmc_shmem_obj_alloc(&spmc_shmem_obj_state, (size_t)v1_1_desc_size);
if (!v1_1_obj) {
ret = FFA_ERROR_NO_MEMORY;
@@ -1126,8 +1110,8 @@
}
/* Perform the conversion from v1.0 to v1.1. */
- v1_1_obj->desc_size = v1_1_desc_size;
- v1_1_obj->desc_filled = v1_1_desc_size;
+ v1_1_obj->desc_size = (uint32_t)v1_1_desc_size;
+ v1_1_obj->desc_filled = (uint32_t)v1_1_desc_size;
if (!spmc_shm_convert_shmem_obj_from_v1_0(v1_1_obj, obj)) {
ERROR("%s: Could not convert mtd!\n", __func__);
spmc_shmem_obj_free(&spmc_shmem_obj_state, v1_1_obj);
diff --git a/tools/cert_create/include/cca/cca_cot.h b/tools/cert_create/include/cca/cca_cot.h
index 56585fb..152cb71 100644
--- a/tools/cert_create/include/cca/cca_cot.h
+++ b/tools/cert_create/include/cca/cca_cot.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2022-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -24,6 +24,7 @@
/* Certificate extensions. */
enum {
/* Extensions used in certificates owned by the silicon provider. */
+ CCA_FW_NVCOUNTER_EXT,
TRUSTED_FW_NVCOUNTER_EXT,
TRUSTED_BOOT_FW_HASH_EXT,
TRUSTED_BOOT_FW_CONFIG_HASH_EXT,
diff --git a/tools/cert_create/include/ext.h b/tools/cert_create/include/ext.h
index 0e7f3be..1d55486 100644
--- a/tools/cert_create/include/ext.h
+++ b/tools/cert_create/include/ext.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -20,7 +20,8 @@
/* NV-Counter types */
enum nvctr_type_e {
NVCTR_TYPE_TFW,
- NVCTR_TYPE_NTFW
+ NVCTR_TYPE_NTFW,
+ NVCTR_TYPE_CCAFW
};
/*
diff --git a/tools/cert_create/src/cca/cot.c b/tools/cert_create/src/cca/cot.c
index 5a35ff6..e39b036 100644
--- a/tools/cert_create/src/cca/cot.c
+++ b/tools/cert_create/src/cca/cot.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2022-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -27,7 +27,7 @@
.key = ROT_KEY,
.issuer = CCA_CONTENT_CERT,
.ext = {
- TRUSTED_FW_NVCOUNTER_EXT,
+ CCA_FW_NVCOUNTER_EXT,
SOC_AP_FW_HASH_EXT,
SOC_FW_CONFIG_HASH_EXT,
RMM_HASH_EXT,
@@ -139,6 +139,17 @@
/* Certificate extensions. */
static ext_t cot_ext[] = {
+ [CCA_FW_NVCOUNTER_EXT] = {
+ .oid = CCA_FW_NVCOUNTER_OID,
+ .opt = "ccafw-nvctr",
+ .help_msg = "CCA Firmware Non-Volatile counter value",
+ .sn = "CCANVCounter",
+ .ln = "CCA Non-Volatile counter",
+ .asn1_type = V_ASN1_INTEGER,
+ .type = EXT_TYPE_NVCOUNTER,
+ .attr.nvctr_type = NVCTR_TYPE_CCAFW
+ },
+
[TRUSTED_FW_NVCOUNTER_EXT] = {
.oid = TRUSTED_FW_NVCOUNTER_OID,
.opt = "tfw-nvctr",
diff --git a/plat/arm/board/juno/plat_fiptool.mk b/tools/fiptool/plat_fiptool/arm/board/juno/plat_fiptool.mk
similarity index 100%
rename from plat/arm/board/juno/plat_fiptool.mk
rename to tools/fiptool/plat_fiptool/arm/board/juno/plat_fiptool.mk
diff --git a/tools/fiptool/plat_fiptool/st/stm32mp1/plat_def_uuid_config.c b/tools/fiptool/plat_fiptool/st/stm32mp1/plat_def_uuid_config.c
index efaf567..4df4144 100644
--- a/tools/fiptool/plat_fiptool/st/stm32mp1/plat_def_uuid_config.c
+++ b/tools/fiptool/plat_fiptool/st/stm32mp1/plat_def_uuid_config.c
@@ -1,9 +1,11 @@
/*
- * Copyright (c) 2022, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2022-2023, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
+#include <stddef.h>
+
#include <firmware_image_package.h>
#include "tbbr_config.h"
@@ -13,6 +15,11 @@
.name = "STM32MP CONFIG CERT",
.uuid = UUID_STM32MP_CONFIG_CERT,
.cmdline_name = "stm32mp-cfg-cert"
+ },
+
+ {
+ .name = NULL,
+ .uuid = { {0} },
+ .cmdline_name = NULL,
}
};
-
diff --git a/tools/memory/memory/buildparser.py b/tools/memory/memory/buildparser.py
index 6f467cd..dedff79 100755
--- a/tools/memory/memory/buildparser.py
+++ b/tools/memory/memory/buildparser.py
@@ -8,14 +8,16 @@
from pathlib import Path
from memory.elfparser import TfaElfParser
+from memory.mapparser import TfaMapParser
class TfaBuildParser:
"""A class for performing analysis on the memory layout of a TF-A build."""
- def __init__(self, path: Path):
+ def __init__(self, path: Path, map_backend=False):
self._modules = dict()
self._path = path
+ self.map_backend = map_backend
self._parse_modules()
def __getitem__(self, module: str):
@@ -23,15 +25,24 @@
return self._modules[module]
def _parse_modules(self):
- """Parse ELF files in the build path."""
- for elf_file in self._path.glob("**/*.elf"):
- module_name = elf_file.name.split("/")[-1].split(".")[0]
- with open(elf_file, "rb") as file:
- self._modules[module_name] = TfaElfParser(file)
+ """Parse the build files using the selected backend."""
+ backend = TfaElfParser
+ files = list(self._path.glob("**/*.elf"))
+ io_perms = "rb"
+
+ if self.map_backend or len(files) == 0:
+ backend = TfaMapParser
+ files = self._path.glob("**/*.map")
+ io_perms = "r"
+
+ for file in files:
+ module_name = file.name.split("/")[-1].split(".")[0]
+ with open(file, io_perms) as f:
+ self._modules[module_name] = backend(f)
if not len(self._modules):
raise FileNotFoundError(
- f"failed to find ELF files in path {self._path}!"
+ f"failed to find files to analyse in path {self._path}!"
)
@property
@@ -50,6 +61,27 @@
reverse=True,
)
+ def get_mem_usage_dict(self) -> dict:
+ """Returns map of memory usage per memory type for each module."""
+ mem_map = {}
+ for k, v in self._modules.items():
+ mod_mem_map = v.get_memory_layout()
+ if len(mod_mem_map):
+ mem_map[k] = mod_mem_map
+ return mem_map
+
+ def get_mem_tree_as_dict(self) -> dict:
+ """Returns _tree of modules, segments and segments and their total
+ memory usage."""
+ return {
+ k: {
+ "name": k,
+ **v.get_mod_mem_usage_dict(),
+ **{"children": v.get_seg_map_as_dict()},
+ }
+ for k, v in self._modules.items()
+ }
+
@property
def module_names(self):
"""Returns sorted list of module names."""
diff --git a/tools/memory/memory/elfparser.py b/tools/memory/memory/elfparser.py
index 3964e6c..2dd2513 100644
--- a/tools/memory/memory/elfparser.py
+++ b/tools/memory/memory/elfparser.py
@@ -4,11 +4,22 @@
# SPDX-License-Identifier: BSD-3-Clause
#
+import re
+from dataclasses import asdict, dataclass
from typing import BinaryIO
from elftools.elf.elffile import ELFFile
+@dataclass(frozen=True)
+class TfaMemObject:
+ name: str
+ start: int
+ end: int
+ size: int
+ children: list
+
+
class TfaElfParser:
"""A class representing an ELF file built for TF-A.
@@ -28,6 +39,123 @@
for sym in elf.get_section_by_name(".symtab").iter_symbols()
}
+ self.set_segment_section_map(elf.iter_segments(), elf.iter_sections())
+ self._memory_layout = self.get_memory_layout_from_symbols()
+ self._start = elf["e_entry"]
+ self._size, self._free = self._get_mem_usage()
+ self._end = self._start + self._size
+
@property
def symbols(self):
return self._symbols.items()
+
+ @staticmethod
+ def tfa_mem_obj_factory(elf_obj, name=None, children=None, segment=False):
+ """Converts a pyelfparser Segment or Section to a TfaMemObject."""
+ # Ensure each segment is provided a name since they aren't in the
+ # program header.
+ assert not (
+ segment and name is None
+ ), "Attempting to make segment without a name"
+
+ if children is None:
+ children = list()
+
+ # Segment and sections header keys have different prefixes.
+ vaddr = "p_vaddr" if segment else "sh_addr"
+ size = "p_memsz" if segment else "sh_size"
+
+ # TODO figure out how to handle free space for sections and segments
+ return TfaMemObject(
+ name if segment else elf_obj.name,
+ elf_obj[vaddr],
+ elf_obj[vaddr] + elf_obj[size],
+ elf_obj[size],
+ [] if not children else children,
+ )
+
+ def _get_mem_usage(self) -> (int, int):
+ """Get total size and free space for this component."""
+ size = free = 0
+
+ # Use information encoded in the segment header if we can't get a
+ # memory configuration.
+ if not self._memory_layout:
+ return sum(s.size for s in self._segments.values()), 0
+
+ for v in self._memory_layout.values():
+ size += v["length"]
+ free += v["start"] + v["length"] - v["end"]
+
+ return size, free
+
+ def set_segment_section_map(self, segments, sections):
+ """Set segment to section mappings."""
+ segments = list(
+ filter(lambda seg: seg["p_type"] == "PT_LOAD", segments)
+ )
+
+ for sec in sections:
+ for n, seg in enumerate(segments):
+ if seg.section_in_segment(sec):
+ if n not in self._segments.keys():
+ self._segments[n] = self.tfa_mem_obj_factory(
+ seg, name=f"{n:#02}", segment=True
+ )
+
+ self._segments[n].children.append(
+ self.tfa_mem_obj_factory(sec)
+ )
+
+ def get_memory_layout_from_symbols(self, expr=None) -> dict:
+ """Retrieve information about the memory configuration from the symbol
+ table.
+ """
+ assert len(self._symbols), "Symbol table is empty!"
+
+ expr = r".*(.?R.M)_REGION.*(START|END|LENGTH)" if not expr else expr
+ region_symbols = filter(lambda s: re.match(expr, s), self._symbols)
+ memory_layout = {}
+
+ for symbol in region_symbols:
+ region, _, attr = tuple(symbol.lower().strip("__").split("_"))
+ if region not in memory_layout:
+ memory_layout[region] = {}
+
+ # Retrieve the value of the symbol using the symbol as the key.
+ memory_layout[region][attr] = self._symbols[symbol]
+
+ return memory_layout
+
+ def get_seg_map_as_dict(self):
+ """Get a dictionary of segments and their section mappings."""
+ return [asdict(v) for k, v in self._segments.items()]
+
+ def get_memory_layout(self):
+ """Get the total memory consumed by this module from the memory
+ configuration.
+ {"rom": {"start": 0x0, "end": 0xFF, "length": ... }
+ """
+ mem_dict = {}
+
+ for mem, attrs in self._memory_layout.items():
+ limit = attrs["start"] + attrs["length"]
+ mem_dict[mem] = {
+ "start": attrs["start"],
+ "limit": limit,
+ "size": attrs["end"] - attrs["start"],
+ "free": limit - attrs["end"],
+ "total": attrs["length"],
+ }
+ return mem_dict
+
+ def get_mod_mem_usage_dict(self):
+ """Get the total memory consumed by the module, this combines the
+ information in the memory configuration.
+ """
+ return {
+ "start": self._start,
+ "end": self._end,
+ "size": self._size,
+ "free": self._free,
+ }
diff --git a/tools/memory/memory/mapparser.py b/tools/memory/memory/mapparser.py
new file mode 100644
index 0000000..b1a4b4c
--- /dev/null
+++ b/tools/memory/memory/mapparser.py
@@ -0,0 +1,75 @@
+#
+# Copyright (c) 2023, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+from re import match, search
+from typing import TextIO
+
+
+class TfaMapParser:
+ """A class representing a map file built for TF-A.
+
+ Provides a basic interface for reading the symbol table. The constructor
+ accepts a file-like object with the contents a Map file. Only GNU map files
+ are supported at this stage.
+ """
+
+ def __init__(self, map_file: TextIO):
+ self._symbols = self.read_symbols(map_file)
+
+ @property
+ def symbols(self):
+ return self._symbols.items()
+
+ @staticmethod
+ def read_symbols(file: TextIO, pattern: str = None) -> dict:
+ pattern = r"\b(0x\w*)\s*(\w*)\s=" if not pattern else pattern
+ symbols = {}
+
+ for line in file.readlines():
+ match = search(pattern, line)
+
+ if match is not None:
+ value, name = match.groups()
+ symbols[name] = int(value, 16)
+
+ return symbols
+
+ def get_memory_layout(self) -> dict:
+ """Get the total memory consumed by this module from the memory
+ configuration.
+ {"rom": {"start": 0x0, "end": 0xFF, "length": ... }
+ """
+ assert len(self._symbols), "Symbol table is empty!"
+ expr = r".*(.?R.M)_REGION.*(START|END|LENGTH)"
+ memory_layout = {}
+
+ region_symbols = filter(lambda s: match(expr, s), self._symbols)
+
+ for symbol in region_symbols:
+ region, _, attr = tuple(symbol.lower().strip("__").split("_"))
+ if region not in memory_layout:
+ memory_layout[region] = {}
+
+ memory_layout[region][attr] = self._symbols[symbol]
+
+ if "start" and "length" and "end" in memory_layout[region]:
+ memory_layout[region]["limit"] = (
+ memory_layout[region]["end"]
+ + memory_layout[region]["length"]
+ )
+ memory_layout[region]["free"] = (
+ memory_layout[region]["limit"]
+ - memory_layout[region]["end"]
+ )
+ memory_layout[region]["total"] = memory_layout[region][
+ "length"
+ ]
+ memory_layout[region]["size"] = (
+ memory_layout[region]["end"]
+ - memory_layout[region]["start"]
+ )
+
+ return memory_layout
diff --git a/tools/memory/memory/memmap.py b/tools/memory/memory/memmap.py
index 7057228..99149b5 100755
--- a/tools/memory/memory/memmap.py
+++ b/tools/memory/memory/memmap.py
@@ -36,11 +36,27 @@
type=click.Choice(["debug", "release"], case_sensitive=False),
)
@click.option(
+ "-f",
+ "--footprint",
+ is_flag=True,
+ show_default=True,
+ help="Generate a high level view of memory usage by memory types.",
+)
+@click.option(
+ "-t",
+ "--tree",
+ is_flag=True,
+ help="Generate a hierarchical view of the modules, segments and sections.",
+)
+@click.option(
+ "--depth",
+ default=3,
+ help="Generate a virtual address map of important TF symbols.",
+)
+@click.option(
"-s",
"--symbols",
is_flag=True,
- show_default=True,
- default=True,
help="Generate a map of important TF symbols.",
)
@click.option("-w", "--width", type=int, envvar="COLUMNS")
@@ -50,24 +66,41 @@
default=False,
help="Display numbers in decimal base.",
)
+@click.option(
+ "--no-elf-images",
+ is_flag=True,
+ help="Analyse the build's map files instead of ELF images.",
+)
def main(
root: Path,
platform: str,
build_type: str,
+ footprint: str,
+ tree: bool,
symbols: bool,
+ depth: int,
width: int,
d: bool,
+ no_elf_images: bool,
):
build_path = root if root else Path("build/", platform, build_type)
click.echo(f"build-path: {build_path.resolve()}")
- parser = TfaBuildParser(build_path)
+ parser = TfaBuildParser(build_path, map_backend=no_elf_images)
printer = TfaPrettyPrinter(columns=width, as_decimal=d)
+ if footprint or not (tree or symbols):
+ printer.print_footprint(parser.get_mem_usage_dict())
+
+ if tree:
+ printer.print_mem_tree(
+ parser.get_mem_tree_as_dict(), parser.module_names, depth=depth
+ )
+
if symbols:
expr = (
r"(.*)(TEXT|BSS|RODATA|STACKS|_OPS|PMF|XLAT|GOT|FCONF"
- r"|R.M)(.*)(START|END)__$"
+ r"|R.M)(.*)(START|UNALIGNED|END)__$"
)
printer.print_symbol_table(
parser.filter_symbols(parser.symbols, expr), parser.module_names
diff --git a/tools/memory/memory/printer.py b/tools/memory/memory/printer.py
index 11fd7f0..4b18560 100755
--- a/tools/memory/memory/printer.py
+++ b/tools/memory/memory/printer.py
@@ -4,6 +4,10 @@
# SPDX-License-Identifier: BSD-3-Clause
#
+from anytree import RenderTree
+from anytree.importer import DictImporter
+from prettytable import PrettyTable
+
class TfaPrettyPrinter:
"""A class for printing the memory layout of ELF files.
@@ -15,6 +19,8 @@
def __init__(self, columns: int = None, as_decimal: bool = False):
self.term_size = columns if columns and columns > 120 else 120
+ self._tree = None
+ self._footprint = None
self._symbol_map = None
self.as_decimal = as_decimal
@@ -23,6 +29,10 @@
fmt = f">{width}x" if not self.as_decimal else f">{width}"
return [f"{arg:{fmt}}" if fmt else arg for arg in args]
+ def format_row(self, leading, *args, width=10, fmt=None):
+ formatted_args = self.format_args(*args, width=width, fmt=fmt)
+ return leading + " ".join(formatted_args)
+
@staticmethod
def map_elf_symbol(
leading: str,
@@ -50,17 +60,51 @@
return leading + sec_row_l + sec_row + sec_row_r
+ def print_footprint(
+ self, app_mem_usage: dict, sort_key: str = None, fields: list = None
+ ):
+ assert len(app_mem_usage), "Empty memory layout dictionary!"
+ if not fields:
+ fields = ["Component", "Start", "Limit", "Size", "Free", "Total"]
+
+ sort_key = fields[0] if not sort_key else sort_key
+
+ # Iterate through all the memory types, create a table for each
+ # type, rows represent a single module.
+ for mem in sorted(set(k for _, v in app_mem_usage.items() for k in v)):
+ table = PrettyTable(
+ sortby=sort_key,
+ title=f"Memory Usage (bytes) [{mem.upper()}]",
+ field_names=fields,
+ )
+
+ for mod, vals in app_mem_usage.items():
+ if mem in vals.keys():
+ val = vals[mem]
+ table.add_row(
+ [
+ mod.upper(),
+ *self.format_args(
+ *[val[k.lower()] for k in fields[1:]]
+ ),
+ ]
+ )
+ print(table, "\n")
+
def print_symbol_table(
self,
symbols: list,
modules: list,
- start: int = 11,
+ start: int = 12,
):
assert len(symbols), "Empty symbol list!"
modules = sorted(modules)
col_width = int((self.term_size - start) / len(modules))
+ address_fixed_width = 11
- num_fmt = "0=#010x" if not self.as_decimal else ">10"
+ num_fmt = (
+ f"0=#0{address_fixed_width}x" if not self.as_decimal else ">10"
+ )
_symbol_map = [
" " * start
@@ -91,3 +135,29 @@
self._symbol_map = ["Memory Layout:"]
self._symbol_map += list(reversed(_symbol_map))
print("\n".join(self._symbol_map))
+
+ def print_mem_tree(
+ self, mem_map_dict, modules, depth=1, min_pad=12, node_right_pad=12
+ ):
+ # Start column should have some padding between itself and its data
+ # values.
+ anchor = min_pad + node_right_pad * (depth - 1)
+ headers = ["start", "end", "size"]
+
+ self._tree = [
+ (f"{'name':<{anchor}}" + " ".join(f"{arg:>10}" for arg in headers))
+ ]
+
+ for mod in sorted(modules):
+ root = DictImporter().import_(mem_map_dict[mod])
+ for pre, fill, node in RenderTree(root, maxlevel=depth):
+ leading = f"{pre}{node.name}".ljust(anchor)
+ self._tree.append(
+ self.format_row(
+ leading,
+ node.start,
+ node.end,
+ node.size,
+ )
+ )
+ print("\n".join(self._tree), "\n")
