rcar_gen3: drivers: pfc: M3W: Checkpatch cleanup
Checkpatch cleanups of the PFC init code and remaining SoC specific macros.
No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I6d48af4b1d56ef487744f4a58126140bbad28132
diff --git a/drivers/staging/renesas/rcar/pfc/M3/pfc_init_m3.c b/drivers/staging/renesas/rcar/pfc/M3/pfc_init_m3.c
index e0e8b07..f455ff2 100644
--- a/drivers/staging/renesas/rcar/pfc/M3/pfc_init_m3.c
+++ b/drivers/staging/renesas/rcar/pfc/M3/pfc_init_m3.c
@@ -13,565 +13,565 @@
#include "rcar_private.h"
#include "../pfc_regs.h"
-#define GPSR0_D15 ((uint32_t)1U << 15U)
-#define GPSR0_D14 ((uint32_t)1U << 14U)
-#define GPSR0_D13 ((uint32_t)1U << 13U)
-#define GPSR0_D12 ((uint32_t)1U << 12U)
-#define GPSR0_D11 ((uint32_t)1U << 11U)
-#define GPSR0_D10 ((uint32_t)1U << 10U)
-#define GPSR0_D9 ((uint32_t)1U << 9U)
-#define GPSR0_D8 ((uint32_t)1U << 8U)
-#define GPSR0_D7 ((uint32_t)1U << 7U)
-#define GPSR0_D6 ((uint32_t)1U << 6U)
-#define GPSR0_D5 ((uint32_t)1U << 5U)
-#define GPSR0_D4 ((uint32_t)1U << 4U)
-#define GPSR0_D3 ((uint32_t)1U << 3U)
-#define GPSR0_D2 ((uint32_t)1U << 2U)
-#define GPSR0_D1 ((uint32_t)1U << 1U)
-#define GPSR0_D0 ((uint32_t)1U << 0U)
-#define GPSR1_CLKOUT ((uint32_t)1U << 28U)
-#define GPSR1_EX_WAIT0_A ((uint32_t)1U << 27U)
-#define GPSR1_WE1 ((uint32_t)1U << 26U)
-#define GPSR1_WE0 ((uint32_t)1U << 25U)
-#define GPSR1_RD_WR ((uint32_t)1U << 24U)
-#define GPSR1_RD ((uint32_t)1U << 23U)
-#define GPSR1_BS ((uint32_t)1U << 22U)
-#define GPSR1_CS1_A26 ((uint32_t)1U << 21U)
-#define GPSR1_CS0 ((uint32_t)1U << 20U)
-#define GPSR1_A19 ((uint32_t)1U << 19U)
-#define GPSR1_A18 ((uint32_t)1U << 18U)
-#define GPSR1_A17 ((uint32_t)1U << 17U)
-#define GPSR1_A16 ((uint32_t)1U << 16U)
-#define GPSR1_A15 ((uint32_t)1U << 15U)
-#define GPSR1_A14 ((uint32_t)1U << 14U)
-#define GPSR1_A13 ((uint32_t)1U << 13U)
-#define GPSR1_A12 ((uint32_t)1U << 12U)
-#define GPSR1_A11 ((uint32_t)1U << 11U)
-#define GPSR1_A10 ((uint32_t)1U << 10U)
-#define GPSR1_A9 ((uint32_t)1U << 9U)
-#define GPSR1_A8 ((uint32_t)1U << 8U)
-#define GPSR1_A7 ((uint32_t)1U << 7U)
-#define GPSR1_A6 ((uint32_t)1U << 6U)
-#define GPSR1_A5 ((uint32_t)1U << 5U)
-#define GPSR1_A4 ((uint32_t)1U << 4U)
-#define GPSR1_A3 ((uint32_t)1U << 3U)
-#define GPSR1_A2 ((uint32_t)1U << 2U)
-#define GPSR1_A1 ((uint32_t)1U << 1U)
-#define GPSR1_A0 ((uint32_t)1U << 0U)
-#define GPSR2_AVB_AVTP_CAPTURE_A ((uint32_t)1U << 14U)
-#define GPSR2_AVB_AVTP_MATCH_A ((uint32_t)1U << 13U)
-#define GPSR2_AVB_LINK ((uint32_t)1U << 12U)
-#define GPSR2_AVB_PHY_INT ((uint32_t)1U << 11U)
-#define GPSR2_AVB_MAGIC ((uint32_t)1U << 10U)
-#define GPSR2_AVB_MDC ((uint32_t)1U << 9U)
-#define GPSR2_PWM2_A ((uint32_t)1U << 8U)
-#define GPSR2_PWM1_A ((uint32_t)1U << 7U)
-#define GPSR2_PWM0 ((uint32_t)1U << 6U)
-#define GPSR2_IRQ5 ((uint32_t)1U << 5U)
-#define GPSR2_IRQ4 ((uint32_t)1U << 4U)
-#define GPSR2_IRQ3 ((uint32_t)1U << 3U)
-#define GPSR2_IRQ2 ((uint32_t)1U << 2U)
-#define GPSR2_IRQ1 ((uint32_t)1U << 1U)
-#define GPSR2_IRQ0 ((uint32_t)1U << 0U)
-#define GPSR3_SD1_WP ((uint32_t)1U << 15U)
-#define GPSR3_SD1_CD ((uint32_t)1U << 14U)
-#define GPSR3_SD0_WP ((uint32_t)1U << 13U)
-#define GPSR3_SD0_CD ((uint32_t)1U << 12U)
-#define GPSR3_SD1_DAT3 ((uint32_t)1U << 11U)
-#define GPSR3_SD1_DAT2 ((uint32_t)1U << 10U)
-#define GPSR3_SD1_DAT1 ((uint32_t)1U << 9U)
-#define GPSR3_SD1_DAT0 ((uint32_t)1U << 8U)
-#define GPSR3_SD1_CMD ((uint32_t)1U << 7U)
-#define GPSR3_SD1_CLK ((uint32_t)1U << 6U)
-#define GPSR3_SD0_DAT3 ((uint32_t)1U << 5U)
-#define GPSR3_SD0_DAT2 ((uint32_t)1U << 4U)
-#define GPSR3_SD0_DAT1 ((uint32_t)1U << 3U)
-#define GPSR3_SD0_DAT0 ((uint32_t)1U << 2U)
-#define GPSR3_SD0_CMD ((uint32_t)1U << 1U)
-#define GPSR3_SD0_CLK ((uint32_t)1U << 0U)
-#define GPSR4_SD3_DS ((uint32_t)1U << 17U)
-#define GPSR4_SD3_DAT7 ((uint32_t)1U << 16U)
-#define GPSR4_SD3_DAT6 ((uint32_t)1U << 15U)
-#define GPSR4_SD3_DAT5 ((uint32_t)1U << 14U)
-#define GPSR4_SD3_DAT4 ((uint32_t)1U << 13U)
-#define GPSR4_SD3_DAT3 ((uint32_t)1U << 12U)
-#define GPSR4_SD3_DAT2 ((uint32_t)1U << 11U)
-#define GPSR4_SD3_DAT1 ((uint32_t)1U << 10U)
-#define GPSR4_SD3_DAT0 ((uint32_t)1U << 9U)
-#define GPSR4_SD3_CMD ((uint32_t)1U << 8U)
-#define GPSR4_SD3_CLK ((uint32_t)1U << 7U)
-#define GPSR4_SD2_DS ((uint32_t)1U << 6U)
-#define GPSR4_SD2_DAT3 ((uint32_t)1U << 5U)
-#define GPSR4_SD2_DAT2 ((uint32_t)1U << 4U)
-#define GPSR4_SD2_DAT1 ((uint32_t)1U << 3U)
-#define GPSR4_SD2_DAT0 ((uint32_t)1U << 2U)
-#define GPSR4_SD2_CMD ((uint32_t)1U << 1U)
-#define GPSR4_SD2_CLK ((uint32_t)1U << 0U)
-#define GPSR5_MLB_DAT ((uint32_t)1U << 25U)
-#define GPSR5_MLB_SIG ((uint32_t)1U << 24U)
-#define GPSR5_MLB_CLK ((uint32_t)1U << 23U)
-#define GPSR5_MSIOF0_RXD ((uint32_t)1U << 22U)
-#define GPSR5_MSIOF0_SS2 ((uint32_t)1U << 21U)
-#define GPSR5_MSIOF0_TXD ((uint32_t)1U << 20U)
-#define GPSR5_MSIOF0_SS1 ((uint32_t)1U << 19U)
-#define GPSR5_MSIOF0_SYNC ((uint32_t)1U << 18U)
-#define GPSR5_MSIOF0_SCK ((uint32_t)1U << 17U)
-#define GPSR5_HRTS0 ((uint32_t)1U << 16U)
-#define GPSR5_HCTS0 ((uint32_t)1U << 15U)
-#define GPSR5_HTX0 ((uint32_t)1U << 14U)
-#define GPSR5_HRX0 ((uint32_t)1U << 13U)
-#define GPSR5_HSCK0 ((uint32_t)1U << 12U)
-#define GPSR5_RX2_A ((uint32_t)1U << 11U)
-#define GPSR5_TX2_A ((uint32_t)1U << 10U)
-#define GPSR5_SCK2 ((uint32_t)1U << 9U)
-#define GPSR5_RTS1_TANS ((uint32_t)1U << 8U)
-#define GPSR5_CTS1 ((uint32_t)1U << 7U)
-#define GPSR5_TX1_A ((uint32_t)1U << 6U)
-#define GPSR5_RX1_A ((uint32_t)1U << 5U)
-#define GPSR5_RTS0_TANS ((uint32_t)1U << 4U)
-#define GPSR5_CTS0 ((uint32_t)1U << 3U)
-#define GPSR5_TX0 ((uint32_t)1U << 2U)
-#define GPSR5_RX0 ((uint32_t)1U << 1U)
-#define GPSR5_SCK0 ((uint32_t)1U << 0U)
-#define GPSR6_USB31_OVC ((uint32_t)1U << 31U)
-#define GPSR6_USB31_PWEN ((uint32_t)1U << 30U)
-#define GPSR6_USB30_OVC ((uint32_t)1U << 29U)
-#define GPSR6_USB30_PWEN ((uint32_t)1U << 28U)
-#define GPSR6_USB1_OVC ((uint32_t)1U << 27U)
-#define GPSR6_USB1_PWEN ((uint32_t)1U << 26U)
-#define GPSR6_USB0_OVC ((uint32_t)1U << 25U)
-#define GPSR6_USB0_PWEN ((uint32_t)1U << 24U)
-#define GPSR6_AUDIO_CLKB_B ((uint32_t)1U << 23U)
-#define GPSR6_AUDIO_CLKA_A ((uint32_t)1U << 22U)
-#define GPSR6_SSI_SDATA9_A ((uint32_t)1U << 21U)
-#define GPSR6_SSI_SDATA8 ((uint32_t)1U << 20U)
-#define GPSR6_SSI_SDATA7 ((uint32_t)1U << 19U)
-#define GPSR6_SSI_WS78 ((uint32_t)1U << 18U)
-#define GPSR6_SSI_SCK78 ((uint32_t)1U << 17U)
-#define GPSR6_SSI_SDATA6 ((uint32_t)1U << 16U)
-#define GPSR6_SSI_WS6 ((uint32_t)1U << 15U)
-#define GPSR6_SSI_SCK6 ((uint32_t)1U << 14U)
-#define GPSR6_SSI_SDATA5 ((uint32_t)1U << 13U)
-#define GPSR6_SSI_WS5 ((uint32_t)1U << 12U)
-#define GPSR6_SSI_SCK5 ((uint32_t)1U << 11U)
-#define GPSR6_SSI_SDATA4 ((uint32_t)1U << 10U)
-#define GPSR6_SSI_WS4 ((uint32_t)1U << 9U)
-#define GPSR6_SSI_SCK4 ((uint32_t)1U << 8U)
-#define GPSR6_SSI_SDATA3 ((uint32_t)1U << 7U)
-#define GPSR6_SSI_WS34 ((uint32_t)1U << 6U)
-#define GPSR6_SSI_SCK34 ((uint32_t)1U << 5U)
-#define GPSR6_SSI_SDATA2_A ((uint32_t)1U << 4U)
-#define GPSR6_SSI_SDATA1_A ((uint32_t)1U << 3U)
-#define GPSR6_SSI_SDATA0 ((uint32_t)1U << 2U)
-#define GPSR6_SSI_WS0129 ((uint32_t)1U << 1U)
-#define GPSR6_SSI_SCK0129 ((uint32_t)1U << 0U)
-#define GPSR7_HDMI1_CEC ((uint32_t)1U << 3U)
-#define GPSR7_HDMI0_CEC ((uint32_t)1U << 2U)
-#define GPSR7_AVS2 ((uint32_t)1U << 1U)
-#define GPSR7_AVS1 ((uint32_t)1U << 0U)
+#define GPSR0_D15 ((uint32_t)1U << 15U)
+#define GPSR0_D14 ((uint32_t)1U << 14U)
+#define GPSR0_D13 ((uint32_t)1U << 13U)
+#define GPSR0_D12 ((uint32_t)1U << 12U)
+#define GPSR0_D11 ((uint32_t)1U << 11U)
+#define GPSR0_D10 ((uint32_t)1U << 10U)
+#define GPSR0_D9 ((uint32_t)1U << 9U)
+#define GPSR0_D8 ((uint32_t)1U << 8U)
+#define GPSR0_D7 ((uint32_t)1U << 7U)
+#define GPSR0_D6 ((uint32_t)1U << 6U)
+#define GPSR0_D5 ((uint32_t)1U << 5U)
+#define GPSR0_D4 ((uint32_t)1U << 4U)
+#define GPSR0_D3 ((uint32_t)1U << 3U)
+#define GPSR0_D2 ((uint32_t)1U << 2U)
+#define GPSR0_D1 ((uint32_t)1U << 1U)
+#define GPSR0_D0 ((uint32_t)1U << 0U)
+#define GPSR1_CLKOUT ((uint32_t)1U << 28U)
+#define GPSR1_EX_WAIT0_A ((uint32_t)1U << 27U)
+#define GPSR1_WE1 ((uint32_t)1U << 26U)
+#define GPSR1_WE0 ((uint32_t)1U << 25U)
+#define GPSR1_RD_WR ((uint32_t)1U << 24U)
+#define GPSR1_RD ((uint32_t)1U << 23U)
+#define GPSR1_BS ((uint32_t)1U << 22U)
+#define GPSR1_CS1_A26 ((uint32_t)1U << 21U)
+#define GPSR1_CS0 ((uint32_t)1U << 20U)
+#define GPSR1_A19 ((uint32_t)1U << 19U)
+#define GPSR1_A18 ((uint32_t)1U << 18U)
+#define GPSR1_A17 ((uint32_t)1U << 17U)
+#define GPSR1_A16 ((uint32_t)1U << 16U)
+#define GPSR1_A15 ((uint32_t)1U << 15U)
+#define GPSR1_A14 ((uint32_t)1U << 14U)
+#define GPSR1_A13 ((uint32_t)1U << 13U)
+#define GPSR1_A12 ((uint32_t)1U << 12U)
+#define GPSR1_A11 ((uint32_t)1U << 11U)
+#define GPSR1_A10 ((uint32_t)1U << 10U)
+#define GPSR1_A9 ((uint32_t)1U << 9U)
+#define GPSR1_A8 ((uint32_t)1U << 8U)
+#define GPSR1_A7 ((uint32_t)1U << 7U)
+#define GPSR1_A6 ((uint32_t)1U << 6U)
+#define GPSR1_A5 ((uint32_t)1U << 5U)
+#define GPSR1_A4 ((uint32_t)1U << 4U)
+#define GPSR1_A3 ((uint32_t)1U << 3U)
+#define GPSR1_A2 ((uint32_t)1U << 2U)
+#define GPSR1_A1 ((uint32_t)1U << 1U)
+#define GPSR1_A0 ((uint32_t)1U << 0U)
+#define GPSR2_AVB_AVTP_CAPTURE_A ((uint32_t)1U << 14U)
+#define GPSR2_AVB_AVTP_MATCH_A ((uint32_t)1U << 13U)
+#define GPSR2_AVB_LINK ((uint32_t)1U << 12U)
+#define GPSR2_AVB_PHY_INT ((uint32_t)1U << 11U)
+#define GPSR2_AVB_MAGIC ((uint32_t)1U << 10U)
+#define GPSR2_AVB_MDC ((uint32_t)1U << 9U)
+#define GPSR2_PWM2_A ((uint32_t)1U << 8U)
+#define GPSR2_PWM1_A ((uint32_t)1U << 7U)
+#define GPSR2_PWM0 ((uint32_t)1U << 6U)
+#define GPSR2_IRQ5 ((uint32_t)1U << 5U)
+#define GPSR2_IRQ4 ((uint32_t)1U << 4U)
+#define GPSR2_IRQ3 ((uint32_t)1U << 3U)
+#define GPSR2_IRQ2 ((uint32_t)1U << 2U)
+#define GPSR2_IRQ1 ((uint32_t)1U << 1U)
+#define GPSR2_IRQ0 ((uint32_t)1U << 0U)
+#define GPSR3_SD1_WP ((uint32_t)1U << 15U)
+#define GPSR3_SD1_CD ((uint32_t)1U << 14U)
+#define GPSR3_SD0_WP ((uint32_t)1U << 13U)
+#define GPSR3_SD0_CD ((uint32_t)1U << 12U)
+#define GPSR3_SD1_DAT3 ((uint32_t)1U << 11U)
+#define GPSR3_SD1_DAT2 ((uint32_t)1U << 10U)
+#define GPSR3_SD1_DAT1 ((uint32_t)1U << 9U)
+#define GPSR3_SD1_DAT0 ((uint32_t)1U << 8U)
+#define GPSR3_SD1_CMD ((uint32_t)1U << 7U)
+#define GPSR3_SD1_CLK ((uint32_t)1U << 6U)
+#define GPSR3_SD0_DAT3 ((uint32_t)1U << 5U)
+#define GPSR3_SD0_DAT2 ((uint32_t)1U << 4U)
+#define GPSR3_SD0_DAT1 ((uint32_t)1U << 3U)
+#define GPSR3_SD0_DAT0 ((uint32_t)1U << 2U)
+#define GPSR3_SD0_CMD ((uint32_t)1U << 1U)
+#define GPSR3_SD0_CLK ((uint32_t)1U << 0U)
+#define GPSR4_SD3_DS ((uint32_t)1U << 17U)
+#define GPSR4_SD3_DAT7 ((uint32_t)1U << 16U)
+#define GPSR4_SD3_DAT6 ((uint32_t)1U << 15U)
+#define GPSR4_SD3_DAT5 ((uint32_t)1U << 14U)
+#define GPSR4_SD3_DAT4 ((uint32_t)1U << 13U)
+#define GPSR4_SD3_DAT3 ((uint32_t)1U << 12U)
+#define GPSR4_SD3_DAT2 ((uint32_t)1U << 11U)
+#define GPSR4_SD3_DAT1 ((uint32_t)1U << 10U)
+#define GPSR4_SD3_DAT0 ((uint32_t)1U << 9U)
+#define GPSR4_SD3_CMD ((uint32_t)1U << 8U)
+#define GPSR4_SD3_CLK ((uint32_t)1U << 7U)
+#define GPSR4_SD2_DS ((uint32_t)1U << 6U)
+#define GPSR4_SD2_DAT3 ((uint32_t)1U << 5U)
+#define GPSR4_SD2_DAT2 ((uint32_t)1U << 4U)
+#define GPSR4_SD2_DAT1 ((uint32_t)1U << 3U)
+#define GPSR4_SD2_DAT0 ((uint32_t)1U << 2U)
+#define GPSR4_SD2_CMD ((uint32_t)1U << 1U)
+#define GPSR4_SD2_CLK ((uint32_t)1U << 0U)
+#define GPSR5_MLB_DAT ((uint32_t)1U << 25U)
+#define GPSR5_MLB_SIG ((uint32_t)1U << 24U)
+#define GPSR5_MLB_CLK ((uint32_t)1U << 23U)
+#define GPSR5_MSIOF0_RXD ((uint32_t)1U << 22U)
+#define GPSR5_MSIOF0_SS2 ((uint32_t)1U << 21U)
+#define GPSR5_MSIOF0_TXD ((uint32_t)1U << 20U)
+#define GPSR5_MSIOF0_SS1 ((uint32_t)1U << 19U)
+#define GPSR5_MSIOF0_SYNC ((uint32_t)1U << 18U)
+#define GPSR5_MSIOF0_SCK ((uint32_t)1U << 17U)
+#define GPSR5_HRTS0 ((uint32_t)1U << 16U)
+#define GPSR5_HCTS0 ((uint32_t)1U << 15U)
+#define GPSR5_HTX0 ((uint32_t)1U << 14U)
+#define GPSR5_HRX0 ((uint32_t)1U << 13U)
+#define GPSR5_HSCK0 ((uint32_t)1U << 12U)
+#define GPSR5_RX2_A ((uint32_t)1U << 11U)
+#define GPSR5_TX2_A ((uint32_t)1U << 10U)
+#define GPSR5_SCK2 ((uint32_t)1U << 9U)
+#define GPSR5_RTS1_TANS ((uint32_t)1U << 8U)
+#define GPSR5_CTS1 ((uint32_t)1U << 7U)
+#define GPSR5_TX1_A ((uint32_t)1U << 6U)
+#define GPSR5_RX1_A ((uint32_t)1U << 5U)
+#define GPSR5_RTS0_TANS ((uint32_t)1U << 4U)
+#define GPSR5_CTS0 ((uint32_t)1U << 3U)
+#define GPSR5_TX0 ((uint32_t)1U << 2U)
+#define GPSR5_RX0 ((uint32_t)1U << 1U)
+#define GPSR5_SCK0 ((uint32_t)1U << 0U)
+#define GPSR6_USB31_OVC ((uint32_t)1U << 31U)
+#define GPSR6_USB31_PWEN ((uint32_t)1U << 30U)
+#define GPSR6_USB30_OVC ((uint32_t)1U << 29U)
+#define GPSR6_USB30_PWEN ((uint32_t)1U << 28U)
+#define GPSR6_USB1_OVC ((uint32_t)1U << 27U)
+#define GPSR6_USB1_PWEN ((uint32_t)1U << 26U)
+#define GPSR6_USB0_OVC ((uint32_t)1U << 25U)
+#define GPSR6_USB0_PWEN ((uint32_t)1U << 24U)
+#define GPSR6_AUDIO_CLKB_B ((uint32_t)1U << 23U)
+#define GPSR6_AUDIO_CLKA_A ((uint32_t)1U << 22U)
+#define GPSR6_SSI_SDATA9_A ((uint32_t)1U << 21U)
+#define GPSR6_SSI_SDATA8 ((uint32_t)1U << 20U)
+#define GPSR6_SSI_SDATA7 ((uint32_t)1U << 19U)
+#define GPSR6_SSI_WS78 ((uint32_t)1U << 18U)
+#define GPSR6_SSI_SCK78 ((uint32_t)1U << 17U)
+#define GPSR6_SSI_SDATA6 ((uint32_t)1U << 16U)
+#define GPSR6_SSI_WS6 ((uint32_t)1U << 15U)
+#define GPSR6_SSI_SCK6 ((uint32_t)1U << 14U)
+#define GPSR6_SSI_SDATA5 ((uint32_t)1U << 13U)
+#define GPSR6_SSI_WS5 ((uint32_t)1U << 12U)
+#define GPSR6_SSI_SCK5 ((uint32_t)1U << 11U)
+#define GPSR6_SSI_SDATA4 ((uint32_t)1U << 10U)
+#define GPSR6_SSI_WS4 ((uint32_t)1U << 9U)
+#define GPSR6_SSI_SCK4 ((uint32_t)1U << 8U)
+#define GPSR6_SSI_SDATA3 ((uint32_t)1U << 7U)
+#define GPSR6_SSI_WS34 ((uint32_t)1U << 6U)
+#define GPSR6_SSI_SCK34 ((uint32_t)1U << 5U)
+#define GPSR6_SSI_SDATA2_A ((uint32_t)1U << 4U)
+#define GPSR6_SSI_SDATA1_A ((uint32_t)1U << 3U)
+#define GPSR6_SSI_SDATA0 ((uint32_t)1U << 2U)
+#define GPSR6_SSI_WS0129 ((uint32_t)1U << 1U)
+#define GPSR6_SSI_SCK0129 ((uint32_t)1U << 0U)
+#define GPSR7_HDMI1_CEC ((uint32_t)1U << 3U)
+#define GPSR7_HDMI0_CEC ((uint32_t)1U << 2U)
+#define GPSR7_AVS2 ((uint32_t)1U << 1U)
+#define GPSR7_AVS1 ((uint32_t)1U << 0U)
-#define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U)
-#define IPSR_24_FUNC(x) ((uint32_t)(x) << 24U)
-#define IPSR_20_FUNC(x) ((uint32_t)(x) << 20U)
-#define IPSR_16_FUNC(x) ((uint32_t)(x) << 16U)
-#define IPSR_12_FUNC(x) ((uint32_t)(x) << 12U)
-#define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U)
-#define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U)
-#define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U)
+#define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U)
+#define IPSR_24_FUNC(x) ((uint32_t)(x) << 24U)
+#define IPSR_20_FUNC(x) ((uint32_t)(x) << 20U)
+#define IPSR_16_FUNC(x) ((uint32_t)(x) << 16U)
+#define IPSR_12_FUNC(x) ((uint32_t)(x) << 12U)
+#define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U)
+#define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U)
+#define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U)
-#define POC_SD3_DS_33V ((uint32_t)1U << 29U)
-#define POC_SD3_DAT7_33V ((uint32_t)1U << 28U)
-#define POC_SD3_DAT6_33V ((uint32_t)1U << 27U)
-#define POC_SD3_DAT5_33V ((uint32_t)1U << 26U)
-#define POC_SD3_DAT4_33V ((uint32_t)1U << 25U)
-#define POC_SD3_DAT3_33V ((uint32_t)1U << 24U)
-#define POC_SD3_DAT2_33V ((uint32_t)1U << 23U)
-#define POC_SD3_DAT1_33V ((uint32_t)1U << 22U)
-#define POC_SD3_DAT0_33V ((uint32_t)1U << 21U)
-#define POC_SD3_CMD_33V ((uint32_t)1U << 20U)
-#define POC_SD3_CLK_33V ((uint32_t)1U << 19U)
-#define POC_SD2_DS_33V ((uint32_t)1U << 18U)
-#define POC_SD2_DAT3_33V ((uint32_t)1U << 17U)
-#define POC_SD2_DAT2_33V ((uint32_t)1U << 16U)
-#define POC_SD2_DAT1_33V ((uint32_t)1U << 15U)
-#define POC_SD2_DAT0_33V ((uint32_t)1U << 14U)
-#define POC_SD2_CMD_33V ((uint32_t)1U << 13U)
-#define POC_SD2_CLK_33V ((uint32_t)1U << 12U)
-#define POC_SD1_DAT3_33V ((uint32_t)1U << 11U)
-#define POC_SD1_DAT2_33V ((uint32_t)1U << 10U)
-#define POC_SD1_DAT1_33V ((uint32_t)1U << 9U)
-#define POC_SD1_DAT0_33V ((uint32_t)1U << 8U)
-#define POC_SD1_CMD_33V ((uint32_t)1U << 7U)
-#define POC_SD1_CLK_33V ((uint32_t)1U << 6U)
-#define POC_SD0_DAT3_33V ((uint32_t)1U << 5U)
-#define POC_SD0_DAT2_33V ((uint32_t)1U << 4U)
-#define POC_SD0_DAT1_33V ((uint32_t)1U << 3U)
-#define POC_SD0_DAT0_33V ((uint32_t)1U << 2U)
-#define POC_SD0_CMD_33V ((uint32_t)1U << 1U)
-#define POC_SD0_CLK_33V ((uint32_t)1U << 0U)
+#define POC_SD3_DS_33V ((uint32_t)1U << 29U)
+#define POC_SD3_DAT7_33V ((uint32_t)1U << 28U)
+#define POC_SD3_DAT6_33V ((uint32_t)1U << 27U)
+#define POC_SD3_DAT5_33V ((uint32_t)1U << 26U)
+#define POC_SD3_DAT4_33V ((uint32_t)1U << 25U)
+#define POC_SD3_DAT3_33V ((uint32_t)1U << 24U)
+#define POC_SD3_DAT2_33V ((uint32_t)1U << 23U)
+#define POC_SD3_DAT1_33V ((uint32_t)1U << 22U)
+#define POC_SD3_DAT0_33V ((uint32_t)1U << 21U)
+#define POC_SD3_CMD_33V ((uint32_t)1U << 20U)
+#define POC_SD3_CLK_33V ((uint32_t)1U << 19U)
+#define POC_SD2_DS_33V ((uint32_t)1U << 18U)
+#define POC_SD2_DAT3_33V ((uint32_t)1U << 17U)
+#define POC_SD2_DAT2_33V ((uint32_t)1U << 16U)
+#define POC_SD2_DAT1_33V ((uint32_t)1U << 15U)
+#define POC_SD2_DAT0_33V ((uint32_t)1U << 14U)
+#define POC_SD2_CMD_33V ((uint32_t)1U << 13U)
+#define POC_SD2_CLK_33V ((uint32_t)1U << 12U)
+#define POC_SD1_DAT3_33V ((uint32_t)1U << 11U)
+#define POC_SD1_DAT2_33V ((uint32_t)1U << 10U)
+#define POC_SD1_DAT1_33V ((uint32_t)1U << 9U)
+#define POC_SD1_DAT0_33V ((uint32_t)1U << 8U)
+#define POC_SD1_CMD_33V ((uint32_t)1U << 7U)
+#define POC_SD1_CLK_33V ((uint32_t)1U << 6U)
+#define POC_SD0_DAT3_33V ((uint32_t)1U << 5U)
+#define POC_SD0_DAT2_33V ((uint32_t)1U << 4U)
+#define POC_SD0_DAT1_33V ((uint32_t)1U << 3U)
+#define POC_SD0_DAT0_33V ((uint32_t)1U << 2U)
+#define POC_SD0_CMD_33V ((uint32_t)1U << 1U)
+#define POC_SD0_CLK_33V ((uint32_t)1U << 0U)
-#define DRVCTRL0_MASK (0xCCCCCCCCU)
-#define DRVCTRL1_MASK (0xCCCCCCC8U)
-#define DRVCTRL2_MASK (0x88888888U)
-#define DRVCTRL3_MASK (0x88888888U)
-#define DRVCTRL4_MASK (0x88888888U)
-#define DRVCTRL5_MASK (0x88888888U)
-#define DRVCTRL6_MASK (0x88888888U)
-#define DRVCTRL7_MASK (0x88888888U)
-#define DRVCTRL8_MASK (0x88888888U)
-#define DRVCTRL9_MASK (0x88888888U)
-#define DRVCTRL10_MASK (0x88888888U)
-#define DRVCTRL11_MASK (0x888888CCU)
-#define DRVCTRL12_MASK (0xCCCFFFCFU)
-#define DRVCTRL13_MASK (0xCC888888U)
-#define DRVCTRL14_MASK (0x88888888U)
-#define DRVCTRL15_MASK (0x88888888U)
-#define DRVCTRL16_MASK (0x88888888U)
-#define DRVCTRL17_MASK (0x88888888U)
-#define DRVCTRL18_MASK (0x88888888U)
-#define DRVCTRL19_MASK (0x88888888U)
-#define DRVCTRL20_MASK (0x88888888U)
-#define DRVCTRL21_MASK (0x88888888U)
-#define DRVCTRL22_MASK (0x88888888U)
-#define DRVCTRL23_MASK (0x88888888U)
-#define DRVCTRL24_MASK (0x8888888FU)
+#define DRVCTRL0_MASK (0xCCCCCCCCU)
+#define DRVCTRL1_MASK (0xCCCCCCC8U)
+#define DRVCTRL2_MASK (0x88888888U)
+#define DRVCTRL3_MASK (0x88888888U)
+#define DRVCTRL4_MASK (0x88888888U)
+#define DRVCTRL5_MASK (0x88888888U)
+#define DRVCTRL6_MASK (0x88888888U)
+#define DRVCTRL7_MASK (0x88888888U)
+#define DRVCTRL8_MASK (0x88888888U)
+#define DRVCTRL9_MASK (0x88888888U)
+#define DRVCTRL10_MASK (0x88888888U)
+#define DRVCTRL11_MASK (0x888888CCU)
+#define DRVCTRL12_MASK (0xCCCFFFCFU)
+#define DRVCTRL13_MASK (0xCC888888U)
+#define DRVCTRL14_MASK (0x88888888U)
+#define DRVCTRL15_MASK (0x88888888U)
+#define DRVCTRL16_MASK (0x88888888U)
+#define DRVCTRL17_MASK (0x88888888U)
+#define DRVCTRL18_MASK (0x88888888U)
+#define DRVCTRL19_MASK (0x88888888U)
+#define DRVCTRL20_MASK (0x88888888U)
+#define DRVCTRL21_MASK (0x88888888U)
+#define DRVCTRL22_MASK (0x88888888U)
+#define DRVCTRL23_MASK (0x88888888U)
+#define DRVCTRL24_MASK (0x8888888FU)
-#define DRVCTRL0_QSPI0_SPCLK(x) ((uint32_t)(x) << 28U)
-#define DRVCTRL0_QSPI0_MOSI_IO0(x) ((uint32_t)(x) << 24U)
-#define DRVCTRL0_QSPI0_MISO_IO1(x) ((uint32_t)(x) << 20U)
-#define DRVCTRL0_QSPI0_IO2(x) ((uint32_t)(x) << 16U)
-#define DRVCTRL0_QSPI0_IO3(x) ((uint32_t)(x) << 12U)
-#define DRVCTRL0_QSPI0_SSL(x) ((uint32_t)(x) << 8U)
-#define DRVCTRL0_QSPI1_SPCLK(x) ((uint32_t)(x) << 4U)
-#define DRVCTRL0_QSPI1_MOSI_IO0(x) ((uint32_t)(x) << 0U)
-#define DRVCTRL1_QSPI1_MISO_IO1(x) ((uint32_t)(x) << 28U)
-#define DRVCTRL1_QSPI1_IO2(x) ((uint32_t)(x) << 24U)
-#define DRVCTRL1_QSPI1_IO3(x) ((uint32_t)(x) << 20U)
-#define DRVCTRL1_QSPI1_SS(x) ((uint32_t)(x) << 16U)
-#define DRVCTRL1_RPC_INT(x) ((uint32_t)(x) << 12U)
-#define DRVCTRL1_RPC_WP(x) ((uint32_t)(x) << 8U)
-#define DRVCTRL1_RPC_RESET(x) ((uint32_t)(x) << 4U)
-#define DRVCTRL1_AVB_RX_CTL(x) ((uint32_t)(x) << 0U)
-#define DRVCTRL2_AVB_RXC(x) ((uint32_t)(x) << 28U)
-#define DRVCTRL2_AVB_RD0(x) ((uint32_t)(x) << 24U)
-#define DRVCTRL2_AVB_RD1(x) ((uint32_t)(x) << 20U)
-#define DRVCTRL2_AVB_RD2(x) ((uint32_t)(x) << 16U)
-#define DRVCTRL2_AVB_RD3(x) ((uint32_t)(x) << 12U)
-#define DRVCTRL2_AVB_TX_CTL(x) ((uint32_t)(x) << 8U)
-#define DRVCTRL2_AVB_TXC(x) ((uint32_t)(x) << 4U)
-#define DRVCTRL2_AVB_TD0(x) ((uint32_t)(x) << 0U)
-#define DRVCTRL3_AVB_TD1(x) ((uint32_t)(x) << 28U)
-#define DRVCTRL3_AVB_TD2(x) ((uint32_t)(x) << 24U)
-#define DRVCTRL3_AVB_TD3(x) ((uint32_t)(x) << 20U)
-#define DRVCTRL3_AVB_TXCREFCLK(x) ((uint32_t)(x) << 16U)
-#define DRVCTRL3_AVB_MDIO(x) ((uint32_t)(x) << 12U)
-#define DRVCTRL3_AVB_MDC(x) ((uint32_t)(x) << 8U)
-#define DRVCTRL3_AVB_MAGIC(x) ((uint32_t)(x) << 4U)
-#define DRVCTRL3_AVB_PHY_INT(x) ((uint32_t)(x) << 0U)
-#define DRVCTRL4_AVB_LINK(x) ((uint32_t)(x) << 28U)
-#define DRVCTRL4_AVB_AVTP_MATCH(x) ((uint32_t)(x) << 24U)
-#define DRVCTRL4_AVB_AVTP_CAPTURE(x) ((uint32_t)(x) << 20U)
-#define DRVCTRL4_IRQ0(x) ((uint32_t)(x) << 16U)
-#define DRVCTRL4_IRQ1(x) ((uint32_t)(x) << 12U)
-#define DRVCTRL4_IRQ2(x) ((uint32_t)(x) << 8U)
-#define DRVCTRL4_IRQ3(x) ((uint32_t)(x) << 4U)
-#define DRVCTRL4_IRQ4(x) ((uint32_t)(x) << 0U)
-#define DRVCTRL5_IRQ5(x) ((uint32_t)(x) << 28U)
-#define DRVCTRL5_PWM0(x) ((uint32_t)(x) << 24U)
-#define DRVCTRL5_PWM1(x) ((uint32_t)(x) << 20U)
-#define DRVCTRL5_PWM2(x) ((uint32_t)(x) << 16U)
-#define DRVCTRL5_A0(x) ((uint32_t)(x) << 12U)
-#define DRVCTRL5_A1(x) ((uint32_t)(x) << 8U)
-#define DRVCTRL5_A2(x) ((uint32_t)(x) << 4U)
-#define DRVCTRL5_A3(x) ((uint32_t)(x) << 0U)
-#define DRVCTRL6_A4(x) ((uint32_t)(x) << 28U)
-#define DRVCTRL6_A5(x) ((uint32_t)(x) << 24U)
-#define DRVCTRL6_A6(x) ((uint32_t)(x) << 20U)
-#define DRVCTRL6_A7(x) ((uint32_t)(x) << 16U)
-#define DRVCTRL6_A8(x) ((uint32_t)(x) << 12U)
-#define DRVCTRL6_A9(x) ((uint32_t)(x) << 8U)
-#define DRVCTRL6_A10(x) ((uint32_t)(x) << 4U)
-#define DRVCTRL6_A11(x) ((uint32_t)(x) << 0U)
-#define DRVCTRL7_A12(x) ((uint32_t)(x) << 28U)
-#define DRVCTRL7_A13(x) ((uint32_t)(x) << 24U)
-#define DRVCTRL7_A14(x) ((uint32_t)(x) << 20U)
-#define DRVCTRL7_A15(x) ((uint32_t)(x) << 16U)
-#define DRVCTRL7_A16(x) ((uint32_t)(x) << 12U)
-#define DRVCTRL7_A17(x) ((uint32_t)(x) << 8U)
-#define DRVCTRL7_A18(x) ((uint32_t)(x) << 4U)
-#define DRVCTRL7_A19(x) ((uint32_t)(x) << 0U)
-#define DRVCTRL8_CLKOUT(x) ((uint32_t)(x) << 28U)
-#define DRVCTRL8_CS0(x) ((uint32_t)(x) << 24U)
-#define DRVCTRL8_CS1_A2(x) ((uint32_t)(x) << 20U)
-#define DRVCTRL8_BS(x) ((uint32_t)(x) << 16U)
-#define DRVCTRL8_RD(x) ((uint32_t)(x) << 12U)
-#define DRVCTRL8_RD_W(x) ((uint32_t)(x) << 8U)
-#define DRVCTRL8_WE0(x) ((uint32_t)(x) << 4U)
-#define DRVCTRL8_WE1(x) ((uint32_t)(x) << 0U)
-#define DRVCTRL9_EX_WAIT0(x) ((uint32_t)(x) << 28U)
-#define DRVCTRL9_PRESETOU(x) ((uint32_t)(x) << 24U)
-#define DRVCTRL9_D0(x) ((uint32_t)(x) << 20U)
-#define DRVCTRL9_D1(x) ((uint32_t)(x) << 16U)
-#define DRVCTRL9_D2(x) ((uint32_t)(x) << 12U)
-#define DRVCTRL9_D3(x) ((uint32_t)(x) << 8U)
-#define DRVCTRL9_D4(x) ((uint32_t)(x) << 4U)
-#define DRVCTRL9_D5(x) ((uint32_t)(x) << 0U)
-#define DRVCTRL10_D6(x) ((uint32_t)(x) << 28U)
-#define DRVCTRL10_D7(x) ((uint32_t)(x) << 24U)
-#define DRVCTRL10_D8(x) ((uint32_t)(x) << 20U)
-#define DRVCTRL10_D9(x) ((uint32_t)(x) << 16U)
-#define DRVCTRL10_D10(x) ((uint32_t)(x) << 12U)
-#define DRVCTRL10_D11(x) ((uint32_t)(x) << 8U)
-#define DRVCTRL10_D12(x) ((uint32_t)(x) << 4U)
-#define DRVCTRL10_D13(x) ((uint32_t)(x) << 0U)
-#define DRVCTRL11_D14(x) ((uint32_t)(x) << 28U)
-#define DRVCTRL11_D15(x) ((uint32_t)(x) << 24U)
-#define DRVCTRL11_AVS1(x) ((uint32_t)(x) << 20U)
-#define DRVCTRL11_AVS2(x) ((uint32_t)(x) << 16U)
-#define DRVCTRL11_HDMI0_CEC(x) ((uint32_t)(x) << 12U)
-#define DRVCTRL11_HDMI1_CEC(x) ((uint32_t)(x) << 8U)
-#define DRVCTRL11_DU_DOTCLKIN0(x) ((uint32_t)(x) << 4U)
-#define DRVCTRL11_DU_DOTCLKIN1(x) ((uint32_t)(x) << 0U)
-#define DRVCTRL12_DU_DOTCLKIN2(x) ((uint32_t)(x) << 28U)
-#define DRVCTRL12_DU_DOTCLKIN3(x) ((uint32_t)(x) << 24U)
-#define DRVCTRL12_DU_FSCLKST(x) ((uint32_t)(x) << 20U)
-#define DRVCTRL12_DU_TMS(x) ((uint32_t)(x) << 4U)
-#define DRVCTRL13_TDO(x) ((uint32_t)(x) << 28U)
-#define DRVCTRL13_ASEBRK(x) ((uint32_t)(x) << 24U)
-#define DRVCTRL13_SD0_CLK(x) ((uint32_t)(x) << 20U)
-#define DRVCTRL13_SD0_CMD(x) ((uint32_t)(x) << 16U)
-#define DRVCTRL13_SD0_DAT0(x) ((uint32_t)(x) << 12U)
-#define DRVCTRL13_SD0_DAT1(x) ((uint32_t)(x) << 8U)
-#define DRVCTRL13_SD0_DAT2(x) ((uint32_t)(x) << 4U)
-#define DRVCTRL13_SD0_DAT3(x) ((uint32_t)(x) << 0U)
-#define DRVCTRL14_SD1_CLK(x) ((uint32_t)(x) << 28U)
-#define DRVCTRL14_SD1_CMD(x) ((uint32_t)(x) << 24U)
-#define DRVCTRL14_SD1_DAT0(x) ((uint32_t)(x) << 20U)
-#define DRVCTRL14_SD1_DAT1(x) ((uint32_t)(x) << 16U)
-#define DRVCTRL14_SD1_DAT2(x) ((uint32_t)(x) << 12U)
-#define DRVCTRL14_SD1_DAT3(x) ((uint32_t)(x) << 8U)
-#define DRVCTRL14_SD2_CLK(x) ((uint32_t)(x) << 4U)
-#define DRVCTRL14_SD2_CMD(x) ((uint32_t)(x) << 0U)
-#define DRVCTRL15_SD2_DAT0(x) ((uint32_t)(x) << 28U)
-#define DRVCTRL15_SD2_DAT1(x) ((uint32_t)(x) << 24U)
-#define DRVCTRL15_SD2_DAT2(x) ((uint32_t)(x) << 20U)
-#define DRVCTRL15_SD2_DAT3(x) ((uint32_t)(x) << 16U)
-#define DRVCTRL15_SD2_DS(x) ((uint32_t)(x) << 12U)
-#define DRVCTRL15_SD3_CLK(x) ((uint32_t)(x) << 8U)
-#define DRVCTRL15_SD3_CMD(x) ((uint32_t)(x) << 4U)
-#define DRVCTRL15_SD3_DAT0(x) ((uint32_t)(x) << 0U)
-#define DRVCTRL16_SD3_DAT1(x) ((uint32_t)(x) << 28U)
-#define DRVCTRL16_SD3_DAT2(x) ((uint32_t)(x) << 24U)
-#define DRVCTRL16_SD3_DAT3(x) ((uint32_t)(x) << 20U)
-#define DRVCTRL16_SD3_DAT4(x) ((uint32_t)(x) << 16U)
-#define DRVCTRL16_SD3_DAT5(x) ((uint32_t)(x) << 12U)
-#define DRVCTRL16_SD3_DAT6(x) ((uint32_t)(x) << 8U)
-#define DRVCTRL16_SD3_DAT7(x) ((uint32_t)(x) << 4U)
-#define DRVCTRL16_SD3_DS(x) ((uint32_t)(x) << 0U)
-#define DRVCTRL17_SD0_CD(x) ((uint32_t)(x) << 28U)
-#define DRVCTRL17_SD0_WP(x) ((uint32_t)(x) << 24U)
-#define DRVCTRL17_SD1_CD(x) ((uint32_t)(x) << 20U)
-#define DRVCTRL17_SD1_WP(x) ((uint32_t)(x) << 16U)
-#define DRVCTRL17_SCK0(x) ((uint32_t)(x) << 12U)
-#define DRVCTRL17_RX0(x) ((uint32_t)(x) << 8U)
-#define DRVCTRL17_TX0(x) ((uint32_t)(x) << 4U)
-#define DRVCTRL17_CTS0(x) ((uint32_t)(x) << 0U)
-#define DRVCTRL18_RTS0_TANS(x) ((uint32_t)(x) << 28U)
-#define DRVCTRL18_RX1(x) ((uint32_t)(x) << 24U)
-#define DRVCTRL18_TX1(x) ((uint32_t)(x) << 20U)
-#define DRVCTRL18_CTS1(x) ((uint32_t)(x) << 16U)
-#define DRVCTRL18_RTS1_TANS(x) ((uint32_t)(x) << 12U)
-#define DRVCTRL18_SCK2(x) ((uint32_t)(x) << 8U)
-#define DRVCTRL18_TX2(x) ((uint32_t)(x) << 4U)
-#define DRVCTRL18_RX2(x) ((uint32_t)(x) << 0U)
-#define DRVCTRL19_HSCK0(x) ((uint32_t)(x) << 28U)
-#define DRVCTRL19_HRX0(x) ((uint32_t)(x) << 24U)
-#define DRVCTRL19_HTX0(x) ((uint32_t)(x) << 20U)
-#define DRVCTRL19_HCTS0(x) ((uint32_t)(x) << 16U)
-#define DRVCTRL19_HRTS0(x) ((uint32_t)(x) << 12U)
-#define DRVCTRL19_MSIOF0_SCK(x) ((uint32_t)(x) << 8U)
-#define DRVCTRL19_MSIOF0_SYNC(x) ((uint32_t)(x) << 4U)
-#define DRVCTRL19_MSIOF0_SS1(x) ((uint32_t)(x) << 0U)
-#define DRVCTRL20_MSIOF0_TXD(x) ((uint32_t)(x) << 28U)
-#define DRVCTRL20_MSIOF0_SS2(x) ((uint32_t)(x) << 24U)
-#define DRVCTRL20_MSIOF0_RXD(x) ((uint32_t)(x) << 20U)
-#define DRVCTRL20_MLB_CLK(x) ((uint32_t)(x) << 16U)
-#define DRVCTRL20_MLB_SIG(x) ((uint32_t)(x) << 12U)
-#define DRVCTRL20_MLB_DAT(x) ((uint32_t)(x) << 8U)
-#define DRVCTRL20_MLB_REF(x) ((uint32_t)(x) << 4U)
-#define DRVCTRL20_SSI_SCK0129(x) ((uint32_t)(x) << 0U)
-#define DRVCTRL21_SSI_WS0129(x) ((uint32_t)(x) << 28U)
-#define DRVCTRL21_SSI_SDATA0(x) ((uint32_t)(x) << 24U)
-#define DRVCTRL21_SSI_SDATA1(x) ((uint32_t)(x) << 20U)
-#define DRVCTRL21_SSI_SDATA2(x) ((uint32_t)(x) << 16U)
-#define DRVCTRL21_SSI_SCK34(x) ((uint32_t)(x) << 12U)
-#define DRVCTRL21_SSI_WS34(x) ((uint32_t)(x) << 8U)
-#define DRVCTRL21_SSI_SDATA3(x) ((uint32_t)(x) << 4U)
-#define DRVCTRL21_SSI_SCK4(x) ((uint32_t)(x) << 0U)
-#define DRVCTRL22_SSI_WS4(x) ((uint32_t)(x) << 28U)
-#define DRVCTRL22_SSI_SDATA4(x) ((uint32_t)(x) << 24U)
-#define DRVCTRL22_SSI_SCK5(x) ((uint32_t)(x) << 20U)
-#define DRVCTRL22_SSI_WS5(x) ((uint32_t)(x) << 16U)
-#define DRVCTRL22_SSI_SDATA5(x) ((uint32_t)(x) << 12U)
-#define DRVCTRL22_SSI_SCK6(x) ((uint32_t)(x) << 8U)
-#define DRVCTRL22_SSI_WS6(x) ((uint32_t)(x) << 4U)
-#define DRVCTRL22_SSI_SDATA6(x) ((uint32_t)(x) << 0U)
-#define DRVCTRL23_SSI_SCK78(x) ((uint32_t)(x) << 28U)
-#define DRVCTRL23_SSI_WS78(x) ((uint32_t)(x) << 24U)
-#define DRVCTRL23_SSI_SDATA7(x) ((uint32_t)(x) << 20U)
-#define DRVCTRL23_SSI_SDATA8(x) ((uint32_t)(x) << 16U)
-#define DRVCTRL23_SSI_SDATA9(x) ((uint32_t)(x) << 12U)
-#define DRVCTRL23_AUDIO_CLKA(x) ((uint32_t)(x) << 8U)
-#define DRVCTRL23_AUDIO_CLKB(x) ((uint32_t)(x) << 4U)
-#define DRVCTRL23_USB0_PWEN(x) ((uint32_t)(x) << 0U)
-#define DRVCTRL24_USB0_OVC(x) ((uint32_t)(x) << 28U)
-#define DRVCTRL24_USB1_PWEN(x) ((uint32_t)(x) << 24U)
-#define DRVCTRL24_USB1_OVC(x) ((uint32_t)(x) << 20U)
-#define DRVCTRL24_USB30_PWEN(x) ((uint32_t)(x) << 16U)
-#define DRVCTRL24_USB30_OVC(x) ((uint32_t)(x) << 12U)
-#define DRVCTRL24_USB31_PWEN(x) ((uint32_t)(x) << 8U)
-#define DRVCTRL24_USB31_OVC(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL0_QSPI0_SPCLK(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL0_QSPI0_MOSI_IO0(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL0_QSPI0_MISO_IO1(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL0_QSPI0_IO2(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL0_QSPI0_IO3(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL0_QSPI0_SSL(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL0_QSPI1_SPCLK(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL0_QSPI1_MOSI_IO0(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL1_QSPI1_MISO_IO1(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL1_QSPI1_IO2(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL1_QSPI1_IO3(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL1_QSPI1_SS(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL1_RPC_INT(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL1_RPC_WP(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL1_RPC_RESET(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL1_AVB_RX_CTL(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL2_AVB_RXC(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL2_AVB_RD0(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL2_AVB_RD1(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL2_AVB_RD2(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL2_AVB_RD3(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL2_AVB_TX_CTL(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL2_AVB_TXC(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL2_AVB_TD0(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL3_AVB_TD1(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL3_AVB_TD2(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL3_AVB_TD3(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL3_AVB_TXCREFCLK(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL3_AVB_MDIO(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL3_AVB_MDC(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL3_AVB_MAGIC(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL3_AVB_PHY_INT(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL4_AVB_LINK(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL4_AVB_AVTP_MATCH(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL4_AVB_AVTP_CAPTURE(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL4_IRQ0(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL4_IRQ1(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL4_IRQ2(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL4_IRQ3(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL4_IRQ4(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL5_IRQ5(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL5_PWM0(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL5_PWM1(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL5_PWM2(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL5_A0(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL5_A1(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL5_A2(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL5_A3(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL6_A4(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL6_A5(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL6_A6(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL6_A7(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL6_A8(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL6_A9(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL6_A10(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL6_A11(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL7_A12(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL7_A13(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL7_A14(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL7_A15(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL7_A16(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL7_A17(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL7_A18(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL7_A19(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL8_CLKOUT(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL8_CS0(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL8_CS1_A2(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL8_BS(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL8_RD(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL8_RD_W(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL8_WE0(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL8_WE1(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL9_EX_WAIT0(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL9_PRESETOU(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL9_D0(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL9_D1(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL9_D2(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL9_D3(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL9_D4(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL9_D5(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL10_D6(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL10_D7(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL10_D8(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL10_D9(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL10_D10(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL10_D11(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL10_D12(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL10_D13(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL11_D14(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL11_D15(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL11_AVS1(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL11_AVS2(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL11_HDMI0_CEC(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL11_HDMI1_CEC(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL11_DU_DOTCLKIN0(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL11_DU_DOTCLKIN1(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL12_DU_DOTCLKIN2(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL12_DU_DOTCLKIN3(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL12_DU_FSCLKST(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL12_DU_TMS(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL13_TDO(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL13_ASEBRK(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL13_SD0_CLK(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL13_SD0_CMD(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL13_SD0_DAT0(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL13_SD0_DAT1(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL13_SD0_DAT2(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL13_SD0_DAT3(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL14_SD1_CLK(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL14_SD1_CMD(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL14_SD1_DAT0(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL14_SD1_DAT1(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL14_SD1_DAT2(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL14_SD1_DAT3(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL14_SD2_CLK(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL14_SD2_CMD(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL15_SD2_DAT0(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL15_SD2_DAT1(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL15_SD2_DAT2(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL15_SD2_DAT3(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL15_SD2_DS(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL15_SD3_CLK(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL15_SD3_CMD(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL15_SD3_DAT0(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL16_SD3_DAT1(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL16_SD3_DAT2(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL16_SD3_DAT3(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL16_SD3_DAT4(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL16_SD3_DAT5(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL16_SD3_DAT6(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL16_SD3_DAT7(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL16_SD3_DS(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL17_SD0_CD(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL17_SD0_WP(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL17_SD1_CD(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL17_SD1_WP(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL17_SCK0(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL17_RX0(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL17_TX0(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL17_CTS0(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL18_RTS0_TANS(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL18_RX1(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL18_TX1(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL18_CTS1(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL18_RTS1_TANS(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL18_SCK2(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL18_TX2(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL18_RX2(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL19_HSCK0(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL19_HRX0(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL19_HTX0(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL19_HCTS0(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL19_HRTS0(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL19_MSIOF0_SCK(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL19_MSIOF0_SYNC(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL19_MSIOF0_SS1(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL20_MSIOF0_TXD(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL20_MSIOF0_SS2(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL20_MSIOF0_RXD(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL20_MLB_CLK(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL20_MLB_SIG(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL20_MLB_DAT(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL20_MLB_REF(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL20_SSI_SCK0129(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL21_SSI_WS0129(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL21_SSI_SDATA0(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL21_SSI_SDATA1(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL21_SSI_SDATA2(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL21_SSI_SCK34(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL21_SSI_WS34(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL21_SSI_SDATA3(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL21_SSI_SCK4(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL22_SSI_WS4(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL22_SSI_SDATA4(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL22_SSI_SCK5(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL22_SSI_WS5(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL22_SSI_SDATA5(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL22_SSI_SCK6(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL22_SSI_WS6(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL22_SSI_SDATA6(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL23_SSI_SCK78(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL23_SSI_WS78(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL23_SSI_SDATA7(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL23_SSI_SDATA8(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL23_SSI_SDATA9(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL23_AUDIO_CLKA(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL23_AUDIO_CLKB(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL23_USB0_PWEN(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL24_USB0_OVC(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL24_USB1_PWEN(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL24_USB1_OVC(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL24_USB30_PWEN(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL24_USB30_OVC(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL24_USB31_PWEN(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL24_USB31_OVC(x) ((uint32_t)(x) << 4U)
-#define MOD_SEL0_MSIOF3_A ((uint32_t)0U << 29U)
-#define MOD_SEL0_MSIOF3_B ((uint32_t)1U << 29U)
-#define MOD_SEL0_MSIOF3_C ((uint32_t)2U << 29U)
-#define MOD_SEL0_MSIOF3_D ((uint32_t)3U << 29U)
-#define MOD_SEL0_MSIOF3_E ((uint32_t)4U << 29U)
-#define MOD_SEL0_MSIOF2_A ((uint32_t)0U << 27U)
-#define MOD_SEL0_MSIOF2_B ((uint32_t)1U << 27U)
-#define MOD_SEL0_MSIOF2_C ((uint32_t)2U << 27U)
-#define MOD_SEL0_MSIOF2_D ((uint32_t)3U << 27U)
-#define MOD_SEL0_MSIOF1_A ((uint32_t)0U << 24U)
-#define MOD_SEL0_MSIOF1_B ((uint32_t)1U << 24U)
-#define MOD_SEL0_MSIOF1_C ((uint32_t)2U << 24U)
-#define MOD_SEL0_MSIOF1_D ((uint32_t)3U << 24U)
-#define MOD_SEL0_MSIOF1_E ((uint32_t)4U << 24U)
-#define MOD_SEL0_MSIOF1_F ((uint32_t)5U << 24U)
-#define MOD_SEL0_MSIOF1_G ((uint32_t)6U << 24U)
-#define MOD_SEL0_LBSC_A ((uint32_t)0U << 23U)
-#define MOD_SEL0_LBSC_B ((uint32_t)1U << 23U)
-#define MOD_SEL0_IEBUS_A ((uint32_t)0U << 22U)
-#define MOD_SEL0_IEBUS_B ((uint32_t)1U << 22U)
-#define MOD_SEL0_I2C2_A ((uint32_t)0U << 21U)
-#define MOD_SEL0_I2C2_B ((uint32_t)1U << 21U)
-#define MOD_SEL0_I2C1_A ((uint32_t)0U << 20U)
-#define MOD_SEL0_I2C1_B ((uint32_t)1U << 20U)
-#define MOD_SEL0_HSCIF4_A ((uint32_t)0U << 19U)
-#define MOD_SEL0_HSCIF4_B ((uint32_t)1U << 19U)
-#define MOD_SEL0_HSCIF3_A ((uint32_t)0U << 17U)
-#define MOD_SEL0_HSCIF3_B ((uint32_t)1U << 17U)
-#define MOD_SEL0_HSCIF3_C ((uint32_t)2U << 17U)
-#define MOD_SEL0_HSCIF3_D ((uint32_t)3U << 17U)
-#define MOD_SEL0_HSCIF1_A ((uint32_t)0U << 16U)
-#define MOD_SEL0_HSCIF1_B ((uint32_t)1U << 16U)
-#define MOD_SEL0_FSO_A ((uint32_t)0U << 15U)
-#define MOD_SEL0_FSO_B ((uint32_t)1U << 15U)
-#define MOD_SEL0_HSCIF2_A ((uint32_t)0U << 13U)
-#define MOD_SEL0_HSCIF2_B ((uint32_t)1U << 13U)
-#define MOD_SEL0_HSCIF2_C ((uint32_t)2U << 13U)
-#define MOD_SEL0_ETHERAVB_A ((uint32_t)0U << 12U)
-#define MOD_SEL0_ETHERAVB_B ((uint32_t)1U << 12U)
-#define MOD_SEL0_DRIF3_A ((uint32_t)0U << 11U)
-#define MOD_SEL0_DRIF3_B ((uint32_t)1U << 11U)
-#define MOD_SEL0_DRIF2_A ((uint32_t)0U << 10U)
-#define MOD_SEL0_DRIF2_B ((uint32_t)1U << 10U)
-#define MOD_SEL0_DRIF1_A ((uint32_t)0U << 8U)
-#define MOD_SEL0_DRIF1_B ((uint32_t)1U << 8U)
-#define MOD_SEL0_DRIF1_C ((uint32_t)2U << 8U)
-#define MOD_SEL0_DRIF0_A ((uint32_t)0U << 6U)
-#define MOD_SEL0_DRIF0_B ((uint32_t)1U << 6U)
-#define MOD_SEL0_DRIF0_C ((uint32_t)2U << 6U)
-#define MOD_SEL0_CANFD0_A ((uint32_t)0U << 5U)
-#define MOD_SEL0_CANFD0_B ((uint32_t)1U << 5U)
-#define MOD_SEL0_ADG_A_A ((uint32_t)0U << 3U)
-#define MOD_SEL0_ADG_A_B ((uint32_t)1U << 3U)
-#define MOD_SEL0_ADG_A_C ((uint32_t)2U << 3U)
-#define MOD_SEL1_TSIF1_A ((uint32_t)0U << 30U)
-#define MOD_SEL1_TSIF1_B ((uint32_t)1U << 30U)
-#define MOD_SEL1_TSIF1_C ((uint32_t)2U << 30U)
-#define MOD_SEL1_TSIF1_D ((uint32_t)3U << 30U)
-#define MOD_SEL1_TSIF0_A ((uint32_t)0U << 27U)
-#define MOD_SEL1_TSIF0_B ((uint32_t)1U << 27U)
-#define MOD_SEL1_TSIF0_C ((uint32_t)2U << 27U)
-#define MOD_SEL1_TSIF0_D ((uint32_t)3U << 27U)
-#define MOD_SEL1_TSIF0_E ((uint32_t)4U << 27U)
-#define MOD_SEL1_TIMER_TMU_A ((uint32_t)0U << 26U)
-#define MOD_SEL1_TIMER_TMU_B ((uint32_t)1U << 26U)
-#define MOD_SEL1_SSP1_1_A ((uint32_t)0U << 24U)
-#define MOD_SEL1_SSP1_1_B ((uint32_t)1U << 24U)
-#define MOD_SEL1_SSP1_1_C ((uint32_t)2U << 24U)
-#define MOD_SEL1_SSP1_1_D ((uint32_t)3U << 24U)
-#define MOD_SEL1_SSP1_0_A ((uint32_t)0U << 21U)
-#define MOD_SEL1_SSP1_0_B ((uint32_t)1U << 21U)
-#define MOD_SEL1_SSP1_0_C ((uint32_t)2U << 21U)
-#define MOD_SEL1_SSP1_0_D ((uint32_t)3U << 21U)
-#define MOD_SEL1_SSP1_0_E ((uint32_t)4U << 21U)
-#define MOD_SEL1_SSI_A ((uint32_t)0U << 20U)
-#define MOD_SEL1_SSI_B ((uint32_t)1U << 20U)
-#define MOD_SEL1_SPEED_PULSE_IF_A ((uint32_t)0U << 19U)
-#define MOD_SEL1_SPEED_PULSE_IF_B ((uint32_t)1U << 19U)
-#define MOD_SEL1_SIMCARD_A ((uint32_t)0U << 17U)
-#define MOD_SEL1_SIMCARD_B ((uint32_t)1U << 17U)
-#define MOD_SEL1_SIMCARD_C ((uint32_t)2U << 17U)
-#define MOD_SEL1_SIMCARD_D ((uint32_t)3U << 17U)
-#define MOD_SEL1_SDHI2_A ((uint32_t)0U << 16U)
-#define MOD_SEL1_SDHI2_B ((uint32_t)1U << 16U)
-#define MOD_SEL1_SCIF4_A ((uint32_t)0U << 14U)
-#define MOD_SEL1_SCIF4_B ((uint32_t)1U << 14U)
-#define MOD_SEL1_SCIF4_C ((uint32_t)2U << 14U)
-#define MOD_SEL1_SCIF3_A ((uint32_t)0U << 13U)
-#define MOD_SEL1_SCIF3_B ((uint32_t)1U << 13U)
-#define MOD_SEL1_SCIF2_A ((uint32_t)0U << 12U)
-#define MOD_SEL1_SCIF2_B ((uint32_t)1U << 12U)
-#define MOD_SEL1_SCIF1_A ((uint32_t)0U << 11U)
-#define MOD_SEL1_SCIF1_B ((uint32_t)1U << 11U)
-#define MOD_SEL1_SCIF_A ((uint32_t)0U << 10U)
-#define MOD_SEL1_SCIF_B ((uint32_t)1U << 10U)
-#define MOD_SEL1_REMOCON_A ((uint32_t)0U << 9U)
-#define MOD_SEL1_REMOCON_B ((uint32_t)1U << 9U)
-#define MOD_SEL1_RCAN0_A ((uint32_t)0U << 6U)
-#define MOD_SEL1_RCAN0_B ((uint32_t)1U << 6U)
-#define MOD_SEL1_PWM6_A ((uint32_t)0U << 5U)
-#define MOD_SEL1_PWM6_B ((uint32_t)1U << 5U)
-#define MOD_SEL1_PWM5_A ((uint32_t)0U << 4U)
-#define MOD_SEL1_PWM5_B ((uint32_t)1U << 4U)
-#define MOD_SEL1_PWM4_A ((uint32_t)0U << 3U)
-#define MOD_SEL1_PWM4_B ((uint32_t)1U << 3U)
-#define MOD_SEL1_PWM3_A ((uint32_t)0U << 2U)
-#define MOD_SEL1_PWM3_B ((uint32_t)1U << 2U)
-#define MOD_SEL1_PWM2_A ((uint32_t)0U << 1U)
-#define MOD_SEL1_PWM2_B ((uint32_t)1U << 1U)
-#define MOD_SEL1_PWM1_A ((uint32_t)0U << 0U)
-#define MOD_SEL1_PWM1_B ((uint32_t)1U << 0U)
-#define MOD_SEL2_I2C_5_A ((uint32_t)0U << 31U)
-#define MOD_SEL2_I2C_5_B ((uint32_t)1U << 31U)
-#define MOD_SEL2_I2C_3_A ((uint32_t)0U << 30U)
-#define MOD_SEL2_I2C_3_B ((uint32_t)1U << 30U)
-#define MOD_SEL2_I2C_0_A ((uint32_t)0U << 29U)
-#define MOD_SEL2_I2C_0_B ((uint32_t)1U << 29U)
-#define MOD_SEL2_FM_A ((uint32_t)0U << 27U)
-#define MOD_SEL2_FM_B ((uint32_t)1U << 27U)
-#define MOD_SEL2_FM_C ((uint32_t)2U << 27U)
-#define MOD_SEL2_FM_D ((uint32_t)3U << 27U)
-#define MOD_SEL2_SCIF5_A ((uint32_t)0U << 26U)
-#define MOD_SEL2_SCIF5_B ((uint32_t)1U << 26U)
-#define MOD_SEL2_I2C6_A ((uint32_t)0U << 23U)
-#define MOD_SEL2_I2C6_B ((uint32_t)1U << 23U)
-#define MOD_SEL2_I2C6_C ((uint32_t)2U << 23U)
-#define MOD_SEL2_NDF_A ((uint32_t)0U << 22U)
-#define MOD_SEL2_NDF_B ((uint32_t)1U << 22U)
-#define MOD_SEL2_SSI2_A ((uint32_t)0U << 21U)
-#define MOD_SEL2_SSI2_B ((uint32_t)1U << 21U)
-#define MOD_SEL2_SSI9_A ((uint32_t)0U << 20U)
-#define MOD_SEL2_SSI9_B ((uint32_t)1U << 20U)
-#define MOD_SEL2_TIMER_TMU2_A ((uint32_t)0U << 19U)
-#define MOD_SEL2_TIMER_TMU2_B ((uint32_t)1U << 19U)
-#define MOD_SEL2_ADG_B_A ((uint32_t)0U << 18U)
-#define MOD_SEL2_ADG_B_B ((uint32_t)1U << 18U)
-#define MOD_SEL2_ADG_C_A ((uint32_t)0U << 17U)
-#define MOD_SEL2_ADG_C_B ((uint32_t)1U << 17U)
-#define MOD_SEL2_VIN4_A ((uint32_t)0U << 0U)
-#define MOD_SEL2_VIN4_B ((uint32_t)1U << 0U)
+#define MOD_SEL0_MSIOF3_A ((uint32_t)0U << 29U)
+#define MOD_SEL0_MSIOF3_B ((uint32_t)1U << 29U)
+#define MOD_SEL0_MSIOF3_C ((uint32_t)2U << 29U)
+#define MOD_SEL0_MSIOF3_D ((uint32_t)3U << 29U)
+#define MOD_SEL0_MSIOF3_E ((uint32_t)4U << 29U)
+#define MOD_SEL0_MSIOF2_A ((uint32_t)0U << 27U)
+#define MOD_SEL0_MSIOF2_B ((uint32_t)1U << 27U)
+#define MOD_SEL0_MSIOF2_C ((uint32_t)2U << 27U)
+#define MOD_SEL0_MSIOF2_D ((uint32_t)3U << 27U)
+#define MOD_SEL0_MSIOF1_A ((uint32_t)0U << 24U)
+#define MOD_SEL0_MSIOF1_B ((uint32_t)1U << 24U)
+#define MOD_SEL0_MSIOF1_C ((uint32_t)2U << 24U)
+#define MOD_SEL0_MSIOF1_D ((uint32_t)3U << 24U)
+#define MOD_SEL0_MSIOF1_E ((uint32_t)4U << 24U)
+#define MOD_SEL0_MSIOF1_F ((uint32_t)5U << 24U)
+#define MOD_SEL0_MSIOF1_G ((uint32_t)6U << 24U)
+#define MOD_SEL0_LBSC_A ((uint32_t)0U << 23U)
+#define MOD_SEL0_LBSC_B ((uint32_t)1U << 23U)
+#define MOD_SEL0_IEBUS_A ((uint32_t)0U << 22U)
+#define MOD_SEL0_IEBUS_B ((uint32_t)1U << 22U)
+#define MOD_SEL0_I2C2_A ((uint32_t)0U << 21U)
+#define MOD_SEL0_I2C2_B ((uint32_t)1U << 21U)
+#define MOD_SEL0_I2C1_A ((uint32_t)0U << 20U)
+#define MOD_SEL0_I2C1_B ((uint32_t)1U << 20U)
+#define MOD_SEL0_HSCIF4_A ((uint32_t)0U << 19U)
+#define MOD_SEL0_HSCIF4_B ((uint32_t)1U << 19U)
+#define MOD_SEL0_HSCIF3_A ((uint32_t)0U << 17U)
+#define MOD_SEL0_HSCIF3_B ((uint32_t)1U << 17U)
+#define MOD_SEL0_HSCIF3_C ((uint32_t)2U << 17U)
+#define MOD_SEL0_HSCIF3_D ((uint32_t)3U << 17U)
+#define MOD_SEL0_HSCIF1_A ((uint32_t)0U << 16U)
+#define MOD_SEL0_HSCIF1_B ((uint32_t)1U << 16U)
+#define MOD_SEL0_FSO_A ((uint32_t)0U << 15U)
+#define MOD_SEL0_FSO_B ((uint32_t)1U << 15U)
+#define MOD_SEL0_HSCIF2_A ((uint32_t)0U << 13U)
+#define MOD_SEL0_HSCIF2_B ((uint32_t)1U << 13U)
+#define MOD_SEL0_HSCIF2_C ((uint32_t)2U << 13U)
+#define MOD_SEL0_ETHERAVB_A ((uint32_t)0U << 12U)
+#define MOD_SEL0_ETHERAVB_B ((uint32_t)1U << 12U)
+#define MOD_SEL0_DRIF3_A ((uint32_t)0U << 11U)
+#define MOD_SEL0_DRIF3_B ((uint32_t)1U << 11U)
+#define MOD_SEL0_DRIF2_A ((uint32_t)0U << 10U)
+#define MOD_SEL0_DRIF2_B ((uint32_t)1U << 10U)
+#define MOD_SEL0_DRIF1_A ((uint32_t)0U << 8U)
+#define MOD_SEL0_DRIF1_B ((uint32_t)1U << 8U)
+#define MOD_SEL0_DRIF1_C ((uint32_t)2U << 8U)
+#define MOD_SEL0_DRIF0_A ((uint32_t)0U << 6U)
+#define MOD_SEL0_DRIF0_B ((uint32_t)1U << 6U)
+#define MOD_SEL0_DRIF0_C ((uint32_t)2U << 6U)
+#define MOD_SEL0_CANFD0_A ((uint32_t)0U << 5U)
+#define MOD_SEL0_CANFD0_B ((uint32_t)1U << 5U)
+#define MOD_SEL0_ADG_A_A ((uint32_t)0U << 3U)
+#define MOD_SEL0_ADG_A_B ((uint32_t)1U << 3U)
+#define MOD_SEL0_ADG_A_C ((uint32_t)2U << 3U)
+#define MOD_SEL1_TSIF1_A ((uint32_t)0U << 30U)
+#define MOD_SEL1_TSIF1_B ((uint32_t)1U << 30U)
+#define MOD_SEL1_TSIF1_C ((uint32_t)2U << 30U)
+#define MOD_SEL1_TSIF1_D ((uint32_t)3U << 30U)
+#define MOD_SEL1_TSIF0_A ((uint32_t)0U << 27U)
+#define MOD_SEL1_TSIF0_B ((uint32_t)1U << 27U)
+#define MOD_SEL1_TSIF0_C ((uint32_t)2U << 27U)
+#define MOD_SEL1_TSIF0_D ((uint32_t)3U << 27U)
+#define MOD_SEL1_TSIF0_E ((uint32_t)4U << 27U)
+#define MOD_SEL1_TIMER_TMU_A ((uint32_t)0U << 26U)
+#define MOD_SEL1_TIMER_TMU_B ((uint32_t)1U << 26U)
+#define MOD_SEL1_SSP1_1_A ((uint32_t)0U << 24U)
+#define MOD_SEL1_SSP1_1_B ((uint32_t)1U << 24U)
+#define MOD_SEL1_SSP1_1_C ((uint32_t)2U << 24U)
+#define MOD_SEL1_SSP1_1_D ((uint32_t)3U << 24U)
+#define MOD_SEL1_SSP1_0_A ((uint32_t)0U << 21U)
+#define MOD_SEL1_SSP1_0_B ((uint32_t)1U << 21U)
+#define MOD_SEL1_SSP1_0_C ((uint32_t)2U << 21U)
+#define MOD_SEL1_SSP1_0_D ((uint32_t)3U << 21U)
+#define MOD_SEL1_SSP1_0_E ((uint32_t)4U << 21U)
+#define MOD_SEL1_SSI_A ((uint32_t)0U << 20U)
+#define MOD_SEL1_SSI_B ((uint32_t)1U << 20U)
+#define MOD_SEL1_SPEED_PULSE_IF_A ((uint32_t)0U << 19U)
+#define MOD_SEL1_SPEED_PULSE_IF_B ((uint32_t)1U << 19U)
+#define MOD_SEL1_SIMCARD_A ((uint32_t)0U << 17U)
+#define MOD_SEL1_SIMCARD_B ((uint32_t)1U << 17U)
+#define MOD_SEL1_SIMCARD_C ((uint32_t)2U << 17U)
+#define MOD_SEL1_SIMCARD_D ((uint32_t)3U << 17U)
+#define MOD_SEL1_SDHI2_A ((uint32_t)0U << 16U)
+#define MOD_SEL1_SDHI2_B ((uint32_t)1U << 16U)
+#define MOD_SEL1_SCIF4_A ((uint32_t)0U << 14U)
+#define MOD_SEL1_SCIF4_B ((uint32_t)1U << 14U)
+#define MOD_SEL1_SCIF4_C ((uint32_t)2U << 14U)
+#define MOD_SEL1_SCIF3_A ((uint32_t)0U << 13U)
+#define MOD_SEL1_SCIF3_B ((uint32_t)1U << 13U)
+#define MOD_SEL1_SCIF2_A ((uint32_t)0U << 12U)
+#define MOD_SEL1_SCIF2_B ((uint32_t)1U << 12U)
+#define MOD_SEL1_SCIF1_A ((uint32_t)0U << 11U)
+#define MOD_SEL1_SCIF1_B ((uint32_t)1U << 11U)
+#define MOD_SEL1_SCIF_A ((uint32_t)0U << 10U)
+#define MOD_SEL1_SCIF_B ((uint32_t)1U << 10U)
+#define MOD_SEL1_REMOCON_A ((uint32_t)0U << 9U)
+#define MOD_SEL1_REMOCON_B ((uint32_t)1U << 9U)
+#define MOD_SEL1_RCAN0_A ((uint32_t)0U << 6U)
+#define MOD_SEL1_RCAN0_B ((uint32_t)1U << 6U)
+#define MOD_SEL1_PWM6_A ((uint32_t)0U << 5U)
+#define MOD_SEL1_PWM6_B ((uint32_t)1U << 5U)
+#define MOD_SEL1_PWM5_A ((uint32_t)0U << 4U)
+#define MOD_SEL1_PWM5_B ((uint32_t)1U << 4U)
+#define MOD_SEL1_PWM4_A ((uint32_t)0U << 3U)
+#define MOD_SEL1_PWM4_B ((uint32_t)1U << 3U)
+#define MOD_SEL1_PWM3_A ((uint32_t)0U << 2U)
+#define MOD_SEL1_PWM3_B ((uint32_t)1U << 2U)
+#define MOD_SEL1_PWM2_A ((uint32_t)0U << 1U)
+#define MOD_SEL1_PWM2_B ((uint32_t)1U << 1U)
+#define MOD_SEL1_PWM1_A ((uint32_t)0U << 0U)
+#define MOD_SEL1_PWM1_B ((uint32_t)1U << 0U)
+#define MOD_SEL2_I2C_5_A ((uint32_t)0U << 31U)
+#define MOD_SEL2_I2C_5_B ((uint32_t)1U << 31U)
+#define MOD_SEL2_I2C_3_A ((uint32_t)0U << 30U)
+#define MOD_SEL2_I2C_3_B ((uint32_t)1U << 30U)
+#define MOD_SEL2_I2C_0_A ((uint32_t)0U << 29U)
+#define MOD_SEL2_I2C_0_B ((uint32_t)1U << 29U)
+#define MOD_SEL2_FM_A ((uint32_t)0U << 27U)
+#define MOD_SEL2_FM_B ((uint32_t)1U << 27U)
+#define MOD_SEL2_FM_C ((uint32_t)2U << 27U)
+#define MOD_SEL2_FM_D ((uint32_t)3U << 27U)
+#define MOD_SEL2_SCIF5_A ((uint32_t)0U << 26U)
+#define MOD_SEL2_SCIF5_B ((uint32_t)1U << 26U)
+#define MOD_SEL2_I2C6_A ((uint32_t)0U << 23U)
+#define MOD_SEL2_I2C6_B ((uint32_t)1U << 23U)
+#define MOD_SEL2_I2C6_C ((uint32_t)2U << 23U)
+#define MOD_SEL2_NDF_A ((uint32_t)0U << 22U)
+#define MOD_SEL2_NDF_B ((uint32_t)1U << 22U)
+#define MOD_SEL2_SSI2_A ((uint32_t)0U << 21U)
+#define MOD_SEL2_SSI2_B ((uint32_t)1U << 21U)
+#define MOD_SEL2_SSI9_A ((uint32_t)0U << 20U)
+#define MOD_SEL2_SSI9_B ((uint32_t)1U << 20U)
+#define MOD_SEL2_TIMER_TMU2_A ((uint32_t)0U << 19U)
+#define MOD_SEL2_TIMER_TMU2_B ((uint32_t)1U << 19U)
+#define MOD_SEL2_ADG_B_A ((uint32_t)0U << 18U)
+#define MOD_SEL2_ADG_B_B ((uint32_t)1U << 18U)
+#define MOD_SEL2_ADG_C_A ((uint32_t)0U << 17U)
+#define MOD_SEL2_ADG_C_B ((uint32_t)1U << 17U)
+#define MOD_SEL2_VIN4_A ((uint32_t)0U << 0U)
+#define MOD_SEL2_VIN4_B ((uint32_t)1U << 0U)
/* SCIF3 Registers for Dummy write */
#define SCIF3_BASE (0xE6C50000U)
@@ -580,7 +580,7 @@
#define SCFCR_DATA (0x0000U)
/* Realtime module stop control */
-#define CPG_BASE (0xE6150000U)
+#define CPG_BASE (0xE6150000U)
#define CPG_SCMSTPCR0 (CPG_BASE + 0x0B20U)
#define CPG_MSTPSR0 (CPG_BASE + 0x0030U)
#define SCMSTPCR0_RTDMAC (0x00200000U)
@@ -626,7 +626,7 @@
mstpcr_write(CPG_SCMSTPCR0, CPG_MSTPSR0, SCMSTPCR0_RTDMAC);
/* Initialize ch0, Reset Descriptor */
- mmio_write_32(RTDMAC_RDMCHCLR, ((uint32_t) 1U << RTDMAC_CH));
+ mmio_write_32(RTDMAC_RDMCHCLR, ((uint32_t)1U << RTDMAC_CH));
mmio_write_32(RTDMAC_RDMCHCRB(RTDMAC_CH), RDMCHCRB_DRST);
/* Enable DMA */
@@ -665,7 +665,7 @@
if (prr == (RCAR_PRODUCT_M3_CUT10)) {
mmio_write_16(SCIF3_SCFCR, SCFCR_DATA); /* Dummy write */
}
- mmio_write_32((uintptr_t) addr, data);
+ mmio_write_32((uintptr_t)addr, data);
if (prr == (RCAR_PRODUCT_M3_CUT10)) {
mmio_write_16(SCIF3_SCFCR, SCFCR_DATA); /* Dummy write */
}