Merge changes Ic92c2abf,Id9182f65 into integration
* changes:
docs(juno): update PSCI instrumentation data
docs(n1sdp): update PSCI instrumentation data
diff --git a/bl31/bl31_traps.c b/bl31/bl31_traps.c
index 47a555a..984fdaa 100644
--- a/bl31/bl31_traps.c
+++ b/bl31/bl31_traps.c
@@ -96,6 +96,14 @@
*
* NOTE: This piece of code must be reviewed every release to ensure that
* we keep up with new ARCH features which introduces a new SPSR bit.
+ *
+ * TF-A 2.12 release review
+ * The latest version available is 2024-09, which has two extra features which
+ * impacts generation of SPSR, since these features are not implemented in TF-A
+ * at the time of release, just log the feature names here to be taken up when
+ * feature support is introduced.
+ * - FEAT_PAuth_LR (2023 extension)
+ * - FEAT_UINJ (2024 extension)
*/
u_register_t create_spsr(u_register_t old_spsr, unsigned int target_el)
{
diff --git a/changelog.yaml b/changelog.yaml
index 3591f02..f2403d0 100644
--- a/changelog.yaml
+++ b/changelog.yaml
@@ -161,6 +161,18 @@
- title: DynamIQ Shared Unit (DSU)
scope: dsu
+ - title: Extension to SCTLR_ELx (FEAT_SCTLR2)
+ scope: sctlr2
+
+ deprecated:
+ - feat_sctlr2
+
+ - title: 128-bit Translation Tables (FEAT_D128)
+ scope: d128
+
+ - title: Translation Hardening Extension (FEAT_THE)
+ scope: the
+
- title: Platforms
scope: platforms
@@ -252,6 +264,7 @@
deprecated:
- board/rdn2
+ - rdfremont
deprecated:
- neoverse
@@ -272,6 +285,9 @@
- title: Corstone-1000
scope: corstone-1000
+ deprecated:
+ - corstone1000
+
- title: Automotive RD
scope: automotive_rd
@@ -302,6 +318,9 @@
- title: HiKey960
scope: hikey960
+ - title: Poplar
+ scope: poplar
+
- title: Intel
scope: intel
@@ -616,6 +635,9 @@
- title: RK3328
scope: rk3328
+ - title: RK3588
+ scope: rk3588
+
- title: Socionext
scope: socionext
@@ -649,6 +671,10 @@
- title: STM32MP2
scope: stm32mp2
+ subsections:
+ - title: STM32MP25
+ scope: stm32mp25
+
- title: Texas Instruments
scope: ti
@@ -730,6 +756,9 @@
- title: Services
scope: services
+ deprecated:
+ - std_svc
+
subsections:
- title: FF-A
scope: ff-a
@@ -787,6 +816,28 @@
- title: ChromeOS
scope: cros
+ - title: Secure Payload Dispatcher
+ scope: spd
+
+ subsections:
+ - title: OP-TEE
+ scope: optee
+
+ deprecated:
+ - lib/optee
+
+ - title: ProvenCore
+ scope: pncd
+
+ - title: Trusted Little Kernel
+ scope: tlkd
+
+ - title: Trusty
+ scope: trusty
+
+ - title: TSP
+ scope: tspd
+
- title: Libraries
scope: lib
@@ -821,12 +872,6 @@
- title: MPMM
scope: mpmm
- - title: OP-TEE
- scope: optee
-
- deprecated:
- - lib/optee
-
- title: PSCI
scope: psci
@@ -1335,6 +1380,10 @@
- title: STM32MP2
scope: stm32mp2-fdts
+ subsections:
+ - title: STM32MP25
+ scope: stm32mp25-fdts
+
- title: PIE
scope: pie
diff --git a/docs/components/context-management-library.rst b/docs/components/context-management-library.rst
index 266b82a..6a76ada 100644
--- a/docs/components/context-management-library.rst
+++ b/docs/components/context-management-library.rst
@@ -244,25 +244,22 @@
typedef struct cpu_context {
gp_regs_t gpregs_ctx;
el3_state_t el3state_ctx;
- el1_sysregs_t el1_sysregs_ctx;
- #if CTX_INCLUDE_EL2_REGS
- el2_sysregs_t el2_sysregs_ctx;
- #endif
+ cve_2018_3639_t cve_2018_3639_ctx;
- #if CTX_INCLUDE_FPREGS
- fp_regs_t fpregs_ctx;
+ #if ERRATA_SPECULATIVE_AT
+ errata_speculative_at_t errata_speculative_at_ctx;
#endif
- cve_2018_3639_t cve_2018_3639_ctx;
#if CTX_INCLUDE_PAUTH_REGS
pauth_t pauth_ctx;
#endif
- #if CTX_INCLUDE_MPAM_REGS
- mpam_t mpam_ctx;
+ #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31)
+ el2_sysregs_t el2_sysregs_ctx;
+ #else
+ el1_sysregs_t el1_sysregs_ctx;
#endif
-
} cpu_context_t;
Context Memory Allocation
@@ -509,6 +506,55 @@
identical values across all cores for the individual Non-secure, Secure, and
Realm worlds.
+Root-Context (EL3-Execution-Context)
+====================================
+
+EL3/Root Context is the execution environment while the CPU is running at EL3.
+
+Previously, while the CPU is in execution at EL3, the system registers persist
+with the values of the incoming world. This implies that if the CPU is entering
+EL3 from NS world, the EL1 and EL2 system registers which might be modified in
+lower exception levels NS(EL2/EL1) will carry forward those values to EL3.
+Further the EL3 registers also hold on to the values configured for Non-secure
+world, written during the previous ERET from EL3 to NS(EL2/EL1).
+Same policy is followed with respect to other worlds (Secure/Realm) depending on
+the system configuration.
+
+The firmware at EL3 has traditionally operated within the context of the incoming
+world (Secure/Non-Secure/Realm). This becomes problematic in scenarios where the
+EL3/Root world must explicitly use architectural features that depend on system
+registers configured for lower exception levels.
+A good example of this is the PAuth regs. The Root world would need to program
+its own PAuth Keys while executing in EL3 and this needs to be restored in entry
+to EL3 from any world.
+Therefore, Root world should maintain its own distinct settings to access
+features for its own execution at EL3.
+
+Register values which are currently known to be of importance during EL3 execution,
+is referred to as the EL3/Root context.
+This includes ( MDCR_EL3.SDD, SCR_EL3.{EA, SIF}, PMCR_EL0.DP, PSTATE.DIT)
+EL3 Context ensures, CPU executes under fixed EL3 system register settings
+which is not affected by settings of other worlds.
+
+Root Context needs to be setup as early as possible before we try and access/modify
+architectural features at EL3. Its a simple restore operation ``setup_el3_execution_context``
+that overwrites the selected bits listed above. EL3 never changes its mind about
+what those values should be, sets it as required for EL3. Henceforth, a Root
+context save operation is not required.
+
+The figure below illustrates the same with NS-world as a reference while entering
+EL3.
+
+|Root Context Sequence|
+
+.. code:: c
+
+ # EL3/Root_Context routine
+ .macro setup_el3_execution_context
+
+EL3 execution context needs to setup at both boot time (cold and warm boot)
+entrypaths and at all the possible exception handlers routing to EL3 at runtime.
+
*Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.*
.. |Context Memory Allocation| image:: ../resources/diagrams/context_memory_allocation.png
@@ -516,6 +562,7 @@
.. |CPU Data Structure| image:: ../resources/diagrams/percpu-data-struct.png
.. |Context Init ColdBoot| image:: ../resources/diagrams/context_init_coldboot.png
.. |Context Init WarmBoot| image:: ../resources/diagrams/context_init_warmboot.png
+.. |Root Context Sequence| image:: ../resources/diagrams/root_context_sequence.png
.. _Trustzone for AArch64: https://developer.arm.com/documentation/102418/0101/TrustZone-in-the-processor/Switching-between-Security-states
.. _Security States with RME: https://developer.arm.com/documentation/den0126/0100/Security-states
.. _lib/el3_runtime/(aarch32/aarch64): https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/lib/el3_runtime
diff --git a/docs/getting_started/prerequisites.rst b/docs/getting_started/prerequisites.rst
index de2da2f..dea1825 100644
--- a/docs/getting_started/prerequisites.rst
+++ b/docs/getting_started/prerequisites.rst
@@ -34,7 +34,7 @@
mbed TLS\ [#f1]_ 3.6.1
Node.js [#f2]_ 16
OpenSSL 1.0.0
-Poetry [#f2]_ 1.3.2
+Poetry 1.3.2
QCBOR\ [#f3]_ 1.2
Sphinx\ [#f2]_ 2.4.4
======================== =====================
@@ -103,9 +103,11 @@
^^^^^^
Required for managing Python dependencies, this will allow you to reliably
-reproduce a Python environment to build documentation and run analysis tools.
-Most importantly, it ensures your system environment will not be affected by
-dependencies in the Python scripts.
+reproduce a Python environment to build documentation and run some of the
+integrated Python tools. Most importantly, it ensures your system environment
+will not be affected by dependencies in the Python scripts.
+
+For installation instructions, see the `official Poetry documentation`_.
.. _prerequisites_software_and_libraries:
@@ -191,3 +193,4 @@
.. _Arm-DS: https://developer.arm.com/Tools%20and%20Software/Arm%20Development%20Studio
.. _Linaro Release 20.01: http://releases.linaro.org/members/arm/platforms/20.01
.. _TrustedFirmware.org: https://www.trustedfirmware.org/
+.. _official Poetry documentation: https://python-poetry.org/docs/#installation
diff --git a/docs/plat/arm/juno/index.rst b/docs/plat/arm/juno/index.rst
index 5320a3b..1e37696 100644
--- a/docs/plat/arm/juno/index.rst
+++ b/docs/plat/arm/juno/index.rst
@@ -56,7 +56,7 @@
#. Obtain SCP binaries (Juno)
- This version of TF-A is tested with SCP version 2.12.0 on Juno. You can
+ This version of TF-A is tested with SCP version 2.15.0 on Juno. You can
download pre-built SCP binaries (``scp_bl1.bin`` and ``scp_bl2.bin``)
from `TF-A downloads page`_. Alternatively, you can `build
the binaries from source`_.
@@ -241,11 +241,11 @@
--------------
-*Copyright (c) 2019-2023, Arm Limited. All rights reserved.*
+*Copyright (c) 2019-2024, Arm Limited. All rights reserved.*
.. _Linaro release software stack: http://releases.linaro.org/members/arm/platforms/
.. _Juno platform software user guide: https://git.linaro.org/landing-teams/working/arm/arm-reference-platforms.git/about/docs/juno/user-guide.rst
-.. _TF-A downloads page: https://downloads.trustedfirmware.org/tf-a/css_scp_2.12.0/juno/
+.. _TF-A downloads page: https://downloads.trustedfirmware.org/tf-a/css_scp_2.15.0/juno/
.. _build the binaries from source: https://github.com/ARM-software/SCP-firmware/blob/master/user_guide.md#scp-firmware-user-guide
.. _Arm Platforms Portal: https://community.arm.com/dev-platforms/
.. _Juno Getting Started Guide: https://developer.arm.com/documentation/den0928/f/?lang=en
diff --git a/docs/resources/diagrams/root_context_sequence.png b/docs/resources/diagrams/root_context_sequence.png
new file mode 100644
index 0000000..67783f1
--- /dev/null
+++ b/docs/resources/diagrams/root_context_sequence.png
Binary files differ
diff --git a/fdts/tc3-4-base.dtsi b/fdts/tc3-4-base.dtsi
index 169d68f..2de5fd3 100644
--- a/fdts/tc3-4-base.dtsi
+++ b/fdts/tc3-4-base.dtsi
@@ -15,7 +15,7 @@
#define MHU_OFFSET 0x10000
#define MHU_MBOX_CELLS 3
#define MHU_RX_INT_NUM 300
-#define MHU_RX_INT_NAME "combined-mbx"
+#define MHU_RX_INT_NAME "combined"
#define MPAM_ADDR 0x0 0x5f010000 /* 0x5f01_0000 */
#define UARTCLK_FREQ 3750000
diff --git a/include/services/rmm_core_manifest.h b/include/services/rmm_core_manifest.h
index 578bc14..6b57267 100644
--- a/include/services/rmm_core_manifest.h
+++ b/include/services/rmm_core_manifest.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022-2023, Arm Limited. All rights reserved.
+ * Copyright (c) 2022-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -67,7 +67,7 @@
uintptr_t base; /* Console base address */
uint64_t map_pages; /* Num of pages to be mapped in RMM for the console MMIO */
char name[RMM_CONSOLE_MAX_NAME_LEN]; /* Name of console */
- uint64_t clk_in_hz; /* UART clock (in HZ) for the console */
+ uint64_t clk_in_hz; /* UART clock (in Hz) for the console */
uint64_t baud_rate; /* Baud rate */
uint64_t flags; /* Additional flags RES0 */
};
@@ -87,8 +87,8 @@
struct console_list {
uint64_t num_consoles; /* Number of consoles */
- struct console_info *consoles; /* Pointer to ns_dram_bank[] */
- uint64_t checksum; /* Checksum of ns_dram_info data */
+ struct console_info *consoles; /* Pointer to console_info[] */
+ uint64_t checksum; /* Checksum of console_list data */
};
CASSERT(offsetof(struct console_list, num_consoles) == 0UL,
diff --git a/plat/arm/board/fvp/fvp_common.c b/plat/arm/board/fvp/fvp_common.c
index 0c5a76c..bdc2cac 100644
--- a/plat/arm/board/fvp/fvp_common.c
+++ b/plat/arm/board/fvp/fvp_common.c
@@ -575,6 +575,23 @@
return (size_t)RMM_SHARED_SIZE;
}
+/*
+ * Calculate checksum of 64-bit words @buffer with @size length
+ */
+static uint64_t checksum_calc(uint64_t *buffer, size_t size)
+{
+ uint64_t sum = 0UL;
+
+ assert(((uintptr_t)buffer & (sizeof(uint64_t) - 1UL)) == 0UL);
+ assert((size & (sizeof(uint64_t) - 1UL)) == 0UL);
+
+ for (unsigned long i = 0UL; i < (size / sizeof(uint64_t)); i++) {
+ sum += buffer[i];
+ }
+
+ return sum;
+}
+
int plat_rmmd_load_manifest(struct rmm_manifest *manifest)
{
uint64_t checksum, num_banks, num_consoles;
@@ -661,16 +678,13 @@
/* Store FVP DRAM banks data in Boot Manifest */
for (unsigned long i = 0UL; i < num_banks; i++) {
- uintptr_t base = FCONF_GET_PROPERTY(hw_config, dram_layout, dram_bank[i].base);
- uint64_t size = FCONF_GET_PROPERTY(hw_config, dram_layout, dram_bank[i].size);
-
- bank_ptr[i].base = base;
- bank_ptr[i].size = size;
-
- /* Update checksum */
- checksum += base + size;
+ bank_ptr[i].base = FCONF_GET_PROPERTY(hw_config, dram_layout, dram_bank[i].base);
+ bank_ptr[i].size = FCONF_GET_PROPERTY(hw_config, dram_layout, dram_bank[i].size);
}
+ /* Update checksum */
+ checksum += checksum_calc((uint64_t *)bank_ptr, sizeof(struct ns_dram_bank) * num_banks);
+
/* Checksum must be 0 */
manifest->plat_dram.checksum = ~checksum + 1UL;
@@ -678,18 +692,18 @@
checksum = num_consoles + (uint64_t)console_ptr;
/* Zero out the console info struct */
- memset((void *)console_ptr, '\0', sizeof(struct console_info) * num_consoles);
+ (void)memset((void *)console_ptr, '\0', sizeof(struct console_info) * num_consoles);
- console_ptr[0].map_pages = 1;
console_ptr[0].base = FVP_RMM_CONSOLE_BASE;
+ console_ptr[0].map_pages = 1UL;
console_ptr[0].clk_in_hz = FVP_RMM_CONSOLE_CLK_IN_HZ;
console_ptr[0].baud_rate = FVP_RMM_CONSOLE_BAUD;
- strlcpy(console_ptr[0].name, FVP_RMM_CONSOLE_NAME, RMM_CONSOLE_MAX_NAME_LEN-1UL);
+ (void)strlcpy(console_ptr[0].name, FVP_RMM_CONSOLE_NAME, RMM_CONSOLE_MAX_NAME_LEN - 1UL);
/* Update checksum */
- checksum += console_ptr[0].base + console_ptr[0].map_pages +
- console_ptr[0].clk_in_hz + console_ptr[0].baud_rate;
+ checksum += checksum_calc((uint64_t *)console_ptr,
+ sizeof(struct console_info) * num_consoles);
/* Checksum must be 0 */
manifest->plat_console.checksum = ~checksum + 1UL;
diff --git a/plat/st/stm32mp2/bl31_plat_setup.c b/plat/st/stm32mp2/bl31_plat_setup.c
index 586bfe8..a7a3721 100644
--- a/plat/st/stm32mp2/bl31_plat_setup.c
+++ b/plat/st/stm32mp2/bl31_plat_setup.c
@@ -62,6 +62,8 @@
panic();
}
+ generic_delay_timer_init();
+
(void)stm32mp_uart_console_setup();
/*
@@ -122,8 +124,6 @@
void bl31_plat_arch_setup(void)
{
- generic_delay_timer_init();
-
stm32mp_gic_init();
}
diff --git a/plat/st/stm32mp2/platform.mk b/plat/st/stm32mp2/platform.mk
index 2a9b6fd..f461656 100644
--- a/plat/st/stm32mp2/platform.mk
+++ b/plat/st/stm32mp2/platform.mk
@@ -74,10 +74,13 @@
STM32MP_DDR_FW := ${STM32MP_DDR_FW_PATH}/${STM32MP_DDR_FW_NAME}
endif
FDT_SOURCES += $(addprefix fdts/, $(patsubst %.dtb,%.dts,$(STM32MP_FW_CONFIG_NAME)))
+
# Add the FW_CONFIG to FIP and specify the same to certtool
$(eval $(call TOOL_ADD_PAYLOAD,${STM32MP_FW_CONFIG},--fw-config))
+
# Add the SOC_FW_CONFIG to FIP and specify the same to certtool
-$(eval $(call TOOL_ADD_IMG,STM32MP_SOC_FW_CONFIG,--soc-fw-config))
+$(eval $(call TOOL_ADD_IMG_PAYLOAD,STM32MP_SOC_FW_CONFIG,$(STM32MP_SOC_FW_CONFIG),--soc-fw-config,$(patsubst %.dtb,%.dts,$(STM32MP_SOC_FW_CONFIG))))
+
ifeq (${STM32MP_DDR_FIP_IO_STORAGE},1)
# Add the FW_DDR to FIP and specify the same to certtool
$(eval $(call TOOL_ADD_IMG,STM32MP_DDR_FW,--ddr-fw))
@@ -219,6 +222,4 @@
@echo '#include "$(patsubst fdts/%,%,$<)"' > $@
@echo '#include "${BL31_DTSI}"' >> $@
-${BUILD_PLAT}/fdts/%-bl31.dtb: ${BUILD_PLAT}/fdts/%-bl31.dts
-
include plat/st/common/common_rules.mk
