commit 36a9f3067df5be26c04677ec26c0a92235820fd9
author Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Tue Dec 24 10:42:52 2019 +0800
committer Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Thu Jan 16 10:56:42 2020 +0800
tree ade953ad592051ee1684791dead6e5cb1d03893d
parent 0c6dae21b3d2a16dabe70703bf3ce0f0f3970710

intel: Add bridge control for FPGA reconfig

This is to make sure that bridge access in disabled before doing full
FPGA reconfiguration and turn re-enable it once the configuration
succeed.

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I1f42fbf04ac1625048bbdf21b8a0443464ed833d

plat/intel/soc/agilex/platform.mk

diff --git a/plat/intel/soc/agilex/platform.mk b/plat/intel/soc/agilex/platform.mk
index d04d630..f47c3f1 100644
--- a/plat/intel/soc/agilex/platform.mk
+++ b/plat/intel/soc/agilex/platform.mk
@@ -60,6 +60,7 @@
 		plat/intel/soc/common/socfpga_sip_svc.c			\
 		plat/intel/soc/common/socfpga_topology.c		\
 		plat/intel/soc/common/soc/socfpga_mailbox.c		\
+		plat/intel/soc/common/soc/socfpga_reset_manager.c
 
 PROGRAMMABLE_RESET_ADDRESS	:= 0
 BL2_AT_EL3			:= 1

plat/intel/soc/common/socfpga_sip_svc.c

diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c
index f9ba235..41dae9e 100644
--- a/plat/intel/soc/common/socfpga_sip_svc.c
+++ b/plat/intel/soc/common/socfpga_sip_svc.c
@@ -11,6 +11,7 @@
 #include <tools_share/uuid.h>
 
 #include "socfpga_mailbox.h"
+#include "socfpga_reset_manager.h"
 #include "socfpga_sip_svc.h"
 
 /* Number of SiP Calls implemented */
@@ -27,6 +28,7 @@
 static int max_blocks;
 static uint32_t bytes_per_block;
 static uint32_t blocks_submitted;
+static int is_partial_reconfig;
 
 struct fpga_config_info {
 	uint32_t addr;
@@ -109,6 +111,12 @@
 			return INTEL_SIP_SMC_STATUS_ERROR;
 	}
 
+	if (query_type != 1) {
+		/* full reconfiguration */
+		if (!is_partial_reconfig)
+			socfpga_bridges_enable();	/* Enable bridge */
+	}
+
 	return INTEL_SIP_SMC_STATUS_OK;
 }
 
@@ -196,6 +204,8 @@
 	uint32_t response[3];
 	int status = 0;
 
+	is_partial_reconfig = config_type;
+
 	mailbox_clear_response();
 
 	mailbox_send_cmd(1, MBOX_CMD_CANCEL, 0, 0, 0, NULL, 0);
@@ -225,6 +235,12 @@
 	send_id = 0;
 	rcv_id = 0;
 
+	/* full reconfiguration */
+	if (!is_partial_reconfig) {
+		/* Disable bridge */
+		socfpga_bridges_disable();
+	}
+
 	return 0;
 }
 

plat/intel/soc/stratix10/platform.mk

diff --git a/plat/intel/soc/stratix10/platform.mk b/plat/intel/soc/stratix10/platform.mk
index a89c3d4..efbab24 100644
--- a/plat/intel/soc/stratix10/platform.mk
+++ b/plat/intel/soc/stratix10/platform.mk
@@ -59,6 +59,7 @@
 		plat/intel/soc/common/socfpga_sip_svc.c			\
 		plat/intel/soc/common/socfpga_topology.c		\
 		plat/intel/soc/common/soc/socfpga_mailbox.c		\
+		plat/intel/soc/common/soc/socfpga_reset_manager.c
 
 PROGRAMMABLE_RESET_ADDRESS	:= 0
 BL2_AT_EL3			:= 1