feat(nxp-clk): set MC_CGM divider's rate
The MC_CGM divider's frequency is saved as part of the object metadata.
No checks are performed on the requested frequency. It will be validated
during the enablement process.
Change-Id: Ide9c8c64be16a66b66f129735cebfc4d1f1772c5
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
diff --git a/drivers/nxp/clk/s32cc/s32cc_clk_drv.c b/drivers/nxp/clk/s32cc/s32cc_clk_drv.c
index 81fe961..5882123 100644
--- a/drivers/nxp/clk/s32cc/s32cc_clk_drv.c
+++ b/drivers/nxp/clk/s32cc/s32cc_clk_drv.c
@@ -1208,6 +1208,29 @@
return 0;
}
+static int set_cgm_div_freq(const struct s32cc_clk_obj *module,
+ unsigned long rate, unsigned long *orate,
+ unsigned int *depth)
+{
+ struct s32cc_cgm_div *cgm_div = s32cc_obj2cgmdiv(module);
+ int ret;
+
+ ret = update_stack_depth(depth);
+ if (ret != 0) {
+ return ret;
+ }
+
+ if (cgm_div->parent == NULL) {
+ ERROR("Failed to identify the CGM divider's parent\n");
+ return -EINVAL;
+ }
+
+ cgm_div->freq = rate;
+ *orate = rate;
+
+ return 0;
+}
+
static int no_enable(struct s32cc_clk_obj *module,
const struct s32cc_clk_drv *drv,
unsigned int depth)
@@ -1891,6 +1914,9 @@
case s32cc_shared_clkmux_t:
ret = set_mux_freq(module, rate, orate, depth);
break;
+ case s32cc_cgm_div_t:
+ ret = set_cgm_div_freq(module, rate, orate, depth);
+ break;
case s32cc_dfs_t:
ERROR("Setting the frequency of a DFS is not allowed!");
break;