Rename Cortex-Hercules to Cortex-A78
Change-Id: I89b90cbdfc8f2aa898b4f3676a4764f060f8e138
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index 258f73d..591f2f8 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -227,11 +227,10 @@
- ``ERRATA_A76_1275112``: This applies errata 1275112 workaround to Cortex-A76
CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
-For Hercules, the following errata build flags are defined :
+For Cortex-A78, the following errata build flags are defined :
-- ``ERRATA_HERCULES_1688305``: This applies errata 1688305 workaround to
- Hercules CPU. This needs to be enabled only for revision r0p0 - r1p0 of
- the CPU.
+- ``ERRATA_A78_1688305``: This applies errata 1688305 workaround to Cortex-A78
+ CPU. This needs to be enabled only for revision r0p0 - r1p0 of the CPU.
For Neoverse N1, the following errata build flags are defined :
@@ -338,7 +337,7 @@
--------------
-*Copyright (c) 2014-2019, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2014-2020, Arm Limited and Contributors. All rights reserved.*
.. _CVE-2017-5715: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2017-5715
.. _CVE-2018-3639: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2018-3639
diff --git a/include/lib/cpus/aarch64/cortex_a78.h b/include/lib/cpus/aarch64/cortex_a78.h
index 563d668..0d4712b 100644
--- a/include/lib/cpus/aarch64/cortex_a78.h
+++ b/include/lib/cpus/aarch64/cortex_a78.h
@@ -4,31 +4,31 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef CORTEX_HERCULES_H
-#define CORTEX_HERCULES_H
+#ifndef CORTEX_A78_H
+#define CORTEX_A78_H
#include <lib/utils_def.h>
-#define CORTEX_HERCULES_MIDR U(0x410FD410)
+#define CORTEX_A78_MIDR U(0x410FD410)
/*******************************************************************************
* CPU Extended Control register specific definitions.
******************************************************************************/
-#define CORTEX_HERCULES_CPUECTLR_EL1 S3_0_C15_C1_4
+#define CORTEX_A78_CPUECTLR_EL1 S3_0_C15_C1_4
/*******************************************************************************
* CPU Power Control register specific definitions
******************************************************************************/
-#define CORTEX_HERCULES_CPUPWRCTLR_EL1 S3_0_C15_C2_7
-#define CORTEX_HERCULES_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1)
+#define CORTEX_A78_CPUPWRCTLR_EL1 S3_0_C15_C2_7
+#define CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1)
/*******************************************************************************
* CPU Auxiliary Control register specific definitions.
******************************************************************************/
-#define CORTEX_HERCULES_ACTLR_TAM_BIT (ULL(1) << 30)
+#define CORTEX_A78_ACTLR_TAM_BIT (ULL(1) << 30)
-#define CORTEX_HERCULES_ACTLR2_EL1 S3_0_C15_C1_1
-#define CORTEX_HERCULES_ACTLR2_EL1_BIT_1 (ULL(1) << 1)
+#define CORTEX_A78_ACTLR2_EL1 S3_0_C15_C1_1
+#define CORTEX_A78_ACTLR2_EL1_BIT_1 (ULL(1) << 1)
/*******************************************************************************
* CPU Activity Monitor Unit register specific definitions.
@@ -38,7 +38,7 @@
#define CPUAMCNTENCLR1_EL0 S3_3_C15_C3_0
#define CPUAMCNTENSET1_EL0 S3_3_C15_C3_1
-#define CORTEX_HERCULES_AMU_GROUP0_MASK U(0xF)
-#define CORTEX_HERCULES_AMU_GROUP1_MASK U(0x7)
+#define CORTEX_A78_AMU_GROUP0_MASK U(0xF)
+#define CORTEX_A78_AMU_GROUP1_MASK U(0x7)
-#endif /* CORTEX_HERCULES_H */
+#endif /* CORTEX_A78_H */
diff --git a/lib/cpus/aarch64/cortex_a78.S b/lib/cpus/aarch64/cortex_a78.S
index 2293109..9914f12 100644
--- a/lib/cpus/aarch64/cortex_a78.S
+++ b/lib/cpus/aarch64/cortex_a78.S
@@ -13,30 +13,30 @@
/* Hardware handled coherency */
#if HW_ASSISTED_COHERENCY == 0
-#error "cortex_hercules must be compiled with HW_ASSISTED_COHERENCY enabled"
+#error "cortex_a78 must be compiled with HW_ASSISTED_COHERENCY enabled"
#endif
/* --------------------------------------------------
- * Errata Workaround for Hercules Erratum 1688305.
- * This applies to revision r0p0 and r1p0 of Hercules.
+ * Errata Workaround for A78 Erratum 1688305.
+ * This applies to revision r0p0 and r1p0 of A78.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* --------------------------------------------------
*/
-func errata_hercules_1688305_wa
+func errata_a78_1688305_wa
/* Compare x0 against revision r1p0 */
mov x17, x30
bl check_errata_1688305
cbz x0, 1f
- mrs x1, CORTEX_HERCULES_ACTLR2_EL1
- orr x1, x1, CORTEX_HERCULES_ACTLR2_EL1_BIT_1
- msr CORTEX_HERCULES_ACTLR2_EL1, x1
+ mrs x1, CORTEX_A78_ACTLR2_EL1
+ orr x1, x1, CORTEX_A78_ACTLR2_EL1_BIT_1
+ msr CORTEX_A78_ACTLR2_EL1, x1
isb
1:
ret x17
-endfunc errata_hercules_1688305_wa
+endfunc errata_a78_1688305_wa
func check_errata_1688305
/* Applies to r0p0 and r1p0 */
@@ -45,64 +45,64 @@
endfunc check_errata_1688305
/* -------------------------------------------------
- * The CPU Ops reset function for Cortex-Hercules
+ * The CPU Ops reset function for Cortex-A78
* -------------------------------------------------
*/
-func cortex_hercules_reset_func
+func cortex_a78_reset_func
mov x19, x30
bl cpu_get_rev_var
mov x18, x0
-#if ERRATA_HERCULES_1688305
+#if ERRATA_A78_1688305
mov x0, x18
- bl errata_hercules_1688305_wa
+ bl errata_a78_1688305_wa
#endif
#if ENABLE_AMU
/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
mrs x0, actlr_el3
- bic x0, x0, #CORTEX_HERCULES_ACTLR_TAM_BIT
+ bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT
msr actlr_el3, x0
/* Make sure accesses from non-secure EL0/EL1 are not trapped to EL2 */
mrs x0, actlr_el2
- bic x0, x0, #CORTEX_HERCULES_ACTLR_TAM_BIT
+ bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT
msr actlr_el2, x0
/* Enable group0 counters */
- mov x0, #CORTEX_HERCULES_AMU_GROUP0_MASK
+ mov x0, #CORTEX_A78_AMU_GROUP0_MASK
msr CPUAMCNTENSET0_EL0, x0
/* Enable group1 counters */
- mov x0, #CORTEX_HERCULES_AMU_GROUP1_MASK
+ mov x0, #CORTEX_A78_AMU_GROUP1_MASK
msr CPUAMCNTENSET1_EL0, x0
#endif
isb
ret x19
-endfunc cortex_hercules_reset_func
+endfunc cortex_a78_reset_func
/* ---------------------------------------------
* HW will do the cache maintenance while powering down
* ---------------------------------------------
*/
-func cortex_hercules_core_pwr_dwn
+func cortex_a78_core_pwr_dwn
/* ---------------------------------------------
* Enable CPU power down bit in power control register
* ---------------------------------------------
*/
- mrs x0, CORTEX_HERCULES_CPUPWRCTLR_EL1
- orr x0, x0, #CORTEX_HERCULES_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
- msr CORTEX_HERCULES_CPUPWRCTLR_EL1, x0
+ mrs x0, CORTEX_A78_CPUPWRCTLR_EL1
+ orr x0, x0, #CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
+ msr CORTEX_A78_CPUPWRCTLR_EL1, x0
isb
ret
-endfunc cortex_hercules_core_pwr_dwn
+endfunc cortex_a78_core_pwr_dwn
/*
- * Errata printing function for cortex_hercules. Must follow AAPCS.
+ * Errata printing function for cortex_a78. Must follow AAPCS.
*/
#if REPORT_ERRATA
-func cortex_hercules_errata_report
+func cortex_a78_errata_report
stp x8, x30, [sp, #-16]!
bl cpu_get_rev_var
@@ -112,15 +112,15 @@
* Report all errata. The revision-variant information is passed to
* checking functions of each errata.
*/
- report_errata ERRATA_HERCULES_1688305, cortex_hercules, 1688305
+ report_errata ERRATA_A78_1688305, cortex_a78, 1688305
ldp x8, x30, [sp], #16
ret
-endfunc cortex_hercules_errata_report
+endfunc cortex_a78_errata_report
#endif
/* ---------------------------------------------
- * This function provides cortex_hercules specific
+ * This function provides cortex_a78 specific
* register information for crash reporting.
* It needs to return with x6 pointing to
* a list of register names in ascii and
@@ -128,16 +128,16 @@
* reported.
* ---------------------------------------------
*/
-.section .rodata.cortex_hercules_regs, "aS"
-cortex_hercules_regs: /* The ascii list of register names to be reported */
+.section .rodata.cortex_a78_regs, "aS"
+cortex_a78_regs: /* The ascii list of register names to be reported */
.asciz "cpuectlr_el1", ""
-func cortex_hercules_cpu_reg_dump
- adr x6, cortex_hercules_regs
- mrs x8, CORTEX_HERCULES_CPUECTLR_EL1
+func cortex_a78_cpu_reg_dump
+ adr x6, cortex_a78_regs
+ mrs x8, CORTEX_A78_CPUECTLR_EL1
ret
-endfunc cortex_hercules_cpu_reg_dump
+endfunc cortex_a78_cpu_reg_dump
-declare_cpu_ops cortex_hercules, CORTEX_HERCULES_MIDR, \
- cortex_hercules_reset_func, \
- cortex_hercules_core_pwr_dwn
+declare_cpu_ops cortex_a78, CORTEX_A78_MIDR, \
+ cortex_a78_reset_func, \
+ cortex_a78_core_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_hercules_ae.S b/lib/cpus/aarch64/cortex_hercules_ae.S
index c4a2163..4452c41 100644
--- a/lib/cpus/aarch64/cortex_hercules_ae.S
+++ b/lib/cpus/aarch64/cortex_hercules_ae.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, ARM Limited. All rights reserved.
+ * Copyright (c) 2019-2020, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -24,20 +24,20 @@
func cortex_hercules_ae_reset_func
/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
mrs x0, actlr_el3
- bic x0, x0, #CORTEX_HERCULES_ACTLR_TAM_BIT
+ bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT
msr actlr_el3, x0
/* Make sure accesses from non-secure EL0/EL1 are not trapped to EL2 */
mrs x0, actlr_el2
- bic x0, x0, #CORTEX_HERCULES_ACTLR_TAM_BIT
+ bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT
msr actlr_el2, x0
/* Enable group0 counters */
- mov x0, #CORTEX_HERCULES_AMU_GROUP0_MASK
+ mov x0, #CORTEX_A78_AMU_GROUP0_MASK
msr CPUAMCNTENSET0_EL0, x0
/* Enable group1 counters */
- mov x0, #CORTEX_HERCULES_AMU_GROUP1_MASK
+ mov x0, #CORTEX_A78_AMU_GROUP1_MASK
msr CPUAMCNTENSET1_EL0, x0
isb
@@ -54,9 +54,9 @@
* Enable CPU power down bit in power control register
* -------------------------------------------------------
*/
- mrs x0, CORTEX_HERCULES_CPUPWRCTLR_EL1
- orr x0, x0, #CORTEX_HERCULES_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
- msr CORTEX_HERCULES_CPUPWRCTLR_EL1, x0
+ mrs x0, CORTEX_A78_CPUPWRCTLR_EL1
+ orr x0, x0, #CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
+ msr CORTEX_A78_CPUPWRCTLR_EL1, x0
isb
ret
endfunc cortex_hercules_ae_core_pwr_dwn
@@ -85,7 +85,7 @@
func cortex_hercules_ae_cpu_reg_dump
adr x6, cortex_hercules_ae_regs
- mrs x8, CORTEX_HERCULES_CPUECTLR_EL1
+ mrs x8, CORTEX_A78_CPUECTLR_EL1
ret
endfunc cortex_hercules_ae_cpu_reg_dump
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index 3c0c9cd..1bc082d 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -251,8 +251,8 @@
ERRATA_A76_1286807 ?=0
# Flag to apply erratum 1688305 workaround during reset. This erratum applies
-# to revisions r0p0 - r1p0 of the Hercules cpu.
-ERRATA_HERCULES_1688305 ?=0
+# to revisions r0p0 - r1p0 of the A78 cpu.
+ERRATA_A78_1688305 ?=0
# Flag to apply T32 CLREX workaround during reset. This erratum applies
# only to r0p0 and r1p0 of the Neoverse N1 cpu.
@@ -487,9 +487,9 @@
$(eval $(call assert_boolean,ERRATA_A76_1286807))
$(eval $(call add_define,ERRATA_A76_1286807))
-# Process ERRATA_HERCULES_1688305 flag
-$(eval $(call assert_boolean,ERRATA_HERCULES_1688305))
-$(eval $(call add_define,ERRATA_HERCULES_1688305))
+# Process ERRATA_A78_1688305 flag
+$(eval $(call assert_boolean,ERRATA_A78_1688305))
+$(eval $(call add_define,ERRATA_A78_1688305))
# Process ERRATA_N1_1043202 flag
$(eval $(call assert_boolean,ERRATA_N1_1043202))