diff --git a/plat/amd/versal2/aarch64/common.c b/plat/amd/versal2/aarch64/common.c
index 0e46edc..c78d711 100644
--- a/plat/amd/versal2/aarch64/common.c
+++ b/plat/amd/versal2/aarch64/common.c
@@ -75,8 +75,8 @@
 	uint32_t version_type;
 
 	version_type = mmio_read_32(PMC_TAP_VERSION);
-	platform_id = FIELD_GET(PLATFORM_MASK, version_type);
-	platform_version = FIELD_GET(PLATFORM_VERSION_MASK, version_type);
+	platform_id = FIELD_GET((uint32_t)PLATFORM_MASK, version_type);
+	platform_version = FIELD_GET((uint32_t)PLATFORM_VERSION_MASK, version_type);
 
 	if (platform_id == QEMU_COSIM) {
 		platform_id = QEMU;
diff --git a/plat/amd/versal2/bl31_setup.c b/plat/amd/versal2/bl31_setup.c
index 47d4c2c..6e7fffe 100644
--- a/plat/amd/versal2/bl31_setup.c
+++ b/plat/amd/versal2/bl31_setup.c
@@ -63,7 +63,7 @@
 	bl32_image_ep_info.args.arg3 = XILINX_OF_BOARD_DTB_ADDR;
 #endif
 	bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
-	bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX,
+	bl33_image_ep_info.spsr = (uint32_t)SPSR_64(MODE_EL2, MODE_SP_ELX,
 					  DISABLE_ALL_EXCEPTIONS);
 }
 
@@ -229,7 +229,7 @@
 
 void bl31_plat_runtime_setup(void)
 {
-	uint64_t flags = 0;
+	uint32_t flags = 0;
 	int32_t rc;
 
 	set_interrupt_rm_flag(flags, NON_SECURE);
diff --git a/plat/amd/versal2/include/def.h b/plat/amd/versal2/include/def.h
index f3a7907..0c43d1b 100644
--- a/plat/amd/versal2/include/def.h
+++ b/plat/amd/versal2/include/def.h
@@ -12,7 +12,7 @@
 #include <plat/arm/common/smccc_def.h>
 #include <plat/common/common_def.h>
 
-#define MAX_INTR_EL3			2
+#define MAX_INTR_EL3			2U
 
 /* List all consoles */
 #define VERSAL2_CONSOLE_ID_none		0
diff --git a/plat/amd/versal2/include/versal2-scmi.h b/plat/amd/versal2/include/versal2-scmi.h
index c08b4b1..218fbf6 100644
--- a/plat/amd/versal2/include/versal2-scmi.h
+++ b/plat/amd/versal2/include/versal2-scmi.h
@@ -10,96 +10,96 @@
 #ifndef _VERSAL2_SCMI_H
 #define _VERSAL2_SCMI_H
 
-#define CLK_GEM0_0	0
-#define CLK_GEM0_1	1
-#define CLK_GEM0_2	2
-#define CLK_GEM0_3	3
-#define CLK_GEM0_4	4
-#define CLK_GEM1_0	5
-#define CLK_GEM1_1	6
-#define CLK_GEM1_2	7
-#define CLK_GEM1_3	8
-#define CLK_GEM1_4	9
-#define CLK_SERIAL0_0	10
-#define CLK_SERIAL0_1	11
-#define CLK_SERIAL1_0	12
-#define CLK_SERIAL1_1	13
-#define CLK_UFS0_0	14
-#define CLK_UFS0_1	15
-#define CLK_UFS0_2	16
-#define CLK_USB0_0	17
-#define CLK_USB0_1	18
-#define CLK_USB0_2	19
-#define CLK_USB1_0	20
-#define CLK_USB1_1	21
-#define CLK_USB1_2	22
-#define CLK_MMC0_0	23
-#define CLK_MMC0_1	24
-#define CLK_MMC0_2	25
-#define CLK_MMC1_0	26
-#define CLK_MMC1_1	27
-#define CLK_MMC1_2	28
-#define CLK_TTC0_0	29
-#define CLK_TTC1_0	30
-#define CLK_TTC2_0	31
-#define CLK_TTC3_0	32
-#define CLK_TTC4_0	33
-#define CLK_TTC5_0	34
-#define CLK_TTC6_0	35
-#define CLK_TTC7_0	36
-#define CLK_I2C0_0	37
-#define CLK_I2C1_0	38
-#define CLK_I2C2_0	39
-#define CLK_I2C3_0	40
-#define CLK_I2C4_0	41
-#define CLK_I2C5_0	42
-#define CLK_I2C6_0	43
-#define CLK_I2C7_0	44
-#define CLK_OSPI0_0	45
-#define CLK_QSPI0_0	46
-#define CLK_QSPI0_1	47
-#define CLK_WWDT0_0	48
-#define CLK_WWDT1_0	49
-#define CLK_WWDT2_0	50
-#define CLK_WWDT3_0	51
-#define CLK_ADMA0_0	52
-#define CLK_ADMA0_1	53
-#define CLK_ADMA1_0	54
-#define CLK_ADMA1_1	55
-#define CLK_ADMA2_0	56
-#define CLK_ADMA2_1	57
-#define CLK_ADMA3_0	58
-#define CLK_ADMA3_1	59
-#define CLK_ADMA4_0	60
-#define CLK_ADMA4_1	61
-#define CLK_ADMA5_0	62
-#define CLK_ADMA5_1	63
-#define CLK_ADMA6_0	64
-#define CLK_ADMA6_1	65
-#define CLK_ADMA7_0	66
-#define CLK_ADMA7_1	67
-#define CLK_CAN0_0	68
-#define CLK_CAN0_1	69
-#define CLK_CAN1_0	70
-#define CLK_CAN1_1	71
-#define CLK_CAN2_0	72
-#define CLK_CAN2_1	73
-#define CLK_CAN3_0	74
-#define CLK_CAN3_1	75
-#define CLK_PS_GPIO_0	76
-#define CLK_PMC_GPIO_0	77
-#define CLK_SPI0_0	78
-#define CLK_SPI0_1	79
-#define CLK_SPI1_0	80
-#define CLK_SPI1_1	81
-#define CLK_I3C0_0	82
-#define CLK_I3C1_0	83
-#define CLK_I3C2_0	84
-#define CLK_I3C3_0	85
-#define CLK_I3C4_0	86
-#define CLK_I3C5_0	87
-#define CLK_I3C6_0	88
-#define CLK_I3C7_0	89
+#define CLK_GEM0_0	0U
+#define CLK_GEM0_1	1U
+#define CLK_GEM0_2	2U
+#define CLK_GEM0_3	3U
+#define CLK_GEM0_4	4U
+#define CLK_GEM1_0	5U
+#define CLK_GEM1_1	6U
+#define CLK_GEM1_2	7U
+#define CLK_GEM1_3	8U
+#define CLK_GEM1_4	9U
+#define CLK_SERIAL0_0	10U
+#define CLK_SERIAL0_1	11U
+#define CLK_SERIAL1_0	12U
+#define CLK_SERIAL1_1	13U
+#define CLK_UFS0_0	14U
+#define CLK_UFS0_1	15U
+#define CLK_UFS0_2	16U
+#define CLK_USB0_0	17U
+#define CLK_USB0_1	18U
+#define CLK_USB0_2	19U
+#define CLK_USB1_0	20U
+#define CLK_USB1_1	21U
+#define CLK_USB1_2	22U
+#define CLK_MMC0_0	23U
+#define CLK_MMC0_1	24U
+#define CLK_MMC0_2	25U
+#define CLK_MMC1_0	26U
+#define CLK_MMC1_1	27U
+#define CLK_MMC1_2	28U
+#define CLK_TTC0_0	29U
+#define CLK_TTC1_0	30U
+#define CLK_TTC2_0	31U
+#define CLK_TTC3_0	32U
+#define CLK_TTC4_0	33U
+#define CLK_TTC5_0	34U
+#define CLK_TTC6_0	35U
+#define CLK_TTC7_0	36U
+#define CLK_I2C0_0	37U
+#define CLK_I2C1_0	38U
+#define CLK_I2C2_0	39U
+#define CLK_I2C3_0	40U
+#define CLK_I2C4_0	41U
+#define CLK_I2C5_0	42U
+#define CLK_I2C6_0	43U
+#define CLK_I2C7_0	44U
+#define CLK_OSPI0_0	45U
+#define CLK_QSPI0_0	46U
+#define CLK_QSPI0_1	47U
+#define CLK_WWDT0_0	48U
+#define CLK_WWDT1_0	49U
+#define CLK_WWDT2_0	50U
+#define CLK_WWDT3_0	51U
+#define CLK_ADMA0_0	52U
+#define CLK_ADMA0_1	53U
+#define CLK_ADMA1_0	54U
+#define CLK_ADMA1_1	55U
+#define CLK_ADMA2_0	56U
+#define CLK_ADMA2_1	57U
+#define CLK_ADMA3_0	58U
+#define CLK_ADMA3_1	59U
+#define CLK_ADMA4_0	60U
+#define CLK_ADMA4_1	61U
+#define CLK_ADMA5_0	62U
+#define CLK_ADMA5_1	63U
+#define CLK_ADMA6_0	64U
+#define CLK_ADMA6_1	65U
+#define CLK_ADMA7_0	66U
+#define CLK_ADMA7_1	67U
+#define CLK_CAN0_0	68U
+#define CLK_CAN0_1	69U
+#define CLK_CAN1_0	70U
+#define CLK_CAN1_1	71U
+#define CLK_CAN2_0	72U
+#define CLK_CAN2_1	73U
+#define CLK_CAN3_0	74U
+#define CLK_CAN3_1	75U
+#define CLK_PS_GPIO_0	76U
+#define CLK_PMC_GPIO_0	77U
+#define CLK_SPI0_0	78U
+#define CLK_SPI0_1	79U
+#define CLK_SPI1_0	80U
+#define CLK_SPI1_1	81U
+#define CLK_I3C0_0	82U
+#define CLK_I3C1_0	83U
+#define CLK_I3C2_0	84U
+#define CLK_I3C3_0	85U
+#define CLK_I3C4_0	86U
+#define CLK_I3C5_0	87U
+#define CLK_I3C6_0	88U
+#define CLK_I3C7_0	89U
 
 #define RESET_GEM0_0	0
 #define RESET_GEM1_0	1
diff --git a/plat/amd/versal2/plat_psci.c b/plat/amd/versal2/plat_psci.c
index eab032d..e8dc5d3 100644
--- a/plat/amd/versal2/plat_psci.c
+++ b/plat/amd/versal2/plat_psci.c
@@ -35,9 +35,9 @@
 
 static int32_t zynqmp_nopmu_pwr_domain_on(u_register_t mpidr)
 {
-	uint32_t cpu_id = plat_core_pos_by_mpidr(mpidr) & ~BIT(MPIDR_MT_BIT);
-	uint32_t cpu = cpu_id % PLATFORM_CORE_COUNT_PER_CLUSTER;
-	uint32_t cluster = cpu_id / PLATFORM_CORE_COUNT_PER_CLUSTER;
+	int32_t cpu_id = plat_core_pos_by_mpidr(mpidr) & ~BIT(MPIDR_MT_BIT);
+	int32_t cpu = cpu_id % PLATFORM_CORE_COUNT_PER_CLUSTER;
+	int32_t cluster = cpu_id / PLATFORM_CORE_COUNT_PER_CLUSTER;
 	uintptr_t apu_cluster_base = 0, apu_pcli_base, apu_pcli_cluster = 0;
 	uintptr_t rst_apu_cluster = PSX_CRF + RST_APU0_OFFSET + ((uint64_t)cluster * 0x4U);
 
@@ -48,7 +48,7 @@
 		return PSCI_E_INTERN_FAIL;
 	}
 
-	if (cluster > 3) {
+	if (cluster > 3U) {
 		panic();
 	}
 
@@ -69,7 +69,7 @@
 	mmio_write_32(apu_cluster_base + APU_RVBAR_L_0 + (cpu << 3),
 		      (uint32_t)_sec_entry);
 	mmio_write_32(apu_cluster_base + APU_RVBAR_H_0 + (cpu << 3),
-		      _sec_entry >> 32);
+		      (uint32_t)(_sec_entry >> 32));
 
 	/* de-assert core reset */
 	mmio_clrbits_32(rst_apu_cluster, ((RST_APU_COLD_RESET|RST_APU_WARN_RESET) << cpu));
@@ -178,9 +178,9 @@
 		ret = (int32_t) mmio_read_32(PMXC_IOU_SLCR_TX_RX_CONFIG_RDY);
 		break;
 	case IOCTL_UFS_SRAM_CSR_SEL:
-		if (arg1 == 1) {
+		if (arg1 == 1U) {
 			ret = (int32_t) mmio_read_32(PMXC_IOU_SLCR_SRAM_CSR);
-		} else if (arg1 == 0) {
+		} else if (arg1 == 0U) {
 			mmio_write_32(PMXC_IOU_SLCR_SRAM_CSR, arg2);
 		}
 		break;
diff --git a/plat/amd/versal2/scmi.c b/plat/amd/versal2/scmi.c
index 6375df3..eec8205 100644
--- a/plat/amd/versal2/scmi.c
+++ b/plat/amd/versal2/scmi.c
@@ -293,7 +293,7 @@
 		return SCMI_NOT_FOUND;
 	}
 
-	if (start_idx > 0) {
+	if (start_idx > 0U) {
 		return SCMI_OUT_OF_RANGE;
 	}
 
@@ -328,7 +328,7 @@
 				 unsigned long rate)
 {
 	struct scmi_clk *clock = clk_find(agent_id, scmi_id);
-	unsigned long ret = UL(SCMI_SUCCESS);
+	int32_t ret = SCMI_SUCCESS;
 
 	if ((clock == NULL)) {
 		ret = SCMI_NOT_FOUND;
@@ -564,17 +564,19 @@
 			       unsigned int state)
 {
 	struct scmi_pd *pd = find_pd(agent_id, pd_id);
+	int32_t ret = SCMI_SUCCESS;
 
 	if (pd == NULL) {
-		return SCMI_NOT_SUPPORTED;
-	}
+		ret = SCMI_NOT_SUPPORTED;
+	} else {
 
-	NOTICE("SCMI: PD: set id: %d, orig state: %x, new state: %x,  flags: %x\n",
-	       pd_id, pd->state, state, flags);
+		NOTICE("SCMI: PD: set id: %d, orig state: %x, new state: %x,  flags: %x\n",
+				pd_id, pd->state, state, flags);
 
-	pd->state = state;
+		pd->state = state;
+	}
 
-	return 0U;
+	return ret;
 }
 
 
diff --git a/plat/amd/versal2/sip_svc_setup.c b/plat/amd/versal2/sip_svc_setup.c
index 6850030..4a1be3e 100644
--- a/plat/amd/versal2/sip_svc_setup.c
+++ b/plat/amd/versal2/sip_svc_setup.c
@@ -71,7 +71,7 @@
 	VERBOSE("SMCID: 0x%08x, x1: 0x%016" PRIx64 ", x2: 0x%016" PRIx64 ", x3: 0x%016" PRIx64 ", x4: 0x%016" PRIx64 "\n",
 		smc_fid, x1, x2, x3, x4);
 
-	if ((smc_fid & SIP_FID_MASK) != 0) {
+	if ((smc_fid & SIP_FID_MASK) != 0U) {
 		WARN("SMC out of SiP assinged range: 0x%x\n", smc_fid);
 		SMC_RET1(handle, SMC_UNK);
 	}
diff --git a/plat/arm/board/neoverse_rd/common/nrd_bl31_setup.c b/plat/arm/board/neoverse_rd/common/nrd_bl31_setup.c
index bce8834..39a86b1 100644
--- a/plat/arm/board/neoverse_rd/common/nrd_bl31_setup.c
+++ b/plat/arm/board/neoverse_rd/common/nrd_bl31_setup.c
@@ -152,6 +152,9 @@
 	nrd_plat_info.config_id = plat_arm_nrd_get_config_id();
 	nrd_plat_info.multi_chip_mode = plat_arm_nrd_get_multi_chip_mode();
 
+	/* Initialize generic timer */
+	generic_delay_timer_init();
+
 	arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
 }
 
@@ -216,7 +219,6 @@
 
 void nrd_bl31_common_platform_setup(void)
 {
-	generic_delay_timer_init();
 
 	arm_bl31_platform_setup();
 
diff --git a/plat/xilinx/common/include/ipi.h b/plat/xilinx/common/include/ipi.h
index 1d62f3e..d792710 100644
--- a/plat/xilinx/common/include/ipi.h
+++ b/plat/xilinx/common/include/ipi.h
@@ -29,7 +29,7 @@
  ********************************************************************/
 #define IPI_SECURE_MASK  (0x1U)
 #define IPI_IS_SECURE(I) ((ipi_table[(I)].secure_only & \
-			   IPI_SECURE_MASK) ? 1 : 0)
+			   IPI_SECURE_MASK) ? true : false)
 
 /*********************************************************************
  * Struct definitions
diff --git a/plat/xilinx/common/ipi.c b/plat/xilinx/common/ipi.c
index d7c70f3..cc4b04d 100644
--- a/plat/xilinx/common/ipi.c
+++ b/plat/xilinx/common/ipi.c
@@ -90,11 +90,11 @@
 {
 	int ret = 0;
 
-	if (!is_ipi_mb_within_range(local, remote)) {
+	if (is_ipi_mb_within_range(local, remote) == 0) {
 		ret = -EINVAL;
-	} else if (IPI_IS_SECURE(local) && !is_secure) {
+	} else if (IPI_IS_SECURE(local) && (is_secure == 0U)) {
 		ret = -EPERM;
-	} else if (IPI_IS_SECURE(remote) && !is_secure) {
+	} else if (IPI_IS_SECURE(remote) && (is_secure == 0U)) {
 		ret = -EPERM;
 	} else {
 		/* To fix the misra 15.7 warning */
@@ -111,9 +111,12 @@
  */
 void ipi_mb_open(uint32_t local, uint32_t remote)
 {
-	mmio_write_32(IPI_REG_BASE(local) + IPI_IDR_OFFSET,
+	uint64_t idr_offset = (uint64_t)(IPI_REG_BASE(local) + IPI_IDR_OFFSET);
+	uint64_t isr_offset = (uint64_t)(IPI_REG_BASE(local) + IPI_ISR_OFFSET);
+
+	mmio_write_32(idr_offset,
 		      IPI_BIT_MASK(remote));
-	mmio_write_32(IPI_REG_BASE(local) + IPI_ISR_OFFSET,
+	mmio_write_32(isr_offset,
 		      IPI_BIT_MASK(remote));
 }
 
@@ -125,7 +128,9 @@
  */
 void ipi_mb_release(uint32_t local, uint32_t remote)
 {
-	mmio_write_32(IPI_REG_BASE(local) + IPI_IDR_OFFSET,
+	uint64_t idr_offset = (uint64_t)(IPI_REG_BASE(local) + IPI_IDR_OFFSET);
+
+	mmio_write_32(idr_offset,
 		      IPI_BIT_MASK(remote));
 }
 
@@ -142,12 +147,14 @@
 {
 	int ret = 0U;
 	uint32_t status;
+	uint64_t obr_offset = (uint64_t)(IPI_REG_BASE(local) + IPI_OBR_OFFSET);
+	uint64_t isr_offset = (uint64_t)(IPI_REG_BASE(local) + IPI_ISR_OFFSET);
 
-	status = mmio_read_32(IPI_REG_BASE(local) + IPI_OBR_OFFSET);
+	status = mmio_read_32(obr_offset);
 	if ((status & IPI_BIT_MASK(remote)) != 0U) {
 		ret |= IPI_MB_STATUS_SEND_PENDING;
 	}
-	status = mmio_read_32(IPI_REG_BASE(local) + IPI_ISR_OFFSET);
+	status = mmio_read_32(isr_offset);
 	if ((status & IPI_BIT_MASK(remote)) != 0U) {
 		ret |= IPI_MB_STATUS_RECV_PENDING;
 	}
@@ -167,13 +174,14 @@
 void ipi_mb_notify(uint32_t local, uint32_t remote, uint32_t is_blocking)
 {
 	uint32_t status;
+	uint64_t trig_offset = (uint64_t)(IPI_REG_BASE(local) + IPI_TRIG_OFFSET);
+	uint64_t obr_offset = (uint64_t)(IPI_REG_BASE(local) + IPI_OBR_OFFSET);
 
-	mmio_write_32(IPI_REG_BASE(local) + IPI_TRIG_OFFSET,
+	mmio_write_32(trig_offset,
 		      IPI_BIT_MASK(remote));
 	if (is_blocking != 0U) {
 		do {
-			status = mmio_read_32(IPI_REG_BASE(local) +
-					      IPI_OBR_OFFSET);
+			status = mmio_read_32(obr_offset);
 		} while ((status & IPI_BIT_MASK(remote)) != 0U);
 	}
 }
@@ -188,7 +196,9 @@
  */
 void ipi_mb_ack(uint32_t local, uint32_t remote)
 {
-	mmio_write_32(IPI_REG_BASE(local) + IPI_ISR_OFFSET,
+	uint64_t isr_offset = (uint64_t)(IPI_REG_BASE(local) + IPI_ISR_OFFSET);
+
+	mmio_write_32(isr_offset,
 		      IPI_BIT_MASK(remote));
 }
 
@@ -202,7 +212,9 @@
  */
 void ipi_mb_disable_irq(uint32_t local, uint32_t remote)
 {
-	mmio_write_32(IPI_REG_BASE(local) + IPI_IDR_OFFSET,
+	uint64_t idr_offset = (uint64_t)(IPI_REG_BASE(local) + IPI_IDR_OFFSET);
+
+	mmio_write_32(idr_offset,
 		      IPI_BIT_MASK(remote));
 }
 
@@ -216,6 +228,8 @@
  */
 void ipi_mb_enable_irq(uint32_t local, uint32_t remote)
 {
-	mmio_write_32(IPI_REG_BASE(local) + IPI_IER_OFFSET,
+	uint64_t ier_offset = (uint64_t)(IPI_REG_BASE(local) + IPI_IER_OFFSET);
+
+	mmio_write_32(ier_offset,
 		      IPI_BIT_MASK(remote));
 }
diff --git a/plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c b/plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c
index 9a0149b..cdff3c8 100644
--- a/plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c
+++ b/plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c
@@ -78,8 +78,8 @@
 	uint32_t ipi_remote_id;
 	uint32_t is_secure;
 
-	ipi_local_id = x1 & UNSIGNED32_MASK;
-	ipi_remote_id = x2 & UNSIGNED32_MASK;
+	ipi_local_id = (uint32_t)(x1 & UNSIGNED32_MASK);
+	ipi_remote_id = (uint32_t)(x2 & UNSIGNED32_MASK);
 
 	/* OEN Number 48 to 63 is for Trusted App and OS
 	 * GET_SMC_OEN limits the return value of OEN number to 63 by bitwise
@@ -106,11 +106,11 @@
 		SMC_RET1(handle, 0);
 	case IPI_MAILBOX_STATUS_ENQUIRY:
 	{
-		int32_t disable_interrupt;
+		bool disable_interrupt;
 
-		disable_interrupt = (x3 & IPI_SMC_ENQUIRY_DIRQ_MASK) ? 1 : 0;
+		disable_interrupt = ((x3 & IPI_SMC_ENQUIRY_DIRQ_MASK) != 0U);
 		ret = ipi_mb_enquire_status(ipi_local_id, ipi_remote_id);
-		if ((ret & IPI_MB_STATUS_RECV_PENDING) && disable_interrupt)
+		if ((((uint32_t)ret & IPI_MB_STATUS_RECV_PENDING) > 0U) && disable_interrupt)
 			ipi_mb_disable_irq(ipi_local_id, ipi_remote_id);
 		SMC_RET1(handle, ret);
 	}
@@ -118,15 +118,15 @@
 	{
 		uint32_t is_blocking;
 
-		is_blocking = (x3 & IPI_SMC_NOTIFY_BLOCK_MASK) ? 1 : 0;
+		is_blocking = ((x3 & IPI_SMC_NOTIFY_BLOCK_MASK) != 0U);
 		ipi_mb_notify(ipi_local_id, ipi_remote_id, is_blocking);
 		SMC_RET1(handle, 0);
 	}
 	case IPI_MAILBOX_ACK:
 	{
-		int32_t enable_interrupt;
+		bool enable_interrupt;
 
-		enable_interrupt = (x3 & IPI_SMC_ACK_EIRQ_MASK) ? 1 : 0;
+		enable_interrupt = ((x3 & IPI_SMC_ACK_EIRQ_MASK) != 0U);
 		ipi_mb_ack(ipi_local_id, ipi_remote_id);
 		if (enable_interrupt != 0)
 			ipi_mb_enable_irq(ipi_local_id, ipi_remote_id);
diff --git a/plat/xilinx/common/plat_startup.c b/plat/xilinx/common/plat_startup.c
index 149ba2d..9f829c9 100644
--- a/plat/xilinx/common/plat_startup.c
+++ b/plat/xilinx/common/plat_startup.c
@@ -72,11 +72,13 @@
  * Return: XBL_FLAGS_A53_0, XBL_FLAGS_A53_1, XBL_FLAGS_A53_2 or XBL_FLAGS_A53_3.
  *
  */
-static int32_t get_xbl_cpu(const struct xbl_partition *partition)
+static uint32_t get_xbl_cpu(const struct xbl_partition *partition)
 {
 	uint64_t flags = partition->flags & XBL_FLAGS_CPU_MASK;
 
-	return flags >> XBL_FLAGS_CPU_SHIFT;
+	flags >>= XBL_FLAGS_CPU_SHIFT;
+
+	return (uint32_t)flags;
 }
 
 /**
@@ -86,11 +88,13 @@
  * Return: XBL_FLAGS_EL0, XBL_FLAGS_EL1, XBL_FLAGS_EL2 or XBL_FLAGS_EL3.
  *
  */
-static int32_t get_xbl_el(const struct xbl_partition *partition)
+static uint32_t get_xbl_el(const struct xbl_partition *partition)
 {
 	uint64_t flags = partition->flags & XBL_FLAGS_EL_MASK;
 
+	flags >>= XBL_FLAGS_EL_SHIFT;
+
-	return flags >> XBL_FLAGS_EL_SHIFT;
+	return (uint32_t)flags;
 }
 
 /**
@@ -100,11 +104,13 @@
  * Return: XBL_FLAGS_NON_SECURE or XBL_FLAGS_SECURE.
  *
  */
-static int32_t get_xbl_ss(const struct xbl_partition *partition)
+static uint32_t get_xbl_ss(const struct xbl_partition *partition)
 {
 	uint64_t flags = partition->flags & XBL_FLAGS_TZ_MASK;
 
-	return flags >> XBL_FLAGS_TZ_SHIFT;
+	flags >>= XBL_FLAGS_TZ_SHIFT;
+
+	return (uint32_t)flags;
 }
 
 /**
@@ -114,7 +120,7 @@
  * Return: SPSR_E_LITTLE or SPSR_E_BIG.
  *
  */
-static int32_t get_xbl_endian(const struct xbl_partition *partition)
+static uint32_t get_xbl_endian(const struct xbl_partition *partition)
 {
 	uint64_t flags = partition->flags & XBL_FLAGS_ENDIAN_MASK;
 
@@ -134,11 +140,13 @@
  * Return: XBL_FLAGS_ESTATE_A32 or XBL_FLAGS_ESTATE_A64.
  *
  */
-static int32_t get_xbl_estate(const struct xbl_partition *partition)
+static uint32_t get_xbl_estate(const struct xbl_partition *partition)
 {
 	uint64_t flags = partition->flags & XBL_FLAGS_ESTATE_MASK;
 
-	return flags >> XBL_FLAGS_ESTATE_SHIFT;
+	flags >>= XBL_FLAGS_ESTATE_SHIFT;
+
+	return flags;
 }
 
 #if defined(PLAT_versal_net)
@@ -148,11 +156,11 @@
  *
  * Return: cluster number for the partition.
  */
-static int32_t get_xbl_cluster(const struct xbl_partition *partition)
+static uint32_t get_xbl_cluster(const struct xbl_partition *partition)
 {
 	uint64_t flags = partition->flags & XBL_FLAGS_CLUSTER_MASK;
 
-	return (int32_t)(flags >> XBL_FLAGS_CLUSTER_SHIFT);
+	return (flags >> XBL_FLAGS_CLUSTER_SHIFT);
 }
 #endif /* PLAT_versal_net */
 
@@ -175,16 +183,16 @@
 {
 	const struct xbl_handoff_params *HandoffParams;
 
-	if (!handoff_addr) {
+	if (handoff_addr == 0U) {
 		WARN("BL31: No handoff structure passed\n");
 		return XBL_HANDOFF_NO_STRUCT;
 	}
 
 	HandoffParams = (struct xbl_handoff_params *)handoff_addr;
-	if ((HandoffParams->magic[0] != 'X') ||
-	    (HandoffParams->magic[1] != 'L') ||
-	    (HandoffParams->magic[2] != 'N') ||
-	    (HandoffParams->magic[3] != 'X')) {
+	if ((HandoffParams->magic[0] != (uint8_t)'X') ||
+	    (HandoffParams->magic[1] != (uint8_t)'L') ||
+	    (HandoffParams->magic[2] != (uint8_t)'N') ||
+	    (HandoffParams->magic[3] != (uint8_t)'X')) {
 		ERROR("BL31: invalid handoff structure at %" PRIx64 "\n", handoff_addr);
 		return XBL_HANDOFF_INVAL_STRUCT;
 	}
@@ -204,7 +212,7 @@
 	 */
 	for (size_t i = 0; i < HandoffParams->num_entries; i++) {
 		entry_point_info_t *image;
-		int32_t target_estate, target_secure, target_cpu;
+		uint32_t target_estate, target_secure, target_cpu;
 		uint32_t target_endianness, target_el;
 
 		VERBOSE("BL31: %zd: entry:0x%" PRIx64 ", flags:0x%" PRIx64 "\n", i,
@@ -251,8 +259,8 @@
 			image = bl32;
 
 			if (target_estate == XBL_FLAGS_ESTATE_A32) {
-				bl32->spsr = SPSR_MODE32(MODE32_svc, SPSR_T_ARM,
-							 target_endianness,
+				bl32->spsr = (uint32_t)SPSR_MODE32(MODE32_svc, SPSR_T_ARM,
+							 (uint64_t)target_endianness,
 							 DISABLE_ALL_EXCEPTIONS);
 			} else {
 				bl32->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX,
@@ -268,8 +276,8 @@
 					target_el = MODE32_sys;
 				}
 
-				bl33->spsr = SPSR_MODE32(target_el, SPSR_T_ARM,
-							 target_endianness,
+				bl33->spsr = (uint32_t)SPSR_MODE32((uint64_t)target_el, SPSR_T_ARM,
+							 (uint64_t)target_endianness,
 							 DISABLE_ALL_EXCEPTIONS);
 			} else {
 				if (target_el == XBL_FLAGS_EL2) {
@@ -278,7 +286,7 @@
 					target_el = MODE_EL1;
 				}
 
-				bl33->spsr = SPSR_64(target_el, MODE_SP_ELX,
+				bl33->spsr = (uint32_t)SPSR_64((uint64_t)target_el, MODE_SP_ELX,
 						     DISABLE_ALL_EXCEPTIONS);
 			}
 		}
diff --git a/plat/xilinx/common/pm_service/pm_api_sys.c b/plat/xilinx/common/pm_service/pm_api_sys.c
index e9c5f13..627266d 100644
--- a/plat/xilinx/common/pm_service/pm_api_sys.c
+++ b/plat/xilinx/common/pm_service/pm_api_sys.c
@@ -56,7 +56,8 @@
 
 	for (reg_num = 0U; reg_num < NUM_GICD_ISENABLER; reg_num++) {
 		uint32_t base_irq = reg_num << ISENABLER_SHIFT;
-		uint32_t reg = mmio_read_32(isenabler1 + (reg_num << 2));
+		isenabler1 += (reg_num << 2);
+		uint32_t reg = mmio_read_32((uint64_t)isenabler1);
 
 		if (reg == 0U) {
 			continue;
@@ -117,7 +118,7 @@
 	module_id = (x0 & MODULE_ID_MASK) >> 8U;
 
 	//default module id is for LIBPM
-	if (module_id == 0) {
+	if (module_id == 0U) {
 		module_id = LIBPM_MODULE_ID;
 	}
 
@@ -218,7 +219,7 @@
 	/* Send request to the PMU */
 	PM_PACK_PAYLOAD4(payload, LIBPM_MODULE_ID, flag, PM_REQ_SUSPEND, target,
 			 latency, state);
-	if (ack == IPI_BLOCKING) {
+	if (ack == (uint32_t)IPI_BLOCKING) {
 		return pm_ipi_send_sync(primary_proc, payload, NULL, 0);
 	} else {
 		return pm_ipi_send(primary_proc, payload);
@@ -273,7 +274,7 @@
 {
 	enum pm_ret_status ret = PM_RET_SUCCESS;
 	/* Return if interrupt is not from PMU */
-	if (pm_ipi_irq_status(primary_proc) == 0) {
+	if (pm_ipi_irq_status(primary_proc) == 0U) {
 		return ret;
 	}
 
@@ -306,7 +307,7 @@
 	PM_PACK_PAYLOAD3(payload, LIBPM_MODULE_ID, flag, PM_FORCE_POWERDOWN,
 			 target, ack);
 
-	if (ack == IPI_BLOCKING) {
+	if (ack == (uint32_t)IPI_BLOCKING) {
 		return pm_ipi_send_sync(primary_proc, payload, NULL, 0);
 	} else {
 		return pm_ipi_send(primary_proc, payload);
@@ -431,7 +432,7 @@
 	 * feature check should be done only for LIBPM module
 	 * If module_id is 0, then we consider it LIBPM module as default id
 	 */
-	if ((module_id > 0) && (module_id != LIBPM_MODULE_ID)) {
+	if ((module_id > 0U) && (module_id != LIBPM_MODULE_ID)) {
 		return PM_RET_SUCCESS;
 	}
 
diff --git a/plat/xilinx/common/pm_service/pm_ipi.c b/plat/xilinx/common/pm_service/pm_ipi.c
index c3872fc..e12e74d 100644
--- a/plat/xilinx/common/pm_service/pm_ipi.c
+++ b/plat/xilinx/common/pm_service/pm_ipi.c
@@ -226,7 +226,7 @@
 				IPI_BUFFER_REQ_OFFSET;
 	enum pm_ret_status ret = PM_RET_SUCCESS;
 
-	if (local_count > IPI_BUFFER_MAX_WORDS) {
+	if (local_count > (uint32_t)IPI_BUFFER_MAX_WORDS) {
 		local_count = IPI_BUFFER_MAX_WORDS;
 	}
 
@@ -273,7 +273,7 @@
 		goto unlock;
 	}
 
-	ret = ERROR_CODE_MASK & (pm_ipi_buff_read(proc, value, count));
+	ret = ERROR_CODE_MASK & (uint32_t)(pm_ipi_buff_read(proc, value, count));
 
 unlock:
 	pm_ipi_lock_release();
@@ -297,7 +297,7 @@
 
 	ret = ipi_mb_enquire_status(proc->ipi->local_ipi_id,
 				    proc->ipi->remote_ipi_id);
-	if (ret & IPI_MB_STATUS_RECV_PENDING) {
+	if (((uint32_t)ret & IPI_MB_STATUS_RECV_PENDING) != 0U) {
 		return 1;
 	} else {
 		return 0;
diff --git a/plat/xilinx/common/pm_service/pm_svc_main.c b/plat/xilinx/common/pm_service/pm_svc_main.c
index afb9a96..fe496f3 100644
--- a/plat/xilinx/common/pm_service/pm_svc_main.c
+++ b/plat/xilinx/common/pm_service/pm_svc_main.c
@@ -113,7 +113,7 @@
 
 	/* Send powerdown request to online secondary core(s) */
 	ret = psci_stop_other_cores(PWRDWN_WAIT_TIMEOUT, raise_pwr_down_interrupt);
-	if (ret != PSCI_E_SUCCESS) {
+	if (ret != (uint32_t)PSCI_E_SUCCESS) {
 		ERROR("Failed to powerdown secondary core(s)\n");
 	}
 
@@ -140,11 +140,11 @@
 	(void)plat_ic_acknowledge_interrupt();
 
 	/* Check status register for each IPI except PMC */
-	for (i = IPI_ID_APU; i <= IPI_ID_5; i++) {
+	for (i = (int32_t)IPI_ID_APU; i <= IPI_ID_5; i++) {
 		ipi_status = ipi_mb_enquire_status(IPI_ID_APU, i);
 
 		/* If any agent other than PMC has generated IPI FIQ then send SGI to mbox driver */
-		if (ipi_status & IPI_MB_STATUS_RECV_PENDING) {
+		if ((uint32_t)ipi_status & IPI_MB_STATUS_RECV_PENDING) {
 			plat_ic_raise_ns_sgi(MBOX_SGI_SHARED_IPI, read_mpidr_el1());
 			break;
 		}
@@ -152,7 +152,7 @@
 
 	/* If PMC has not generated interrupt then end ISR */
 	ipi_status = ipi_mb_enquire_status(IPI_ID_APU, IPI_ID_PMC);
-	if ((ipi_status & IPI_MB_STATUS_RECV_PENDING) == 0) {
+	if (((uint32_t)ipi_status & IPI_MB_STATUS_RECV_PENDING) == 0U) {
 		plat_ic_end_of_interrupt(id);
 		return 0;
 	}
@@ -160,7 +160,7 @@
 	/* Handle PMC case */
 	ret = pm_get_callbackdata(payload, ARRAY_SIZE(payload), 0, 0);
 	if (ret != PM_RET_SUCCESS) {
-		payload[0] = ret;
+		payload[0] = (uint32_t)ret;
 	}
 
 	switch (payload[0]) {
@@ -278,7 +278,7 @@
 	gicd_write_irouter(gicv3_driver_data->gicd_base, PLAT_VERSAL_IPI_IRQ, MODE);
 
 	/* Register for idle callback during force power down/restart */
-	ret = pm_register_notifier(primary_proc->node_id, EVENT_CPU_PWRDWN,
+	ret = (int32_t)pm_register_notifier(primary_proc->node_id, EVENT_CPU_PWRDWN,
 				   0x0U, 0x1U, SECURE_FLAG);
 	if (ret != 0) {
 		WARN("BL31: registering idle callback for restart/force power down failed\n");
@@ -428,7 +428,7 @@
 
 		ret = pm_get_callbackdata(result, ARRAY_SIZE(result), security_flag, 1U);
 		if (ret != 0) {
-			result[0] = ret;
+			result[0] = (uint32_t)ret;
 		}
 
 		SMC_RET2(handle,
@@ -478,8 +478,8 @@
 	 * than other eemi calls.
 	 */
 	if (api_id == (uint32_t)PM_QUERY_DATA) {
-		if (((pm_arg[0] == XPM_QID_CLOCK_GET_NAME) ||
-		    (pm_arg[0] == XPM_QID_PINCTRL_GET_FUNCTION_NAME)) &&
+		if (((pm_arg[0] == (uint32_t)XPM_QID_CLOCK_GET_NAME) ||
+		    (pm_arg[0] == (uint32_t)XPM_QID_PINCTRL_GET_FUNCTION_NAME)) &&
 		    (ret == PM_RET_SUCCESS)) {
 			SMC_RET2(handle, (uint64_t)buf[0] | ((uint64_t)buf[1] << 32U),
 				(uint64_t)buf[2] | ((uint64_t)buf[3] << 32U));
diff --git a/plat/xilinx/common/versal.c b/plat/xilinx/common/versal.c
index b37dc76..7c29bae 100644
--- a/plat/xilinx/common/versal.c
+++ b/plat/xilinx/common/versal.c
@@ -60,5 +60,5 @@
  */
 int32_t plat_get_soc_revision(void)
 {
-	return (platform_id & SOC_ID_REV_MASK);
+	return (int32_t)(platform_id & SOC_ID_REV_MASK);
 }
diff --git a/plat/xilinx/versal/bl31_versal_setup.c b/plat/xilinx/versal/bl31_versal_setup.c
index 819a55b..54badf5 100644
--- a/plat/xilinx/versal/bl31_versal_setup.c
+++ b/plat/xilinx/versal/bl31_versal_setup.c
@@ -117,7 +117,7 @@
 	SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0);
 	SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
 
-	PM_PACK_PAYLOAD4(payload, LOADER_MODULE_ID, 1, PM_LOAD_GET_HANDOFF_PARAMS,
+	PM_PACK_PAYLOAD4(payload, LOADER_MODULE_ID, 1U, PM_LOAD_GET_HANDOFF_PARAMS,
 			(uintptr_t)addr >> 32U, (uintptr_t)addr, max_size);
 	ret_status = pm_ipi_send_sync(primary_proc, payload, NULL, 0);
 	if (ret_status == PM_RET_SUCCESS) {
diff --git a/plat/xilinx/versal/include/versal_def.h b/plat/xilinx/versal/include/versal_def.h
index 3a1c127..f7149c7 100644
--- a/plat/xilinx/versal/include/versal_def.h
+++ b/plat/xilinx/versal/include/versal_def.h
@@ -16,7 +16,7 @@
 #define PLATFORM_VERSION_MASK          GENMASK(31U, 28U)
 
 /* number of interrupt handlers. increase as required */
-#define MAX_INTR_EL3			2
+#define MAX_INTR_EL3			2U
 /* List all consoles */
 #define VERSAL_CONSOLE_ID_none		0
 #define VERSAL_CONSOLE_ID_pl011	1
diff --git a/plat/xilinx/versal/plat_psci.c b/plat/xilinx/versal/plat_psci.c
index 3fc6dbd..f160563 100644
--- a/plat/xilinx/versal/plat_psci.c
+++ b/plat/xilinx/versal/plat_psci.c
@@ -222,7 +222,7 @@
 	 * be set.
 	 */
 	ret = pm_feature_check((uint32_t)PM_SELF_SUSPEND, &version_type[0], SECURE_FLAG);
-	if (ret == PM_RET_SUCCESS) {
+	if (ret == (uint32_t)PM_RET_SUCCESS) {
 		fw_api_version = version_type[0] & 0xFFFFU;
 		if (fw_api_version >= 3U) {
 			(void)pm_self_suspend(proc->node_id, MAX_LATENCY, PM_STATE_CPU_OFF, 0,
diff --git a/plat/xilinx/versal/pm_service/pm_client.c b/plat/xilinx/versal/pm_service/pm_client.c
index 3e44153..de2cac8 100644
--- a/plat/xilinx/versal/pm_service/pm_client.c
+++ b/plat/xilinx/versal/pm_service/pm_client.c
@@ -26,7 +26,7 @@
 #include "pm_defs.h"
 #include <versal_def.h>
 
-#define UNDEFINED_CPUID		(~0)
+#define UNDEFINED_CPUID		(~0U)
 
 DEFINE_BAKERY_LOCK(pm_client_secure_lock);
 
@@ -232,12 +232,16 @@
  */
 static uint32_t pm_get_cpuid(uint32_t nid)
 {
-	for (size_t i = 0U; i < ARRAY_SIZE(pm_procs_all); i++) {
+	uint32_t ret = UNDEFINED_CPUID;
+	uint32_t i;
+
+	for (i = 0U; i < ARRAY_SIZE(pm_procs_all); i++) {
 		if (pm_procs_all[i].node_id == nid) {
-			return i;
+			ret = i;
+			break;
 		}
 	}
-	return UNDEFINED_CPUID;
+	return ret;
 }
 
 /**
diff --git a/plat/xilinx/versal_net/bl31_versal_net_setup.c b/plat/xilinx/versal_net/bl31_versal_net_setup.c
index cf2368a..faeeda0 100644
--- a/plat/xilinx/versal_net/bl31_versal_net_setup.c
+++ b/plat/xilinx/versal_net/bl31_versal_net_setup.c
@@ -55,7 +55,7 @@
 	bl32_image_ep_info.pc = BL32_BASE;
 	bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry();
 	bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
-	bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX,
+	bl33_image_ep_info.spsr = (uint32_t)SPSR_64(MODE_EL2, MODE_SP_ELX,
 					DISABLE_ALL_EXCEPTIONS);
 }
 
@@ -140,7 +140,7 @@
 	SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0);
 	SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
 #if !(TFA_NO_PM)
-	PM_PACK_PAYLOAD4(payload, LOADER_MODULE_ID, 1, PM_LOAD_GET_HANDOFF_PARAMS,
+	PM_PACK_PAYLOAD4(payload, LOADER_MODULE_ID, 1U, PM_LOAD_GET_HANDOFF_PARAMS,
 			 (uintptr_t)buff >> 32U, (uintptr_t)buff, max_size);
 
 	ret_status = pm_ipi_send_sync(primary_proc, payload, NULL, 0);
diff --git a/plat/xilinx/versal_net/include/versal_net_def.h b/plat/xilinx/versal_net/include/versal_net_def.h
index 5caf376..54f9cc9 100644
--- a/plat/xilinx/versal_net/include/versal_net_def.h
+++ b/plat/xilinx/versal_net/include/versal_net_def.h
@@ -12,7 +12,7 @@
 #include <plat/arm/common/smccc_def.h>
 #include <plat/common/common_def.h>
 
-#define MAX_INTR_EL3			2
+#define MAX_INTR_EL3			2U
 
 /* List all consoles */
 #define VERSAL_NET_CONSOLE_ID_none	U(0)
diff --git a/plat/xilinx/versal_net/plat_psci_pm.c b/plat/xilinx/versal_net/plat_psci_pm.c
index 1c32879..9f95574 100644
--- a/plat/xilinx/versal_net/plat_psci_pm.c
+++ b/plat/xilinx/versal_net/plat_psci_pm.c
@@ -27,7 +27,7 @@
 
 static int32_t versal_net_pwr_domain_on(u_register_t mpidr)
 {
-	uint32_t cpu_id = plat_core_pos_by_mpidr(mpidr);
+	int32_t cpu_id = plat_core_pos_by_mpidr(mpidr);
 	const struct pm_proc *proc;
 
 	VERBOSE("%s: mpidr: 0x%lx, cpuid: %x\n",
@@ -84,7 +84,7 @@
 	 * be set.
 	 */
 	ret = pm_feature_check((uint32_t)PM_SELF_SUSPEND, &version_type[0], SECURE_FLAG);
-	if (ret == PM_RET_SUCCESS) {
+	if (ret == (uint32_t)PM_RET_SUCCESS) {
 		fw_api_version = version_type[0] & 0xFFFFU;
 		if (fw_api_version >= 3U) {
 			(void)pm_self_suspend(proc->node_id, MAX_LATENCY, PM_STATE_CPU_OFF, 0,
@@ -245,7 +245,7 @@
 {
 	VERBOSE("%s: power_state: 0x%x\n", __func__, power_state);
 
-	int32_t pstate = psci_get_pstate_type(power_state);
+	uint32_t pstate = psci_get_pstate_type(power_state);
 
 	assert(req_state != NULL);
 
diff --git a/plat/xilinx/versal_net/plat_topology.c b/plat/xilinx/versal_net/plat_topology.c
index ee756c4..4e2d36e 100644
--- a/plat/xilinx/versal_net/plat_topology.c
+++ b/plat/xilinx/versal_net/plat_topology.c
@@ -44,8 +44,8 @@
 
 	mpidr &= MPIDR_AFFINITY_MASK;
 
-	cluster_id = MPIDR_AFFLVL2_VAL(mpidr);
-	cpu_id = MPIDR_AFFLVL1_VAL(mpidr);
+	cluster_id = (uint32_t)MPIDR_AFFLVL2_VAL(mpidr);
+	cpu_id = (uint32_t)MPIDR_AFFLVL1_VAL(mpidr);
 
 	if (cluster_id >= PLATFORM_CLUSTER_COUNT) {
 		return -3;
@@ -59,5 +59,5 @@
 		return -1;
 	}
 
-	return (cpu_id + (cluster_id * PLATFORM_CORE_COUNT_PER_CLUSTER));
+	return (int32_t)(cpu_id + (cluster_id * PLATFORM_CORE_COUNT_PER_CLUSTER));
 }
diff --git a/plat/xilinx/versal_net/pm_service/pm_client.c b/plat/xilinx/versal_net/pm_service/pm_client.c
index cff400c..9b2ca6f 100644
--- a/plat/xilinx/versal_net/pm_service/pm_client.c
+++ b/plat/xilinx/versal_net/pm_service/pm_client.c
@@ -26,7 +26,7 @@
 #include "pm_client.h"
 #include <versal_net_def.h>
 
-#define UNDEFINED_CPUID		(~0)
+#define UNDEFINED_CPUID		(~0U)
 
 DEFINE_RENAME_SYSREG_RW_FUNCS(cpu_pwrctrl_val, S3_0_C15_C2_7)
 
@@ -340,12 +340,16 @@
  */
 static uint32_t pm_get_cpuid(uint32_t nid)
 {
-	for (size_t i = 0; i < ARRAY_SIZE(pm_procs_all); i++) {
+	uint32_t ret = UNDEFINED_CPUID;
+	uint32_t i;
+
+	for (i = 0; i < ARRAY_SIZE(pm_procs_all); i++) {
 		if (pm_procs_all[i].node_id == nid) {
-			return i;
+			ret = i;
+			break;
 		}
 	}
-	return UNDEFINED_CPUID;
+	return ret;
 }
 
 /**
diff --git a/plat/xilinx/zynqmp/aarch64/zynqmp_common.c b/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
index 0e698f7..1361eda 100644
--- a/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
+++ b/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
@@ -42,9 +42,9 @@
 
 static uint32_t zynqmp_get_silicon_ver(void)
 {
-	static unsigned int ver;
+	static uint32_t ver;
 
-	if (!ver) {
+	if (ver == 0U) {
 		ver = mmio_read_32(ZYNQMP_CSU_BASEADDR +
 				   ZYNQMP_CSU_VERSION_OFFSET);
 		ver &= ZYNQMP_SILICON_VER_MASK;
@@ -270,7 +270,7 @@
 		return zynqmp_devices[i].name;
 	}
 
-	len = strlen(zynqmp_devices[i].name) - 2;
+	len = strlen(zynqmp_devices[i].name) - 2U;
 	for (j = 0; j < strlen(name); j++) {
 		zynqmp_devices[i].name[len] = name[j];
 		len++;
@@ -326,13 +326,14 @@
 {
 	uint32_t chip_id = zynqmp_get_silicon_ver();
 	uint32_t manfid = SOC_ID_SET_JEP_106(JEDEC_XILINX_BKID, JEDEC_XILINX_MFID);
+	uint32_t result = (manfid | (chip_id & 0xFFFFU));
 
-	return (int32_t)(manfid | (chip_id & 0xFFFF));
+	return (int32_t)result;
 }
 
 int32_t plat_get_soc_revision(void)
 {
-	return mmio_read_32(ZYNQMP_CSU_BASEADDR + ZYNQMP_CSU_IDCODE_OFFSET);
+	return (int32_t)mmio_read_32(ZYNQMP_CSU_BASEADDR + ZYNQMP_CSU_IDCODE_OFFSET);
 }
 
 static uint32_t zynqmp_get_ps_ver(void)
@@ -366,7 +367,7 @@
 	VERBOSE("TF-A running on %s/%s at 0x%x\n",
 		zynqmp_print_silicon_idcode(), label, BL31_BASE);
 	VERBOSE("TF-A running on v%d/RTL%d.%d\n",
-	       zynqmp_get_ps_ver(), (rtl & 0xf0) >> 4, rtl & 0xf);
+	       zynqmp_get_ps_ver(), (rtl & 0xf0U) >> 4U, rtl & 0xfU);
 }
 #else
 static inline void zynqmp_print_platform_name(void) { }
@@ -375,7 +376,7 @@
 uint32_t zynqmp_get_bootmode(void)
 {
 	uint32_t r;
-	unsigned int ret;
+	enum pm_ret_status ret;
 
 	ret = pm_mmio_read(CRL_APB_BOOT_MODE_USER, &r);
 
@@ -411,6 +412,6 @@
 	if (ver == ZYNQMP_CSU_VERSION_QEMU) {
 		return 65000000;
 	} else {
-		return mmio_read_32(IOU_SCNTRS_BASEFREQ);
+		return mmio_read_32((uint64_t)IOU_SCNTRS_BASEFREQ);
 	}
 }
diff --git a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
index ede3a21..77fbb58 100644
--- a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
+++ b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
@@ -59,7 +59,7 @@
 	bl32_image_ep_info.pc = BL32_BASE;
 	bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry();
 	bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
-	bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX,
+	bl33_image_ep_info.spsr = (uint32_t)SPSR_64(MODE_EL2, MODE_SP_ELX,
 					  DISABLE_ALL_EXCEPTIONS);
 }
 
@@ -96,7 +96,7 @@
 	SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0);
 	SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
 
-	tfa_handoff_addr = mmio_read_32(PMU_GLOBAL_GEN_STORAGE6);
+	tfa_handoff_addr = (uint64_t)mmio_read_32(PMU_GLOBAL_GEN_STORAGE6);
 
 	if (zynqmp_get_bootmode() == ZYNQMP_BOOTMODE_JTAG) {
 		bl31_set_default_config();
@@ -109,10 +109,10 @@
 			panic();
 		}
 	}
-	if (bl32_image_ep_info.pc != 0) {
+	if (bl32_image_ep_info.pc != 0U) {
 		NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc);
 	}
-	if (bl33_image_ep_info.pc != 0) {
+	if (bl33_image_ep_info.pc != 0U) {
 		NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc);
 	}
 
diff --git a/plat/xilinx/zynqmp/include/zynqmp_def.h b/plat/xilinx/zynqmp/include/zynqmp_def.h
index 68485cf..cd3bbbc 100644
--- a/plat/xilinx/zynqmp/include/zynqmp_def.h
+++ b/plat/xilinx/zynqmp/include/zynqmp_def.h
@@ -60,9 +60,9 @@
 
 /* CRL registers and bitfields */
 #define CRL_APB_BASE			U(0xFF5E0000)
-#define CRL_APB_BOOT_MODE_USER		(CRL_APB_BASE + 0x200)
-#define CRL_APB_RESET_CTRL		(CRL_APB_BASE + 0x218)
-#define CRL_APB_RST_LPD_TOP		(CRL_APB_BASE + 0x23C)
+#define CRL_APB_BOOT_MODE_USER		(CRL_APB_BASE + U(0x200))
+#define CRL_APB_RESET_CTRL		(CRL_APB_BASE + U(0x218))
+#define CRL_APB_RST_LPD_TOP		(CRL_APB_BASE + U(0x23C))
 #define CRL_APB_BOOT_PIN_CTRL		(CRL_APB_BASE + U(0x250))
 #define CRL_APB_CLK_BASE		U(0xFF5E0020)
 
@@ -75,18 +75,15 @@
 #define CRL_APB_BOOT_PIN_MASK		(U(0xf0f) << 0)
 #define CRL_APB_BOOT_DRIVE_PIN_1_SHIFT	U(9)
 #define CRL_APB_BOOT_ENABLE_PIN_1_SHIFT	U(1)
-#define CRL_APB_BOOT_ENABLE_PIN_1	(U(0x1) << \
-					CRL_APB_BOOT_ENABLE_PIN_1_SHIFT)
-#define CRL_APB_BOOT_DRIVE_PIN_1	(U(0x1) << \
-					CRL_APB_BOOT_DRIVE_PIN_1_SHIFT)
+#define CRL_APB_BOOT_ENABLE_PIN_1	(U(0x1) << CRL_APB_BOOT_ENABLE_PIN_1_SHIFT)
+#define CRL_APB_BOOT_DRIVE_PIN_1	(U(0x1) << CRL_APB_BOOT_DRIVE_PIN_1_SHIFT)
 #define ZYNQMP_BOOTMODE_JTAG		U(0)
-#define ZYNQMP_ULPI_RESET_VAL_HIGH	(CRL_APB_BOOT_ENABLE_PIN_1 | \
-					 CRL_APB_BOOT_DRIVE_PIN_1)
+#define ZYNQMP_ULPI_RESET_VAL_HIGH	(CRL_APB_BOOT_ENABLE_PIN_1 | CRL_APB_BOOT_DRIVE_PIN_1)
 #define ZYNQMP_ULPI_RESET_VAL_LOW	CRL_APB_BOOT_ENABLE_PIN_1
 
 /* system counter registers and bitfields */
 #define IOU_SCNTRS_BASE			U(0xFF260000)
-#define IOU_SCNTRS_BASEFREQ		(IOU_SCNTRS_BASE + 0x20)
+#define IOU_SCNTRS_BASEFREQ		(IOU_SCNTRS_BASE + U(0x20))
 
 /* APU registers and bitfields */
 #define APU_BASE		U(0xFD5C0000)
@@ -104,11 +101,11 @@
 /* PMU registers and bitfields */
 #define PMU_GLOBAL_BASE			U(0xFFD80000)
 #define PMU_GLOBAL_CNTRL		(PMU_GLOBAL_BASE + 0)
-#define PMU_GLOBAL_GEN_STORAGE6		(PMU_GLOBAL_BASE + 0x48)
-#define PMU_GLOBAL_REQ_PWRUP_STATUS	(PMU_GLOBAL_BASE + 0x110)
-#define PMU_GLOBAL_REQ_PWRUP_EN		(PMU_GLOBAL_BASE + 0x118)
-#define PMU_GLOBAL_REQ_PWRUP_DIS	(PMU_GLOBAL_BASE + 0x11c)
-#define PMU_GLOBAL_REQ_PWRUP_TRIG	(PMU_GLOBAL_BASE + 0x120)
+#define PMU_GLOBAL_GEN_STORAGE6		(PMU_GLOBAL_BASE + U(0x48))
+#define PMU_GLOBAL_REQ_PWRUP_STATUS	(PMU_GLOBAL_BASE + U(0x110))
+#define PMU_GLOBAL_REQ_PWRUP_EN		(PMU_GLOBAL_BASE + U(0x118))
+#define PMU_GLOBAL_REQ_PWRUP_DIS	(PMU_GLOBAL_BASE + U(0x11c))
+#define PMU_GLOBAL_REQ_PWRUP_TRIG	(PMU_GLOBAL_BASE + U(0x120))
 
 #define PMU_GLOBAL_CNTRL_FW_IS_PRESENT	(1 << 4)
 
@@ -191,10 +188,10 @@
 #define UART_BAUDRATE		115200
 
 /* Silicon version detection */
-#define ZYNQMP_SILICON_VER_MASK		0xF000
+#define ZYNQMP_SILICON_VER_MASK		U(0xF000)
 #define ZYNQMP_SILICON_VER_SHIFT	12
 #define ZYNQMP_CSU_VERSION_SILICON	0
-#define ZYNQMP_CSU_VERSION_QEMU		3
+#define ZYNQMP_CSU_VERSION_QEMU		U(3)
 
 #define ZYNQMP_RTL_VER_MASK		0xFF0U
 #define ZYNQMP_RTL_VER_SHIFT		4
@@ -203,38 +200,32 @@
 #define ZYNQMP_PS_VER_SHIFT		0
 
 #define ZYNQMP_CSU_BASEADDR		U(0xFFCA0000)
-#define ZYNQMP_CSU_IDCODE_OFFSET	0x40U
+#define ZYNQMP_CSU_IDCODE_OFFSET	U(0x40)
 
-#define ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT	0U
-#define ZYNQMP_CSU_IDCODE_XILINX_ID_MASK	(0xFFFU << \
-					ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT)
-#define ZYNQMP_CSU_IDCODE_XILINX_ID		0x093
+#define ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT	U(0)
+#define ZYNQMP_CSU_IDCODE_XILINX_ID_MASK	(U(0xFFF) << ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT)
+#define ZYNQMP_CSU_IDCODE_XILINX_ID		U(0x093)
 
-#define ZYNQMP_CSU_IDCODE_SVD_SHIFT		12U
-#define ZYNQMP_CSU_IDCODE_SVD_MASK		(0x7U << \
-						 ZYNQMP_CSU_IDCODE_SVD_SHIFT)
-#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT	15U
-#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK	(0xFU << \
-					ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT)
-#define ZYNQMP_CSU_IDCODE_SUB_FAMILY_SHIFT	19U
-#define ZYNQMP_CSU_IDCODE_SUB_FAMILY_MASK	(0x3U << \
-					ZYNQMP_CSU_IDCODE_SUB_FAMILY_SHIFT)
-#define ZYNQMP_CSU_IDCODE_FAMILY_SHIFT		21U
-#define ZYNQMP_CSU_IDCODE_FAMILY_MASK		(0x7FU << \
-					ZYNQMP_CSU_IDCODE_FAMILY_SHIFT)
-#define ZYNQMP_CSU_IDCODE_FAMILY		0x23
+#define ZYNQMP_CSU_IDCODE_SVD_SHIFT		U(12)
+#define ZYNQMP_CSU_IDCODE_SVD_MASK		(0x7U << ZYNQMP_CSU_IDCODE_SVD_SHIFT)
+#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT	U(15)
+#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK	(U(0xF) << ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT)
+#define ZYNQMP_CSU_IDCODE_SUB_FAMILY_SHIFT	U(19)
+#define ZYNQMP_CSU_IDCODE_SUB_FAMILY_MASK	(U(0x3) << ZYNQMP_CSU_IDCODE_SUB_FAMILY_SHIFT)
+#define ZYNQMP_CSU_IDCODE_FAMILY_SHIFT		U(21)
+#define ZYNQMP_CSU_IDCODE_FAMILY_MASK		(U(0x7F) << ZYNQMP_CSU_IDCODE_FAMILY_SHIFT)
+#define ZYNQMP_CSU_IDCODE_FAMILY		U(0x23)
 
-#define ZYNQMP_CSU_IDCODE_REVISION_SHIFT	28U
-#define ZYNQMP_CSU_IDCODE_REVISION_MASK		(0xFU << \
-					ZYNQMP_CSU_IDCODE_REVISION_SHIFT)
-#define ZYNQMP_CSU_IDCODE_REVISION		0U
+#define ZYNQMP_CSU_IDCODE_REVISION_SHIFT	U(28)
+#define ZYNQMP_CSU_IDCODE_REVISION_MASK		(U(0xF) << ZYNQMP_CSU_IDCODE_REVISION_SHIFT)
+#define ZYNQMP_CSU_IDCODE_REVISION		U(0)
 
-#define ZYNQMP_CSU_VERSION_OFFSET	0x44U
+#define ZYNQMP_CSU_VERSION_OFFSET	U(0x44)
 
 /* Efuse */
 #define EFUSE_BASEADDR		U(0xFFCC0000)
 #define EFUSE_IPDISABLE_OFFSET	0x1018
-#define EFUSE_IPDISABLE_VERSION	0x1FFU
+#define EFUSE_IPDISABLE_VERSION	U(0x1FF)
 #define ZYNQMP_EFUSE_IPDISABLE_SHIFT	20
 
 /* Access control register defines */
@@ -356,11 +347,11 @@
 #define IOU_SLCR_WDT_CLK_SEL		(IOU_SLCR_BASEADDR + 0x300)
 
 /* Global general storage register base address */
-#define GGS_BASEADDR		(0xFFD80030U)
+#define GGS_BASEADDR		U(0xFFD80030)
 #define GGS_NUM_REGS		U(4)
 
 /* Persistent global general storage register base address */
-#define PGGS_BASEADDR		(0xFFD80050U)
+#define PGGS_BASEADDR		U(0xFFD80050)
 #define PGGS_NUM_REGS		U(4)
 
 /* PMU GGS4 register 4 is used for warm restart boot health status */
@@ -369,7 +360,7 @@
 #define PM_BOOT_HEALTH_STATUS_MASK		U(0x01)
 /* WDT restart scope shift and mask */
 #define RESTART_SCOPE_SHIFT			(3)
-#define RESTART_SCOPE_MASK			(0x3U << RESTART_SCOPE_SHIFT)
+#define RESTART_SCOPE_MASK			(U(0x3) << RESTART_SCOPE_SHIFT)
 
 /* AFI registers */
 #define  AFIFM6_WRCTRL		U(13)
diff --git a/plat/xilinx/zynqmp/plat_psci.c b/plat/xilinx/zynqmp/plat_psci.c
index 58db2e4..a619359 100644
--- a/plat/xilinx/zynqmp/plat_psci.c
+++ b/plat/xilinx/zynqmp/plat_psci.c
@@ -32,7 +32,7 @@
 
 static int32_t zynqmp_pwr_domain_on(u_register_t mpidr)
 {
-	uint32_t cpu_id = plat_core_pos_by_mpidr(mpidr);
+	int32_t cpu_id = plat_core_pos_by_mpidr(mpidr);
 	const struct pm_proc *proc;
 	uint32_t buff[3];
 	enum pm_ret_status ret;
diff --git a/plat/xilinx/zynqmp/plat_zynqmp.c b/plat/xilinx/zynqmp/plat_zynqmp.c
index 65faa2f..e7c0378 100644
--- a/plat/xilinx/zynqmp/plat_zynqmp.c
+++ b/plat/xilinx/zynqmp/plat_zynqmp.c
@@ -18,5 +18,5 @@
 		return -1;
 	}
 
-	return zynqmp_calc_core_pos(mpidr);
+	return (int32_t)zynqmp_calc_core_pos(mpidr);
 }
diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_clock.c b/plat/xilinx/zynqmp/pm_service/pm_api_clock.c
index 91adb07..dbc5f13 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_api_clock.c
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_clock.c
@@ -110,8 +110,8 @@
 		.type = TYPE_MUX,			\
 		.offset = PERIPH_MUX_SHIFT,		\
 		.width = PERIPH_MUX_WIDTH,		\
-		.clkflags = CLK_SET_RATE_NO_REPARENT |	\
-			    CLK_IS_BASIC,		\
+		.clkflags = (uint16_t)(CLK_SET_RATE_NO_REPARENT |\
+			    CLK_IS_BASIC),		\
 		.typeflags = NA_TYPE_FLAGS,		\
 		.mult = NA_MULT,			\
 		.div = NA_DIV,				\
@@ -122,9 +122,9 @@
 		.type = TYPE_MUX,			\
 		.offset = PERIPH_MUX_SHIFT,		\
 		.width = PERIPH_MUX_WIDTH,		\
-		.clkflags = CLK_IGNORE_UNUSED |		\
+		.clkflags = (uint16_t)(CLK_IGNORE_UNUSED |\
 			    CLK_SET_RATE_NO_REPARENT |	\
-			    CLK_IS_BASIC,		\
+			    CLK_IS_BASIC),		\
 		.typeflags = NA_TYPE_FLAGS,		\
 		.mult = NA_MULT,			\
 		.div = NA_DIV,				\
@@ -135,10 +135,10 @@
 		.type = TYPE_DIV1,				\
 		.offset = PERIPH_DIV1_SHIFT,			\
 		.width = PERIPH_DIV1_WIDTH,			\
-		.clkflags = CLK_SET_RATE_NO_REPARENT |		\
-			    CLK_IS_BASIC,			\
-		.typeflags = CLK_DIVIDER_ONE_BASED |		\
-			     CLK_DIVIDER_ALLOW_ZERO,		\
+		.clkflags = (uint16_t)(CLK_SET_RATE_NO_REPARENT |\
+			    CLK_IS_BASIC),			\
+		.typeflags = (uint16_t)(CLK_DIVIDER_ONE_BASED |	\
+			     CLK_DIVIDER_ALLOW_ZERO),		\
 		.mult = NA_MULT,				\
 		.div = NA_DIV,					\
 	}
@@ -148,11 +148,11 @@
 		.type = TYPE_DIV2,				\
 		.offset = PERIPH_DIV2_SHIFT,			\
 		.width = PERIPH_DIV2_WIDTH,			\
-		.clkflags = CLK_SET_RATE_NO_REPARENT |		\
+		.clkflags = (uint16_t)(CLK_SET_RATE_NO_REPARENT |\
 			    CLK_SET_RATE_PARENT |		\
-			    CLK_IS_BASIC,			\
-		.typeflags = CLK_DIVIDER_ONE_BASED |		\
-			     CLK_DIVIDER_ALLOW_ZERO,		\
+			    CLK_IS_BASIC),			\
+		.typeflags = (uint16_t)(CLK_DIVIDER_ONE_BASED |	\
+			     CLK_DIVIDER_ALLOW_ZERO),		\
 		.mult = NA_MULT,				\
 		.div = NA_DIV,					\
 	}
@@ -162,11 +162,11 @@
 		.type = TYPE_DIV##id,				\
 		.offset = PERIPH_DIV##id##_SHIFT,		\
 		.width = PERIPH_DIV##id##_WIDTH,		\
-		.clkflags = CLK_IGNORE_UNUSED |			\
+		.clkflags = (uint16_t)(CLK_IGNORE_UNUSED |	\
 			    CLK_SET_RATE_NO_REPARENT |		\
-			    CLK_IS_BASIC,			\
-		.typeflags = CLK_DIVIDER_ONE_BASED |		\
-			     CLK_DIVIDER_ALLOW_ZERO,		\
+			    CLK_IS_BASIC),			\
+		.typeflags = (uint16_t)(CLK_DIVIDER_ONE_BASED |	\
+			     CLK_DIVIDER_ALLOW_ZERO),		\
 		.mult = NA_MULT,				\
 		.div = NA_DIV,					\
 	}
@@ -176,9 +176,9 @@
 		.type = TYPE_GATE,				\
 		.offset = PERIPH_GATE_SHIFT,			\
 		.width = PERIPH_GATE_WIDTH,			\
-		.clkflags = CLK_SET_RATE_PARENT |		\
+		.clkflags = (uint16_t)(CLK_SET_RATE_PARENT |	\
 			    CLK_SET_RATE_GATE |			\
-			    CLK_IS_BASIC,			\
+			    CLK_IS_BASIC),			\
 		.typeflags = NA_TYPE_FLAGS,			\
 		.mult = NA_MULT,				\
 		.div = NA_DIV,					\
@@ -189,9 +189,9 @@
 		.type = TYPE_GATE,				\
 		.offset = PERIPH_GATE_SHIFT,			\
 		.width = PERIPH_GATE_WIDTH,			\
-		.clkflags = CLK_SET_RATE_PARENT |		\
+		.clkflags = (uint16_t)(CLK_SET_RATE_PARENT |	\
 			    CLK_IGNORE_UNUSED |			\
-			    CLK_IS_BASIC,			\
+			    CLK_IS_BASIC),			\
 		.typeflags = NA_TYPE_FLAGS,			\
 		.mult = NA_MULT,				\
 		.div = NA_DIV,					\
@@ -253,7 +253,7 @@
 		.type = TYPE_PLL,
 		.offset = NA_SHIFT,
 		.width = NA_WIDTH,
-		.clkflags = CLK_SET_RATE_NO_REPARENT,
+		.clkflags = (uint16_t)CLK_SET_RATE_NO_REPARENT,
 		.typeflags = NA_TYPE_FLAGS,
 		.mult = NA_MULT,
 		.div = NA_DIV,
@@ -265,7 +265,7 @@
 		.type = TYPE_PLL,
 		.offset = NA_SHIFT,
 		.width = NA_WIDTH,
-		.clkflags = CLK_IGNORE_UNUSED | CLK_SET_RATE_NO_REPARENT,
+		.clkflags = (uint16_t)(CLK_IGNORE_UNUSED | CLK_SET_RATE_NO_REPARENT),
 		.typeflags = NA_TYPE_FLAGS,
 		.mult = NA_MULT,
 		.div = NA_DIV,
@@ -277,7 +277,7 @@
 		.type = TYPE_MUX,
 		.offset = PLL_PRESRC_MUX_SHIFT,
 		.width = PLL_PRESRC_MUX_WIDTH,
-		.clkflags = CLK_IS_BASIC,
+		.clkflags = (uint16_t)CLK_IS_BASIC,
 		.typeflags = NA_TYPE_FLAGS,
 		.mult = NA_MULT,
 		.div = NA_DIV,
@@ -289,7 +289,7 @@
 		.type = TYPE_FIXEDFACTOR,
 		.offset = NA_SHIFT,
 		.width = NA_WIDTH,
-		.clkflags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
+		.clkflags = (uint16_t)(CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT),
 		.typeflags = NA_TYPE_FLAGS,
 		.mult = 1,
 		.div = 2,
@@ -301,9 +301,9 @@
 		.type = TYPE_MUX,
 		.offset = PLL_DIV2_MUX_SHIFT,
 		.width =  PLL_DIV2_MUX_WIDTH,
-		.clkflags = CLK_SET_RATE_NO_REPARENT |
+		.clkflags = (uint16_t)(CLK_SET_RATE_NO_REPARENT |
 			    CLK_SET_RATE_PARENT |
-			    CLK_IS_BASIC,
+			    CLK_IS_BASIC),
 		.typeflags = NA_TYPE_FLAGS,
 		.mult = NA_MULT,
 		.div = NA_DIV,
@@ -315,7 +315,7 @@
 		.type = TYPE_MUX,
 		.offset = PLL_POSTSRC_MUX_SHIFT,
 		.width = PLL_POSTSRC_MUX_WIDTH,
-		.clkflags = CLK_IS_BASIC,
+		.clkflags = (uint16_t)CLK_IS_BASIC,
 		.typeflags = NA_TYPE_FLAGS,
 		.mult = NA_MULT,
 		.div = NA_DIV,
@@ -327,9 +327,9 @@
 		.type = TYPE_MUX,
 		.offset = PLL_BYPASS_MUX_SHIFT,
 		.width = PLL_BYPASS_MUX_WIDTH,
-		.clkflags = CLK_SET_RATE_NO_REPARENT |
+		.clkflags = (uint16_t)(CLK_SET_RATE_NO_REPARENT |
 			    CLK_SET_RATE_PARENT |
-			    CLK_IS_BASIC,
+			    CLK_IS_BASIC),
 		.typeflags = NA_TYPE_FLAGS,
 		.mult = NA_MULT,
 		.div = NA_DIV,
@@ -341,7 +341,7 @@
 		.type = TYPE_MUX,
 		.offset = PERIPH_MUX_SHIFT,
 		.width = PERIPH_MUX_WIDTH,
-		.clkflags = CLK_SET_RATE_NO_REPARENT | CLK_IS_BASIC,
+		.clkflags = (uint16_t)(CLK_SET_RATE_NO_REPARENT | CLK_IS_BASIC),
 		.typeflags = NA_TYPE_FLAGS,
 		.mult = NA_MULT,
 		.div = NA_DIV,
@@ -350,8 +350,8 @@
 		.type = TYPE_DIV1,
 		.offset = PERIPH_DIV1_SHIFT,
 		.width = PERIPH_DIV1_WIDTH,
-		.clkflags = CLK_IS_BASIC,
-		.typeflags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
+		.clkflags = (uint16_t)CLK_IS_BASIC,
+		.typeflags = (uint16_t)(CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO),
 		.mult = NA_MULT,
 		.div = NA_DIV,
 	},
@@ -386,9 +386,9 @@
 		.type = TYPE_MUX,
 		.offset = PERIPH_MUX_SHIFT,
 		.width = PERIPH_MUX_WIDTH,
-		.clkflags = CLK_SET_RATE_NO_REPARENT |
-			    CLK_SET_RATE_PARENT | CLK_IS_BASIC,
-		.typeflags = CLK_FRAC,
+		.clkflags = (uint16_t)(CLK_SET_RATE_NO_REPARENT |
+			    CLK_SET_RATE_PARENT | CLK_IS_BASIC),
+		.typeflags = (uint16_t)CLK_FRAC,
 		.mult = NA_MULT,
 		.div = NA_DIV,
 	},
@@ -396,10 +396,10 @@
 		.type = TYPE_DIV1,
 		.offset = PERIPH_DIV1_SHIFT,
 		.width = PERIPH_DIV1_WIDTH,
-		.clkflags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT |
-			    CLK_IS_BASIC,
-		.typeflags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO |
-			     CLK_FRAC,
+		.clkflags = (uint16_t)(CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT |
+			    CLK_IS_BASIC),
+		.typeflags = (uint16_t)(CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO |
+			     CLK_FRAC),
 		.mult = NA_MULT,
 		.div = NA_DIV,
 	},
@@ -407,10 +407,10 @@
 		.type = TYPE_DIV2,
 		.offset = PERIPH_DIV2_SHIFT,
 		.width = PERIPH_DIV2_WIDTH,
-		.clkflags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT |
-			    CLK_IS_BASIC,
-		.typeflags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO |
-			     CLK_FRAC,
+		.clkflags = (uint16_t)(CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT |
+			    CLK_IS_BASIC),
+		.typeflags = (uint16_t)(CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO |
+			     CLK_FRAC),
 		.mult = NA_MULT,
 		.div = NA_DIV,
 	},
@@ -418,9 +418,9 @@
 		.type = TYPE_GATE,
 		.offset = PERIPH_GATE_SHIFT,
 		.width = PERIPH_GATE_WIDTH,
-		.clkflags = CLK_SET_RATE_PARENT |
+		.clkflags = (uint16_t)(CLK_SET_RATE_PARENT |
 			    CLK_SET_RATE_GATE |
-			    CLK_IS_BASIC,
+			    CLK_IS_BASIC),
 		.typeflags = NA_TYPE_FLAGS,
 		.mult = NA_MULT,
 		.div = NA_DIV,
@@ -435,8 +435,8 @@
 		.type = TYPE_GATE,
 		.offset = USB_GATE_SHIFT,
 		.width = PERIPH_GATE_WIDTH,
-		.clkflags = CLK_SET_RATE_PARENT | CLK_IS_BASIC |
-			    CLK_SET_RATE_GATE,
+		.clkflags = (uint16_t)(CLK_SET_RATE_PARENT | CLK_IS_BASIC |
+			    CLK_SET_RATE_GATE),
 		.typeflags = NA_TYPE_FLAGS,
 		.mult = NA_MULT,
 		.div = NA_DIV,
@@ -448,8 +448,8 @@
 		.type = TYPE_DIV1,
 		.offset = 8,
 		.width = 6,
-		.clkflags = CLK_IS_BASIC,
-		.typeflags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
+		.clkflags = (uint16_t)CLK_IS_BASIC,
+		.typeflags = (uint16_t)(CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO),
 		.mult = NA_MULT,
 		.div = NA_DIV,
 	},
@@ -460,8 +460,8 @@
 		.type = TYPE_DIV1,
 		.offset = 8,
 		.width = 6,
-		.clkflags = CLK_SET_RATE_PARENT | CLK_IS_BASIC,
-		.typeflags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
+		.clkflags = (uint16_t)(CLK_SET_RATE_PARENT | CLK_IS_BASIC),
+		.typeflags = (uint16_t)(CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO),
 		.mult = NA_MULT,
 		.div = NA_DIV,
 	},
@@ -481,9 +481,9 @@
 		.type = TYPE_GATE,
 		.offset = 25,
 		.width = PERIPH_GATE_WIDTH,
-		.clkflags = CLK_IGNORE_UNUSED |
+		.clkflags = (uint16_t)(CLK_IGNORE_UNUSED |
 			    CLK_SET_RATE_PARENT |
-			    CLK_IS_BASIC,
+			    CLK_IS_BASIC),
 		.typeflags = NA_TYPE_FLAGS,
 		.mult = NA_MULT,
 		.div = NA_DIV,
@@ -495,9 +495,9 @@
 		.type = TYPE_GATE,
 		.offset = 24,
 		.width = PERIPH_GATE_WIDTH,
-		.clkflags = CLK_IGNORE_UNUSED |
+		.clkflags = (uint16_t)(CLK_IGNORE_UNUSED |
 			    CLK_SET_RATE_PARENT |
-			    CLK_IS_BASIC,
+			    CLK_IS_BASIC),
 		.typeflags = NA_TYPE_FLAGS,
 		.mult = NA_MULT,
 		.div = NA_DIV,
@@ -509,9 +509,9 @@
 		.type = TYPE_MUX,
 		.offset = 0,
 		.width = 1,
-		.clkflags = CLK_SET_RATE_PARENT |
+		.clkflags = (uint16_t)(CLK_SET_RATE_PARENT |
 			    CLK_SET_RATE_NO_REPARENT |
-			    CLK_IS_BASIC,
+			    CLK_IS_BASIC),
 		.typeflags = NA_TYPE_FLAGS,
 		.mult = NA_MULT,
 		.div = NA_DIV,
@@ -524,8 +524,8 @@
 		.type = TYPE_DIV1,
 		.offset = 8,
 		.width = 6,
-		.clkflags = CLK_IS_BASIC | CLK_IS_CRITICAL,
-		.typeflags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
+		.clkflags = (uint16_t)(CLK_IS_BASIC | CLK_IS_CRITICAL),
+		.typeflags = (uint16_t)(CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO),
 		.mult = NA_MULT,
 		.div = NA_DIV,
 	},
@@ -537,8 +537,8 @@
 		.type = TYPE_DIV1,
 		.offset = PERIPH_DIV1_SHIFT,
 		.width = PERIPH_DIV1_WIDTH,
-		.clkflags = CLK_IS_BASIC,
-		.typeflags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
+		.clkflags = (uint16_t)(CLK_IS_BASIC),
+		.typeflags = (uint16_t)(CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO),
 		.mult = NA_MULT,
 		.div = NA_DIV,
 	},
@@ -546,8 +546,8 @@
 		.type = TYPE_DIV2,
 		.offset = PERIPH_DIV2_SHIFT,
 		.width = PERIPH_DIV2_WIDTH,
-		.clkflags = CLK_IS_BASIC | CLK_SET_RATE_PARENT,
-		.typeflags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
+		.clkflags = (uint16_t)(CLK_IS_BASIC | CLK_SET_RATE_PARENT),
+		.typeflags = (uint16_t)(CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO),
 		.mult = NA_MULT,
 		.div = NA_DIV,
 	},
@@ -555,7 +555,7 @@
 		.type = TYPE_GATE,
 		.offset = PERIPH_GATE_SHIFT,
 		.width = PERIPH_GATE_WIDTH,
-		.clkflags = CLK_SET_RATE_PARENT | CLK_IS_BASIC,
+		.clkflags = (uint16_t)(CLK_SET_RATE_PARENT | CLK_IS_BASIC),
 		.typeflags = NA_TYPE_FLAGS,
 		.mult = NA_MULT,
 		.div = NA_DIV,
@@ -567,7 +567,7 @@
 		.type = TYPE_GATE,
 		.offset = 25,
 		.width = PERIPH_GATE_WIDTH,
-		.clkflags = CLK_SET_RATE_PARENT | CLK_IS_BASIC,
+		.clkflags = (uint16_t)(CLK_SET_RATE_PARENT | CLK_IS_BASIC),
 		.typeflags = NA_TYPE_FLAGS,
 		.mult = NA_MULT,
 		.div = NA_DIV,
@@ -579,7 +579,7 @@
 		.type = TYPE_GATE,
 		.offset = 26,
 		.width = PERIPH_GATE_WIDTH,
-		.clkflags = CLK_SET_RATE_PARENT | CLK_IS_BASIC,
+		.clkflags = (uint16_t)(CLK_SET_RATE_PARENT | CLK_IS_BASIC),
 		.typeflags = NA_TYPE_FLAGS,
 		.mult = NA_MULT,
 		.div = NA_DIV,
@@ -592,8 +592,8 @@
 		.type = TYPE_DIV1,
 		.offset = 8,
 		.width = 6,
-		.clkflags = CLK_SET_RATE_NO_REPARENT | CLK_IS_BASIC,
-		.typeflags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
+		.clkflags = (uint16_t)(CLK_SET_RATE_NO_REPARENT | CLK_IS_BASIC),
+		.typeflags = (uint16_t)(CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO),
 		.mult = NA_MULT,
 		.div = NA_DIV,
 	},
@@ -601,9 +601,9 @@
 		.type = TYPE_DIV2,
 		.offset = 16,
 		.width = 6,
-		.clkflags = CLK_SET_RATE_NO_REPARENT | CLK_IS_BASIC |
-			    CLK_SET_RATE_PARENT,
-		.typeflags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
+		.clkflags = (uint16_t)(CLK_SET_RATE_NO_REPARENT | CLK_IS_BASIC |
+			    CLK_SET_RATE_PARENT),
+		.typeflags = (uint16_t)(CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO),
 		.mult = NA_MULT,
 		.div = NA_DIV,
 	},
@@ -614,9 +614,9 @@
 		.type = TYPE_MUX,
 		.offset = 1,
 		.width = 1,
-		.clkflags = CLK_SET_RATE_PARENT |
+		.clkflags = (uint16_t)(CLK_SET_RATE_PARENT |
 			    CLK_SET_RATE_NO_REPARENT |
-			    CLK_IS_BASIC,
+			    CLK_IS_BASIC),
 		.typeflags = NA_TYPE_FLAGS,
 		.mult = NA_MULT,
 		.div = NA_DIV,
@@ -628,9 +628,9 @@
 		.type = TYPE_MUX,
 		.offset = 6,
 		.width = 1,
-		.clkflags = CLK_SET_RATE_PARENT |
+		.clkflags = (uint16_t)(CLK_SET_RATE_PARENT |
 			    CLK_SET_RATE_NO_REPARENT |
-			    CLK_IS_BASIC,
+			    CLK_IS_BASIC),
 		.typeflags = NA_TYPE_FLAGS,
 		.mult = NA_MULT,
 		.div = NA_DIV,
@@ -642,9 +642,9 @@
 		.type = TYPE_MUX,
 		.offset = 11,
 		.width = 1,
-		.clkflags = CLK_SET_RATE_PARENT |
+		.clkflags = (uint16_t)(CLK_SET_RATE_PARENT |
 			    CLK_SET_RATE_NO_REPARENT |
-			    CLK_IS_BASIC,
+			    CLK_IS_BASIC),
 		.typeflags = NA_TYPE_FLAGS,
 		.mult = NA_MULT,
 		.div = NA_DIV,
@@ -656,9 +656,9 @@
 		.type = TYPE_MUX,
 		.offset = 16,
 		.width = 1,
-		.clkflags = CLK_SET_RATE_PARENT |
+		.clkflags = (uint16_t)(CLK_SET_RATE_PARENT |
 			    CLK_SET_RATE_NO_REPARENT |
-			    CLK_IS_BASIC,
+			    CLK_IS_BASIC),
 		.typeflags = NA_TYPE_FLAGS,
 		.mult = NA_MULT,
 		.div = NA_DIV,
@@ -670,7 +670,7 @@
 		.type = TYPE_GATE,
 		.offset = 25,
 		.width = PERIPH_GATE_WIDTH,
-		.clkflags = CLK_SET_RATE_PARENT | CLK_IS_BASIC,
+		.clkflags = (uint16_t)(CLK_SET_RATE_PARENT | CLK_IS_BASIC),
 		.typeflags = NA_TYPE_FLAGS,
 		.mult = NA_MULT,
 		.div = NA_DIV,
@@ -682,7 +682,7 @@
 		.type = TYPE_GATE,
 		.offset = 26,
 		.width = PERIPH_GATE_WIDTH,
-		.clkflags = CLK_IS_BASIC,
+		.clkflags = (uint16_t)(CLK_IS_BASIC),
 		.typeflags = NA_TYPE_FLAGS,
 		.mult = NA_MULT,
 		.div = NA_DIV,
@@ -694,9 +694,9 @@
 		.type = TYPE_MUX,
 		.offset = 20,
 		.width = 2,
-		.clkflags = CLK_SET_RATE_PARENT |
+		.clkflags = (uint16_t)(CLK_SET_RATE_PARENT |
 			    CLK_SET_RATE_NO_REPARENT |
-			    CLK_IS_BASIC,
+			    CLK_IS_BASIC),
 		.typeflags = NA_TYPE_FLAGS,
 		.mult = NA_MULT,
 		.div = NA_DIV,
@@ -708,9 +708,9 @@
 		.type = TYPE_MUX,
 		.offset = 0,
 		.width = 7,
-		.clkflags = CLK_SET_RATE_PARENT |
+		.clkflags = (uint16_t)(CLK_SET_RATE_PARENT |
 			    CLK_SET_RATE_NO_REPARENT |
-			    CLK_IS_BASIC,
+			    CLK_IS_BASIC),
 		.typeflags = NA_TYPE_FLAGS,
 		.mult = NA_MULT,
 		.div = NA_DIV,
@@ -722,9 +722,9 @@
 		.type = TYPE_MUX,
 		.offset = 15,
 		.width = 1,
-		.clkflags = CLK_SET_RATE_PARENT |
+		.clkflags = (uint16_t)(CLK_SET_RATE_PARENT |
 			    CLK_SET_RATE_NO_REPARENT |
-			    CLK_IS_BASIC,
+			    CLK_IS_BASIC),
 		.typeflags = NA_TYPE_FLAGS,
 		.mult = NA_MULT,
 		.div = NA_DIV,
@@ -736,9 +736,9 @@
 		.type = TYPE_MUX,
 		.offset = 7,
 		.width = 1,
-		.clkflags = CLK_SET_RATE_PARENT |
+		.clkflags = (uint16_t)(CLK_SET_RATE_PARENT |
 			    CLK_SET_RATE_NO_REPARENT |
-			    CLK_IS_BASIC,
+			    CLK_IS_BASIC),
 		.typeflags = NA_TYPE_FLAGS,
 		.mult = NA_MULT,
 		.div = NA_DIV,
@@ -750,9 +750,9 @@
 		.type = TYPE_MUX,
 		.offset = 22,
 		.width = 1,
-		.clkflags = CLK_SET_RATE_PARENT |
+		.clkflags = (uint16_t)(CLK_SET_RATE_PARENT |
 			    CLK_SET_RATE_NO_REPARENT |
-			    CLK_IS_BASIC,
+			    CLK_IS_BASIC),
 		.typeflags = NA_TYPE_FLAGS,
 		.mult = NA_MULT,
 		.div = NA_DIV,
@@ -764,8 +764,8 @@
 		.type = TYPE_GATE,
 		.offset = 25,
 		.width = PERIPH_GATE_WIDTH,
-		.clkflags = CLK_IGNORE_UNUSED |
-			    CLK_IS_BASIC,
+		.clkflags = (uint16_t)(CLK_IGNORE_UNUSED |
+			    CLK_IS_BASIC),
 		.typeflags = NA_TYPE_FLAGS,
 		.mult = NA_MULT,
 		.div = NA_DIV,
@@ -777,9 +777,9 @@
 		.type = TYPE_MUX,
 		.offset = 0,
 		.width = 3,
-		.clkflags = CLK_SET_RATE_PARENT |
+		.clkflags = (uint16_t)(CLK_SET_RATE_PARENT |
 			    CLK_SET_RATE_NO_REPARENT |
-			    CLK_IS_BASIC,
+			    CLK_IS_BASIC),
 		.typeflags = NA_TYPE_FLAGS,
 		.mult = NA_MULT,
 		.div = NA_DIV,
@@ -792,8 +792,8 @@
 		.type = TYPE_DIV1,
 		.offset = 8,
 		.width = 6,
-		.clkflags = CLK_IS_BASIC,
-		.typeflags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
+		.clkflags = (uint16_t)CLK_IS_BASIC,
+		.typeflags = (uint16_t)(CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO),
 		.mult = NA_MULT,
 		.div = NA_DIV,
 	},
@@ -831,7 +831,7 @@
 		.status_reg = CRF_APB_PLL_STATUS,
 		.parents = &((int32_t []) {CLK_APLL_PRE_SRC, CLK_NA_PARENT}),
 		.nodes = &ignore_unused_pll_nodes,
-		.num_nodes = ARRAY_SIZE(ignore_unused_pll_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(ignore_unused_pll_nodes),
 	},
 	[CLK_APLL_PRE_SRC] = {
 		.name = "apll_pre_src",
@@ -849,7 +849,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &generic_pll_pre_src_nodes,
-		.num_nodes = ARRAY_SIZE(generic_pll_pre_src_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(generic_pll_pre_src_nodes),
 	},
 	[CLK_APLL_HALF] = {
 		.name = "apll_half",
@@ -857,7 +857,7 @@
 		.status_reg = CRF_APB_PLL_STATUS,
 		.parents = &((int32_t []) {CLK_APLL_INT, CLK_NA_PARENT}),
 		.nodes = &generic_pll_half_nodes,
-		.num_nodes = ARRAY_SIZE(generic_pll_half_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(generic_pll_half_nodes),
 	},
 	[CLK_APLL_INT_MUX] = {
 		.name = "apll_int_mux",
@@ -869,7 +869,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &generic_pll_int_nodes,
-		.num_nodes = ARRAY_SIZE(generic_pll_int_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(generic_pll_int_nodes),
 	},
 	[CLK_APLL_POST_SRC] = {
 		.name = "apll_post_src",
@@ -887,7 +887,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &generic_pll_post_src_nodes,
-		.num_nodes = ARRAY_SIZE(generic_pll_post_src_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(generic_pll_post_src_nodes),
 	},
 	[CLK_APLL] = {
 		.name = "apll",
@@ -899,7 +899,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &generic_pll_system_nodes,
-		.num_nodes = ARRAY_SIZE(generic_pll_system_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(generic_pll_system_nodes),
 	},
 	[CLK_DPLL_INT] = {
 		.name = "dpll_int",
@@ -907,7 +907,7 @@
 		.status_reg = CRF_APB_PLL_STATUS,
 		.parents = &((int32_t []) {CLK_DPLL_PRE_SRC, CLK_NA_PARENT}),
 		.nodes = &generic_pll_nodes,
-		.num_nodes = ARRAY_SIZE(generic_pll_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(generic_pll_nodes),
 	},
 	[CLK_DPLL_PRE_SRC] = {
 		.name = "dpll_pre_src",
@@ -925,7 +925,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &generic_pll_pre_src_nodes,
-		.num_nodes = ARRAY_SIZE(generic_pll_pre_src_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(generic_pll_pre_src_nodes),
 	},
 	[CLK_DPLL_HALF] = {
 		.name = "dpll_half",
@@ -933,7 +933,7 @@
 		.status_reg = CRF_APB_PLL_STATUS,
 		.parents = &((int32_t []) {CLK_DPLL_INT, CLK_NA_PARENT}),
 		.nodes = &generic_pll_half_nodes,
-		.num_nodes = ARRAY_SIZE(generic_pll_half_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(generic_pll_half_nodes),
 	},
 	[CLK_DPLL_INT_MUX] = {
 		.name = "dpll_int_mux",
@@ -945,7 +945,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &generic_pll_int_nodes,
-		.num_nodes = ARRAY_SIZE(generic_pll_int_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(generic_pll_int_nodes),
 	},
 	[CLK_DPLL_POST_SRC] = {
 		.name = "dpll_post_src",
@@ -963,7 +963,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &generic_pll_post_src_nodes,
-		.num_nodes = ARRAY_SIZE(generic_pll_post_src_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(generic_pll_post_src_nodes),
 	},
 	[CLK_DPLL] = {
 		.name = "dpll",
@@ -975,7 +975,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &generic_pll_system_nodes,
-		.num_nodes = ARRAY_SIZE(generic_pll_system_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(generic_pll_system_nodes),
 	},
 	[CLK_VPLL_INT] = {
 		.name = "vpll_int",
@@ -983,7 +983,7 @@
 		.status_reg = CRF_APB_PLL_STATUS,
 		.parents = &((int32_t []) {CLK_VPLL_PRE_SRC, CLK_NA_PARENT}),
 		.nodes = &ignore_unused_pll_nodes,
-		.num_nodes = ARRAY_SIZE(ignore_unused_pll_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(ignore_unused_pll_nodes),
 	},
 	[CLK_VPLL_PRE_SRC] = {
 		.name = "vpll_pre_src",
@@ -1001,7 +1001,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &generic_pll_pre_src_nodes,
-		.num_nodes = ARRAY_SIZE(generic_pll_pre_src_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(generic_pll_pre_src_nodes),
 	},
 	[CLK_VPLL_HALF] = {
 		.name = "vpll_half",
@@ -1009,7 +1009,7 @@
 		.status_reg = CRF_APB_PLL_STATUS,
 		.parents = &((int32_t []) {CLK_VPLL_INT, CLK_NA_PARENT}),
 		.nodes = &generic_pll_half_nodes,
-		.num_nodes = ARRAY_SIZE(generic_pll_half_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(generic_pll_half_nodes),
 	},
 	[CLK_VPLL_INT_MUX] = {
 		.name = "vpll_int_mux",
@@ -1021,7 +1021,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &generic_pll_int_nodes,
-		.num_nodes = ARRAY_SIZE(generic_pll_int_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(generic_pll_int_nodes),
 	},
 	[CLK_VPLL_POST_SRC] = {
 		.name = "vpll_post_src",
@@ -1051,7 +1051,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &generic_pll_system_nodes,
-		.num_nodes = ARRAY_SIZE(generic_pll_system_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(generic_pll_system_nodes),
 	},
 	[CLK_IOPLL_INT] = {
 		.name = "iopll_int",
@@ -1059,7 +1059,7 @@
 		.status_reg = CRF_APB_PLL_STATUS,
 		.parents = &((int32_t []) {CLK_IOPLL_PRE_SRC, CLK_NA_PARENT}),
 		.nodes = &generic_pll_nodes,
-		.num_nodes = ARRAY_SIZE(generic_pll_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(generic_pll_nodes),
 	},
 	[CLK_IOPLL_PRE_SRC] = {
 		.name = "iopll_pre_src",
@@ -1077,7 +1077,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &generic_pll_pre_src_nodes,
-		.num_nodes = ARRAY_SIZE(generic_pll_pre_src_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(generic_pll_pre_src_nodes),
 	},
 	[CLK_IOPLL_HALF] = {
 		.name = "iopll_half",
@@ -1085,7 +1085,7 @@
 		.status_reg = CRF_APB_PLL_STATUS,
 		.parents = &((int32_t []) {CLK_IOPLL_INT, CLK_NA_PARENT}),
 		.nodes = &generic_pll_half_nodes,
-		.num_nodes = ARRAY_SIZE(generic_pll_half_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(generic_pll_half_nodes),
 	},
 	[CLK_IOPLL_INT_MUX] = {
 		.name = "iopll_int_mux",
@@ -1097,7 +1097,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &generic_pll_int_nodes,
-		.num_nodes = ARRAY_SIZE(generic_pll_int_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(generic_pll_int_nodes),
 	},
 	[CLK_IOPLL_POST_SRC] = {
 		.name = "iopll_post_src",
@@ -1115,7 +1115,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &generic_pll_post_src_nodes,
-		.num_nodes = ARRAY_SIZE(generic_pll_post_src_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(generic_pll_post_src_nodes),
 	},
 	[CLK_IOPLL] = {
 		.name = "iopll",
@@ -1127,7 +1127,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &generic_pll_system_nodes,
-		.num_nodes = ARRAY_SIZE(generic_pll_system_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(generic_pll_system_nodes),
 	},
 	[CLK_RPLL_INT] = {
 		.name = "rpll_int",
@@ -1135,7 +1135,7 @@
 		.status_reg = CRF_APB_PLL_STATUS,
 		.parents = &((int32_t []) {CLK_RPLL_PRE_SRC, CLK_NA_PARENT}),
 		.nodes = &generic_pll_nodes,
-		.num_nodes = ARRAY_SIZE(generic_pll_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(generic_pll_nodes),
 	},
 	[CLK_RPLL_PRE_SRC] = {
 		.name = "rpll_pre_src",
@@ -1154,7 +1154,7 @@
 		}),
 
 		.nodes = &generic_pll_pre_src_nodes,
-		.num_nodes = ARRAY_SIZE(generic_pll_pre_src_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(generic_pll_pre_src_nodes),
 	},
 	[CLK_RPLL_HALF] = {
 		.name = "rpll_half",
@@ -1162,7 +1162,7 @@
 		.status_reg = CRF_APB_PLL_STATUS,
 		.parents = &((int32_t []) {CLK_RPLL_INT, CLK_NA_PARENT}),
 		.nodes = &generic_pll_half_nodes,
-		.num_nodes = ARRAY_SIZE(generic_pll_half_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(generic_pll_half_nodes),
 	},
 	[CLK_RPLL_INT_MUX] = {
 		.name = "rpll_int_mux",
@@ -1174,7 +1174,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &generic_pll_int_nodes,
-		.num_nodes = ARRAY_SIZE(generic_pll_int_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(generic_pll_int_nodes),
 	},
 	[CLK_RPLL_POST_SRC] = {
 		.name = "rpll_post_src",
@@ -1192,7 +1192,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &generic_pll_post_src_nodes,
-		.num_nodes = ARRAY_SIZE(generic_pll_post_src_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(generic_pll_post_src_nodes),
 	},
 	[CLK_RPLL] = {
 		.name = "rpll",
@@ -1204,7 +1204,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &generic_pll_system_nodes,
-		.num_nodes = ARRAY_SIZE(generic_pll_system_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(generic_pll_system_nodes),
 	},
 	/* Peripheral Clocks */
 	[CLK_ACPU] = {
@@ -1219,7 +1219,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &acpu_nodes,
-		.num_nodes = ARRAY_SIZE(acpu_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(acpu_nodes),
 	},
 	[CLK_ACPU_FULL] = {
 		.name = "acpu_full",
@@ -1244,7 +1244,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &generic_mux_div_gate_nodes,
-		.num_nodes = ARRAY_SIZE(generic_mux_div_gate_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(generic_mux_div_gate_nodes),
 	},
 	[CLK_DBG_FPD] = {
 		.name = "dbg_fpd",
@@ -1258,7 +1258,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &generic_mux_div_gate_nodes,
-		.num_nodes = ARRAY_SIZE(generic_mux_div_gate_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(generic_mux_div_gate_nodes),
 	},
 	[CLK_DBG_TSTMP] = {
 		.name = "dbg_tstmp",
@@ -1272,7 +1272,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &generic_mux_div_nodes,
-		.num_nodes = ARRAY_SIZE(generic_mux_div_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(generic_mux_div_nodes),
 	},
 	[CLK_DP_VIDEO_REF] = {
 		.name = "dp_video_ref",
@@ -1286,7 +1286,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &dp_audio_video_ref_nodes,
-		.num_nodes = ARRAY_SIZE(dp_audio_video_ref_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(dp_audio_video_ref_nodes),
 	},
 	[CLK_DP_AUDIO_REF] = {
 		.name = "dp_audio_ref",
@@ -1300,7 +1300,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &dp_audio_video_ref_nodes,
-		.num_nodes = ARRAY_SIZE(dp_audio_video_ref_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(dp_audio_video_ref_nodes),
 	},
 	[CLK_DP_STC_REF] = {
 		.name = "dp_stc_ref",
@@ -1314,7 +1314,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &generic_mux_div_div_gate_nodes,
-		.num_nodes = ARRAY_SIZE(generic_mux_div_div_gate_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(generic_mux_div_div_gate_nodes),
 	},
 	[CLK_DPDMA_REF] = {
 		.name = "dpdma_ref",
@@ -1328,7 +1328,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &generic_mux_div_gate_nodes,
-		.num_nodes = ARRAY_SIZE(generic_mux_div_gate_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(generic_mux_div_gate_nodes),
 	},
 	[CLK_DDR_REF] = {
 		.name = "ddr_ref",
@@ -1340,7 +1340,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &ddr_nodes,
-		.num_nodes = ARRAY_SIZE(ddr_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(ddr_nodes),
 	},
 	[CLK_GPU_REF] = {
 		.name = "gpu_ref",
@@ -1354,7 +1354,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &generic_mux_div_gate_nodes,
-		.num_nodes = ARRAY_SIZE(generic_mux_div_gate_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(generic_mux_div_gate_nodes),
 	},
 	[CLK_SATA_REF] = {
 		.name = "sata_ref",
@@ -1368,7 +1368,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &generic_mux_div_gate_nodes,
-		.num_nodes = ARRAY_SIZE(generic_mux_div_gate_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(generic_mux_div_gate_nodes),
 	},
 	[CLK_PCIE_REF] = {
 		.name = "pcie_ref",
@@ -1382,7 +1382,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &generic_mux_div_gate_nodes,
-		.num_nodes = ARRAY_SIZE(generic_mux_div_gate_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(generic_mux_div_gate_nodes),
 	},
 	[CLK_GDMA_REF] = {
 		.name = "gdma_ref",
@@ -1396,7 +1396,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &generic_mux_div_gate_nodes,
-		.num_nodes = ARRAY_SIZE(generic_mux_div_gate_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(generic_mux_div_gate_nodes),
 	},
 	[CLK_GTGREF0_REF] = {
 		.name = "gtgref0_ref",
@@ -1410,7 +1410,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &generic_mux_div_gate_nodes,
-		.num_nodes = ARRAY_SIZE(generic_mux_div_gate_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(generic_mux_div_gate_nodes),
 	},
 	[CLK_TOPSW_MAIN] = {
 		.name = "topsw_main",
@@ -1424,7 +1424,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &generic_mux_div_unused_gate_nodes,
-		.num_nodes = ARRAY_SIZE(generic_mux_div_unused_gate_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(generic_mux_div_unused_gate_nodes),
 	},
 	[CLK_TOPSW_LSBUS] = {
 		.name = "topsw_lsbus",
@@ -1438,7 +1438,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &generic_mux_div_unused_gate_nodes,
-		.num_nodes = ARRAY_SIZE(generic_mux_div_unused_gate_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(generic_mux_div_unused_gate_nodes),
 	},
 	[CLK_IOU_SWITCH] = {
 		.name = "iou_switch",
@@ -1452,7 +1452,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &generic_mux_div_unused_gate_nodes,
-		.num_nodes = ARRAY_SIZE(generic_mux_div_unused_gate_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(generic_mux_div_unused_gate_nodes),
 	},
 	[CLK_GEM0_REF_UNGATED] = {
 		.name = "gem0_ref_ung",
@@ -1574,7 +1574,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &usb_nodes,
-		.num_nodes = ARRAY_SIZE(usb_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(usb_nodes),
 	},
 	[CLK_USB1_BUS_REF] = {
 		.name = "usb1_bus_ref",
@@ -1588,7 +1588,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &usb_nodes,
-		.num_nodes = ARRAY_SIZE(usb_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(usb_nodes),
 	},
 	[CLK_USB3_DUAL_REF] = {
 		.name = "usb3_dual_ref",
@@ -1602,7 +1602,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &usb_nodes,
-		.num_nodes = ARRAY_SIZE(usb_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(usb_nodes),
 	},
 	[CLK_QSPI_REF] = {
 		.name = "qspi_ref",
@@ -1616,7 +1616,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &generic_mux_div_div_gate_nodes,
-		.num_nodes = ARRAY_SIZE(generic_mux_div_div_gate_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(generic_mux_div_div_gate_nodes),
 	},
 	[CLK_SDIO0_REF] = {
 		.name = "sdio0_ref",
@@ -1630,7 +1630,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &generic_mux_div_div_gate_nodes,
-		.num_nodes = ARRAY_SIZE(generic_mux_div_div_gate_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(generic_mux_div_div_gate_nodes),
 	},
 	[CLK_SDIO1_REF] = {
 		.name = "sdio1_ref",
@@ -1644,7 +1644,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &generic_mux_div_div_gate_nodes,
-		.num_nodes = ARRAY_SIZE(generic_mux_div_div_gate_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(generic_mux_div_div_gate_nodes),
 	},
 	[CLK_UART0_REF] = {
 		.name = "uart0_ref",
@@ -1658,7 +1658,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &generic_mux_div_div_gate_nodes,
-		.num_nodes = ARRAY_SIZE(generic_mux_div_div_gate_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(generic_mux_div_div_gate_nodes),
 	},
 	[CLK_UART1_REF] = {
 		.name = "uart1_ref",
@@ -1672,7 +1672,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &generic_mux_div_div_gate_nodes,
-		.num_nodes = ARRAY_SIZE(generic_mux_div_div_gate_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(generic_mux_div_div_gate_nodes),
 	},
 	[CLK_SPI0_REF] = {
 		.name = "spi0_ref",
@@ -1686,7 +1686,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &generic_mux_div_div_gate_nodes,
-		.num_nodes = ARRAY_SIZE(generic_mux_div_div_gate_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(generic_mux_div_div_gate_nodes),
 	},
 	[CLK_SPI1_REF] = {
 		.name = "spi1_ref",
@@ -1700,7 +1700,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &generic_mux_div_div_gate_nodes,
-		.num_nodes = ARRAY_SIZE(generic_mux_div_div_gate_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(generic_mux_div_div_gate_nodes),
 	},
 	[CLK_CAN0_REF] = {
 		.name = "can0_ref",
@@ -1714,7 +1714,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &generic_mux_div_div_gate_nodes,
-		.num_nodes = ARRAY_SIZE(generic_mux_div_div_gate_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(generic_mux_div_div_gate_nodes),
 	},
 	[CLK_CAN1_REF] = {
 		.name = "can1_ref",
@@ -1728,7 +1728,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &generic_mux_div_div_gate_nodes,
-		.num_nodes = ARRAY_SIZE(generic_mux_div_div_gate_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(generic_mux_div_div_gate_nodes),
 	},
 	[CLK_NAND_REF] = {
 		.name = "nand_ref",
@@ -1742,7 +1742,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &generic_mux_div_div_gate_nodes,
-		.num_nodes = ARRAY_SIZE(generic_mux_div_div_gate_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(generic_mux_div_div_gate_nodes),
 	},
 	[CLK_GEM_TSU_REF] = {
 		.name = "gem_tsu_ref",
@@ -1756,7 +1756,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &generic_mux_div_div_gate_nodes,
-		.num_nodes = ARRAY_SIZE(generic_mux_div_div_gate_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(generic_mux_div_div_gate_nodes),
 	},
 	[CLK_DLL_REF] = {
 		.name = "dll_ref",
@@ -1768,7 +1768,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &dll_ref_nodes,
-		.num_nodes = ARRAY_SIZE(dll_ref_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(dll_ref_nodes),
 	},
 	[CLK_ADMA_REF] = {
 		.name = "adma_ref",
@@ -1782,7 +1782,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &generic_mux_div_gate_nodes,
-		.num_nodes = ARRAY_SIZE(generic_mux_div_gate_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(generic_mux_div_gate_nodes),
 	},
 	[CLK_DBG_LPD] = {
 		.name = "dbg_lpd",
@@ -1796,7 +1796,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &generic_mux_div_gate_nodes,
-		.num_nodes = ARRAY_SIZE(generic_mux_div_gate_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(generic_mux_div_gate_nodes),
 	},
 	[CLK_CPU_R5] = {
 		.name = "cpu_r5",
@@ -1810,7 +1810,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &generic_mux_div_unused_gate_nodes,
-		.num_nodes = ARRAY_SIZE(generic_mux_div_unused_gate_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(generic_mux_div_unused_gate_nodes),
 	},
 	[CLK_CSU_PLL] = {
 		.name = "csu_pll",
@@ -1824,7 +1824,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &generic_mux_div_gate_nodes,
-		.num_nodes = ARRAY_SIZE(generic_mux_div_gate_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(generic_mux_div_gate_nodes),
 	},
 	[CLK_PCAP] = {
 		.name = "pcap",
@@ -1838,7 +1838,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &generic_mux_div_gate_nodes,
-		.num_nodes = ARRAY_SIZE(generic_mux_div_gate_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(generic_mux_div_gate_nodes),
 	},
 	[CLK_LPD_LSBUS] = {
 		.name = "lpd_lsbus",
@@ -1852,7 +1852,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &generic_mux_div_unused_gate_nodes,
-		.num_nodes = ARRAY_SIZE(generic_mux_div_unused_gate_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(generic_mux_div_unused_gate_nodes),
 	},
 	[CLK_LPD_SWITCH] = {
 		.name = "lpd_switch",
@@ -1866,7 +1866,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &generic_mux_div_unused_gate_nodes,
-		.num_nodes = ARRAY_SIZE(generic_mux_div_unused_gate_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(generic_mux_div_unused_gate_nodes),
 	},
 	[CLK_I2C0_REF] = {
 		.name = "i2c0_ref",
@@ -1880,7 +1880,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &generic_mux_div_div_gate_nodes,
-		.num_nodes = ARRAY_SIZE(generic_mux_div_div_gate_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(generic_mux_div_div_gate_nodes),
 	},
 	[CLK_I2C1_REF] = {
 		.name = "i2c1_ref",
@@ -1894,7 +1894,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &generic_mux_div_div_gate_nodes,
-		.num_nodes = ARRAY_SIZE(generic_mux_div_div_gate_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(generic_mux_div_div_gate_nodes),
 	},
 	[CLK_TIMESTAMP_REF] = {
 		.name = "timestamp_ref",
@@ -1912,7 +1912,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &timestamp_ref_nodes,
-		.num_nodes = ARRAY_SIZE(timestamp_ref_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(timestamp_ref_nodes),
 	},
 	[CLK_PL0_REF] = {
 		.name = "pl0_ref",
@@ -1926,7 +1926,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &pl_nodes,
-		.num_nodes = ARRAY_SIZE(pl_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(pl_nodes),
 	},
 	[CLK_PL1_REF] = {
 		.name = "pl1_ref",
@@ -1940,7 +1940,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &pl_nodes,
-		.num_nodes = ARRAY_SIZE(pl_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(pl_nodes),
 	},
 	[CLK_PL2_REF] = {
 		.name = "pl2_ref",
@@ -1954,7 +1954,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &pl_nodes,
-		.num_nodes = ARRAY_SIZE(pl_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(pl_nodes),
 	},
 	[CLK_PL3_REF] = {
 		.name = "pl3_ref",
@@ -1968,7 +1968,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &pl_nodes,
-		.num_nodes = ARRAY_SIZE(pl_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(pl_nodes),
 	},
 	[CLK_AMS_REF] = {
 		.name = "ams_ref",
@@ -1982,7 +1982,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &generic_mux_div_div_gate_nodes,
-		.num_nodes = ARRAY_SIZE(generic_mux_div_div_gate_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(generic_mux_div_div_gate_nodes),
 	},
 	[CLK_IOPLL_TO_FPD] = {
 		.name = "iopll_to_fpd",
@@ -1990,7 +1990,7 @@
 		.status_reg = 0,
 		.parents = &((int32_t []) {CLK_IOPLL, CLK_NA_PARENT}),
 		.nodes = &generic_domain_crossing_nodes,
-		.num_nodes = ARRAY_SIZE(generic_domain_crossing_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(generic_domain_crossing_nodes),
 	},
 	[CLK_RPLL_TO_FPD] = {
 		.name = "rpll_to_fpd",
@@ -1998,7 +1998,7 @@
 		.status_reg = 0,
 		.parents = &((int32_t []) {CLK_RPLL, CLK_NA_PARENT}),
 		.nodes = &rpll_to_fpd_nodes,
-		.num_nodes = ARRAY_SIZE(rpll_to_fpd_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(rpll_to_fpd_nodes),
 	},
 	[CLK_APLL_TO_LPD] = {
 		.name = "apll_to_lpd",
@@ -2006,7 +2006,7 @@
 		.status_reg = 0,
 		.parents = &((int32_t []) {CLK_APLL, CLK_NA_PARENT}),
 		.nodes = &generic_domain_crossing_nodes,
-		.num_nodes = ARRAY_SIZE(generic_domain_crossing_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(generic_domain_crossing_nodes),
 	},
 	[CLK_DPLL_TO_LPD] = {
 		.name = "dpll_to_lpd",
@@ -2014,7 +2014,7 @@
 		.status_reg = 0,
 		.parents = &((int32_t []) {CLK_DPLL, CLK_NA_PARENT}),
 		.nodes = &generic_domain_crossing_nodes,
-		.num_nodes = ARRAY_SIZE(generic_domain_crossing_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(generic_domain_crossing_nodes),
 	},
 	[CLK_VPLL_TO_LPD] = {
 		.name = "vpll_to_lpd",
@@ -2022,7 +2022,7 @@
 		.status_reg = 0,
 		.parents = &((int32_t []) {CLK_VPLL, CLK_NA_PARENT}),
 		.nodes = &generic_domain_crossing_nodes,
-		.num_nodes = ARRAY_SIZE(generic_domain_crossing_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(generic_domain_crossing_nodes),
 	},
 	[CLK_GEM0_TX] = {
 		.name = "gem0_tx",
@@ -2033,7 +2033,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &gem_tx_nodes,
-		.num_nodes = ARRAY_SIZE(gem_tx_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(gem_tx_nodes),
 	},
 	[CLK_GEM1_TX] = {
 		.name = "gem1_tx",
@@ -2044,7 +2044,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &gem_tx_nodes,
-		.num_nodes = ARRAY_SIZE(gem_tx_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(gem_tx_nodes),
 	},
 	[CLK_GEM2_TX] = {
 		.name = "gem2_tx",
@@ -2055,7 +2055,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &gem_tx_nodes,
-		.num_nodes = ARRAY_SIZE(gem_tx_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(gem_tx_nodes),
 	},
 	[CLK_GEM3_TX] = {
 		.name = "gem3_tx",
@@ -2066,7 +2066,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &gem_tx_nodes,
-		.num_nodes = ARRAY_SIZE(gem_tx_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(gem_tx_nodes),
 	},
 	[CLK_GEM0_RX] = {
 		.name = "gem0_rx",
@@ -2077,7 +2077,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &gem_rx_nodes,
-		.num_nodes = ARRAY_SIZE(gem_rx_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(gem_rx_nodes),
 	},
 	[CLK_GEM1_RX] = {
 		.name = "gem1_rx",
@@ -2088,7 +2088,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &gem_rx_nodes,
-		.num_nodes = ARRAY_SIZE(gem_rx_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(gem_rx_nodes),
 	},
 	[CLK_GEM2_RX] = {
 		.name = "gem2_rx",
@@ -2099,7 +2099,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &gem_rx_nodes,
-		.num_nodes = ARRAY_SIZE(gem_rx_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(gem_rx_nodes),
 	},
 	[CLK_GEM3_RX] = {
 		.name = "gem3_rx",
@@ -2110,7 +2110,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &gem_rx_nodes,
-		.num_nodes = ARRAY_SIZE(gem_rx_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(gem_rx_nodes),
 	},
 	[CLK_ACPU_HALF] = {
 		.name = "acpu_half",
@@ -2121,7 +2121,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &acpu_half_nodes,
-		.num_nodes = ARRAY_SIZE(acpu_half_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(acpu_half_nodes),
 	},
 	[CLK_FPD_WDT] = {
 		.name = "fpd_wdt",
@@ -2133,7 +2133,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &wdt_nodes,
-		.num_nodes = ARRAY_SIZE(wdt_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(wdt_nodes),
 	},
 	[CLK_GPU_PP0_REF] = {
 		.name = "gpu_pp0_ref",
@@ -2144,7 +2144,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &gpu_pp0_nodes,
-		.num_nodes = ARRAY_SIZE(gpu_pp0_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(gpu_pp0_nodes),
 	},
 	[CLK_GPU_PP1_REF] = {
 		.name = "gpu_pp1_ref",
@@ -2155,7 +2155,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &gpu_pp1_nodes,
-		.num_nodes = ARRAY_SIZE(gpu_pp1_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(gpu_pp1_nodes),
 	},
 	[CLK_GEM_TSU] = {
 		.name = "gem_tsu",
@@ -2169,7 +2169,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &gem_tsu_nodes,
-		.num_nodes = ARRAY_SIZE(gem_tsu_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(gem_tsu_nodes),
 	},
 	[CLK_CPU_R5_CORE] = {
 		.name = "cpu_r5_core",
@@ -2181,7 +2181,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &cpu_r5_core_nodes,
-		.num_nodes = ARRAY_SIZE(cpu_r5_core_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(cpu_r5_core_nodes),
 	},
 	[CLK_CAN0_MIO] = {
 		.name = "can0_mio",
@@ -2209,7 +2209,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &can0_nodes,
-		.num_nodes = ARRAY_SIZE(can0_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(can0_nodes),
 	},
 	[CLK_CAN1] = {
 		.name = "can1",
@@ -2221,7 +2221,7 @@
 			CLK_NA_PARENT
 		}),
 		.nodes = &can1_nodes,
-		.num_nodes = ARRAY_SIZE(can1_nodes),
+		.num_nodes = (uint8_t)ARRAY_SIZE(can1_nodes),
 	},
 	[CLK_LPD_WDT] = {
 		.name = "lpd_wdt",
@@ -2455,15 +2455,17 @@
  */
 void pm_api_clock_get_name(uint32_t clock_id, char *name)
 {
-	if (clock_id == CLK_MAX) {
+	uint32_t clock_id_num = clock_id;
+
+	if (clock_id_num == CLK_MAX) {
 		(void)memcpy(name, END_OF_CLK, ((sizeof(END_OF_CLK) > CLK_NAME_LEN) ?
 					 CLK_NAME_LEN : sizeof(END_OF_CLK)));
 	} else if ((clock_id > CLK_MAX) || (!pm_clock_valid(clock_id))) {
 		(void)memset(name, 0, CLK_NAME_LEN);
-	} else if (clock_id < CLK_MAX_OUTPUT_CLK) {
-		(void)memcpy(name, clocks[clock_id].name, CLK_NAME_LEN);
+	} else if (clock_id_num < (uint32_t)CLK_MAX_OUTPUT_CLK) {
+		(void)memcpy(name, clocks[clock_id_num].name, CLK_NAME_LEN);
 	} else {
-		(void)memcpy(name, ext_clocks[clock_id - CLK_MAX_OUTPUT_CLK].name,
+		(void)memcpy(name, ext_clocks[clock_id_num - (uint32_t)CLK_MAX_OUTPUT_CLK].name,
 		       CLK_NAME_LEN);
 	}
 }
@@ -2514,13 +2516,13 @@
 		}
 
 		topology[i] = clock_nodes[index + i].type;
-		topology[i] |= clock_nodes[index + i].clkflags <<
-					CLK_CLKFLAGS_SHIFT;
+		topology[i] |= ((uint32_t)clock_nodes[index + i].clkflags <<
+					CLK_CLKFLAGS_SHIFT);
 		typeflags = clock_nodes[index + i].typeflags;
-		topology[i] |= (typeflags & CLK_TYPEFLAGS_BITS_MASK) <<
-					CLK_TYPEFLAGS_SHIFT;
-		topology[i] |= (typeflags & CLK_TYPEFLAGS2_BITS_MASK) >>
-				(CLK_TYPEFLAGS_BITS - CLK_TYPEFLAGS2_SHIFT);
+		topology[i] |= ((uint32_t)(typeflags & CLK_TYPEFLAGS_BITS_MASK) <<
+					CLK_TYPEFLAGS_SHIFT);
+		topology[i] |= ((uint32_t)(typeflags & CLK_TYPEFLAGS2_BITS_MASK) >>
+				(CLK_TYPEFLAGS_BITS - CLK_TYPEFLAGS2_SHIFT));
 	}
 
 	return PM_RET_SUCCESS;
@@ -2623,7 +2625,7 @@
 	}
 
 	for (i = 0; i < 3U; i++) {
-		parents[i] = clk_parents[index + i];
+		parents[i] = (uint32_t)clk_parents[index + i];
 		if (clk_parents[index + i] == CLK_NA_PARENT) {
 			break;
 		}
@@ -2646,7 +2648,7 @@
 enum pm_ret_status pm_api_clock_get_attributes(uint32_t clock_id,
 					       uint32_t *attr)
 {
-	if (clock_id >= CLK_MAX) {
+	if (clock_id >= (uint32_t)CLK_MAX) {
 		return PM_RET_ERROR_ARGS;
 	}
 
@@ -2685,10 +2687,11 @@
 	for (i = 0; i < clocks[clock_id].num_nodes; i++) {
 		if (nodes[i].type == div_type) {
 			if ((CLK_DIVIDER_POWER_OF_TWO &
-					nodes[i].typeflags) != 0U) {
-				*max_div = (1U << (BIT(nodes[i].width) - 1U));
+						nodes[i].typeflags) != 0U) {
+				*max_div = (((uint32_t)1U <<
+						((uint32_t)BIT(nodes[i].width) - (uint32_t)1U)));
 			} else {
-				*max_div = BIT(nodes[i].width) - 1U;
+				*max_div = (uint32_t)BIT(nodes[i].width) - (uint32_t)1U;
 			}
 			return PM_RET_SUCCESS;
 		}
@@ -2993,7 +2996,7 @@
 	if ((pll == NULL) || ((mode != PLL_FRAC_MODE) && (mode != PLL_INT_MODE))) {
 		return PM_RET_ERROR_ARGS;
 	}
-	pll->mode = mode;
+	pll->mode = (uint8_t)mode;
 
 	return PM_RET_SUCCESS;
 }
@@ -3054,7 +3057,7 @@
 	uint32_t i;
 	const struct pm_clock_node *nodes;
 
-	if (clock_id >= CLK_MAX_OUTPUT_CLK) {
+	if (clock_id >= (uint32_t)CLK_MAX_OUTPUT_CLK) {
 		return 0;
 	}
 
diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c b/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c
index 0dbfa57..a8404ba 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c
@@ -266,7 +266,7 @@
 
 	if (type == PM_TAPDELAY_INPUT) {
 		ret = pm_mmio_write(ZYNQMP_SD_ITAP_DLY,
-				    (ZYNQMP_SD_ITAPCHGWIN_MASK << shift),
+				    (uint64_t)(ZYNQMP_SD_ITAPCHGWIN_MASK << shift),
 				    (ZYNQMP_SD_ITAPCHGWIN << shift));
 
 		if (ret != PM_RET_SUCCESS) {
@@ -275,12 +275,12 @@
 
 		if (value == 0U) {
 			ret = pm_mmio_write(ZYNQMP_SD_ITAP_DLY,
-					    (ZYNQMP_SD_ITAPDLYENA_MASK <<
+					    (uint64_t)(ZYNQMP_SD_ITAPDLYENA_MASK <<
 					     shift), 0);
 		} else {
 			ret = pm_mmio_write(ZYNQMP_SD_ITAP_DLY,
-					    (ZYNQMP_SD_ITAPDLYENA_MASK <<
-					    shift), (ZYNQMP_SD_ITAPDLYENA <<
+					    (uint64_t)(ZYNQMP_SD_ITAPDLYENA_MASK <<
+					    shift), (uint64_t)(ZYNQMP_SD_ITAPDLYENA <<
 					    shift));
 		}
 
@@ -289,7 +289,7 @@
 		}
 
 		ret = pm_mmio_write(ZYNQMP_SD_ITAP_DLY,
-				    (ZYNQMP_SD_ITAPDLYSEL_MASK << shift),
+				    (uint64_t)(ZYNQMP_SD_ITAPDLYSEL_MASK << shift),
 				    (value << shift));
 
 		if (ret != PM_RET_SUCCESS) {
@@ -297,17 +297,17 @@
 		}
 
 		ret = pm_mmio_write(ZYNQMP_SD_ITAP_DLY,
-				    (ZYNQMP_SD_ITAPCHGWIN_MASK << shift), 0);
+				    (uint64_t)(ZYNQMP_SD_ITAPCHGWIN_MASK << shift), 0);
 	} else if (type == PM_TAPDELAY_OUTPUT) {
 		ret = pm_mmio_write(ZYNQMP_SD_OTAP_DLY,
-				    (ZYNQMP_SD_OTAPDLYENA_MASK << shift), 0);
+				    (uint64_t)(ZYNQMP_SD_OTAPDLYENA_MASK << shift), 0);
 
 		if (ret != PM_RET_SUCCESS) {
 			goto reset_release;
 		}
 
 		ret = pm_mmio_write(ZYNQMP_SD_OTAP_DLY,
-				    (ZYNQMP_SD_OTAPDLYSEL_MASK << shift),
+				    (uint64_t)(ZYNQMP_SD_OTAPDLYSEL_MASK << shift),
 				    (value << shift));
 	} else {
 		ret = PM_RET_ERROR_ARGS;
@@ -422,7 +422,7 @@
 		return PM_RET_ERROR_ARGS;
 	}
 
-	return pm_mmio_write(GGS_BASEADDR + (index << 2),
+	return pm_mmio_write((uint64_t)(GGS_BASEADDR + (index << 2)),
 			     0xFFFFFFFFU, value);
 }
 
@@ -444,7 +444,7 @@
 		return PM_RET_ERROR_ARGS;
 	}
 
-	return pm_mmio_read(GGS_BASEADDR + (index << 2), value);
+	return pm_mmio_read((uint64_t)(GGS_BASEADDR + (index << 2)), value);
 }
 
 /**
@@ -465,7 +465,7 @@
 		return PM_RET_ERROR_ARGS;
 	}
 
-	return pm_mmio_write(PGGS_BASEADDR + (index << 2),
+	return pm_mmio_write((uint64_t)(PGGS_BASEADDR + (index << 2)),
 			     0xFFFFFFFFU, value);
 }
 
@@ -530,7 +530,7 @@
 		return PM_RET_ERROR_ARGS;
 	}
 
-	return pm_mmio_read(PGGS_BASEADDR + (index << 2), value);
+	return pm_mmio_read((uint64_t)(PGGS_BASEADDR + (index << 2)), value);
 }
 
 /**
@@ -703,7 +703,7 @@
 		IOCTL_AFI,
 	};
 	uint8_t i, ioctl_id;
-	int32_t ret;
+	enum pm_ret_status ret;
 
 	for (i = 0U; i < ARRAY_SIZE(supported_ids); i++) {
 		ioctl_id = supported_ids[i];
diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c b/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c
index 1477e25..763d9fa 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c
@@ -1991,7 +1991,7 @@
 enum pm_ret_status pm_api_pinctrl_get_num_func_groups(uint32_t fid,
 						      uint32_t *ngroups)
 {
-	if (fid >= MAX_FUNCTION) {
+	if (fid >= (uint32_t)MAX_FUNCTION) {
 		return PM_RET_ERROR_ARGS;
 	}
 
@@ -2011,7 +2011,7 @@
  */
 void pm_api_pinctrl_get_function_name(uint32_t fid, char *name)
 {
-	if (fid >= MAX_FUNCTION) {
+	if (fid >= (uint32_t)MAX_FUNCTION) {
 		(void)memcpy(name, END_OF_FUNCTION, FUNCTION_NAME_LEN);
 	} else {
 		(void)memcpy(name, pinctrl_functions[fid].name, FUNCTION_NAME_LEN);
@@ -2045,7 +2045,7 @@
 	uint16_t end_of_grp_offset;
 	uint16_t i;
 
-	if (fid >= MAX_FUNCTION) {
+	if (fid >= (uint32_t)MAX_FUNCTION) {
 		return PM_RET_ERROR_ARGS;
 	}
 
@@ -2058,7 +2058,7 @@
 		if ((grps + index + i) >= end_of_grp_offset) {
 			break;
 		}
-		groups[i] = (grps + index + i);
+		groups[i] = (uint16_t)(grps + index + i);
 	}
 
 	return PM_RET_SUCCESS;
@@ -2090,7 +2090,7 @@
 	uint32_t i;
 	const uint16_t *grps;
 
-	if (pin >= MAX_PIN) {
+	if (pin >= (uint32_t)MAX_PIN) {
 		return PM_RET_ERROR_ARGS;
 	}
 
diff --git a/plat/xilinx/zynqmp/pm_service/pm_client.c b/plat/xilinx/zynqmp/pm_service/pm_client.c
index a517257..9882e30 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_client.c
+++ b/plat/xilinx/zynqmp/pm_service/pm_client.c
@@ -46,22 +46,22 @@
 /* Order in pm_procs_all array must match cpu ids */
 static const struct pm_proc pm_procs_all[] = {
 	{
-		.node_id = NODE_APU_0,
+		.node_id = (uint32_t)NODE_APU_0,
 		.pwrdn_mask = APU_0_PWRCTL_CPUPWRDWNREQ_MASK,
 		.ipi = &apu_ipi,
 	},
 	{
-		.node_id = NODE_APU_1,
+		.node_id = (uint32_t)NODE_APU_1,
 		.pwrdn_mask = APU_1_PWRCTL_CPUPWRDWNREQ_MASK,
 		.ipi = &apu_ipi,
 	},
 	{
-		.node_id = NODE_APU_2,
+		.node_id = (uint32_t)NODE_APU_2,
 		.pwrdn_mask = APU_2_PWRCTL_CPUPWRDWNREQ_MASK,
 		.ipi = &apu_ipi,
 	},
 	{
-		.node_id = NODE_APU_3,
+		.node_id = (uint32_t)NODE_APU_3,
 		.pwrdn_mask = APU_3_PWRCTL_CPUPWRDWNREQ_MASK,
 		.ipi = &apu_ipi,
 	},
@@ -198,7 +198,7 @@
 
 	for (reg_num = 0U; reg_num < NUM_GICD_ISENABLER; reg_num++) {
 		uint32_t base_irq = reg_num << ISENABLER_SHIFT;
-		uint32_t reg = mmio_read_32(isenabler1 + (reg_num << 2U));
+		uint32_t reg = mmio_read_32(isenabler1 + (uint64_t)(reg_num << 2U));
 
 		if (reg == 0) {
 			continue;
@@ -206,9 +206,10 @@
 
 		while (reg != 0U) {
 			enum pm_node_id node;
-			uint32_t idx, ret, irq, lowest_set = reg & (-reg);
+			uint32_t idx, irq, lowest_set = reg & (-reg);
+			enum pm_ret_status ret;
 
-			idx = __builtin_ctz(lowest_set);
+			idx = (uint32_t)__builtin_ctz(lowest_set);
 			irq = base_irq + idx;
 
 			if (irq > IRQ_MAX) {
diff --git a/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.c b/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.c
index 719ab6f..215bf30 100644
--- a/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.c
+++ b/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.c
@@ -51,164 +51,164 @@
 /* Dependent APIs for TF-A to check their version from firmware */
 static const eemi_api_dependency api_dep_table[] = {
 	{
-		.id = PM_SELF_SUSPEND,
-		.api_id = PM_SELF_SUSPEND,
+		.id = (uint8_t)PM_SELF_SUSPEND,
+		.api_id = (uint8_t)PM_SELF_SUSPEND,
 	},
 	{
-		.id = PM_REQ_WAKEUP,
-		.api_id = PM_REQ_WAKEUP,
+		.id = (uint8_t)PM_REQ_WAKEUP,
+		.api_id = (uint8_t)PM_REQ_WAKEUP,
 	},
 	{
-		.id = PM_ABORT_SUSPEND,
-		.api_id = PM_ABORT_SUSPEND,
+		.id = (uint8_t)PM_ABORT_SUSPEND,
+		.api_id = (uint8_t)PM_ABORT_SUSPEND,
 	},
 	{
-		.id = PM_SET_WAKEUP_SOURCE,
-		.api_id = PM_SET_WAKEUP_SOURCE,
+		.id = (uint8_t)PM_SET_WAKEUP_SOURCE,
+		.api_id = (uint8_t)PM_SET_WAKEUP_SOURCE,
 	},
 	{
-		.id = PM_SYSTEM_SHUTDOWN,
-		.api_id = PM_SYSTEM_SHUTDOWN,
+		.id = (uint8_t)PM_SYSTEM_SHUTDOWN,
+		.api_id = (uint8_t)PM_SYSTEM_SHUTDOWN,
 	},
 	{
-		.id = PM_GET_API_VERSION,
-		.api_id = PM_GET_API_VERSION,
+		.id = (uint8_t)PM_GET_API_VERSION,
+		.api_id = (uint8_t)PM_GET_API_VERSION,
 	},
 	{
-		.id = PM_CLOCK_ENABLE,
-		.api_id = PM_PLL_SET_MODE,
+		.id = (uint8_t)PM_CLOCK_ENABLE,
+		.api_id = (uint8_t)PM_PLL_SET_MODE,
 	},
 	{
-		.id = PM_CLOCK_ENABLE,
-		.api_id = PM_CLOCK_ENABLE,
+		.id = (uint8_t)PM_CLOCK_ENABLE,
+		.api_id = (uint8_t)PM_CLOCK_ENABLE,
 	},
 	{
-		.id = PM_CLOCK_DISABLE,
-		.api_id = PM_PLL_SET_MODE,
+		.id = (uint8_t)PM_CLOCK_DISABLE,
+		.api_id = (uint8_t)PM_PLL_SET_MODE,
 	},
 	{
-		.id = PM_CLOCK_DISABLE,
-		.api_id = PM_CLOCK_DISABLE,
+		.id = (uint8_t)PM_CLOCK_DISABLE,
+		.api_id = (uint8_t)PM_CLOCK_DISABLE,
 	},
 	{
-		.id = PM_CLOCK_GETSTATE,
-		.api_id = PM_PLL_GET_MODE,
+		.id = (uint8_t)PM_CLOCK_GETSTATE,
+		.api_id = (uint8_t)PM_PLL_GET_MODE,
 	},
 	{
-		.id = PM_CLOCK_GETSTATE,
-		.api_id = PM_CLOCK_GETSTATE,
+		.id = (uint8_t)PM_CLOCK_GETSTATE,
+		.api_id = (uint8_t)PM_CLOCK_GETSTATE,
 	},
 	{
-		.id = PM_CLOCK_SETDIVIDER,
-		.api_id = PM_PLL_SET_PARAMETER,
+		.id = (uint8_t)PM_CLOCK_SETDIVIDER,
+		.api_id = (uint8_t)PM_PLL_SET_PARAMETER,
 	},
 	{
-		.id = PM_CLOCK_SETDIVIDER,
-		.api_id = PM_CLOCK_SETDIVIDER,
+		.id = (uint8_t)PM_CLOCK_SETDIVIDER,
+		.api_id = (uint8_t)PM_CLOCK_SETDIVIDER,
 	},
 	{
-		.id = PM_CLOCK_GETDIVIDER,
-		.api_id = PM_PLL_GET_PARAMETER,
+		.id = (uint8_t)PM_CLOCK_GETDIVIDER,
+		.api_id = (uint8_t)PM_PLL_GET_PARAMETER,
 	},
 	{
-		.id = PM_CLOCK_GETDIVIDER,
-		.api_id = PM_CLOCK_GETDIVIDER,
+		.id = (uint8_t)PM_CLOCK_GETDIVIDER,
+		.api_id = (uint8_t)PM_CLOCK_GETDIVIDER,
 	},
 	{
-		.id = PM_CLOCK_SETPARENT,
-		.api_id = PM_PLL_SET_PARAMETER,
+		.id = (uint8_t)PM_CLOCK_SETPARENT,
+		.api_id = (uint8_t)PM_PLL_SET_PARAMETER,
 	},
 	{
-		.id = PM_CLOCK_SETPARENT,
-		.api_id = PM_CLOCK_SETPARENT,
+		.id = (uint8_t)PM_CLOCK_SETPARENT,
+		.api_id = (uint8_t)PM_CLOCK_SETPARENT,
 	},
 	{
-		.id = PM_CLOCK_GETPARENT,
-		.api_id = PM_PLL_GET_PARAMETER,
+		.id = (uint8_t)PM_CLOCK_GETPARENT,
+		.api_id = (uint8_t)PM_PLL_GET_PARAMETER,
 	},
 	{
-		.id = PM_CLOCK_GETPARENT,
-		.api_id = PM_CLOCK_GETPARENT,
+		.id = (uint8_t)PM_CLOCK_GETPARENT,
+		.api_id = (uint8_t)PM_CLOCK_GETPARENT,
 	},
 	{
-		.id = PM_PLL_SET_PARAMETER,
-		.api_id = PM_PLL_SET_PARAMETER,
+		.id = (uint8_t)PM_PLL_SET_PARAMETER,
+		.api_id = (uint8_t)PM_PLL_SET_PARAMETER,
 	},
 	{
-		.id = PM_PLL_GET_PARAMETER,
-		.api_id = PM_PLL_GET_PARAMETER,
+		.id = (uint8_t)PM_PLL_GET_PARAMETER,
+		.api_id = (uint8_t)PM_PLL_GET_PARAMETER,
 	},
 	{
-		.id = PM_PLL_SET_MODE,
-		.api_id = PM_PLL_SET_MODE,
+		.id = (uint8_t)PM_PLL_SET_MODE,
+		.api_id = (uint8_t)PM_PLL_SET_MODE,
 	},
 	{
-		.id = PM_PLL_GET_MODE,
-		.api_id = PM_PLL_GET_MODE,
+		.id = (uint8_t)PM_PLL_GET_MODE,
+		.api_id = (uint8_t)PM_PLL_GET_MODE,
 	},
 	{
-		.id = PM_REGISTER_ACCESS,
-		.api_id = PM_MMIO_WRITE,
+		.id = (uint8_t)PM_REGISTER_ACCESS,
+		.api_id = (uint8_t)PM_MMIO_WRITE,
 	},
 	{
-		.id = PM_REGISTER_ACCESS,
-		.api_id = PM_MMIO_READ,
+		.id = (uint8_t)PM_REGISTER_ACCESS,
+		.api_id = (uint8_t)PM_MMIO_READ,
 	},
 	{
-		.id = PM_FEATURE_CHECK,
-		.api_id = PM_FEATURE_CHECK,
+		.id = (uint8_t)PM_FEATURE_CHECK,
+		.api_id = (uint8_t)PM_FEATURE_CHECK,
 	},
 	{
-		.id = IOCTL_SET_TAPDELAY_BYPASS,
-		.api_id = PM_MMIO_WRITE,
+		.id = (uint8_t)IOCTL_SET_TAPDELAY_BYPASS,
+		.api_id = (uint8_t)PM_MMIO_WRITE,
 	},
 	{
-		.id = IOCTL_SD_DLL_RESET,
-		.api_id = PM_MMIO_WRITE,
+		.id = (uint8_t)IOCTL_SD_DLL_RESET,
+		.api_id = (uint8_t)PM_MMIO_WRITE,
 	},
 	{
-		.id = IOCTL_SET_SD_TAPDELAY,
-		.api_id = PM_MMIO_WRITE,
+		.id = (uint8_t)IOCTL_SET_SD_TAPDELAY,
+		.api_id = (uint8_t)PM_MMIO_WRITE,
 	},
 	{
-		.id = IOCTL_SET_SD_TAPDELAY,
-		.api_id = PM_MMIO_READ,
+		.id = (uint8_t)IOCTL_SET_SD_TAPDELAY,
+		.api_id = (uint8_t)PM_MMIO_READ,
 	},
 	{
-		.id = IOCTL_SET_PLL_FRAC_DATA,
-		.api_id = PM_PLL_SET_PARAMETER,
+		.id = (uint8_t)IOCTL_SET_PLL_FRAC_DATA,
+		.api_id = (uint8_t)PM_PLL_SET_PARAMETER,
 	},
 	{
-		.id = IOCTL_GET_PLL_FRAC_DATA,
-		.api_id = PM_PLL_GET_PARAMETER,
+		.id = (uint8_t)IOCTL_GET_PLL_FRAC_DATA,
+		.api_id = (uint8_t)PM_PLL_GET_PARAMETER,
 	},
 	{
-		.id = IOCTL_WRITE_GGS,
-		.api_id = PM_MMIO_WRITE,
+		.id = (uint8_t)IOCTL_WRITE_GGS,
+		.api_id = (uint8_t)PM_MMIO_WRITE,
 	},
 	{
-		.id = IOCTL_READ_GGS,
-		.api_id = PM_MMIO_READ,
+		.id = (uint8_t)IOCTL_READ_GGS,
+		.api_id = (uint8_t)PM_MMIO_READ,
 	},
 	{
-		.id = IOCTL_WRITE_PGGS,
-		.api_id = PM_MMIO_WRITE,
+		.id = (uint8_t)IOCTL_WRITE_PGGS,
+		.api_id = (uint8_t)PM_MMIO_WRITE,
 	},
 	{
-		.id = IOCTL_READ_PGGS,
-		.api_id = PM_MMIO_READ,
+		.id = (uint8_t)IOCTL_READ_PGGS,
+		.api_id = (uint8_t)PM_MMIO_READ,
 	},
 	{
-		.id = IOCTL_ULPI_RESET,
-		.api_id = PM_MMIO_WRITE,
+		.id = (uint8_t)IOCTL_ULPI_RESET,
+		.api_id = (uint8_t)PM_MMIO_WRITE,
 	},
 	{
-		.id = IOCTL_SET_BOOT_HEALTH_STATUS,
-		.api_id = PM_MMIO_WRITE,
+		.id = (uint8_t)IOCTL_SET_BOOT_HEALTH_STATUS,
+		.api_id = (uint8_t)PM_MMIO_WRITE,
 	},
 	{
-		.id = IOCTL_AFI,
-		.api_id = PM_MMIO_WRITE,
+		.id = (uint8_t)IOCTL_AFI,
+		.api_id = (uint8_t)PM_MMIO_WRITE,
 	},
 };
 
@@ -343,7 +343,7 @@
 
 	/* encode set Address into 1st bit of address */
 	encoded_address = address;
-	encoded_address |= !!set_address;
+	encoded_address |= (uint32_t)!!set_address;
 
 	/* Send request to the PMU to perform the wake of the PU */
 	PM_PACK_PAYLOAD5(payload, PM_REQ_WAKEUP, target, encoded_address,
@@ -440,7 +440,7 @@
 {
 	uint32_t payload[PAYLOAD_ARG_CNT];
 
-	if (type == PMF_SHUTDOWN_TYPE_SETSCOPE_ONLY) {
+	if (type == (uint32_t)PMF_SHUTDOWN_TYPE_SETSCOPE_ONLY) {
 		/* Setting scope for subsequent PSCI reboot or shutdown */
 		pm_shutdown_scope = subtype;
 		return PM_RET_SUCCESS;
@@ -710,7 +710,7 @@
 {
 	enum pm_ret_status ret = PM_RET_SUCCESS;
 	/* Return if interrupt is not from PMU */
-	if (!pm_ipi_irq_status(primary_proc)) {
+	if ((pm_ipi_irq_status(primary_proc) == 0U)) {
 		return ret;
 	}
 
@@ -770,7 +770,7 @@
 {
 	uint8_t i;
 	uint32_t version_type;
-	int ret;
+	enum pm_ret_status ret;
 
 	for (i = 0U; i < ARRAY_SIZE(api_dep_table); i++) {
 		if (api_dep_table[i].id == id) {
@@ -780,7 +780,7 @@
 
 			ret = fw_api_version(api_dep_table[i].api_id,
 					     &version_type, 1);
-			if (ret != PM_RET_SUCCESS) {
+			if (ret != (uint32_t)PM_RET_SUCCESS) {
 				return ret;
 			}
 
@@ -898,7 +898,7 @@
 	case PM_REGISTER_ACCESS:
 	case PM_FEATURE_CHECK:
 		status = check_api_dependency(api_id);
-		if (status != PM_RET_SUCCESS) {
+		if (status != (uint32_t)PM_RET_SUCCESS) {
 			return status;
 		}
 		return get_tfa_version_for_partial_apis(api_id, version);
@@ -925,13 +925,13 @@
 
 	/* Get API version implemented in TF-A */
 	status = feature_check_tfa(api_id, version, bit_mask);
-	if (status != PM_RET_ERROR_NO_FEATURE) {
+	if (status != (uint32_t)PM_RET_ERROR_NO_FEATURE) {
 		return status;
 	}
 
 	/* Get API version implemented by firmware and TF-A both */
 	status = feature_check_partial(api_id, version);
-	if (status != PM_RET_ERROR_NO_FEATURE) {
+	if (status != (uint32_t)PM_RET_ERROR_NO_FEATURE) {
 		return status;
 	}
 
@@ -940,20 +940,20 @@
 	/* IOCTL call may return failure whose ID is not implemented in
 	 * firmware but implemented in TF-A
 	 */
-	if ((api_id != PM_IOCTL) && (status != PM_RET_SUCCESS)) {
+	if ((api_id != (uint32_t)PM_IOCTL) && (status != PM_RET_SUCCESS)) {
 		return status;
 	}
 
 	*version = ret_payload[0];
 
 	/* Update IOCTL bit mask which are implemented in TF-A */
-	if ((api_id == PM_IOCTL) || (api_id == PM_GET_OP_CHARACTERISTIC)) {
-		if (len < 2) {
+	if ((api_id == (uint32_t)PM_IOCTL) || (api_id == (uint32_t)PM_GET_OP_CHARACTERISTIC)) {
+		if (len < 2U) {
 			return PM_RET_ERROR_ARGS;
 		}
 		bit_mask[0] = ret_payload[1];
 		bit_mask[1] = ret_payload[2];
-		if (api_id == PM_IOCTL) {
+		if (api_id == (uint32_t)PM_IOCTL) {
 			/* Get IOCTL's implemented by TF-A */
 			status = tfa_ioctl_bitmask(bit_mask);
 		}
@@ -1521,47 +1521,47 @@
 		pm_clock_get_name(arg1, (char *)data);
 		break;
 	case PM_QID_CLOCK_GET_TOPOLOGY:
-		data[0] = pm_clock_get_topology(arg1, arg2, &data[1]);
+		data[0] = (uint32_t)pm_clock_get_topology(arg1, arg2, &data[1]);
 		break;
 	case PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS:
-		data[0] = pm_clock_get_fixedfactor_params(arg1, &data[1],
+		data[0] = (uint32_t)pm_clock_get_fixedfactor_params(arg1, &data[1],
 							  &data[2]);
 		break;
 	case PM_QID_CLOCK_GET_PARENTS:
-		data[0] = pm_clock_get_parents(arg1, arg2, &data[1]);
+		data[0] = (uint32_t)pm_clock_get_parents(arg1, arg2, &data[1]);
 		break;
 	case PM_QID_CLOCK_GET_ATTRIBUTES:
-		data[0] = pm_clock_get_attributes(arg1, &data[1]);
+		data[0] = (uint32_t)pm_clock_get_attributes(arg1, &data[1]);
 		break;
 	case PM_QID_PINCTRL_GET_NUM_PINS:
-		data[0] = pm_pinctrl_get_num_pins(&data[1]);
+		data[0] = (uint32_t)pm_pinctrl_get_num_pins(&data[1]);
 		break;
 	case PM_QID_PINCTRL_GET_NUM_FUNCTIONS:
-		data[0] = pm_pinctrl_get_num_functions(&data[1]);
+		data[0] = (uint32_t)pm_pinctrl_get_num_functions(&data[1]);
 		break;
 	case PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS:
-		data[0] = pm_pinctrl_get_num_function_groups(arg1, &data[1]);
+		data[0] = (uint32_t)pm_pinctrl_get_num_function_groups(arg1, &data[1]);
 		break;
 	case PM_QID_PINCTRL_GET_FUNCTION_NAME:
 		pm_pinctrl_get_function_name(arg1, (char *)data);
 		break;
 	case PM_QID_PINCTRL_GET_FUNCTION_GROUPS:
-		data[0] = pm_pinctrl_get_function_groups(arg1, arg2,
+		data[0] = (uint32_t)pm_pinctrl_get_function_groups(arg1, arg2,
 							 (uint16_t *)&data[1]);
 		break;
 	case PM_QID_PINCTRL_GET_PIN_GROUPS:
-		data[0] = pm_pinctrl_get_pin_groups(arg1, arg2,
+		data[0] = (uint32_t)pm_pinctrl_get_pin_groups(arg1, arg2,
 						    (uint16_t *)&data[1]);
 		break;
 	case PM_QID_CLOCK_GET_NUM_CLOCKS:
-		data[0] = pm_clock_get_num_clocks(&data[1]);
+		data[0] = (uint32_t)pm_clock_get_num_clocks(&data[1]);
 		break;
 
 	case PM_QID_CLOCK_GET_MAX_DIVISOR:
-		data[0] = pm_clock_get_max_divisor(arg1, arg2, &data[1]);
+		data[0] = (uint32_t)pm_clock_get_max_divisor(arg1, (uint8_t)arg2, &data[1]);
 		break;
 	default:
-		data[0] = PM_RET_ERROR_ARGS;
+		data[0] = (uint32_t)PM_RET_ERROR_ARGS;
 		WARN("Unimplemented query service call: 0x%x\n", qid);
 		break;
 	}
diff --git a/plat/xilinx/zynqmp/pm_service/zynqmp_pm_defs.h b/plat/xilinx/zynqmp/pm_service/zynqmp_pm_defs.h
index af75c5c..c7d2b2c 100644
--- a/plat/xilinx/zynqmp/pm_service/zynqmp_pm_defs.h
+++ b/plat/xilinx/zynqmp/pm_service/zynqmp_pm_defs.h
@@ -187,9 +187,9 @@
  *
  */
 enum pm_shutdown_subtype {
-	PMF_SHUTDOWN_SUBTYPE_SUBSYSTEM,
-	PMF_SHUTDOWN_SUBTYPE_PS_ONLY,
-	PMF_SHUTDOWN_SUBTYPE_SYSTEM,
+	PMF_SHUTDOWN_SUBTYPE_SUBSYSTEM  = (0U),
+	PMF_SHUTDOWN_SUBTYPE_PS_ONLY = (1U),
+	PMF_SHUTDOWN_SUBTYPE_SYSTEM = (2U),
 };
 
 /**
diff --git a/plat/xilinx/zynqmp/pm_service/zynqmp_pm_svc_main.c b/plat/xilinx/zynqmp/pm_service/zynqmp_pm_svc_main.c
index 738699e..21435c6 100644
--- a/plat/xilinx/zynqmp/pm_service/zynqmp_pm_svc_main.c
+++ b/plat/xilinx/zynqmp/pm_service/zynqmp_pm_svc_main.c
@@ -253,7 +253,7 @@
 		ret = status;
 	}
 
-	pm_up = !status;
+	pm_up = (status == 0);
 
 	return ret;
 }
@@ -322,7 +322,7 @@
 		uint32_t set_addr = pm_arg[1] & 0x1U;
 		uint64_t address = (uint64_t)pm_arg[2] << 32U;
 
-		address |= pm_arg[1] & (~0x1U);
+		address |= (uint64_t)(pm_arg[1] & (~0x1U));
 		ret = pm_req_wakeup(pm_arg[0], set_addr, address,
 				    pm_arg[3]);
 		SMC_RET1(handle, (uint64_t)ret);
@@ -354,7 +354,7 @@
 		SMC_RET1(handle, (uint64_t)ret);
 
 	case PM_GET_API_VERSION:
-		if (ipi_irq_flag == 0U) {
+		if ((uint32_t)ipi_irq_flag == 0U) {
 			/*
 			 * Enable IPI IRQ
 			 * assume the rich OS is OK to handle callback IRQs now.
@@ -560,7 +560,7 @@
 		uint32_t bit_mask[2] = {0};
 
 		ret = pm_feature_check(pm_arg[0], &version_type, bit_mask,
-				       ARRAY_SIZE(bit_mask));
+				       (uint8_t)ARRAY_SIZE(bit_mask));
 		SMC_RET2(handle, ((uint64_t)ret | ((uint64_t)version_type << 32U)),
 			 ((uint64_t)bit_mask[0] | ((uint64_t)bit_mask[1] << 32U)));
 	}