feat(mt8189): disable L3C shared SRAM if the bootloader is coreboot
The coreboot of MT8189 does not disable the L3C shared SRAM because the
ramstage still needs access to it. Therefore, we disable it at the
start of ATF.
Change-Id: If87223a1f41afd639859ff0ce80d4e64a9e02a2e
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
diff --git a/plat/mediatek/common/mtk_bl31_setup.c b/plat/mediatek/common/mtk_bl31_setup.c
index 0d264b9..a6d1e73 100644
--- a/plat/mediatek/common/mtk_bl31_setup.c
+++ b/plat/mediatek/common/mtk_bl31_setup.c
@@ -24,6 +24,9 @@
#endif
/* MTK headers */
+#if CONFIG_MTK_DISABLE_CACHE_AS_RAM
+#include <cache_ops.h>
+#endif
#if MTK_SIP_KERNEL_BOOT_ENABLE
#include <cold_boot.h>
#endif
@@ -101,6 +104,9 @@
u_register_t hw_config, u_register_t plat_params_from_bl2)
{
+#if CONFIG_MTK_DISABLE_CACHE_AS_RAM
+ disable_cache_as_ram();
+#endif
#if COREBOOT
static console_t console;