feat(mt8189): disable L3C shared SRAM if the bootloader is coreboot
The coreboot of MT8189 does not disable the L3C shared SRAM because the
ramstage still needs access to it. Therefore, we disable it at the
start of ATF.
Change-Id: If87223a1f41afd639859ff0ce80d4e64a9e02a2e
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
diff --git a/plat/mediatek/common/cache_ops.h b/plat/mediatek/common/cache_ops.h
new file mode 100644
index 0000000..aeec6be
--- /dev/null
+++ b/plat/mediatek/common/cache_ops.h
@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _CACHES_OPS_H_
+#define _CACHES_OPS_H_
+
+void disable_cache_as_ram(void);
+
+#endif /* _CACHES_OPS_H_ */