feat(mt8189): disable L3C shared SRAM if the bootloader is coreboot
The coreboot of MT8189 does not disable the L3C shared SRAM because the
ramstage still needs access to it. Therefore, we disable it at the
start of ATF.
Change-Id: If87223a1f41afd639859ff0ce80d4e64a9e02a2e
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
diff --git a/plat/mediatek/common/cache_ops.c b/plat/mediatek/common/cache_ops.c
new file mode 100644
index 0000000..df43667
--- /dev/null
+++ b/plat/mediatek/common/cache_ops.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch_helpers.h>
+#include <lib/mmio.h>
+
+#include <cache_ops.h>
+#include <mcucfg.h>
+
+#define L3_SHARE_EN 9
+#define L3_SHARE_PRE_EN 8
+
+void disable_cache_as_ram(void)
+{
+ unsigned long v;
+
+ mmio_clrbits_32(MP0_CLUSTER_CFG0, 1 << L3_SHARE_EN);
+ dsb();
+
+ __asm__ volatile ("mrs %0, S3_0_C15_C3_5" : "=r" (v));
+ v |= (0xf << 4);
+ __asm__ volatile ("msr S3_0_C15_C3_5, %0" : : "r" (v));
+ dsb();
+
+ do {
+ __asm__ volatile ("mrs %0, S3_0_C15_C3_7" : "=r" (v));
+ } while (((v >> 0x4) & 0xf) != 0xf);
+
+ mmio_clrbits_32(MP0_CLUSTER_CFG0, 1 << L3_SHARE_PRE_EN);
+ dsb();
+}