feat(mt8189): disable L3C shared SRAM if the bootloader is coreboot
The coreboot of MT8189 does not disable the L3C shared SRAM because the
ramstage still needs access to it. Therefore, we disable it at the
start of ATF.
Change-Id: If87223a1f41afd639859ff0ce80d4e64a9e02a2e
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
diff --git a/plat/mediatek/build_helpers/options.mk b/plat/mediatek/build_helpers/options.mk
index c55f50e..080e735 100644
--- a/plat/mediatek/build_helpers/options.mk
+++ b/plat/mediatek/build_helpers/options.mk
@@ -9,6 +9,7 @@
CONFIG_MTK_CPU_PM_ARCH \
CONFIG_MTK_CPU_PM_SUPPORT \
CONFIG_MTK_CPU_SUSPEND_EN \
+ CONFIG_MTK_DISABLE_CACHE_AS_RAM \
CONFIG_MTK_MCUSYS \
CONFIG_MTK_MTCMOS \
CONFIG_MTK_PM_ARCH \
diff --git a/plat/mediatek/common/cache_ops.c b/plat/mediatek/common/cache_ops.c
new file mode 100644
index 0000000..df43667
--- /dev/null
+++ b/plat/mediatek/common/cache_ops.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch_helpers.h>
+#include <lib/mmio.h>
+
+#include <cache_ops.h>
+#include <mcucfg.h>
+
+#define L3_SHARE_EN 9
+#define L3_SHARE_PRE_EN 8
+
+void disable_cache_as_ram(void)
+{
+ unsigned long v;
+
+ mmio_clrbits_32(MP0_CLUSTER_CFG0, 1 << L3_SHARE_EN);
+ dsb();
+
+ __asm__ volatile ("mrs %0, S3_0_C15_C3_5" : "=r" (v));
+ v |= (0xf << 4);
+ __asm__ volatile ("msr S3_0_C15_C3_5, %0" : : "r" (v));
+ dsb();
+
+ do {
+ __asm__ volatile ("mrs %0, S3_0_C15_C3_7" : "=r" (v));
+ } while (((v >> 0x4) & 0xf) != 0xf);
+
+ mmio_clrbits_32(MP0_CLUSTER_CFG0, 1 << L3_SHARE_PRE_EN);
+ dsb();
+}
diff --git a/plat/mediatek/common/cache_ops.h b/plat/mediatek/common/cache_ops.h
new file mode 100644
index 0000000..aeec6be
--- /dev/null
+++ b/plat/mediatek/common/cache_ops.h
@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _CACHES_OPS_H_
+#define _CACHES_OPS_H_
+
+void disable_cache_as_ram(void);
+
+#endif /* _CACHES_OPS_H_ */
diff --git a/plat/mediatek/common/mtk_bl31_setup.c b/plat/mediatek/common/mtk_bl31_setup.c
index 0d264b9..a6d1e73 100644
--- a/plat/mediatek/common/mtk_bl31_setup.c
+++ b/plat/mediatek/common/mtk_bl31_setup.c
@@ -24,6 +24,9 @@
#endif
/* MTK headers */
+#if CONFIG_MTK_DISABLE_CACHE_AS_RAM
+#include <cache_ops.h>
+#endif
#if MTK_SIP_KERNEL_BOOT_ENABLE
#include <cold_boot.h>
#endif
@@ -101,6 +104,9 @@
u_register_t hw_config, u_register_t plat_params_from_bl2)
{
+#if CONFIG_MTK_DISABLE_CACHE_AS_RAM
+ disable_cache_as_ram();
+#endif
#if COREBOOT
static console_t console;
diff --git a/plat/mediatek/mt8189/plat_config.mk b/plat/mediatek/mt8189/plat_config.mk
index 6b4064a..f06555b 100644
--- a/plat/mediatek/mt8189/plat_config.mk
+++ b/plat/mediatek/mt8189/plat_config.mk
@@ -21,6 +21,7 @@
#
MCUSYS_VERSION := v1
PLAT_EXTRA_RODATA_INCLUDES := 1
+CONFIG_MTK_DISABLE_CACHE_AS_RAM := $(COREBOOT)
# Configs for A78 and A55
CTX_INCLUDE_AARCH32_REGS := 0
diff --git a/plat/mediatek/mt8189/platform.mk b/plat/mediatek/mt8189/platform.mk
index 7e40146..238c76d 100644
--- a/plat/mediatek/mt8189/platform.mk
+++ b/plat/mediatek/mt8189/platform.mk
@@ -52,6 +52,10 @@
$(MTK_PLAT)/$(MTK_SOC)/drivers/gpio/mtgpio.c \
$(MTK_PLAT)/$(MTK_SOC)/plat_mmap.c
+ifeq (${CONFIG_MTK_DISABLE_CACHE_AS_RAM}, 1)
+BL31_SOURCES += ${MTK_PLAT}/common/cache_ops.c
+endif
+
include plat/mediatek/build_helpers/mtk_build_helpers_epilogue.mk
include lib/coreboot/coreboot.mk