feat(cm): handle asymmetry for FEAT_TCR2
With introduction of FEAT_STATE_CHECK_ASYMMETRIC, the asymmetry of cores
can be handled. FEAT_TCR2 is one of the features which can be
asymmetric across cores and the respective support is added here.
Adding a function to handle this asymmetry by re-visting the
feature presence on running core.
There are two possible cases:
- If the primary core has the feature and secondary does not have it
then the feature is disabled.
- If the primary does not have the feature and secondary has it then,
the feature need to be enabled in secondary cores.
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: I73a70891d52268ddfa4effe40edf04115f5821ca
diff --git a/lib/extensions/tcr/tcr2.c b/lib/extensions/tcr/tcr2.c
new file mode 100644
index 0000000..70bc5f8
--- /dev/null
+++ b/lib/extensions/tcr/tcr2.c
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <arch_features.h>
+#include <arch_helpers.h>
+#include <lib/extensions/tcr2.h>
+
+void tcr2_enable(cpu_context_t *ctx)
+{
+ u_register_t reg;
+ el3_state_t *state;
+
+ state = get_el3state_ctx(ctx);
+
+ /* Set the TCR2EN bit in SCR_EL3 to enable access to TCR2_EL1,
+ * and TCR2_EL2 registers .
+ */
+
+ reg = read_ctx_reg(state, CTX_SCR_EL3);
+ reg |= SCR_TCR2EN_BIT;
+ write_ctx_reg(state, CTX_SCR_EL3, reg);
+}
+
+void tcr2_disable(cpu_context_t *ctx)
+{
+ u_register_t reg;
+ el3_state_t *state;
+
+ state = get_el3state_ctx(ctx);
+
+ /* Clear the TCR2EN bit in SCR_EL3 to disable access to TCR2_EL1,
+ * and TCR2_EL2 registers .
+ */
+
+ reg = read_ctx_reg(state, CTX_SCR_EL3);
+ reg &= ~SCR_TCR2EN_BIT;
+ write_ctx_reg(state, CTX_SCR_EL3, reg);
+}