feat(ethos-n)!: add support for SMMU streams
The Arm(R) Ethos(TM)-N NPU driver now supports configuring the SMMU
streams that the NPU shall use and will therefore no longer delegate
access to these registers to the non-secure world. In order for the
driver to support this, the device tree parsing has been updated to
support parsing the allocators used by the NPU and what SMMU stream that
is associated with each allocator.
To keep track of what NPU device each allocator is associated with, the
resulting config from the device tree parsing will now group the NPU
cores and allocators into their respective NPU device.
The SMC API has been changed to allow the caller to specify what
allocator the NPU shall be configured to use and the API version has
been bumped to indicate this change.
Signed-off-by: Mikael Olsson <mikael.olsson@arm.com>
Change-Id: I6ac43819133138614e3f55a014e93466fe3d5277
diff --git a/include/drivers/arm/ethosn.h b/include/drivers/arm/ethosn.h
index 9310733..dbaf16c 100644
--- a/include/drivers/arm/ethosn.h
+++ b/include/drivers/arm/ethosn.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2022, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -38,7 +38,7 @@
#define is_ethosn_fid(_fid) (((_fid) & ETHOSN_FID_MASK) == ETHOSN_FID_VALUE)
/* Service version */
-#define ETHOSN_VERSION_MAJOR U(1)
+#define ETHOSN_VERSION_MAJOR U(2)
#define ETHOSN_VERSION_MINOR U(0)
/* Return codes for function calls */
@@ -48,10 +48,11 @@
/* -3 Reserved for INVALID_PARAMETER */
#define ETHOSN_FAILURE -4
#define ETHOSN_UNKNOWN_CORE_ADDRESS -5
+#define ETHOSN_UNKNOWN_ALLOCATOR_IDX -6
uintptr_t ethosn_smc_handler(uint32_t smc_fid,
u_register_t core_addr,
- u_register_t x2,
+ u_register_t asset_alloc_idx,
u_register_t x3,
u_register_t x4,
void *cookie,
diff --git a/include/plat/arm/common/arm_sip_svc.h b/include/plat/arm/common/arm_sip_svc.h
index 2eeed95..025d10e 100644
--- a/include/plat/arm/common/arm_sip_svc.h
+++ b/include/plat/arm/common/arm_sip_svc.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2019,2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019,2021-2022, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -26,7 +26,7 @@
/* DEBUGFS_SMC_64 0xC2000030U */
/*
- * Arm Ethos-N NPU SiP SMC function IDs
+ * Arm(R) Ethos(TM)-N NPU SiP SMC function IDs
* 0xC2000050-0xC200005F
* 0x82000050-0x8200005F
*/
diff --git a/include/plat/arm/common/fconf_ethosn_getter.h b/include/plat/arm/common/fconf_ethosn_getter.h
index fcdc31f..5b9a7ed 100644
--- a/include/plat/arm/common/fconf_ethosn_getter.h
+++ b/include/plat/arm/common/fconf_ethosn_getter.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2022, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -8,27 +8,52 @@
#define FCONF_ETHOSN_GETTER_H
#include <assert.h>
+#include <stdbool.h>
#include <lib/fconf/fconf.h>
#define hw_config__ethosn_config_getter(prop) ethosn_config.prop
-#define hw_config__ethosn_core_addr_getter(idx) __extension__ ({ \
- assert(idx < ethosn_config.num_cores); \
- ethosn_config.core[idx].addr; \
+#define hw_config__ethosn_device_getter(dev_idx) __extension__ ({ \
+ assert(dev_idx < ethosn_config.num_devices); \
+ ðosn_config.devices[dev_idx]; \
})
-#define ETHOSN_STATUS_DISABLED U(0)
-#define ETHOSN_STATUS_ENABLED U(1)
+#define ETHOSN_DEV_NUM_MAX U(2)
+#define ETHOSN_DEV_CORE_NUM_MAX U(8)
+#define ETHOSN_DEV_ASSET_ALLOCATOR_NUM_MAX U(16)
-#define ETHOSN_CORE_NUM_MAX U(64)
+struct ethosn_allocator_t {
+ uint32_t stream_id;
+};
+
+struct ethosn_main_allocator_t {
+ struct ethosn_allocator_t firmware;
+ struct ethosn_allocator_t working_data;
+};
+
+struct ethosn_asset_allocator_t {
+ struct ethosn_allocator_t command_stream;
+ struct ethosn_allocator_t weight_data;
+ struct ethosn_allocator_t buffer_data;
+ struct ethosn_allocator_t intermediate_data;
+};
struct ethosn_core_t {
uint64_t addr;
+ struct ethosn_main_allocator_t main_allocator;
};
-struct ethosn_config_t {
+struct ethosn_device_t {
+ bool has_reserved_memory;
uint32_t num_cores;
- struct ethosn_core_t core[ETHOSN_CORE_NUM_MAX];
+ struct ethosn_core_t cores[ETHOSN_DEV_CORE_NUM_MAX];
+ uint32_t num_allocators;
+ struct ethosn_asset_allocator_t asset_allocators[ETHOSN_DEV_ASSET_ALLOCATOR_NUM_MAX];
+};
+
+struct ethosn_config_t {
+ uint32_t num_devices;
+ struct ethosn_device_t devices[ETHOSN_DEV_NUM_MAX];
};
int fconf_populate_arm_ethosn(uintptr_t config);