Merge "uniphier: call uniphier_scp_is_running() only when on-chip STM is supported" into integration
diff --git a/Makefile b/Makefile
index 073c2ed..42fdb73 100644
--- a/Makefile
+++ b/Makefile
@@ -736,6 +736,7 @@
$(eval $(call assert_boolean,RESET_TO_BL31))
$(eval $(call assert_boolean,SAVE_KEYS))
$(eval $(call assert_boolean,SEPARATE_CODE_AND_RODATA))
+$(eval $(call assert_boolean,SEPARATE_NOBITS_REGION))
$(eval $(call assert_boolean,SPIN_ON_BL1_EXIT))
$(eval $(call assert_boolean,SPM_MM))
$(eval $(call assert_boolean,TRUSTED_BOARD_BOOT))
@@ -800,6 +801,7 @@
$(eval $(call add_define,RAS_EXTENSION))
$(eval $(call add_define,RESET_TO_BL31))
$(eval $(call add_define,SEPARATE_CODE_AND_RODATA))
+$(eval $(call add_define,SEPARATE_NOBITS_REGION))
$(eval $(call add_define,RECLAIM_INIT_CODE))
$(eval $(call add_define,SPD_${SPD}))
$(eval $(call add_define,SPIN_ON_BL1_EXIT))
diff --git a/bl31/bl31.ld.S b/bl31/bl31.ld.S
index a598e59..42227f0 100644
--- a/bl31/bl31.ld.S
+++ b/bl31/bl31.ld.S
@@ -15,6 +15,11 @@
MEMORY {
RAM (rwx): ORIGIN = BL31_BASE, LENGTH = BL31_LIMIT - BL31_BASE
+#if SEPARATE_NOBITS_REGION
+ NOBITS (rw!a): ORIGIN = BL31_NOBITS_BASE, LENGTH = BL31_NOBITS_LIMIT - BL31_NOBITS_BASE
+#else
+#define NOBITS RAM
+#endif
}
#ifdef PLAT_EXTRA_LD_SCRIPT
@@ -198,11 +203,28 @@
ASSERT(. <= BL31_PROGBITS_LIMIT, "BL31 progbits has exceeded its limit.")
#endif
+#if SEPARATE_NOBITS_REGION
+ /*
+ * Define a linker symbol to mark end of the RW memory area for this
+ * image.
+ */
+ __RW_END__ = .;
+ __BL31_END__ = .;
+
+ ASSERT(. <= BL31_LIMIT, "BL31 image has exceeded its limit.")
+
+ . = BL31_NOBITS_BASE;
+ ASSERT(. == ALIGN(PAGE_SIZE),
+ "BL31 NOBITS base address is not aligned on a page boundary.")
+
+ __NOBITS_START__ = .;
+#endif
+
stacks (NOLOAD) : {
__STACKS_START__ = .;
*(tzfw_normal_stacks)
__STACKS_END__ = .;
- } >RAM
+ } >NOBITS
/*
* The .bss section gets initialised to 0 at runtime.
@@ -262,7 +284,7 @@
__PMF_TIMESTAMP_END__ = .;
#endif /* ENABLE_PMF */
__BSS_END__ = .;
- } >RAM
+ } >NOBITS
/*
* The xlat_table section is for full, aligned page tables (4K).
@@ -272,7 +294,7 @@
*/
xlat_table (NOLOAD) : {
*(xlat_table)
- } >RAM
+ } >NOBITS
#if USE_COHERENT_MEM
/*
@@ -298,9 +320,18 @@
*/
. = ALIGN(PAGE_SIZE);
__COHERENT_RAM_END__ = .;
- } >RAM
+ } >NOBITS
#endif
+#if SEPARATE_NOBITS_REGION
+ /*
+ * Define a linker symbol to mark end of the NOBITS memory area for this
+ * image.
+ */
+ __NOBITS_END__ = .;
+
+ ASSERT(. <= BL31_NOBITS_LIMIT, "BL31 NOBITS region has exceeded its limit.")
+#else
/*
* Define a linker symbol to mark end of the RW memory area for this
* image.
@@ -309,4 +340,5 @@
__BL31_END__ = .;
ASSERT(. <= BL31_LIMIT, "BL31 image has exceeded its limit.")
+#endif
}
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index 891703b..7fa027f 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -227,6 +227,12 @@
- ``ERRATA_A76_1275112``: This applies errata 1275112 workaround to Cortex-A76
CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
+For Hercules, the following errata build flags are defined :
+
+- ``ERRATA_HERCULES_1688305``: This applies errata 1688305 workaround to
+ Hercules CPU. This needs to be enabled only for revision r0p0 - r1p0 of
+ the CPU.
+
For Neoverse N1, the following errata build flags are defined :
- ``ERRATA_N1_1073348``: This applies errata 1073348 workaround to Neoverse-N1
diff --git a/docs/design/firmware-design.rst b/docs/design/firmware-design.rst
index cae94b5..5fc1335 100644
--- a/docs/design/firmware-design.rst
+++ b/docs/design/firmware-design.rst
@@ -1500,6 +1500,11 @@
this NOBITS section, making the image unnecessarily bigger. Smaller images
allow faster loading from the FIP to the main memory.
+For BL31, a platform can specify an alternate location for NOBITS sections
+(other than immediately following PROGBITS sections) by setting
+``SEPARATE_NOBITS_REGION`` to 1 and defining ``BL31_NOBITS_BASE`` and
+``BL31_NOBITS_LIMIT``.
+
Linker scripts and symbols
~~~~~~~~~~~~~~~~~~~~~~~~~~
diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst
index 37c28a5..d7bb044 100644
--- a/docs/getting_started/build-options.rst
+++ b/docs/getting_started/build-options.rst
@@ -491,6 +491,13 @@
pages" section in :ref:`Firmware Design`. This flag is disabled by default and
affects all BL images.
+- ``SEPARATE_NOBITS_REGION``: Setting this option to ``1`` allows the NOBITS
+ sections of BL31 (.bss, stacks, page tables, and coherent memory) to be
+ allocated in RAM discontiguous from the loaded firmware image. When set, the
+ platform is expected to provide definitons for ``BL31_NOBITS_BASE`` and
+ ``BL31_NOBITS_LIMIT``. When the option is ``0`` (the default), NOBITS
+ sections are placed in RAM immediately following the loaded firmware image.
+
- ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A.
This build option is only valid if ``ARCH=aarch64``. The value should be
the path to the directory containing the SPD source, relative to
diff --git a/docs/getting_started/initial-build.rst b/docs/getting_started/initial-build.rst
index 41cd4d1..893aba2 100644
--- a/docs/getting_started/initial-build.rst
+++ b/docs/getting_started/initial-build.rst
@@ -8,13 +8,13 @@
.. code:: shell
- export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
+ export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-none-elf-
For AArch32:
.. code:: shell
- export CROSS_COMPILE=<path-to-aarch32-gcc>/bin/arm-eabi-
+ export CROSS_COMPILE=<path-to-aarch32-gcc>/bin/arm-none-eabi-
It is possible to build TF-A using Clang or Arm Compiler 6. To do so
``CC`` needs to point to the clang or armclang binary, which will
@@ -32,7 +32,7 @@
.. code:: shell
- export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
+ export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-none-elf-
make CC=<path-to-armclang>/bin/armclang PLAT=<platform> all
Clang will be selected when the base name of the path assigned to ``CC``
@@ -43,7 +43,7 @@
.. code:: shell
- export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
+ export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-none-elf-
make CC=<path-to-clang>/bin/clang PLAT=<platform> all
- Change to the root directory of the TF-A source tree and build.
diff --git a/docs/getting_started/porting-guide.rst b/docs/getting_started/porting-guide.rst
index 17fd546..bb14717 100644
--- a/docs/getting_started/porting-guide.rst
+++ b/docs/getting_started/porting-guide.rst
@@ -1999,7 +1999,7 @@
::
- Argument : unsigned int, const psci_power_state_t *, int
+ Argument : unsigned int, const psci_power_state_t *, unsigned int
Return : u_register_t
This is an optional interface that is is invoked after resuming from a low power
diff --git a/docs/getting_started/prerequisites.rst b/docs/getting_started/prerequisites.rst
index 27ad0ed..3e0c8ff 100644
--- a/docs/getting_started/prerequisites.rst
+++ b/docs/getting_started/prerequisites.rst
@@ -26,7 +26,7 @@
|TF-A| can be built with any of the following *cross-compiler* toolchains that
target the Armv7-A or Armv8-A architectures:
-- GCC >= 8.3-2019.03 (from the `Arm Developer website`_)
+- GCC >= 9.2-2019.12 (from the `Arm Developer website`_)
- Clang >= 4.0
- Arm Compiler >= 6.0
diff --git a/docs/plat/arm/fvp/index.rst b/docs/plat/arm/fvp/index.rst
index b6396b9..37010e1 100644
--- a/docs/plat/arm/fvp/index.rst
+++ b/docs/plat/arm/fvp/index.rst
@@ -223,7 +223,7 @@
.. code:: shell
- CROSS_COMPILE=aarch64-linux-gnu- \
+ CROSS_COMPILE=aarch64-none-elf- \
make PLAT=fvp DEBUG=1 \
RESET_TO_BL31=1 \
ARM_LINUX_KERNEL_AS_BL33=1 \
diff --git a/docs/plat/arm/juno/index.rst b/docs/plat/arm/juno/index.rst
index 6429ede..cf328fa 100644
--- a/docs/plat/arm/juno/index.rst
+++ b/docs/plat/arm/juno/index.rst
@@ -136,7 +136,7 @@
.. code:: shell
- export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
+ export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-none-elf-
- The following parameters should be used to build BL1 and BL2 in AArch64
and point to the BL32 file.
diff --git a/docs/plat/rpi4.rst b/docs/plat/rpi4.rst
index 0f529c1..beb0227 100644
--- a/docs/plat/rpi4.rst
+++ b/docs/plat/rpi4.rst
@@ -24,11 +24,10 @@
CROSS_COMPILE=aarch64-linux-gnu- make PLAT=rpi4 DEBUG=1
-Copy the generated build/rpi4/debug/bl31.bin to the SD card, either
-renaming it to ``armstub8.bin`` or adding an entry starting with ``armstub=``,
-then followed by the respective file name to ``config.txt``.
-You should have AArch64 code in the file loaded as the "kernel", as BL31
-will drop into AArch64/EL2 to the respective load address.
+Copy the generated build/rpi4/debug/bl31.bin to the SD card, adding an entry
+starting with ``armstub=``, then followed by the respective file name to
+``config.txt``. You should have AArch64 code in the file loaded as the
+"kernel", as BL31 will drop into AArch64/EL2 to the respective load address.
arm64 Linux kernels are known to work this way.
Other options that should be set in ``config.txt`` to properly boot 64-bit
diff --git a/drivers/arm/css/scp/css_pm_scmi.c b/drivers/arm/css/scp/css_pm_scmi.c
index 8dbefa1..b945cda 100644
--- a/drivers/arm/css/scp/css_pm_scmi.c
+++ b/drivers/arm/css/scp/css_pm_scmi.c
@@ -186,7 +186,7 @@
void css_scp_on(u_register_t mpidr)
{
unsigned int lvl = 0;
- int ret, core_pos;
+ int core_pos, ret;
uint32_t scmi_pwr_state = 0;
for (; lvl <= PLAT_MAX_PWR_LVL; lvl++)
@@ -196,7 +196,8 @@
SCMI_SET_PWR_STATE_MAX_PWR_LVL(scmi_pwr_state, lvl - 1);
core_pos = plat_core_pos_by_mpidr(mpidr);
- assert(core_pos >= 0 && core_pos < PLATFORM_CORE_COUNT);
+ assert((core_pos >= 0) &&
+ (((unsigned int)core_pos) < PLATFORM_CORE_COUNT));
ret = scmi_pwr_state_set(scmi_handle,
plat_css_core_pos_to_scmi_dmn_id_map[core_pos],
diff --git a/drivers/arm/scu/scu.c b/drivers/arm/scu/scu.c
new file mode 100644
index 0000000..aceac92
--- /dev/null
+++ b/drivers/arm/scu/scu.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <drivers/arm/scu.h>
+#include <lib/mmio.h>
+#include <plat/common/platform.h>
+#include <stdint.h>
+
+/*******************************************************************************
+ * Turn ON snoop control unit. This is needed to synchronize the data between
+ * CPU's.
+ ******************************************************************************/
+void enable_snoop_ctrl_unit(uintptr_t base)
+{
+ uint32_t scu_ctrl;
+
+ INFO("[SCU]: enabling snoop control unit ... \n");
+
+ assert(base != 0U);
+ scu_ctrl = mmio_read_32(base + SCU_CTRL_REG);
+
+ /* already enabled? */
+ if ((scu_ctrl & SCU_ENABLE_BIT) != 0) {
+ return;
+ }
+
+ scu_ctrl |= SCU_ENABLE_BIT;
+ mmio_write_32(base + SCU_CTRL_REG, scu_ctrl);
+}
+
+/*******************************************************************************
+ * Snoop Control Unit configuration register. This is read-only register and
+ * contains information such as
+ * - number of CPUs present
+ * - is a particular CPU operating in SMP mode or AMP mode
+ * - data cache size of a particular CPU
+ * - does SCU has ACP port
+ * - is L2CPRESENT
+ * NOTE: user of this API should interpert the bits in this register according
+ * to the TRM
+ ******************************************************************************/
+uint32_t read_snoop_ctrl_unit_cfg(uintptr_t base)
+{
+ assert(base != 0U);
+
+ return mmio_read_32(base + SCU_CFG_REG);
+}
diff --git a/drivers/auth/auth_mod.c b/drivers/auth/auth_mod.c
index a6538c4..3fb2d1a 100644
--- a/drivers/auth/auth_mod.c
+++ b/drivers/auth/auth_mod.c
@@ -30,9 +30,6 @@
#pragma weak plat_set_nv_ctr2
-/* Pointer to CoT */
-extern const auth_img_desc_t *const *const cot_desc_ptr;
-extern unsigned int auth_img_flags[MAX_NUMBER_IDS];
static int cmp_auth_param_type_desc(const auth_param_type_desc_t *a,
const auth_param_type_desc_t *b)
diff --git a/drivers/staging/renesas/rcar/ddr/boot_init_dram.h b/drivers/renesas/rcar/ddr/boot_init_dram.h
similarity index 100%
rename from drivers/staging/renesas/rcar/ddr/boot_init_dram.h
rename to drivers/renesas/rcar/ddr/boot_init_dram.h
diff --git a/drivers/renesas/rcar/ddr/ddr.mk b/drivers/renesas/rcar/ddr/ddr.mk
new file mode 100644
index 0000000..c26993d
--- /dev/null
+++ b/drivers/renesas/rcar/ddr/ddr.mk
@@ -0,0 +1,17 @@
+#
+# Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+ifeq (${RCAR_LSI},${RCAR_E3})
+ include drivers/renesas/rcar/ddr/ddr_a/ddr_a.mk
+ BL2_SOURCES += drivers/renesas/rcar/ddr/dram_sub_func.c
+else ifeq (${RCAR_LSI},${RCAR_D3})
+ include drivers/renesas/rcar/ddr/ddr_a/ddr_a.mk
+else ifeq (${RCAR_LSI},${RCAR_V3M})
+ include drivers/renesas/rcar/ddr/ddr_a/ddr_a.mk
+else
+ include drivers/renesas/rcar/ddr/ddr_b/ddr_b.mk
+ BL2_SOURCES += drivers/renesas/rcar/ddr/dram_sub_func.c
+endif
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef.h b/drivers/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef.h
similarity index 100%
rename from drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef.h
rename to drivers/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef.h
diff --git a/drivers/renesas/rcar/ddr/ddr_a/ddr_a.mk b/drivers/renesas/rcar/ddr/ddr_a/ddr_a.mk
new file mode 100644
index 0000000..7882558
--- /dev/null
+++ b/drivers/renesas/rcar/ddr/ddr_a/ddr_a.mk
@@ -0,0 +1,13 @@
+#
+# Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+ifeq (${RCAR_LSI},${RCAR_E3})
+BL2_SOURCES += drivers/renesas/rcar/ddr/ddr_a/ddr_init_e3.c
+else ifeq (${RCAR_LSI},${RCAR_D3})
+BL2_SOURCES += drivers/renesas/rcar/ddr/ddr_a/ddr_init_d3.c
+else
+BL2_SOURCES += drivers/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c
+endif
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_d3.c b/drivers/renesas/rcar/ddr/ddr_a/ddr_init_d3.c
similarity index 100%
rename from drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_d3.c
rename to drivers/renesas/rcar/ddr/ddr_a/ddr_init_d3.c
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c b/drivers/renesas/rcar/ddr/ddr_a/ddr_init_e3.c
similarity index 100%
rename from drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c
rename to drivers/renesas/rcar/ddr/ddr_a/ddr_init_e3.c
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c b/drivers/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c
similarity index 100%
rename from drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c
rename to drivers/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c b/drivers/renesas/rcar/ddr/ddr_b/boot_init_dram.c
similarity index 100%
rename from drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c
rename to drivers/renesas/rcar/ddr/ddr_b/boot_init_dram.c
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c b/drivers/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c
similarity index 100%
rename from drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c
rename to drivers/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h b/drivers/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h
similarity index 100%
rename from drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h
rename to drivers/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/ddr_b.mk b/drivers/renesas/rcar/ddr/ddr_b/ddr_b.mk
similarity index 64%
rename from drivers/staging/renesas/rcar/ddr/ddr_b/ddr_b.mk
rename to drivers/renesas/rcar/ddr/ddr_b/ddr_b.mk
index 875f953..2bcc292 100644
--- a/drivers/staging/renesas/rcar/ddr/ddr_b/ddr_b.mk
+++ b/drivers/renesas/rcar/ddr/ddr_b/ddr_b.mk
@@ -4,4 +4,4 @@
# SPDX-License-Identifier: BSD-3-Clause
#
-BL2_SOURCES += drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c
+BL2_SOURCES += drivers/renesas/rcar/ddr/ddr_b/boot_init_dram.c
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/ddr_regdef.h b/drivers/renesas/rcar/ddr/ddr_b/ddr_regdef.h
similarity index 100%
rename from drivers/staging/renesas/rcar/ddr/ddr_b/ddr_regdef.h
rename to drivers/renesas/rcar/ddr/ddr_b/ddr_regdef.h
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3.h b/drivers/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3.h
similarity index 100%
rename from drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3.h
rename to drivers/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3.h
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3ver2.h b/drivers/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3ver2.h
similarity index 100%
rename from drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3ver2.h
rename to drivers/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3ver2.h
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3.h b/drivers/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3.h
similarity index 100%
rename from drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3.h
rename to drivers/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3.h
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h b/drivers/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h
similarity index 100%
rename from drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h
rename to drivers/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_regs.h b/drivers/renesas/rcar/ddr/ddr_regs.h
similarity index 100%
rename from drivers/staging/renesas/rcar/ddr/ddr_regs.h
rename to drivers/renesas/rcar/ddr/ddr_regs.h
diff --git a/drivers/staging/renesas/rcar/ddr/dram_sub_func.c b/drivers/renesas/rcar/ddr/dram_sub_func.c
similarity index 100%
rename from drivers/staging/renesas/rcar/ddr/dram_sub_func.c
rename to drivers/renesas/rcar/ddr/dram_sub_func.c
diff --git a/drivers/staging/renesas/rcar/ddr/dram_sub_func.h b/drivers/renesas/rcar/ddr/dram_sub_func.h
similarity index 100%
rename from drivers/staging/renesas/rcar/ddr/dram_sub_func.h
rename to drivers/renesas/rcar/ddr/dram_sub_func.h
diff --git a/drivers/renesas/rcar/io/io_rcar.c b/drivers/renesas/rcar/io/io_rcar.c
index 650931b..b82c510 100644
--- a/drivers/renesas/rcar/io/io_rcar.c
+++ b/drivers/renesas/rcar/io/io_rcar.c
@@ -28,9 +28,6 @@
extern int32_t plat_get_drv_source(uint32_t id, uintptr_t *dev,
uintptr_t *image_spec);
-extern int auth_mod_verify_img(unsigned int img_id, void *ptr,
- unsigned int len);
-
static int32_t rcar_dev_open(const uintptr_t dev_spec __attribute__ ((unused)),
io_dev_info_t **dev_info);
static int32_t rcar_dev_close(io_dev_info_t *dev_info);
diff --git a/drivers/staging/renesas/rcar/ddr/ddr.mk b/drivers/staging/renesas/rcar/ddr/ddr.mk
deleted file mode 100644
index ed7adc3..0000000
--- a/drivers/staging/renesas/rcar/ddr/ddr.mk
+++ /dev/null
@@ -1,17 +0,0 @@
-#
-# Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-ifeq (${RCAR_LSI},${RCAR_E3})
- include drivers/staging/renesas/rcar/ddr/ddr_a/ddr_a.mk
- BL2_SOURCES += drivers/staging/renesas/rcar/ddr/dram_sub_func.c
-else ifeq (${RCAR_LSI},${RCAR_D3})
- include drivers/staging/renesas/rcar/ddr/ddr_a/ddr_a.mk
-else ifeq (${RCAR_LSI},${RCAR_V3M})
- include drivers/staging/renesas/rcar/ddr/ddr_a/ddr_a.mk
-else
- include drivers/staging/renesas/rcar/ddr/ddr_b/ddr_b.mk
- BL2_SOURCES += drivers/staging/renesas/rcar/ddr/dram_sub_func.c
-endif
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_a.mk b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_a.mk
deleted file mode 100644
index aee27a5..0000000
--- a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_a.mk
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-ifeq (${RCAR_LSI},${RCAR_E3})
-BL2_SOURCES += drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c
-else ifeq (${RCAR_LSI},${RCAR_D3})
-BL2_SOURCES += drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_d3.c
-else
-BL2_SOURCES += drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c
-endif
diff --git a/drivers/ti/uart/aarch32/16550_console.S b/drivers/ti/uart/aarch32/16550_console.S
index 6921884..5cd9b30 100644
--- a/drivers/ti/uart/aarch32/16550_console.S
+++ b/drivers/ti/uart/aarch32/16550_console.S
@@ -89,16 +89,19 @@
.globl console_16550_register
/* -------------------------------------------------------
- * int console_stm32_register(uintptr_t baseaddr,
+ * int console_16550_register(uintptr_t baseaddr,
* uint32_t clock, uint32_t baud,
- * struct console_stm32 *console);
- * Function to initialize and register a new STM32
+ * console_16550_t *console);
+ * Function to initialize and register a new 16550
* console. Storage passed in for the console struct
* *must* be persistent (i.e. not from the stack).
+ * If r1 (UART clock) is 0, initialisation will be
+ * skipped, relying on previous code to have done
+ * this already. r2 is ignored then as well.
* In: r0 - UART register base address
* r1 - UART clock in Hz
- * r2 - Baud rate
- * r3 - pointer to empty console_stm32 struct
+ * r2 - Baud rate (ignored if r1 is 0)
+ * r3 - pointer to empty console_16550_t struct
* Out: return 1 on success, 0 on error
* Clobber list : r0, r1, r2
* -------------------------------------------------------
@@ -110,10 +113,15 @@
beq register_fail
str r0, [r4, #CONSOLE_T_16550_BASE]
+ /* A clock rate of zero means to skip the initialisation. */
+ cmp r1, #0
+ beq register_16550
+
bl console_16550_core_init
cmp r0, #0
beq register_fail
+register_16550:
mov r0, r4
pop {r4, lr}
finish_console_register 16550 putc=1, getc=1, flush=1
diff --git a/drivers/ti/uart/aarch64/16550_console.S b/drivers/ti/uart/aarch64/16550_console.S
index dab46e8..80c1b86 100644
--- a/drivers/ti/uart/aarch64/16550_console.S
+++ b/drivers/ti/uart/aarch64/16550_console.S
@@ -92,9 +92,12 @@
* Function to initialize and register a new 16550
* console. Storage passed in for the console struct
* *must* be persistent (i.e. not from the stack).
+ * If w1 (UART clock) is 0, initialisation will be
+ * skipped, relying on previous code to have done
+ * this already. w2 is ignored then as well.
* In: x0 - UART register base address
* w1 - UART clock in Hz
- * w2 - Baud rate
+ * w2 - Baud rate (ignored if w1 is 0)
* x3 - pointer to empty console_16550_t struct
* Out: return 1 on success, 0 on error
* Clobber list : x0, x1, x2, x6, x7, x14
@@ -106,9 +109,13 @@
cbz x6, register_fail
str x0, [x6, #CONSOLE_T_16550_BASE]
+ /* A clock rate of zero means to skip the initialisation. */
+ cbz w1, register_16550
+
bl console_16550_core_init
cbz x0, register_fail
+register_16550:
mov x0, x6
mov x30, x7
finish_console_register 16550 putc=1, getc=1, flush=1
diff --git a/fdts/a5ds.dts b/fdts/a5ds.dts
index fc8783d..31d635a 100644
--- a/fdts/a5ds.dts
+++ b/fdts/a5ds.dts
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2020, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -64,13 +64,20 @@
arm,tag-latency = <1 1 1>;
};
- refclk100mhz: refclk100mhz {
+ refclk7500khz: refclk7500khz {
compatible = "fixed-clock";
#clock-cells = <0>;
- clock-frequency = <100000000>;
+ clock-frequency = <7500000>;
clock-output-names = "apb_pclk";
};
+ refclk24mhz: refclk24mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "apb_pclk";
+ };
+
smbclk: refclk24mhzx2 {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -82,7 +89,7 @@
rtc@1a220000 {
compatible = "arm,pl031", "arm,primecell";
reg = <0x1a220000 0x1000>;
- clocks = <&refclk100mhz>;
+ clocks = <&refclk24mhz>;
interrupts = <0 6 0xf04>;
clock-names = "apb_pclk";
};
@@ -102,7 +109,7 @@
reg = <0x1a200000 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 8 0xf04>;
- clocks = <&refclk100mhz>;
+ clocks = <&refclk7500khz>;
clock-names = "apb_pclk";
};
@@ -111,7 +118,7 @@
reg = <0x1a210000 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 9 0xf04>;
- clocks = <&refclk100mhz>;
+ clocks = <&refclk7500khz>;
clock-names = "apb_pclk";
};
diff --git a/include/arch/aarch64/el3_common_macros.S b/include/arch/aarch64/el3_common_macros.S
index b14b7b6..156b18a 100644
--- a/include/arch/aarch64/el3_common_macros.S
+++ b/include/arch/aarch64/el3_common_macros.S
@@ -382,6 +382,14 @@
add x1, x1, :lo12:__RW_END__
sub x1, x1, x0
bl inv_dcache_range
+#if defined(IMAGE_BL31) && SEPARATE_NOBITS_REGION
+ adrp x0, __NOBITS_START__
+ add x0, x0, :lo12:__NOBITS_START__
+ adrp x1, __NOBITS_END__
+ add x1, x1, :lo12:__NOBITS_END__
+ sub x1, x1, x0
+ bl inv_dcache_range
+#endif
#endif
adrp x0, __BSS_START__
add x0, x0, :lo12:__BSS_START__
diff --git a/include/drivers/arm/scu.h b/include/drivers/arm/scu.h
new file mode 100644
index 0000000..992539f
--- /dev/null
+++ b/include/drivers/arm/scu.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SCU_H
+#define SCU_H
+
+#include <stdint.h>
+
+#define SCU_CTRL_REG 0x00
+#define SCU_CFG_REG 0x04
+
+#define SCU_ENABLE_BIT (1 << 0)
+
+void enable_snoop_ctrl_unit(uintptr_t base);
+uint32_t read_snoop_ctrl_unit_cfg(uintptr_t base);
+
+#endif /* SCU_H */
diff --git a/include/drivers/ti/uart/uart_16550.h b/include/drivers/ti/uart/uart_16550.h
index 32e38f0..2b95fa3 100644
--- a/include/drivers/ti/uart/uart_16550.h
+++ b/include/drivers/ti/uart/uart_16550.h
@@ -87,6 +87,11 @@
* framework. The |console| pointer must point to storage that will be valid
* for the lifetime of the console, such as a global or static local variable.
* Its contents will be reinitialized from scratch.
+ * When |clock| has a value of 0, the UART will *not* be initialised. This
+ * means the UART should already be enabled and the baudrate and clock setup
+ * should have been done already, either by platform specific code or by
+ * previous firmware stages. The |baud| parameter will be ignored in this
+ * case as well.
*/
int console_16550_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud,
console_16550_t *console);
diff --git a/include/export/lib/utils_def_exp.h b/include/export/lib/utils_def_exp.h
index 86c409c..d4a4a85 100644
--- a/include/export/lib/utils_def_exp.h
+++ b/include/export/lib/utils_def_exp.h
@@ -25,11 +25,13 @@
# define L(_x) (_x)
# define LL(_x) (_x)
#else
-# define U(_x) (_x##U)
+# define U_(_x) (_x##U)
+# define U(_x) U_(_x)
# define UL(_x) (_x##UL)
# define ULL(_x) (_x##ULL)
# define L(_x) (_x##L)
# define LL(_x) (_x##LL)
+
#endif
#endif /* ARM_TRUSTED_FIRMWARE_EXPORT_LIB_UTILS_DEF_EXP_H */
diff --git a/include/lib/cpus/aarch64/cortex_a72.h b/include/lib/cpus/aarch64/cortex_a72.h
index 4a444c6..28b440e 100644
--- a/include/lib/cpus/aarch64/cortex_a72.h
+++ b/include/lib/cpus/aarch64/cortex_a72.h
@@ -43,7 +43,14 @@
******************************************************************************/
#define CORTEX_A72_L2ACTLR_EL1 S3_1_C15_C0_0
+#define CORTEX_A72_L2ACTLR_FORCE_TAG_BANK_CLK_ACTIVE (ULL(1) << 28)
+#define CORTEX_A72_L2ACTLR_FORCE_L2_LOGIC_CLK_ACTIVE (ULL(1) << 27)
+#define CORTEX_A72_L2ACTLR_FORCE_L2_GIC_TIMER_RCG_CLK_ACTIVE (ULL(1) << 26)
#define CORTEX_A72_L2ACTLR_ENABLE_UNIQUE_CLEAN (ULL(1) << 14)
+#define CORTEX_A72_L2ACTLR_DISABLE_DSB_WITH_NO_DVM_SYNC (ULL(1) << 11)
+#define CORTEX_A72_L2ACTLR_DISABLE_DVM_CMO_BROADCAST (ULL(1) << 8)
+#define CORTEX_A72_L2ACTLR_ENABLE_HAZARD_DETECT_TIMEOUT (ULL(1) << 7)
+#define CORTEX_A72_L2ACTLR_DISABLE_ACE_SH_OR_CHI (ULL(1) << 6)
/*******************************************************************************
* L2 Control register specific definitions.
@@ -51,8 +58,12 @@
#define CORTEX_A72_L2CTLR_EL1 S3_1_C11_C0_2
#define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT U(0)
+#define CORTEX_A72_L2CTLR_DATA_RAM_SETUP_SHIFT U(5)
#define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT U(6)
+#define CORTEX_A72_L2CTLR_TAG_RAM_SETUP_SHIFT U(9)
+#define CORTEX_A72_L2_DATA_RAM_LATENCY_MASK U(0x7)
+#define CORTEX_A72_L2_TAG_RAM_LATENCY_MASK U(0x7)
#define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES U(0x2)
#define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES U(0x1)
#define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES U(0x2)
diff --git a/include/lib/cpus/aarch64/cortex_hercules.h b/include/lib/cpus/aarch64/cortex_hercules.h
index b943e7a..d5ca85e 100644
--- a/include/lib/cpus/aarch64/cortex_hercules.h
+++ b/include/lib/cpus/aarch64/cortex_hercules.h
@@ -27,6 +27,9 @@
******************************************************************************/
#define CORTEX_HERCULES_ACTLR_TAM_BIT (ULL(1) << 30)
+#define CORTEX_HERCULES_ACTLR2_EL1 S3_0_C15_C1_1
+#define CORTEX_HERCULES_ACTLR2_EL1_BIT_1 (ULL(1) << 1)
+
/*******************************************************************************
* CPU Activity Monitor Unit register specific definitions.
******************************************************************************/
diff --git a/include/lib/pmf/pmf.h b/include/lib/pmf/pmf.h
index df7c9ff..3fc8e38 100644
--- a/include/lib/pmf/pmf.h
+++ b/include/lib/pmf/pmf.h
@@ -54,108 +54,6 @@
#define PMF_PSCI_STAT_SVC_ID 0
#define PMF_RT_INSTR_SVC_ID 1
-#if ENABLE_PMF
-/*
- * Convenience macros for capturing time-stamp.
- */
-#define PMF_DECLARE_CAPTURE_TIMESTAMP(_name) \
- void pmf_capture_timestamp_with_cache_maint_ ## _name( \
- unsigned int tid, \
- unsigned long long ts); \
- void pmf_capture_timestamp_ ## _name( \
- unsigned int tid, \
- unsigned long long ts);
-
-#define PMF_CAPTURE_TIMESTAMP(_name, _tid, _flags) \
- do { \
- unsigned long long ts = read_cntpct_el0(); \
- if (((_flags) & PMF_CACHE_MAINT) != 0U) \
- pmf_capture_timestamp_with_cache_maint_ ## _name((_tid), ts);\
- else \
- pmf_capture_timestamp_ ## _name((_tid), ts); \
- } while (0)
-
-#define PMF_CAPTURE_AND_GET_TIMESTAMP(_name, _tid, _flags, _tsval) \
- do { \
- (_tsval) = read_cntpct_el0(); \
- CASSERT(sizeof(_tsval) == sizeof(unsigned long long), invalid_tsval_size);\
- if (((_flags) & PMF_CACHE_MAINT) != 0U) \
- pmf_capture_timestamp_with_cache_maint_ ## _name((_tid), (_tsval));\
- else \
- pmf_capture_timestamp_ ## _name((_tid), (_tsval));\
- } while (0)
-
-#define PMF_WRITE_TIMESTAMP(_name, _tid, _flags, _wrval) \
- do { \
- CASSERT(sizeof(_wrval) == sizeof(unsigned long long), invalid_wrval_size);\
- if (((_flags) & PMF_CACHE_MAINT) != 0U) \
- pmf_capture_timestamp_with_cache_maint_ ## _name((_tid), (_wrval));\
- else \
- pmf_capture_timestamp_ ## _name((_tid), (_wrval));\
- } while (0)
-
-/*
- * Convenience macros for retrieving time-stamp.
- */
-#define PMF_DECLARE_GET_TIMESTAMP(_name) \
- unsigned long long pmf_get_timestamp_by_index_ ## _name(\
- unsigned int tid, \
- unsigned int cpuid, \
- unsigned int flags); \
- unsigned long long pmf_get_timestamp_by_mpidr_ ## _name(\
- unsigned int tid, \
- u_register_t mpidr, \
- unsigned int flags);
-
-#define PMF_GET_TIMESTAMP_BY_MPIDR(_name, _tid, _mpidr, _flags, _tsval)\
- _tsval = pmf_get_timestamp_by_mpidr_ ## _name(_tid, _mpidr, _flags)
-
-#define PMF_GET_TIMESTAMP_BY_INDEX(_name, _tid, _cpuid, _flags, _tsval)\
- _tsval = pmf_get_timestamp_by_index_ ## _name(_tid, _cpuid, _flags)
-
-/* Convenience macros to register a PMF service.*/
-/*
- * This macro is used to register a PMF Service. It allocates PMF memory
- * and defines default service-specific PMF functions.
- */
-#define PMF_REGISTER_SERVICE(_name, _svcid, _totalid, _flags) \
- PMF_ALLOCATE_TIMESTAMP_MEMORY(_name, _totalid) \
- PMF_DEFINE_CAPTURE_TIMESTAMP(_name, _flags) \
- PMF_DEFINE_GET_TIMESTAMP(_name)
-
-/*
- * This macro is used to register a PMF service, including an
- * SMC interface to that service.
- */
-#define PMF_REGISTER_SERVICE_SMC(_name, _svcid, _totalid, _flags)\
- PMF_REGISTER_SERVICE(_name, _svcid, _totalid, _flags) \
- PMF_DEFINE_SERVICE_DESC(_name, PMF_ARM_TIF_IMPL_ID, \
- _svcid, _totalid, NULL, \
- pmf_get_timestamp_by_mpidr_ ## _name)
-
-/*
- * This macro is used to register a PMF service that has an SMC interface
- * but provides its own service-specific PMF functions.
- */
-#define PMF_REGISTER_SERVICE_SMC_OWN(_name, _implid, _svcid, _totalid, \
- _init, _getts) \
- PMF_DEFINE_SERVICE_DESC(_name, _implid, _svcid, _totalid, \
- _init, _getts)
-
-#else
-
-#define PMF_REGISTER_SERVICE(_name, _svcid, _totalid, _flags)
-#define PMF_REGISTER_SERVICE_SMC(_name, _svcid, _totalid, _flags)
-#define PMF_REGISTER_SERVICE_SMC_OWN(_name, _implid, _svcid, _totalid, \
- _init, _getts)
-#define PMF_DECLARE_CAPTURE_TIMESTAMP(_name)
-#define PMF_DECLARE_GET_TIMESTAMP(_name)
-#define PMF_CAPTURE_TIMESTAMP(_name, _tid, _flags)
-#define PMF_GET_TIMESTAMP_BY_MPIDR(_name, _tid, _mpidr, _flags, _tsval)
-#define PMF_GET_TIMESTAMP_BY_INDEX(_name, _tid, _cpuid, _flags, _tsval)
-
-#endif /* ENABLE_PMF */
-
/*******************************************************************************
* Function & variable prototypes
******************************************************************************/
diff --git a/include/lib/pmf/pmf_helpers.h b/include/lib/pmf/pmf_helpers.h
index e6798a7..db38e55 100644
--- a/include/lib/pmf/pmf_helpers.h
+++ b/include/lib/pmf/pmf_helpers.h
@@ -43,6 +43,108 @@
pmf_svc_get_ts_t get_ts;
} pmf_svc_desc_t;
+#if ENABLE_PMF
+/*
+ * Convenience macros for capturing time-stamp.
+ */
+#define PMF_DECLARE_CAPTURE_TIMESTAMP(_name) \
+ void pmf_capture_timestamp_with_cache_maint_ ## _name( \
+ unsigned int tid, \
+ unsigned long long ts); \
+ void pmf_capture_timestamp_ ## _name( \
+ unsigned int tid, \
+ unsigned long long ts);
+
+#define PMF_CAPTURE_TIMESTAMP(_name, _tid, _flags) \
+ do { \
+ unsigned long long ts = read_cntpct_el0(); \
+ if (((_flags) & PMF_CACHE_MAINT) != 0U) \
+ pmf_capture_timestamp_with_cache_maint_ ## _name((_tid), ts);\
+ else \
+ pmf_capture_timestamp_ ## _name((_tid), ts); \
+ } while (0)
+
+#define PMF_CAPTURE_AND_GET_TIMESTAMP(_name, _tid, _flags, _tsval) \
+ do { \
+ (_tsval) = read_cntpct_el0(); \
+ CASSERT(sizeof(_tsval) == sizeof(unsigned long long), invalid_tsval_size);\
+ if (((_flags) & PMF_CACHE_MAINT) != 0U) \
+ pmf_capture_timestamp_with_cache_maint_ ## _name((_tid), (_tsval));\
+ else \
+ pmf_capture_timestamp_ ## _name((_tid), (_tsval));\
+ } while (0)
+
+#define PMF_WRITE_TIMESTAMP(_name, _tid, _flags, _wrval) \
+ do { \
+ CASSERT(sizeof(_wrval) == sizeof(unsigned long long), invalid_wrval_size);\
+ if (((_flags) & PMF_CACHE_MAINT) != 0U) \
+ pmf_capture_timestamp_with_cache_maint_ ## _name((_tid), (_wrval));\
+ else \
+ pmf_capture_timestamp_ ## _name((_tid), (_wrval));\
+ } while (0)
+
+/*
+ * Convenience macros for retrieving time-stamp.
+ */
+#define PMF_DECLARE_GET_TIMESTAMP(_name) \
+ unsigned long long pmf_get_timestamp_by_index_ ## _name(\
+ unsigned int tid, \
+ unsigned int cpuid, \
+ unsigned int flags); \
+ unsigned long long pmf_get_timestamp_by_mpidr_ ## _name(\
+ unsigned int tid, \
+ u_register_t mpidr, \
+ unsigned int flags);
+
+#define PMF_GET_TIMESTAMP_BY_MPIDR(_name, _tid, _mpidr, _flags, _tsval)\
+ _tsval = pmf_get_timestamp_by_mpidr_ ## _name(_tid, _mpidr, _flags)
+
+#define PMF_GET_TIMESTAMP_BY_INDEX(_name, _tid, _cpuid, _flags, _tsval)\
+ _tsval = pmf_get_timestamp_by_index_ ## _name(_tid, _cpuid, _flags)
+
+/* Convenience macros to register a PMF service.*/
+/*
+ * This macro is used to register a PMF Service. It allocates PMF memory
+ * and defines default service-specific PMF functions.
+ */
+#define PMF_REGISTER_SERVICE(_name, _svcid, _totalid, _flags) \
+ PMF_ALLOCATE_TIMESTAMP_MEMORY(_name, _totalid) \
+ PMF_DEFINE_CAPTURE_TIMESTAMP(_name, _flags) \
+ PMF_DEFINE_GET_TIMESTAMP(_name)
+
+/*
+ * This macro is used to register a PMF service, including an
+ * SMC interface to that service.
+ */
+#define PMF_REGISTER_SERVICE_SMC(_name, _svcid, _totalid, _flags)\
+ PMF_REGISTER_SERVICE(_name, _svcid, _totalid, _flags) \
+ PMF_DEFINE_SERVICE_DESC(_name, PMF_ARM_TIF_IMPL_ID, \
+ _svcid, _totalid, NULL, \
+ pmf_get_timestamp_by_mpidr_ ## _name)
+
+/*
+ * This macro is used to register a PMF service that has an SMC interface
+ * but provides its own service-specific PMF functions.
+ */
+#define PMF_REGISTER_SERVICE_SMC_OWN(_name, _implid, _svcid, _totalid, \
+ _init, _getts) \
+ PMF_DEFINE_SERVICE_DESC(_name, _implid, _svcid, _totalid, \
+ _init, _getts)
+
+#else
+
+#define PMF_REGISTER_SERVICE(_name, _svcid, _totalid, _flags)
+#define PMF_REGISTER_SERVICE_SMC(_name, _svcid, _totalid, _flags)
+#define PMF_REGISTER_SERVICE_SMC_OWN(_name, _implid, _svcid, _totalid, \
+ _init, _getts)
+#define PMF_DECLARE_CAPTURE_TIMESTAMP(_name)
+#define PMF_DECLARE_GET_TIMESTAMP(_name)
+#define PMF_CAPTURE_TIMESTAMP(_name, _tid, _flags)
+#define PMF_GET_TIMESTAMP_BY_MPIDR(_name, _tid, _mpidr, _flags, _tsval)
+#define PMF_GET_TIMESTAMP_BY_INDEX(_name, _tid, _cpuid, _flags, _tsval)
+
+#endif /* ENABLE_PMF */
+
/*
* Convenience macro to allocate memory for a PMF service.
*
@@ -69,9 +171,6 @@
#define PMF_DEFINE_CAPTURE_TIMESTAMP(_name, _flags) \
void pmf_capture_timestamp_ ## _name( \
unsigned int tid, \
- unsigned long long ts); \
- void pmf_capture_timestamp_ ## _name( \
- unsigned int tid, \
unsigned long long ts) \
{ \
CASSERT(_flags, select_proper_config); \
@@ -84,9 +183,6 @@
} \
void pmf_capture_timestamp_with_cache_maint_ ## _name( \
unsigned int tid, \
- unsigned long long ts); \
- void pmf_capture_timestamp_with_cache_maint_ ## _name( \
- unsigned int tid, \
unsigned long long ts) \
{ \
CASSERT(_flags, select_proper_config); \
@@ -105,8 +201,6 @@
*/
#define PMF_DEFINE_GET_TIMESTAMP(_name) \
unsigned long long pmf_get_timestamp_by_index_ ## _name( \
- unsigned int tid, unsigned int cpuid, unsigned int flags);\
- unsigned long long pmf_get_timestamp_by_index_ ## _name( \
unsigned int tid, unsigned int cpuid, unsigned int flags)\
{ \
PMF_VALIDATE_TID(_name, tid); \
@@ -114,8 +208,6 @@
return __pmf_get_timestamp(base_addr, tid, cpuid, flags);\
} \
unsigned long long pmf_get_timestamp_by_mpidr_ ## _name( \
- unsigned int tid, u_register_t mpidr, unsigned int flags);\
- unsigned long long pmf_get_timestamp_by_mpidr_ ## _name( \
unsigned int tid, u_register_t mpidr, unsigned int flags)\
{ \
PMF_VALIDATE_TID(_name, tid); \
diff --git a/include/lib/psci/psci.h b/include/lib/psci/psci.h
index 7f7b7e3..b56e98b 100644
--- a/include/lib/psci/psci.h
+++ b/include/lib/psci/psci.h
@@ -20,7 +20,7 @@
#ifdef PLAT_NUM_PWR_DOMAINS
#define PSCI_NUM_PWR_DOMAINS PLAT_NUM_PWR_DOMAINS
#else
-#define PSCI_NUM_PWR_DOMAINS (2 * PLATFORM_CORE_COUNT)
+#define PSCI_NUM_PWR_DOMAINS (U(2) * PLATFORM_CORE_COUNT)
#endif
#define PSCI_NUM_NON_CPU_PWR_DOMAINS (PSCI_NUM_PWR_DOMAINS - \
diff --git a/include/lib/smccc.h b/include/lib/smccc.h
index dd3c578..5e13e6f 100644
--- a/include/lib/smccc.h
+++ b/include/lib/smccc.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -41,6 +41,8 @@
#define FUNCID_NUM_MASK U(0xffff)
#define FUNCID_NUM_WIDTH U(16)
+#define GET_SMC_NUM(id) (((id) >> FUNCID_NUM_SHIFT) & \
+ FUNCID_NUM_MASK)
#define GET_SMC_TYPE(id) (((id) >> FUNCID_TYPE_SHIFT) & \
FUNCID_TYPE_MASK)
#define GET_SMC_CC(id) (((id) >> FUNCID_CC_SHIFT) & \
diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h
index 72e2e8e..b419c85 100644
--- a/include/plat/arm/common/arm_def.h
+++ b/include/plat/arm/common/arm_def.h
@@ -21,7 +21,7 @@
/* Special value used to verify platform parameters from BL2 to BL31 */
#define ARM_BL31_PLAT_PARAM_VAL ULL(0x0f1e2d3c4b5a6978)
-#define ARM_SYSTEM_COUNT 1
+#define ARM_SYSTEM_COUNT U(1)
#define ARM_CACHE_WRITEBACK_SHIFT 6
diff --git a/include/plat/common/platform.h b/include/plat/common/platform.h
index 9efb2fd..332cfca 100644
--- a/include/plat/common/platform.h
+++ b/include/plat/common/platform.h
@@ -237,7 +237,7 @@
void plat_psci_stat_accounting_stop(const psci_power_state_t *state_info);
u_register_t plat_psci_stat_get_residency(unsigned int lvl,
const psci_power_state_t *state_info,
- int last_cpu_idx);
+ unsigned int last_cpu_idx);
plat_local_state_t plat_get_target_pwr_state(unsigned int lvl,
const plat_local_state_t *states,
unsigned int ncpu);
diff --git a/lib/cpus/aarch64/cortex_hercules.S b/lib/cpus/aarch64/cortex_hercules.S
index 4e04814..a239196 100644
--- a/lib/cpus/aarch64/cortex_hercules.S
+++ b/lib/cpus/aarch64/cortex_hercules.S
@@ -16,12 +16,49 @@
#error "cortex_hercules must be compiled with HW_ASSISTED_COHERENCY enabled"
#endif
+
+/* --------------------------------------------------
+ * Errata Workaround for Hercules Erratum 1688305.
+ * This applies to revision r0p0 and r1p0 of Hercules.
+ * Inputs:
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x17
+ * --------------------------------------------------
+ */
+func errata_hercules_1688305_wa
+ /* Compare x0 against revision r1p0 */
+ mov x17, x30
+ bl check_errata_1688305
+ cbz x0, 1f
+ mrs x1, CORTEX_HERCULES_ACTLR2_EL1
+ orr x1, x1, CORTEX_HERCULES_ACTLR2_EL1_BIT_1
+ msr CORTEX_HERCULES_ACTLR2_EL1, x1
+ isb
+1:
+ ret x17
+endfunc errata_hercules_1688305_wa
+
+func check_errata_1688305
+ /* Applies to r0p0 and r1p0 */
+ mov x1, #0x10
+ b cpu_rev_var_ls
+endfunc check_errata_1688305
+
/* -------------------------------------------------
* The CPU Ops reset function for Cortex-Hercules
* -------------------------------------------------
*/
-#if ENABLE_AMU
func cortex_hercules_reset_func
+ mov x19, x30
+ bl cpu_get_rev_var
+ mov x18, x0
+
+#if ERRATA_HERCULES_1688305
+ mov x0, x18
+ bl errata_hercules_1688305_wa
+#endif
+
+#if ENABLE_AMU
/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
mrs x0, actlr_el3
bic x0, x0, #CORTEX_HERCULES_ACTLR_TAM_BIT
@@ -39,11 +76,11 @@
/* Enable group1 counters */
mov x0, #CORTEX_HERCULES_AMU_GROUP1_MASK
msr CPUAMCNTENSET1_EL0, x0
- isb
+#endif
- ret
+ isb
+ ret x19
endfunc cortex_hercules_reset_func
-#endif
/* ---------------------------------------------
* HW will do the cache maintenance while powering down
@@ -66,6 +103,18 @@
*/
#if REPORT_ERRATA
func cortex_hercules_errata_report
+ stp x8, x30, [sp, #-16]!
+
+ bl cpu_get_rev_var
+ mov x8, x0
+
+ /*
+ * Report all errata. The revision-variant information is passed to
+ * checking functions of each errata.
+ */
+ report_errata ERRATA_HERCULES_1688305, cortex_hercules, 1688305
+
+ ldp x8, x30, [sp], #16
ret
endfunc cortex_hercules_errata_report
#endif
@@ -89,12 +138,6 @@
ret
endfunc cortex_hercules_cpu_reg_dump
-#if ENABLE_AMU
-#define HERCULES_RESET_FUNC cortex_hercules_reset_func
-#else
-#define HERCULES_RESET_FUNC CPU_NO_RESET_FUNC
-#endif
-
declare_cpu_ops cortex_hercules, CORTEX_HERCULES_MIDR, \
- HERCULES_RESET_FUNC, \
+ cortex_hercules_reset_func, \
cortex_hercules_core_pwr_dwn
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index 078888e..c9b9b38 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -234,6 +234,10 @@
# only to revision <= r3p0 of the Cortex A76 cpu.
ERRATA_A76_1286807 ?=0
+# Flag to apply erratum 1688305 workaround during reset. This erratum applies
+# to revisions r0p0 - r1p0 of the Hercules cpu.
+ERRATA_HERCULES_1688305 ?=0
+
# Flag to apply T32 CLREX workaround during reset. This erratum applies
# only to r0p0 and r1p0 of the Neoverse N1 cpu.
ERRATA_N1_1043202 ?=1
@@ -467,6 +471,10 @@
$(eval $(call assert_boolean,ERRATA_A76_1286807))
$(eval $(call add_define,ERRATA_A76_1286807))
+# Process ERRATA_HERCULES_1688305 flag
+$(eval $(call assert_boolean,ERRATA_HERCULES_1688305))
+$(eval $(call add_define,ERRATA_HERCULES_1688305))
+
# Process ERRATA_N1_1043202 flag
$(eval $(call assert_boolean,ERRATA_N1_1043202))
$(eval $(call add_define,ERRATA_N1_1043202))
diff --git a/lib/psci/psci_main.c b/lib/psci/psci_main.c
index 5c0e952..52a8b8a 100644
--- a/lib/psci/psci_main.c
+++ b/lib/psci/psci_main.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -219,16 +219,19 @@
int psci_affinity_info(u_register_t target_affinity,
unsigned int lowest_affinity_level)
{
- int target_idx;
+ int ret;
+ unsigned int target_idx;
/* We dont support level higher than PSCI_CPU_PWR_LVL */
if (lowest_affinity_level > PSCI_CPU_PWR_LVL)
return PSCI_E_INVALID_PARAMS;
/* Calculate the cpu index of the target */
- target_idx = plat_core_pos_by_mpidr(target_affinity);
- if (target_idx == -1)
+ ret = plat_core_pos_by_mpidr(target_affinity);
+ if (ret == -1) {
return PSCI_E_INVALID_PARAMS;
+ }
+ target_idx = (unsigned int)ret;
/*
* Generic management:
@@ -245,7 +248,7 @@
* target CPUs shutdown was not seen by the current CPU's cluster. And
* so the cache may contain stale data for the target CPU.
*/
- flush_cpu_data_by_index((unsigned int)target_idx,
+ flush_cpu_data_by_index(target_idx,
psci_svc_cpu_data.aff_info_state);
return psci_get_aff_info_state_by_idx(target_idx);
diff --git a/lib/psci/psci_off.c b/lib/psci/psci_off.c
index e8cd8fe..5447045 100644
--- a/lib/psci/psci_off.c
+++ b/lib/psci/psci_off.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -43,7 +43,7 @@
int psci_do_cpu_off(unsigned int end_pwrlvl)
{
int rc = PSCI_E_SUCCESS;
- int idx = (int) plat_my_core_pos();
+ unsigned int idx = plat_my_core_pos();
psci_power_state_t state_info;
unsigned int parent_nodes[PLAT_MAX_PWR_LVL] = {0};
diff --git a/lib/psci/psci_on.c b/lib/psci/psci_on.c
index 470b4f3..dd48e10 100644
--- a/lib/psci/psci_on.c
+++ b/lib/psci/psci_on.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -20,12 +20,12 @@
/*
* Helper functions for the CPU level spinlocks
*/
-static inline void psci_spin_lock_cpu(int idx)
+static inline void psci_spin_lock_cpu(unsigned int idx)
{
spin_lock(&psci_cpu_pd_nodes[idx].cpu_lock);
}
-static inline void psci_spin_unlock_cpu(int idx)
+static inline void psci_spin_unlock_cpu(unsigned int idx)
{
spin_unlock(&psci_cpu_pd_nodes[idx].cpu_lock);
}
@@ -61,12 +61,14 @@
{
int rc;
aff_info_state_t target_aff_state;
- int target_idx = plat_core_pos_by_mpidr(target_cpu);
+ int ret = plat_core_pos_by_mpidr(target_cpu);
+ unsigned int target_idx = (unsigned int)ret;
/* Calling function must supply valid input arguments */
- assert(target_idx >= 0);
+ assert(ret >= 0);
assert(ep != NULL);
+
/*
* This function must only be called on platforms where the
* CPU_ON platform hooks have been implemented.
@@ -93,7 +95,7 @@
* target CPUs shutdown was not seen by the current CPU's cluster. And
* so the cache may contain stale data for the target CPU.
*/
- flush_cpu_data_by_index((unsigned int)target_idx,
+ flush_cpu_data_by_index(target_idx,
psci_svc_cpu_data.aff_info_state);
rc = cpu_on_validate_state(psci_get_aff_info_state_by_idx(target_idx));
if (rc != PSCI_E_SUCCESS)
@@ -113,7 +115,7 @@
* turned OFF.
*/
psci_set_aff_info_state_by_idx(target_idx, AFF_STATE_ON_PENDING);
- flush_cpu_data_by_index((unsigned int)target_idx,
+ flush_cpu_data_by_index(target_idx,
psci_svc_cpu_data.aff_info_state);
/*
@@ -126,7 +128,7 @@
if (target_aff_state != AFF_STATE_ON_PENDING) {
assert(target_aff_state == AFF_STATE_OFF);
psci_set_aff_info_state_by_idx(target_idx, AFF_STATE_ON_PENDING);
- flush_cpu_data_by_index((unsigned int)target_idx,
+ flush_cpu_data_by_index(target_idx,
psci_svc_cpu_data.aff_info_state);
assert(psci_get_aff_info_state_by_idx(target_idx) ==
@@ -146,11 +148,11 @@
if (rc == PSCI_E_SUCCESS)
/* Store the re-entry information for the non-secure world. */
- cm_init_context_by_index((unsigned int)target_idx, ep);
+ cm_init_context_by_index(target_idx, ep);
else {
/* Restore the state on error. */
psci_set_aff_info_state_by_idx(target_idx, AFF_STATE_OFF);
- flush_cpu_data_by_index((unsigned int)target_idx,
+ flush_cpu_data_by_index(target_idx,
psci_svc_cpu_data.aff_info_state);
}
@@ -164,7 +166,7 @@
* are called by the common finisher routine in psci_common.c. The `state_info`
* is the psci_power_state from which this CPU has woken up from.
******************************************************************************/
-void psci_cpu_on_finish(int cpu_idx, const psci_power_state_t *state_info)
+void psci_cpu_on_finish(unsigned int cpu_idx, const psci_power_state_t *state_info)
{
/*
* Plat. management: Perform the platform specific actions
diff --git a/lib/psci/psci_private.h b/lib/psci/psci_private.h
index 0f25e65..e2dcfa8 100644
--- a/lib/psci/psci_private.h
+++ b/lib/psci/psci_private.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -301,7 +301,7 @@
int psci_cpu_on_start(u_register_t target_cpu,
const entry_point_info_t *ep);
-void psci_cpu_on_finish(int cpu_idx, const psci_power_state_t *state_info);
+void psci_cpu_on_finish(unsigned int cpu_idx, const psci_power_state_t *state_info);
/* Private exported functions from psci_off.c */
int psci_do_cpu_off(unsigned int end_pwrlvl);
@@ -312,7 +312,7 @@
psci_power_state_t *state_info,
unsigned int is_power_down_state);
-void psci_cpu_suspend_finish(int cpu_idx, const psci_power_state_t *state_info);
+void psci_cpu_suspend_finish(unsigned int cpu_idx, const psci_power_state_t *state_info);
/* Private exported functions from psci_helpers.S */
void psci_do_pwrdown_cache_maintenance(unsigned int pwr_level);
diff --git a/lib/psci/psci_setup.c b/lib/psci/psci_setup.c
index becb547..d1ec998 100644
--- a/lib/psci/psci_setup.c
+++ b/lib/psci/psci_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -91,9 +91,9 @@
for (cpu_idx = 0; cpu_idx < psci_plat_core_count; cpu_idx++) {
psci_get_parent_pwr_domain_nodes(cpu_idx,
- (unsigned int)PLAT_MAX_PWR_LVL,
+ PLAT_MAX_PWR_LVL,
temp_index);
- for (j = (int) PLAT_MAX_PWR_LVL - 1; j >= 0; j--) {
+ for (j = (int)PLAT_MAX_PWR_LVL - 1; j >= 0; j--) {
if (temp_index[j] != nodes_idx[j]) {
nodes_idx[j] = temp_index[j];
psci_non_cpu_pd_nodes[nodes_idx[j]].cpu_start_idx
@@ -115,8 +115,8 @@
{
unsigned int i, j = 0U, num_nodes_at_lvl = 1U, num_nodes_at_next_lvl;
unsigned int node_index = 0U, num_children;
- int parent_node_index = 0;
- int level = (int) PLAT_MAX_PWR_LVL;
+ unsigned int parent_node_index = 0U;
+ int level = (int)PLAT_MAX_PWR_LVL;
/*
* For each level the inputs are:
@@ -145,8 +145,8 @@
for (j = node_index;
j < (node_index + num_children); j++)
psci_init_pwr_domain_node((unsigned char)j,
- parent_node_index - 1,
- (unsigned char)level);
+ parent_node_index - 1U,
+ (unsigned char)level);
node_index = j;
num_nodes_at_next_lvl += num_children;
@@ -162,7 +162,7 @@
}
/* Validate the sanity of array exported by the platform */
- assert(j <= (unsigned int)PLATFORM_CORE_COUNT);
+ assert(j <= PLATFORM_CORE_COUNT);
return j;
}
diff --git a/lib/psci/psci_stat.c b/lib/psci/psci_stat.c
index 772a184..ecef95a 100644
--- a/lib/psci/psci_stat.c
+++ b/lib/psci/psci_stat.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -28,7 +28,7 @@
* that goes to power down in non cpu power domains.
*/
static int last_cpu_in_non_cpu_pd[PSCI_NUM_NON_CPU_PWR_DOMAINS] = {
- [0 ... PSCI_NUM_NON_CPU_PWR_DOMAINS - 1] = -1};
+ [0 ... PSCI_NUM_NON_CPU_PWR_DOMAINS - 1U] = -1};
/*
* Following are used to store PSCI STAT values for
@@ -77,7 +77,7 @@
const psci_power_state_t *state_info)
{
unsigned int lvl, parent_idx;
- int cpu_idx = (int) plat_my_core_pos();
+ unsigned int cpu_idx = plat_my_core_pos();
assert(end_pwrlvl <= PLAT_MAX_PWR_LVL);
assert(state_info != NULL);
@@ -94,7 +94,7 @@
* The power domain is entering a low power state, so this is
* the last CPU for this power domain
*/
- last_cpu_in_non_cpu_pd[parent_idx] = cpu_idx;
+ last_cpu_in_non_cpu_pd[parent_idx] = (int)cpu_idx;
parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node;
}
@@ -110,7 +110,7 @@
const psci_power_state_t *state_info)
{
unsigned int lvl, parent_idx;
- int cpu_idx = (int) plat_my_core_pos();
+ unsigned int cpu_idx = plat_my_core_pos();
int stat_idx;
plat_local_state_t local_state;
u_register_t residency;
@@ -150,7 +150,7 @@
/* Call into platform interface to calculate residency. */
residency = plat_psci_stat_get_residency(lvl, state_info,
- last_cpu_in_non_cpu_pd[parent_idx]);
+ (unsigned int)last_cpu_in_non_cpu_pd[parent_idx]);
/* Initialize back to reset value */
last_cpu_in_non_cpu_pd[parent_idx] = -1;
diff --git a/lib/psci/psci_suspend.c b/lib/psci/psci_suspend.c
index 98dd2d6..da9f328 100644
--- a/lib/psci/psci_suspend.c
+++ b/lib/psci/psci_suspend.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -25,7 +25,7 @@
* This function does generic and platform specific operations after a wake-up
* from standby/retention states at multiple power levels.
******************************************************************************/
-static void psci_suspend_to_standby_finisher(int cpu_idx,
+static void psci_suspend_to_standby_finisher(unsigned int cpu_idx,
unsigned int end_pwrlvl)
{
unsigned int parent_nodes[PLAT_MAX_PWR_LVL] = {0};
@@ -157,7 +157,7 @@
unsigned int is_power_down_state)
{
int skip_wfi = 0;
- int idx = (int) plat_my_core_pos();
+ unsigned int idx = plat_my_core_pos();
unsigned int parent_nodes[PLAT_MAX_PWR_LVL] = {0};
/*
@@ -276,7 +276,7 @@
* are called by the common finisher routine in psci_common.c. The `state_info`
* is the psci_power_state from which this CPU has woken up from.
******************************************************************************/
-void psci_cpu_suspend_finish(int cpu_idx, const psci_power_state_t *state_info)
+void psci_cpu_suspend_finish(unsigned int cpu_idx, const psci_power_state_t *state_info)
{
unsigned int counter_freq;
unsigned int max_off_lvl;
diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk
index a1f9db9..53832c5 100644
--- a/make_helpers/defaults.mk
+++ b/make_helpers/defaults.mk
@@ -171,6 +171,10 @@
# platform Makefile is free to override this value.
SEPARATE_CODE_AND_RODATA := 0
+# Put NOBITS sections (.bss, stacks, page tables, and coherent memory) in a
+# separate memory region, which may be discontiguous from the rest of BL31.
+SEPARATE_NOBITS_REGION := 0
+
# If the BL31 image initialisation code is recalimed after use for the secondary
# cores stack
RECLAIM_INIT_CODE := 0
diff --git a/plat/allwinner/common/allwinner-common.mk b/plat/allwinner/common/allwinner-common.mk
index 5e8885d..e717e20 100644
--- a/plat/allwinner/common/allwinner-common.mk
+++ b/plat/allwinner/common/allwinner-common.mk
@@ -8,8 +8,7 @@
AW_PLAT := plat/allwinner
-PLAT_INCLUDES := -Iinclude/plat/arm/common \
- -Iinclude/plat/arm/common/aarch64 \
+PLAT_INCLUDES := -Iinclude/plat/arm/common/aarch64 \
-I${AW_PLAT}/common/include \
-I${AW_PLAT}/${PLAT}/include
@@ -56,6 +55,9 @@
# Allow mapping read-only data as execute-never.
SEPARATE_CODE_AND_RODATA := 1
+# Put NOBITS memory in SRAM A1, overwriting U-Boot's SPL.
+SEPARATE_NOBITS_REGION := 1
+
# BL31 gets loaded alongside BL33 (U-Boot) by U-Boot's SPL
RESET_TO_BL31 := 1
diff --git a/plat/allwinner/common/include/platform_def.h b/plat/allwinner/common/include/platform_def.h
index ede3881..4de8b0b 100644
--- a/plat/allwinner/common/include/platform_def.h
+++ b/plat/allwinner/common/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -16,6 +16,10 @@
#define BL31_BASE SUNXI_SRAM_A2_BASE
#define BL31_LIMIT (SUNXI_SRAM_A2_BASE + SUNXI_SRAM_A2_SIZE)
+/* Overwrite U-Boot SPL, but reserve the first page for the SPL header. */
+#define BL31_NOBITS_BASE (SUNXI_SRAM_A1_BASE + 0x1000)
+#define BL31_NOBITS_LIMIT (SUNXI_SRAM_A1_BASE + SUNXI_SRAM_A1_SIZE)
+
/* The traditional U-Boot load address is 160MB into DRAM, so at 0x4a000000 */
#define PLAT_SUNXI_NS_IMAGE_OFFSET (SUNXI_DRAM_BASE + (160U << 20))
diff --git a/plat/arm/board/a5ds/a5ds_common.c b/plat/arm/board/a5ds/a5ds_common.c
index e462fa1..a4a0cff 100644
--- a/plat/arm/board/a5ds/a5ds_common.c
+++ b/plat/arm/board/a5ds/a5ds_common.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2020, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -23,18 +23,18 @@
#ifdef IMAGE_BL1
const mmap_region_t plat_arm_mmap[] = {
ARM_MAP_SHARED_RAM,
- MAP_FLASH1_RW,
MAP_PERIPHBASE,
MAP_A5_PERIPHERALS,
+ MAP_BOOT_RW,
{0}
};
#endif
#ifdef IMAGE_BL2
const mmap_region_t plat_arm_mmap[] = {
ARM_MAP_SHARED_RAM,
- MAP_FLASH1_RW,
MAP_PERIPHBASE,
MAP_A5_PERIPHERALS,
+ MAP_BOOT_RW,
ARM_MAP_NS_DRAM1,
{0}
};
diff --git a/plat/arm/board/a5ds/a5ds_pm.c b/plat/arm/board/a5ds/a5ds_pm.c
index cc734b0..7774002 100644
--- a/plat/arm/board/a5ds/a5ds_pm.c
+++ b/plat/arm/board/a5ds/a5ds_pm.c
@@ -4,11 +4,10 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
-
+#include <drivers/arm/gicv2.h>
#include <lib/psci/psci.h>
#include <plat/arm/common/plat_arm.h>
#include <plat/common/platform.h>
-#include <drivers/arm/gicv2.h>
/*******************************************************************************
* Platform handler called when a power domain is about to be turned on. The
diff --git a/plat/arm/board/a5ds/fdts/a5ds_tb_fw_config.dts b/plat/arm/board/a5ds/fdts/a5ds_tb_fw_config.dts
index 9ab2d96..7b3aa11 100644
--- a/plat/arm/board/a5ds/fdts/a5ds_tb_fw_config.dts
+++ b/plat/arm/board/a5ds/fdts/a5ds_tb_fw_config.dts
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2020, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -10,7 +10,7 @@
/* Platform Config */
plat_arm_bl2 {
compatible = "arm,tb_fw";
- hw_config_addr = <0x0 0x82000000>;
+ hw_config_addr = <0x0 0x83000000>;
hw_config_max_size = <0x01000000>;
/* Disable authentication for development */
disable_auth = <0x0>;
diff --git a/plat/arm/board/a5ds/include/platform_def.h b/plat/arm/board/a5ds/include/platform_def.h
index e9e4b9a..31dfb1c 100644
--- a/plat/arm/board/a5ds/include/platform_def.h
+++ b/plat/arm/board/a5ds/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2020, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -21,14 +21,6 @@
#define ARM_DRAM1_END (ARM_DRAM1_BASE + \
ARM_DRAM1_SIZE - 1)
-#define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE
-/*
- * The last 2MB is meant to be NOLOAD and will not be zero
- * initialized.
- */
-#define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \
- 0x00200000)
-
#define SRAM_BASE 0x2000000
#define SRAM_SIZE 0x200000
@@ -47,7 +39,7 @@
#define A5_PERIPHERALS_BASE 0x1c000000
#define A5_PERIPHERALS_SIZE 0x10000
-#define ARM_CACHE_WRITEBACK_SHIFT 6
+#define ARM_CACHE_WRITEBACK_SHIFT 5
#define ARM_IRQ_SEC_PHY_TIMER 29
@@ -89,28 +81,34 @@
#define A5DS_IRQ_SEC_SYS_TIMER 57
/* Default cluster count for A5DS */
-#define A5DS_CLUSTER_COUNT 1
+#define A5DS_CLUSTER_COUNT U(1)
/* Default number of CPUs per cluster on A5DS */
-#define A5DS_MAX_CPUS_PER_CLUSTER 4
+#define A5DS_MAX_CPUS_PER_CLUSTER U(4)
/* Default number of threads per CPU on A5DS */
-#define A5DS_MAX_PE_PER_CPU 1
+#define A5DS_MAX_PE_PER_CPU U(1)
-#define A5DS_CORE_COUNT 4
+#define A5DS_CORE_COUNT U(4)
#define A5DS_PRIMARY_CPU 0x0
-#define FLASH1_BASE UL(0x8000000)
-#define FLASH1_SIZE UL(0x2800000)
+#define BOOT_BASE ARM_DRAM1_BASE
+#define BOOT_SIZE UL(0x2800000)
-#define MAP_FLASH1_RW MAP_REGION_FLAT(FLASH1_BASE,\
- FLASH1_SIZE, \
- MT_DEVICE | MT_RW | MT_SECURE)
+#define ARM_NS_DRAM1_BASE (ARM_DRAM1_BASE + BOOT_SIZE)
+/*
+ * The last 2MB is meant to be NOLOAD and will not be zero
+ * initialized.
+ */
+#define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \
+ BOOT_SIZE - \
+ 0x00200000)
-#define MAP_FLASH1_RO MAP_REGION_FLAT(FLASH1_BASE,\
- FLASH1_SIZE, \
- MT_RO_DATA | MT_SECURE)
+#define MAP_BOOT_RW MAP_REGION_FLAT( \
+ BOOT_BASE, \
+ BOOT_SIZE, \
+ MT_DEVICE | MT_RW | MT_SECURE)
#define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \
A5DS_SHARED_RAM_BASE, \
@@ -122,9 +120,9 @@
ARM_NS_DRAM1_SIZE, \
MT_MEMORY | MT_RW | MT_NS)
-#define ARM_MAP_SRAM MAP_REGION_FLAT( \
- SRAM_BASE, \
- SRAM_SIZE, \
+#define ARM_MAP_SRAM MAP_REGION_FLAT( \
+ SRAM_BASE, \
+ SRAM_SIZE, \
MT_MEMORY | MT_RW | MT_NS)
/*
@@ -162,7 +160,7 @@
ARM_BL_REGIONS)
/* Memory mapped Generic timer interfaces */
-#define A5DS_TIMER_BASE_FREQUENCY UL(24000000)
+#define A5DS_TIMER_BASE_FREQUENCY UL(7500000)
#define ARM_CONSOLE_BAUDRATE 115200
@@ -231,7 +229,7 @@
/* Required platform porting definitions */
#define PLATFORM_CORE_COUNT A5DS_CORE_COUNT
#define PLAT_NUM_PWR_DOMAINS (A5DS_CLUSTER_COUNT + \
- PLATFORM_CORE_COUNT) + 1
+ PLATFORM_CORE_COUNT) + U(1)
#define PLAT_MAX_PWR_LVL 2
@@ -300,25 +298,25 @@
#define MAX_IO_HANDLES 4
/* Reserve the last block of flash for PSCI MEM PROTECT flag */
-#define PLAT_ARM_FIP_BASE FLASH1_BASE
-#define PLAT_ARM_FIP_MAX_SIZE (FLASH1_SIZE - V2M_FLASH_BLOCK_SIZE)
+#define PLAT_ARM_FIP_BASE BOOT_BASE
+#define PLAT_ARM_FIP_MAX_SIZE (BOOT_SIZE - V2M_FLASH_BLOCK_SIZE)
-#define PLAT_ARM_NVM_BASE FLASH1_BASE
-#define PLAT_ARM_NVM_SIZE (FLASH1_SIZE - V2M_FLASH_BLOCK_SIZE)
+#define PLAT_ARM_NVM_BASE BOOT_BASE
+#define PLAT_ARM_NVM_SIZE (BOOT_SIZE - V2M_FLASH_BLOCK_SIZE)
/*
* PL011 related constants
*/
#define PLAT_ARM_BOOT_UART_BASE 0x1A200000
-#define PLAT_ARM_BOOT_UART_CLK_IN_HZ 24000000
+#define PLAT_ARM_BOOT_UART_CLK_IN_HZ UL(7500000)
#define PLAT_ARM_RUN_UART_BASE 0x1A210000
-#define PLAT_ARM_RUN_UART_CLK_IN_HZ 24000000
+#define PLAT_ARM_RUN_UART_CLK_IN_HZ UL(7500000)
#define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE
#define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ
-#define A5DS_TIMER_BASE_FREQUENCY UL(24000000)
+#define A5DS_TIMER_BASE_FREQUENCY UL(7500000)
/* System timer related constants */
#define PLAT_ARM_NSTIMER_FRAME_ID 1
@@ -334,6 +332,9 @@
#define A5DS_HOLD_STATE_WAIT 0
#define A5DS_HOLD_STATE_GO 1
+/* Snoop Control Unit base address */
+#define A5DS_SCU_BASE 0x1C000000
+
/*
* GIC related constants to cater for GICv2
*/
diff --git a/plat/arm/board/a5ds/sp_min/a5ds_sp_min_setup.c b/plat/arm/board/a5ds/sp_min/a5ds_sp_min_setup.c
index 8b45af8..a951dc7 100644
--- a/plat/arm/board/a5ds/sp_min/a5ds_sp_min_setup.c
+++ b/plat/arm/board/a5ds/sp_min/a5ds_sp_min_setup.c
@@ -4,12 +4,17 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
+#include <drivers/arm/scu.h>
#include <plat/arm/common/plat_arm.h>
+
void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
arm_sp_min_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
+
+ /* enable snoop control unit */
+ enable_snoop_ctrl_unit(A5DS_SCU_BASE);
}
/*
diff --git a/plat/arm/board/a5ds/sp_min/sp_min-a5ds.mk b/plat/arm/board/a5ds/sp_min/sp_min-a5ds.mk
index da1d785..4b0c97d 100644
--- a/plat/arm/board/a5ds/sp_min/sp_min-a5ds.mk
+++ b/plat/arm/board/a5ds/sp_min/sp_min-a5ds.mk
@@ -5,7 +5,8 @@
#
# SP_MIN source files specific to A5DS platform
-BL32_SOURCES += drivers/cfi/v2m/v2m_flash.c \
+BL32_SOURCES += drivers/arm/scu/scu.c \
+ drivers/cfi/v2m/v2m_flash.c \
lib/utils/mem_region.c \
lib/aarch32/arm32_aeabi_divmod.c \
lib/aarch32/arm32_aeabi_divmod_a32.S \
diff --git a/plat/arm/board/corstone700/include/platform_def.h b/plat/arm/board/corstone700/include/platform_def.h
index de99b06..8dff3ec 100644
--- a/plat/arm/board/corstone700/include/platform_def.h
+++ b/plat/arm/board/corstone700/include/platform_def.h
@@ -14,9 +14,9 @@
#include <plat/common/common_def.h>
/* Core/Cluster/Thread counts for Corstone700 */
-#define CORSTONE700_CLUSTER_COUNT 1
-#define CORSTONE700_MAX_CPUS_PER_CLUSTER 4
-#define CORSTONE700_MAX_PE_PER_CPU 1
+#define CORSTONE700_CLUSTER_COUNT U(1)
+#define CORSTONE700_MAX_CPUS_PER_CLUSTER U(4)
+#define CORSTONE700_MAX_PE_PER_CPU U(1)
#define CORSTONE700_CORE_COUNT (CORSTONE700_CLUSTER_COUNT * \
CORSTONE700_MAX_CPUS_PER_CLUSTER * \
CORSTONE700_MAX_PE_PER_CPU)
diff --git a/plat/arm/board/fvp/fvp_def.h b/plat/arm/board/fvp/fvp_def.h
index 1b9f84b..347ba2e 100644
--- a/plat/arm/board/fvp/fvp_def.h
+++ b/plat/arm/board/fvp/fvp_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -10,15 +10,15 @@
#include <lib/utils_def.h>
#ifndef FVP_CLUSTER_COUNT
-#define FVP_CLUSTER_COUNT 2
+#error "FVP_CLUSTER_COUNT is not set in makefile"
#endif
#ifndef FVP_MAX_CPUS_PER_CLUSTER
-#define FVP_MAX_CPUS_PER_CLUSTER 4
+#error "FVP_MAX_CPUS_PER_CLUSTER is not set in makefile"
#endif
#ifndef FVP_MAX_PE_PER_CPU
-# define FVP_MAX_PE_PER_CPU 1
+#error "FVP_MAX_PE_PER_CPU is not set in makefile"
#endif
#define FVP_PRIMARY_CPU 0x0
diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h
index f1afe36..c2b7b98 100644
--- a/plat/arm/board/fvp/include/platform_def.h
+++ b/plat/arm/board/fvp/include/platform_def.h
@@ -17,11 +17,12 @@
#include "../fvp_def.h"
/* Required platform porting definitions */
-#define PLATFORM_CORE_COUNT \
- (FVP_CLUSTER_COUNT * FVP_MAX_CPUS_PER_CLUSTER * FVP_MAX_PE_PER_CPU)
+#define PLATFORM_CORE_COUNT (U(FVP_CLUSTER_COUNT) * \
+ U(FVP_MAX_CPUS_PER_CLUSTER) * \
+ U(FVP_MAX_PE_PER_CPU))
-#define PLAT_NUM_PWR_DOMAINS (FVP_CLUSTER_COUNT + \
- PLATFORM_CORE_COUNT) + 1
+#define PLAT_NUM_PWR_DOMAINS (U(FVP_CLUSTER_COUNT) + \
+ PLATFORM_CORE_COUNT + U(1))
#define PLAT_MAX_PWR_LVL ARM_PWR_LVL2
@@ -32,7 +33,7 @@
/*
* Required ARM standard platform porting definitions
*/
-#define PLAT_ARM_CLUSTER_COUNT FVP_CLUSTER_COUNT
+#define PLAT_ARM_CLUSTER_COUNT U(FVP_CLUSTER_COUNT)
#define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00040000) /* 256 KB */
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index ea72e79..97a326c 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -245,10 +245,12 @@
DYNAMIC_WORKAROUND_CVE_2018_3639 := 1
# Enable reclaiming of BL31 initialisation code for secondary cores
-# stacks for FVP.
+# stacks for FVP. However, don't enable reclaiming for clang.
ifneq (${RESET_TO_BL31},1)
+ifeq ($(findstring clang,$(notdir $(CC))),)
RECLAIM_INIT_CODE := 1
endif
+endif
ifeq (${ENABLE_AMU},1)
BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \
diff --git a/plat/arm/board/fvp_ve/fvp_ve_def.h b/plat/arm/board/fvp_ve/fvp_ve_def.h
index 565753a..98de5f6 100644
--- a/plat/arm/board/fvp_ve/fvp_ve_def.h
+++ b/plat/arm/board/fvp_ve/fvp_ve_def.h
@@ -10,17 +10,17 @@
#include <lib/utils_def.h>
/* Default cluster count for FVP VE */
-#define FVP_VE_CLUSTER_COUNT 1
+#define FVP_VE_CLUSTER_COUNT U(1)
/* Default number of CPUs per cluster on FVP VE */
-#define FVP_VE_MAX_CPUS_PER_CLUSTER 1
+#define FVP_VE_MAX_CPUS_PER_CLUSTER U(1)
/* Default number of threads per CPU on FVP VE */
-#define FVP_VE_MAX_PE_PER_CPU 1
+#define FVP_VE_MAX_PE_PER_CPU U(1)
-#define FVP_VE_CORE_COUNT 1
+#define FVP_VE_CORE_COUNT U(1)
-#define FVP_VE_PRIMARY_CPU 0x0
+#define FVP_VE_PRIMARY_CPU 0x0
/*******************************************************************************
* FVP memory map related constants
diff --git a/plat/arm/board/fvp_ve/include/platform_def.h b/plat/arm/board/fvp_ve/include/platform_def.h
index 4e575e1..1b07a9b 100644
--- a/plat/arm/board/fvp_ve/include/platform_def.h
+++ b/plat/arm/board/fvp_ve/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2020, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -211,9 +211,9 @@
#define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
/* Required platform porting definitions */
-#define PLATFORM_CORE_COUNT 1
+#define PLATFORM_CORE_COUNT FVP_VE_CLUSTER_COUNT
#define PLAT_NUM_PWR_DOMAINS ((FVP_VE_CLUSTER_COUNT + \
- PLATFORM_CORE_COUNT) + 1)
+ PLATFORM_CORE_COUNT) + U(1))
#define PLAT_MAX_PWR_LVL 2
diff --git a/plat/arm/board/juno/juno_def.h b/plat/arm/board/juno/juno_def.h
index 7a8bedf..3b34a9f 100644
--- a/plat/arm/board/juno/juno_def.h
+++ b/plat/arm/board/juno/juno_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -32,9 +32,9 @@
/*******************************************************************************
* Juno topology related constants
******************************************************************************/
-#define JUNO_CLUSTER_COUNT 2
-#define JUNO_CLUSTER0_CORE_COUNT 2
-#define JUNO_CLUSTER1_CORE_COUNT 4
+#define JUNO_CLUSTER_COUNT U(2)
+#define JUNO_CLUSTER0_CORE_COUNT U(2)
+#define JUNO_CLUSTER1_CORE_COUNT U(4)
/*******************************************************************************
* TZC-400 related constants
diff --git a/plat/arm/board/rde1edge/include/platform_def.h b/plat/arm/board/rde1edge/include/platform_def.h
index 50b04f0..2be3f88 100644
--- a/plat/arm/board/rde1edge/include/platform_def.h
+++ b/plat/arm/board/rde1edge/include/platform_def.h
@@ -11,9 +11,9 @@
#include <sgi_base_platform_def.h>
-#define PLAT_ARM_CLUSTER_COUNT 2
-#define CSS_SGI_MAX_CPUS_PER_CLUSTER 8
-#define CSS_SGI_MAX_PE_PER_CPU 2
+#define PLAT_ARM_CLUSTER_COUNT U(2)
+#define CSS_SGI_MAX_CPUS_PER_CLUSTER U(8)
+#define CSS_SGI_MAX_PE_PER_CPU U(2)
#define PLAT_CSS_MHU_BASE UL(0x45400000)
#define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE
diff --git a/plat/arm/board/rdn1edge/include/platform_def.h b/plat/arm/board/rdn1edge/include/platform_def.h
index 580ab8e..c635faa 100644
--- a/plat/arm/board/rdn1edge/include/platform_def.h
+++ b/plat/arm/board/rdn1edge/include/platform_def.h
@@ -11,9 +11,9 @@
#include <sgi_base_platform_def.h>
-#define PLAT_ARM_CLUSTER_COUNT 2
-#define CSS_SGI_MAX_CPUS_PER_CLUSTER 4
-#define CSS_SGI_MAX_PE_PER_CPU 1
+#define PLAT_ARM_CLUSTER_COUNT U(2)
+#define CSS_SGI_MAX_CPUS_PER_CLUSTER U(4)
+#define CSS_SGI_MAX_PE_PER_CPU U(1)
#define PLAT_CSS_MHU_BASE UL(0x45400000)
#define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE
diff --git a/plat/arm/board/sgi575/include/platform_def.h b/plat/arm/board/sgi575/include/platform_def.h
index f00146f..fd59e52 100644
--- a/plat/arm/board/sgi575/include/platform_def.h
+++ b/plat/arm/board/sgi575/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -11,9 +11,9 @@
#include <sgi_base_platform_def.h>
-#define PLAT_ARM_CLUSTER_COUNT 2
-#define CSS_SGI_MAX_CPUS_PER_CLUSTER 4
-#define CSS_SGI_MAX_PE_PER_CPU 1
+#define PLAT_ARM_CLUSTER_COUNT U(2)
+#define CSS_SGI_MAX_CPUS_PER_CLUSTER U(4)
+#define CSS_SGI_MAX_PE_PER_CPU U(1)
#define PLAT_CSS_MHU_BASE UL(0x45000000)
#define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE
diff --git a/plat/arm/board/sgm775/include/platform_def.h b/plat/arm/board/sgm775/include/platform_def.h
index 27d1b33..d165ff9 100644
--- a/plat/arm/board/sgm775/include/platform_def.h
+++ b/plat/arm/board/sgm775/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -9,8 +9,8 @@
#include <sgm_base_platform_def.h>
-#define PLAT_MAX_CPUS_PER_CLUSTER 8
-#define PLAT_MAX_PE_PER_CPU 1
+#define PLAT_MAX_CPUS_PER_CLUSTER U(8)
+#define PLAT_MAX_PE_PER_CPU U(1)
/*
* Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
diff --git a/plat/arm/css/sgm/include/sgm_base_platform_def.h b/plat/arm/css/sgm/include/sgm_base_platform_def.h
index f349c19..24bbed5 100644
--- a/plat/arm/css/sgm/include/sgm_base_platform_def.h
+++ b/plat/arm/css/sgm/include/sgm_base_platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -17,8 +17,8 @@
#include <plat/common/common_def.h>
/* CPU topology */
-#define PLAT_ARM_CLUSTER_COUNT 1
-#define PLAT_ARM_CLUSTER_CORE_COUNT 8
+#define PLAT_ARM_CLUSTER_COUNT U(1)
+#define PLAT_ARM_CLUSTER_CORE_COUNT U(8)
#define PLATFORM_CORE_COUNT PLAT_ARM_CLUSTER_CORE_COUNT
#define PLAT_MAX_PWR_LVL ARM_PWR_LVL2
diff --git a/plat/common/plat_psci_common.c b/plat/common/plat_psci_common.c
index 16bec79..80ed819 100644
--- a/plat/common/plat_psci_common.c
+++ b/plat/common/plat_psci_common.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -31,6 +31,8 @@
#define PSCI_STAT_ID_EXIT_LOW_PWR 1
#define PSCI_STAT_TOTAL_IDS 2
+PMF_DECLARE_CAPTURE_TIMESTAMP(psci_svc)
+PMF_DECLARE_GET_TIMESTAMP(psci_svc)
PMF_REGISTER_SERVICE(psci_svc, PMF_PSCI_STAT_SVC_ID, PSCI_STAT_TOTAL_IDS,
PMF_STORE_ENABLE)
@@ -92,7 +94,7 @@
*/
u_register_t plat_psci_stat_get_residency(unsigned int lvl,
const psci_power_state_t *state_info,
- int last_cpu_idx)
+ unsigned int last_cpu_idx)
{
plat_local_state_t state;
unsigned long long pwrup_ts = 0, pwrdn_ts = 0;
@@ -103,7 +105,7 @@
assert(last_cpu_idx <= PLATFORM_CORE_COUNT);
if (lvl == PSCI_CPU_PWR_LVL)
- assert((unsigned int)last_cpu_idx == plat_my_core_pos());
+ assert(last_cpu_idx == plat_my_core_pos());
/*
* If power down is requested, then timestamp capture will
diff --git a/plat/imx/imx8m/include/imx8m_psci.h b/plat/imx/imx8m/include/imx8m_psci.h
index 4966403..c33d25e 100644
--- a/plat/imx/imx8m/include/imx8m_psci.h
+++ b/plat/imx/imx8m/include/imx8m_psci.h
@@ -15,13 +15,9 @@
void imx_pwr_domain_on_finish(const psci_power_state_t *target_state);
void imx_pwr_domain_off(const psci_power_state_t *target_state);
int imx_validate_ns_entrypoint(uintptr_t ns_entrypoint);
-int imx_validate_power_state(unsigned int power_state, psci_power_state_t *rq_state);
void imx_cpu_standby(plat_local_state_t cpu_state);
void imx_domain_suspend(const psci_power_state_t *target_state);
void imx_domain_suspend_finish(const psci_power_state_t *target_state);
-void imx_get_sys_suspend_power_state(psci_power_state_t *req_state);
-void __dead2 imx_system_reset(void);
-void __dead2 imx_system_off(void);
void __dead2 imx_pwr_domain_pwr_down_wfi(const psci_power_state_t *target_state);
#endif /* IMX8M_PSCI_H */
diff --git a/plat/intel/soc/agilex/include/agilex_system_manager.h b/plat/intel/soc/agilex/include/agilex_system_manager.h
index 381c2d3..be29536 100644
--- a/plat/intel/soc/agilex/include/agilex_system_manager.h
+++ b/plat/intel/soc/agilex/include/agilex_system_manager.h
@@ -73,7 +73,6 @@
#define DISABLE_BRIDGE_FIREWALL 0x0ffe0101
#define DISABLE_L4_FIREWALL (BIT(0) | BIT(16) | BIT(24))
-void enable_nonsecure_access(void);
void enable_ns_bridge_access(void);
#endif
diff --git a/plat/intel/soc/agilex/soc/agilex_memory_controller.c b/plat/intel/soc/agilex/soc/agilex_memory_controller.c
index 5f3cae7..2aabe87 100644
--- a/plat/intel/soc/agilex/soc/agilex_memory_controller.c
+++ b/plat/intel/soc/agilex/soc/agilex_memory_controller.c
@@ -20,9 +20,8 @@
#define PRE_CALIBRATION_DELAY 1
#define POST_CALIBRATION_DELAY 1
#define TIMEOUT_EMIF_CALIBRATION 1000
-#define CLEAR_EMIF_DELAY 50000
-#define CLEAR_EMIF_TIMEOUT 0x100000
-#define TIMEOUT_INT_RESP 10000
+#define CLEAR_EMIF_DELAY 1000
+#define CLEAR_EMIF_TIMEOUT 1000
#define DDR_CONFIG(A, B, C, R) (((A) << 24) | ((B) << 16) | ((C) << 8) | (R))
#define DDR_CONFIG_ELEMENTS (sizeof(ddr_config)/sizeof(uint32_t))
@@ -125,7 +124,7 @@
data = mmio_read_32(AGX_MPFE_HMC_ADP_DDRCALSTAT);
if (AGX_MPFE_HMC_ADP_DDRCALSTAT_CAL(data) == 1)
break;
- mdelay(1);
+ udelay(500);
} while (++timeout < TIMEOUT_EMIF_CALIBRATION);
if (AGX_MPFE_HMC_ADP_DDRCALSTAT_CAL(data) == 0) {
diff --git a/plat/intel/soc/common/drivers/qspi/cadence_qspi.c b/plat/intel/soc/common/drivers/qspi/cadence_qspi.c
index d7cd71b..cecf560 100644
--- a/plat/intel/soc/common/drivers/qspi/cadence_qspi.c
+++ b/plat/intel/soc/common/drivers/qspi/cadence_qspi.c
@@ -688,10 +688,7 @@
if ((offset >= qspi_device_size) ||
(offset + size - 1 >= qspi_device_size) ||
- (size == 0) ||
- ((long) ((int *)buffer) & 0x3) ||
- (offset & 0x3) ||
- (size & 0x3)) {
+ (size == 0)) {
ERROR("Invalid read parameter\n");
return -1;
}
@@ -766,11 +763,9 @@
if ((offset >= qspi_device_size) ||
(offset + size - 1 >= qspi_device_size) ||
- (size == 0) ||
- ((long)buffer & 0x3) ||
- (offset & 0x3) ||
- (size & 0x3))
+ (size == 0)) {
return -2;
+ }
if (CAD_QSPI_INDWR_RDSTAT(mmio_read_32(CAD_QSPI_OFFSET +
CAD_QSPI_INDWR))) {
diff --git a/plat/intel/soc/stratix10/include/s10_system_manager.h b/plat/intel/soc/stratix10/include/s10_system_manager.h
index a67d689..4abfedb 100644
--- a/plat/intel/soc/stratix10/include/s10_system_manager.h
+++ b/plat/intel/soc/stratix10/include/s10_system_manager.h
@@ -69,5 +69,3 @@
#define DISABLE_L4_FIREWALL (BIT(0) | BIT(16) | BIT(24))
-void enable_nonsecure_access(void);
-
diff --git a/plat/intel/soc/stratix10/soc/s10_memory_controller.c b/plat/intel/soc/stratix10/soc/s10_memory_controller.c
index ed06f54..cb45251 100644
--- a/plat/intel/soc/stratix10/soc/s10_memory_controller.c
+++ b/plat/intel/soc/stratix10/soc/s10_memory_controller.c
@@ -22,10 +22,9 @@
#define MAX_MEM_CAL_RETRY 3
#define PRE_CALIBRATION_DELAY 1
#define POST_CALIBRATION_DELAY 1
-#define TIMEOUT_EMIF_CALIBRATION 100
-#define CLEAR_EMIF_DELAY 50000
-#define CLEAR_EMIF_TIMEOUT 0x100000
-#define TIMEOUT_INT_RESP 10000
+#define TIMEOUT_EMIF_CALIBRATION 1000
+#define CLEAR_EMIF_DELAY 1000
+#define CLEAR_EMIF_TIMEOUT 1000
#define DDR_CONFIG(A, B, C, R) (((A) << 24) | ((B) << 16) | ((C) << 8) | (R))
#define DDR_CONFIG_ELEMENTS (sizeof(ddr_config)/sizeof(uint32_t))
@@ -128,13 +127,13 @@
data = mmio_read_32(S10_MPFE_HMC_ADP_DDRCALSTAT);
if (S10_MPFE_HMC_ADP_DDRCALSTAT_CAL(data) == 1)
break;
- udelay(1);
+ udelay(500);
} while (++timeout < TIMEOUT_EMIF_CALIBRATION);
if (S10_MPFE_HMC_ADP_DDRCALSTAT_CAL(data) == 0) {
status = clear_emif();
- if (status)
- ERROR("Failed to clear Emif\n");
+ if (status)
+ ERROR("Failed to clear Emif\n");
} else {
break;
}
diff --git a/plat/mediatek/mt8173/drivers/spm/spm.h b/plat/mediatek/mt8173/drivers/spm/spm.h
index 403303a..0c05410 100644
--- a/plat/mediatek/mt8173/drivers/spm/spm.h
+++ b/plat/mediatek/mt8173/drivers/spm/spm.h
@@ -320,7 +320,6 @@
void spm_go_to_hotplug(void);
void spm_init_event_vector(const struct pcm_desc *pcmdesc);
void spm_kick_im_to_fetch(const struct pcm_desc *pcmdesc);
-void spm_set_sysclk_settle(void);
int is_mcdi_ready(void);
int is_hotplug_ready(void);
int is_suspend_ready(void);
diff --git a/plat/mediatek/mt8183/drivers/spm/spm.c b/plat/mediatek/mt8183/drivers/spm/spm.c
index 547af57..d6d2344 100644
--- a/plat/mediatek/mt8183/drivers/spm/spm.c
+++ b/plat/mediatek/mt8183/drivers/spm/spm.c
@@ -12,6 +12,12 @@
DEFINE_BAKERY_LOCK(spm_lock);
+/* SPM_DVS_LEVEL */
+#define SPM_VMODEM_LEVEL_MASK (0xff << 16)
+#define SPM_VMODEM_LEVEL (1U << 18)
+#define SPM_VCORE_LEVEL_MASK (0xff)
+#define SPM_VCORE_LEVEL (1U << 1)
+
/* CLK_SCP_CFG_0 */
#define SPM_CK_OFF_CONTROL (0x3FF)
@@ -339,6 +345,11 @@
spm_lock_init();
mt_spm_pmic_wrap_set_phase(PMIC_WRAP_PHASE_ALLINONE);
+ /* Set Vmodem / Vcore DVS init level */
+ mmio_clrsetbits_32(SPM_DVS_LEVEL,
+ SPM_VMODEM_LEVEL_MASK | SPM_VCORE_LEVEL_MASK,
+ SPM_VMODEM_LEVEL | SPM_VCORE_LEVEL);
+
/* switch ck_off/axi_26m control to SPM */
mmio_setbits_32(CLK_SCP_CFG_0, SPM_CK_OFF_CONTROL);
mmio_setbits_32(CLK_SCP_CFG_1, SPM_AXI_26M_SEL);
diff --git a/plat/nvidia/tegra/include/drivers/bpmp_ipc.h b/plat/nvidia/tegra/include/drivers/bpmp_ipc.h
index 0d1e405..a0d02c9 100644
--- a/plat/nvidia/tegra/include/drivers/bpmp_ipc.h
+++ b/plat/nvidia/tegra/include/drivers/bpmp_ipc.h
@@ -1,11 +1,12 @@
/*
* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef __BPMP_IPC_H__
-#define __BPMP_IPC_H__
+#ifndef BPMP_IPC_H
+#define BPMP_IPC_H
#include <lib/utils_def.h>
#include <stdbool.h>
@@ -44,4 +45,4 @@
*/
int tegra_bpmp_ipc_disable_clock(uint32_t clk_id);
-#endif /* __BPMP_IPC_H__ */
+#endif /* BPMP_IPC_H */
diff --git a/plat/nvidia/tegra/include/drivers/gpcdma.h b/plat/nvidia/tegra/include/drivers/gpcdma.h
index fb5486a..a59df37 100644
--- a/plat/nvidia/tegra/include/drivers/gpcdma.h
+++ b/plat/nvidia/tegra/include/drivers/gpcdma.h
@@ -1,11 +1,12 @@
/*
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef __GPCDMA_H__
-#define __GPCDMA_H__
+#ifndef GPCDMA_H
+#define GPCDMA_H
#include <stdint.h>
@@ -13,4 +14,4 @@
uint32_t num_bytes);
void tegra_gpcdma_zeromem(uint64_t dst_addr, uint32_t num_bytes);
-#endif /* __GPCDMA_H__ */
+#endif /* GPCDMA_H */
diff --git a/plat/nvidia/tegra/include/drivers/security_engine.h b/plat/nvidia/tegra/include/drivers/security_engine.h
index 4ab2f9a..8a24924 100644
--- a/plat/nvidia/tegra/include/drivers/security_engine.h
+++ b/plat/nvidia/tegra/include/drivers/security_engine.h
@@ -1,5 +1,5 @@
-/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+/*
+ * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
diff --git a/plat/nvidia/tegra/include/drivers/tegra_gic.h b/plat/nvidia/tegra/include/drivers/tegra_gic.h
index 6106b40..6661dff 100644
--- a/plat/nvidia/tegra/include/drivers/tegra_gic.h
+++ b/plat/nvidia/tegra/include/drivers/tegra_gic.h
@@ -1,11 +1,12 @@
/*
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef __TEGRA_GIC_H__
-#define __TEGRA_GIC_H__
+#ifndef TEGRA_GIC_H
+#define TEGRA_GIC_H
#include <common/interrupt_props.h>
@@ -26,4 +27,4 @@
void tegra_gic_setup(const interrupt_prop_t *interrupt_props,
unsigned int interrupt_props_num);
-#endif /* __TEGRA_GIC_H__ */
+#endif /* TEGRA_GIC_H */
diff --git a/plat/nvidia/tegra/include/lib/profiler.h b/plat/nvidia/tegra/include/lib/profiler.h
index 60f8d80..684c872 100644
--- a/plat/nvidia/tegra/include/lib/profiler.h
+++ b/plat/nvidia/tegra/include/lib/profiler.h
@@ -1,11 +1,12 @@
/*
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef __PROFILER_H__
-#define __PROFILER_H__
+#ifndef PROFILER_H
+#define PROFILER_H
/*******************************************************************************
* Number of bytes of memory used by the profiler on Tegra
@@ -16,4 +17,4 @@
void boot_profiler_add_record(const char *str);
void boot_profiler_deinit(void);
-#endif /* __PROFILER_H__ */
+#endif /* PROFILER_H */
diff --git a/plat/nvidia/tegra/include/t194/tegra194_private.h b/plat/nvidia/tegra/include/t194/tegra194_private.h
index e519cdc..8f1deb2 100644
--- a/plat/nvidia/tegra/include/t194/tegra194_private.h
+++ b/plat/nvidia/tegra/include/t194/tegra194_private.h
@@ -1,11 +1,11 @@
/*
- * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef __TEGRA194_PRIVATE_H__
-#define __TEGRA194_PRIVATE_H__
+#ifndef TEGRA194_PRIVATE_H
+#define TEGRA194_PRIVATE_H
void tegra194_cpu_reset_handler(void);
uint64_t tegra194_get_cpu_reset_handler_base(void);
@@ -13,4 +13,4 @@
uint64_t tegra194_get_smmu_ctx_offset(void);
void tegra194_set_system_suspend_entry(void);
-#endif /* __TEGRA194_PRIVATE_H__ */
+#endif /* TEGRA194_PRIVATE_H */
diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h
index 67f5abb..e20b2c6 100644
--- a/plat/nvidia/tegra/include/t194/tegra_def.h
+++ b/plat/nvidia/tegra/include/t194/tegra_def.h
@@ -1,11 +1,11 @@
/*
- * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef __TEGRA_DEF_H__
-#define __TEGRA_DEF_H__
+#ifndef TEGRA_DEF_H
+#define TEGRA_DEF_H
#include <lib/utils_def.h>
@@ -237,4 +237,4 @@
#define TEGRA_SID_XUSB_VF2 U(0x5f)
#define TEGRA_SID_XUSB_VF3 U(0x60)
-#endif /* __TEGRA_DEF_H__ */
+#endif /* TEGRA_DEF_H */
diff --git a/plat/nvidia/tegra/include/t194/tegra_mc_def.h b/plat/nvidia/tegra/include/t194/tegra_mc_def.h
index e0444c1..1433a2e 100644
--- a/plat/nvidia/tegra/include/t194/tegra_mc_def.h
+++ b/plat/nvidia/tegra/include/t194/tegra_mc_def.h
@@ -1,11 +1,11 @@
/*
- * Copyright (c) 2019, NVIDIA Corporation. All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef __TEGRA_MC_DEF_H__
-#define __TEGRA_MC_DEF_H__
+#ifndef TEGRA_MC_DEF_H
+#define TEGRA_MC_DEF_H
/*******************************************************************************
* Memory Controller Order_id registers
@@ -647,4 +647,4 @@
#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK (ULL(0x3) << 11)
#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU (ULL(0) << 11)
-#endif /* __TEGRA_MC_DEF_H__ */
+#endif /* TEGRA_MC_DEF_H */
diff --git a/plat/nvidia/tegra/include/tegra_private.h b/plat/nvidia/tegra/include/tegra_private.h
index cd2f773..761acde 100644
--- a/plat/nvidia/tegra/include/tegra_private.h
+++ b/plat/nvidia/tegra/include/tegra_private.h
@@ -137,7 +137,6 @@
void tegra_delay_timer_init(void);
void tegra_secure_entrypoint(void);
-void tegra186_cpu_reset_handler(void);
/* Declarations for tegra_sip_calls.c */
uintptr_t tegra_sip_handler(uint32_t smc_fid,
diff --git a/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h b/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h
index 3994b2d..226ab5b 100644
--- a/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h
+++ b/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h
@@ -1,11 +1,11 @@
/*
- * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef __MCE_PRIVATE_H__
-#define __MCE_PRIVATE_H__
+#ifndef MCE_PRIVATE_H
+#define MCE_PRIVATE_H
#include <tegra_def.h>
@@ -66,10 +66,9 @@
uint64_t nvg_cache_clean(void);
uint64_t nvg_cache_clean_inval(void);
uint64_t nvg_cache_inval_all(void);
-int32_t nvg_roc_clean_cache_trbits(void);
void nvg_enable_strict_checking_mode(void);
/* MCE helper functions */
void mce_enable_strict_checking(void);
-#endif /* __MCE_PRIVATE_H__ */
+#endif /* MCE_PRIVATE_H */
diff --git a/plat/nvidia/tegra/soc/t194/drivers/include/se.h b/plat/nvidia/tegra/soc/t194/drivers/include/se.h
index 6e656f6..e7cf88d 100644
--- a/plat/nvidia/tegra/soc/t194/drivers/include/se.h
+++ b/plat/nvidia/tegra/soc/t194/drivers/include/se.h
@@ -1,13 +1,13 @@
/*
- * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef __SE_H__
-#define __SE_H__
+#ifndef SE_H
+#define SE_H
int32_t tegra_se_suspend(void);
void tegra_se_resume(void);
-#endif /* __SE_H__ */
+#endif /* SE_H */
diff --git a/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c b/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c
index 1dd1f51..536ed57 100644
--- a/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c
+++ b/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -165,7 +165,7 @@
/* sanity check the core ID value */
if (core > (uint32_t)PLATFORM_CORE_COUNT) {
ERROR("%s: unknown core id (%d)\n", __func__, core);
- ret = EINVAL;
+ ret = -EINVAL;
} else {
/* get a core online */
nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_ONLINE_CORE,
@@ -183,15 +183,15 @@
*/
int32_t nvg_update_ccplex_gsc(uint32_t gsc_idx)
{
- int32_t ret;
+ int32_t ret = 0;
/* sanity check GSC ID */
if (gsc_idx > (uint32_t)TEGRA_NVG_CHANNEL_UPDATE_GSC_VPR) {
ERROR("%s: unknown gsc_idx (%u)\n", __func__, gsc_idx);
- ret = EINVAL;
+ ret = -EINVAL;
} else {
nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_UPDATE_CCPLEX_GSC,
- (uint64_t)gsc_idx);
+ (uint64_t)gsc_idx);
}
return ret;
@@ -209,11 +209,12 @@
ID_AFR0_EL1_CACHE_OPS_MASK) == 1U) {
if (nvg_cache_clean() == 0U) {
ERROR("%s: failed\n", __func__);
- ret = EINVAL;
+ ret = -ENODEV;
}
} else {
- ret = EINVAL;
+ ret = -ENOTSUP;
}
+
return ret;
}
@@ -229,11 +230,12 @@
ID_AFR0_EL1_CACHE_OPS_MASK) == 1U) {
if (nvg_cache_clean_inval() == 0U) {
ERROR("%s: failed\n", __func__);
- ret = EINVAL;
+ ret = -ENODEV;
}
} else {
- ret = EINVAL;
+ ret = -ENOTSUP;
}
+
return ret;
}
@@ -249,11 +251,12 @@
ID_AFR0_EL1_CACHE_OPS_MASK) == 1U) {
if (nvg_cache_inval_all() == 0U) {
ERROR("%s: failed\n", __func__);
- ret = EINVAL;
+ ret = -ENODEV;
}
} else {
- ret = EINVAL;
+ ret = -ENOTSUP;
}
+
return ret;
}
@@ -271,8 +274,8 @@
(state != (uint32_t)TEGRA_NVG_CORE_C6) &&
(state != (uint32_t)TEGRA_NVG_CORE_C7))
{
- ERROR("%s: unknown cstate (%d)\n", __func__, state);
- ret = EINVAL;
+ ERROR("%s: unknown cstate (%u)\n", __func__, state);
+ ret = -EINVAL;
} else {
/* time (TSC ticks) until the core is expected to get a wake event */
nvg_set_wake_time(wake_time);
diff --git a/plat/nvidia/tegra/soc/t194/drivers/se/se.c b/plat/nvidia/tegra/soc/t194/drivers/se/se.c
index 3df670c..a9f4610 100644
--- a/plat/nvidia/tegra/soc/t194/drivers/se/se.c
+++ b/plat/nvidia/tegra/soc/t194/drivers/se/se.c
@@ -1,4 +1,5 @@
-/*
+/*
+ * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
diff --git a/plat/nvidia/tegra/soc/t194/drivers/se/se_private.h b/plat/nvidia/tegra/soc/t194/drivers/se/se_private.h
index 7d531bb..a2c5d1c 100644
--- a/plat/nvidia/tegra/soc/t194/drivers/se/se_private.h
+++ b/plat/nvidia/tegra/soc/t194/drivers/se/se_private.h
@@ -1,11 +1,12 @@
-/*
- * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
+/*
+ * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef __SE_PRIVATE_H__
-#define __SE_PRIVATE_H__
+#ifndef SE_PRIVATE_H
+#define SE_PRIVATE_H
#include <lib/utils_def.h>
@@ -81,4 +82,4 @@
mmio_write_32(TEGRA_SE0_BASE + offset, val);
}
-#endif /* __SE_PRIVATE_H__ */
+#endif /* SE_PRIVATE_H */
diff --git a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c
index 1188a3b..fa5ba62 100644
--- a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c
+++ b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c
@@ -26,7 +26,6 @@
#include <tegra_platform.h>
#include <tegra_private.h>
-extern void tegra194_cpu_reset_handler(void);
extern uint32_t __tegra194_cpu_reset_handler_data,
__tegra194_cpu_reset_handler_end;
diff --git a/plat/nvidia/tegra/soc/t210/drivers/se/se_private.h b/plat/nvidia/tegra/soc/t210/drivers/se/se_private.h
index be1f9cc..352107d 100644
--- a/plat/nvidia/tegra/soc/t210/drivers/se/se_private.h
+++ b/plat/nvidia/tegra/soc/t210/drivers/se/se_private.h
@@ -1,5 +1,5 @@
-/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+/*
+ * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
diff --git a/plat/nvidia/tegra/soc/t210/drivers/se/security_engine.c b/plat/nvidia/tegra/soc/t210/drivers/se/security_engine.c
index 8d7dbf9..d5e0491 100644
--- a/plat/nvidia/tegra/soc/t210/drivers/se/security_engine.c
+++ b/plat/nvidia/tegra/soc/t210/drivers/se/security_engine.c
@@ -1,5 +1,5 @@
-/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+/*
+ * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
diff --git a/plat/renesas/rcar/bl2_plat_mem_params_desc.c b/plat/renesas/rcar/bl2_plat_mem_params_desc.c
index 3b124c7..bf2706d 100644
--- a/plat/renesas/rcar/bl2_plat_mem_params_desc.c
+++ b/plat/renesas/rcar/bl2_plat_mem_params_desc.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -53,6 +53,7 @@
entry_point_info_t, SECURE | EXECUTABLE),
.ep_info.pc = BL32_BASE,
.ep_info.spsr = 0,
+ .ep_info.args.arg3 = (uintptr_t)fdt_blob,
SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2,
image_info_t, 0),
diff --git a/plat/renesas/rcar/platform.mk b/plat/renesas/rcar/platform.mk
index dc58e19..4c41dd3 100644
--- a/plat/renesas/rcar/platform.mk
+++ b/plat/renesas/rcar/platform.mk
@@ -348,12 +348,12 @@
ERRATA_A57_859972 := 1
ERRATA_A57_813419 := 1
-include drivers/staging/renesas/rcar/ddr/ddr.mk
+include drivers/renesas/rcar/ddr/ddr.mk
include drivers/renesas/rcar/qos/qos.mk
include drivers/renesas/rcar/pfc/pfc.mk
include lib/libfdt/libfdt.mk
-PLAT_INCLUDES := -Idrivers/staging/renesas/rcar/ddr \
+PLAT_INCLUDES := -Idrivers/renesas/rcar/ddr \
-Idrivers/renesas/rcar/qos \
-Idrivers/renesas/rcar/iic_dvfs \
-Idrivers/renesas/rcar/board \
diff --git a/plat/rockchip/rk3328/drivers/soc/soc.h b/plat/rockchip/rk3328/drivers/soc/soc.h
index a1f35b2..e8cbc09 100644
--- a/plat/rockchip/rk3328/drivers/soc/soc.h
+++ b/plat/rockchip/rk3328/drivers/soc/soc.h
@@ -16,8 +16,6 @@
#define TIMER_INTSTATUS 0x18
#define TIMER_EN 0x1
-extern const unsigned char rockchip_power_domain_tree_desc[];
-
/**************************** read/write **************************************/
#ifndef BITS_WMSK
#define BITS_WMSK(msk, shift) ((msk) << (shift + REG_MSK_SHIFT))
diff --git a/plat/rockchip/rk3328/platform.mk b/plat/rockchip/rk3328/platform.mk
index 0c5cfae..0219422 100644
--- a/plat/rockchip/rk3328/platform.mk
+++ b/plat/rockchip/rk3328/platform.mk
@@ -59,6 +59,9 @@
include lib/coreboot/coreboot.mk
include lib/libfdt/libfdt.mk
+# Enable workarounds for selected Cortex-A53 errata
+ERRATA_A53_855873 := 1
+
$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT))
$(eval $(call add_define,PLAT_SKIP_OPTEE_S_EL1_INT_REGISTER))
diff --git a/plat/rpi/rpi4/aarch64/plat_helpers.S b/plat/rpi/rpi4/aarch64/plat_helpers.S
index 46073b7..083c30e 100644
--- a/plat/rpi/rpi4/aarch64/plat_helpers.S
+++ b/plat/rpi/rpi4/aarch64/plat_helpers.S
@@ -136,8 +136,8 @@
*/
func plat_crash_console_init
mov_imm x0, PLAT_RPI3_UART_BASE
- mov_imm x1, PLAT_RPI4_VPU_CLK_RATE
- mov_imm x2, PLAT_RPI3_UART_BAUDRATE
+ mov x1, xzr
+ mov x2, xzr
b console_16550_core_init
endfunc plat_crash_console_init
diff --git a/plat/rpi/rpi4/include/rpi_hw.h b/plat/rpi/rpi4/include/rpi_hw.h
index ed367ee..b1dd4e9 100644
--- a/plat/rpi/rpi4/include/rpi_hw.h
+++ b/plat/rpi/rpi4/include/rpi_hw.h
@@ -59,13 +59,6 @@
#define RPI3_PM_RSTS_WRCFG_HALT U(0x00000555)
/*
- * Clock controller
- */
-#define RPI4_IO_CLOCK_OFFSET ULL(0x00101000)
-#define RPI4_CLOCK_BASE (RPI_IO_BASE + RPI4_IO_CLOCK_OFFSET)
-#define RPI4_VPU_CLOCK_DIVIDER ULL(0x0000000c)
-
-/*
* Hardware random number generator.
*/
#define RPI3_IO_RNG_OFFSET ULL(0x00104000)
@@ -88,7 +81,6 @@
*/
#define RPI3_IO_MINI_UART_OFFSET ULL(0x00215040)
#define RPI3_MINI_UART_BASE (RPI_IO_BASE + RPI3_IO_MINI_UART_OFFSET)
-#define PLAT_RPI4_VPU_CLK_RATE ULL(1000000000)
/*
* GPIO controller
diff --git a/plat/rpi/rpi4/rpi4_bl31_setup.c b/plat/rpi/rpi4/rpi4_bl31_setup.c
index 53ab0c2..9e3b539 100644
--- a/plat/rpi/rpi4/rpi4_bl31_setup.c
+++ b/plat/rpi/rpi4/rpi4_bl31_setup.c
@@ -119,8 +119,6 @@
u_register_t arg2, u_register_t arg3)
{
- uint32_t div_reg;
-
/*
* LOCAL_CONTROL:
* Bit 9 clear: Increment by 1 (vs. 2).
@@ -136,16 +134,12 @@
/*
* Initialize the console to provide early debug support.
- * Different GPU firmware revisions set up the VPU divider differently,
- * so read the actual divider register to learn the UART base clock
- * rate. The divider is encoded as a 12.12 fixed point number, but we
- * just care about the integer part of it.
+ * We rely on the GPU firmware to have initialised the UART correctly,
+ * as the baud base clock rate differs across GPU firmware revisions.
+ * Providing a base clock of 0 lets the 16550 UART init routine skip
+ * the initial enablement and baud rate setup.
*/
- div_reg = mmio_read_32(RPI4_CLOCK_BASE + RPI4_VPU_CLOCK_DIVIDER);
- div_reg = (div_reg >> 12) & 0xfff;
- if (div_reg == 0)
- div_reg = 1;
- rpi3_console_init(PLAT_RPI4_VPU_CLK_RATE / div_reg);
+ rpi3_console_init(0);
bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
bl33_image_ep_info.spsr = rpi3_get_spsr_for_bl33_entry();
diff --git a/plat/socionext/uniphier/uniphier_image_desc.c b/plat/socionext/uniphier/uniphier_image_desc.c
index 9e171e0..817029a 100644
--- a/plat/socionext/uniphier/uniphier_image_desc.c
+++ b/plat/socionext/uniphier/uniphier_image_desc.c
@@ -80,7 +80,7 @@
VERSION_2, entry_point_info_t,
NON_SECURE | EXECUTABLE),
.ep_info.pc = UNIPHIER_BL33_BASE,
- .ep_info.spsr = SPSR_64(MODE_EL1, MODE_SP_ELX,
+ .ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX,
DISABLE_ALL_EXCEPTIONS),
.next_handoff_image_id = INVALID_IMAGE_ID,
diff --git a/plat/xilinx/zynqmp/aarch64/zynqmp_common.c b/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
index ab5d95d..d6313a6 100644
--- a/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
+++ b/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
@@ -189,6 +189,18 @@
.id = 0x65,
.name = "25DR",
},
+ {
+ .id = 0x66,
+ .name = "39DR",
+ },
+ {
+ .id = 0x7b,
+ .name = "48DR",
+ },
+ {
+ .id = 0x7e,
+ .name = "49DR",
+ },
};
#define ZYNQMP_PL_STATUS_BIT 9
@@ -338,7 +350,7 @@
unsigned int ver = zynqmp_get_silicon_ver();
if (ver == ZYNQMP_CSU_VERSION_QEMU)
- return 50000000;
+ return 65000000;
else
return mmio_read_32(IOU_SCNTRS_BASEFREQ);
}
diff --git a/plat/xilinx/zynqmp/include/zynqmp_def.h b/plat/xilinx/zynqmp/include/zynqmp_def.h
index 8648b9a..5d335d9 100644
--- a/plat/xilinx/zynqmp/include/zynqmp_def.h
+++ b/plat/xilinx/zynqmp/include/zynqmp_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -330,6 +330,7 @@
#define IOU_SLCR_GEM_CLK_CTRL (IOU_SLCR_BASEADDR + 0x308)
#define IOU_SLCR_CAN_MIO_CTRL (IOU_SLCR_BASEADDR + 0x304)
#define FPD_SLCR_WDT_CLK_SEL (FPD_SLCR_BASEADDR + 0x100)
+#define IOU_SLCR_WDT_CLK_SEL (IOU_SLCR_BASEADDR + 0x300)
/* Global general storage register base address */
#define GGS_BASEADDR (0xFFD80030U)
diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_clock.c b/plat/xilinx/zynqmp/pm_service/pm_api_clock.c
index 85cffcb..e305072 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_api_clock.c
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_clock.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -562,13 +562,13 @@
},
};
-static struct pm_clock_node gem_nodes[] = {
+static struct pm_clock_node gem_ref_ungated_nodes[] = {
GENERIC_MUX,
{
.type = TYPE_DIV1,
.offset = 8,
.width = 6,
- .clkflags = CLK_IS_BASIC,
+ .clkflags = CLK_SET_RATE_NO_REPARENT | CLK_IS_BASIC,
.typeflags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
.mult = NA_MULT,
.div = NA_DIV,
@@ -577,77 +577,73 @@
.type = TYPE_DIV2,
.offset = 16,
.width = 6,
- .clkflags = CLK_IS_BASIC,
+ .clkflags = CLK_SET_RATE_NO_REPARENT | CLK_IS_BASIC,
.typeflags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
.mult = NA_MULT,
.div = NA_DIV,
},
- {
- .type = TYPE_GATE,
- .offset = 25,
- .width = PERIPH_GATE_WIDTH,
- .clkflags = CLK_SET_RATE_PARENT | CLK_IS_BASIC,
- .typeflags = NA_TYPE_FLAGS,
- .mult = NA_MULT,
- .div = NA_DIV,
- },
};
-static struct pm_clock_node gem0_tx_nodes[] = {
+static struct pm_clock_node gem0_ref_nodes[] = {
{
.type = TYPE_MUX,
.offset = 1,
.width = 1,
- .clkflags = CLK_SET_RATE_NO_REPARENT | CLK_IS_BASIC,
- .typeflags = NA_TYPE_FLAGS,
- .mult = NA_MULT,
- .div = NA_DIV,
- },
- {
- .type = TYPE_GATE,
- .offset = 26,
- .width = PERIPH_GATE_WIDTH,
- .clkflags = CLK_SET_RATE_PARENT | CLK_IS_BASIC,
+ .clkflags = CLK_SET_RATE_PARENT |
+ CLK_SET_RATE_NO_REPARENT |
+ CLK_IS_BASIC,
.typeflags = NA_TYPE_FLAGS,
.mult = NA_MULT,
.div = NA_DIV,
},
};
-static struct pm_clock_node gem1_tx_nodes[] = {
+static struct pm_clock_node gem1_ref_nodes[] = {
{
.type = TYPE_MUX,
.offset = 6,
.width = 1,
- .clkflags = CLK_SET_RATE_NO_REPARENT | CLK_IS_BASIC,
+ .clkflags = CLK_SET_RATE_PARENT |
+ CLK_SET_RATE_NO_REPARENT |
+ CLK_IS_BASIC,
.typeflags = NA_TYPE_FLAGS,
.mult = NA_MULT,
.div = NA_DIV,
},
+};
+
+static struct pm_clock_node gem2_ref_nodes[] = {
{
- .type = TYPE_GATE,
- .offset = 26,
- .width = PERIPH_GATE_WIDTH,
- .clkflags = CLK_SET_RATE_PARENT | CLK_IS_BASIC,
+ .type = TYPE_MUX,
+ .offset = 11,
+ .width = 1,
+ .clkflags = CLK_SET_RATE_PARENT |
+ CLK_SET_RATE_NO_REPARENT |
+ CLK_IS_BASIC,
.typeflags = NA_TYPE_FLAGS,
.mult = NA_MULT,
.div = NA_DIV,
},
};
-static struct pm_clock_node gem2_tx_nodes[] = {
+static struct pm_clock_node gem3_ref_nodes[] = {
{
.type = TYPE_MUX,
- .offset = 11,
+ .offset = 16,
.width = 1,
- .clkflags = CLK_SET_RATE_NO_REPARENT | CLK_IS_BASIC,
+ .clkflags = CLK_SET_RATE_PARENT |
+ CLK_SET_RATE_NO_REPARENT |
+ CLK_IS_BASIC,
.typeflags = NA_TYPE_FLAGS,
.mult = NA_MULT,
.div = NA_DIV,
},
+};
+
+static struct pm_clock_node gem_tx_nodes[] = {
{
.type = TYPE_GATE,
- .offset = 26,
+ .offset = 25,
.width = PERIPH_GATE_WIDTH,
.clkflags = CLK_SET_RATE_PARENT | CLK_IS_BASIC,
.typeflags = NA_TYPE_FLAGS,
@@ -656,21 +652,12 @@
},
};
-static struct pm_clock_node gem3_tx_nodes[] = {
- {
- .type = TYPE_MUX,
- .offset = 16,
- .width = 1,
- .clkflags = CLK_SET_RATE_NO_REPARENT | CLK_IS_BASIC,
- .typeflags = NA_TYPE_FLAGS,
- .mult = NA_MULT,
- .div = NA_DIV,
- },
+static struct pm_clock_node gem_rx_nodes[] = {
{
.type = TYPE_GATE,
.offset = 26,
.width = PERIPH_GATE_WIDTH,
- .clkflags = CLK_SET_RATE_PARENT | CLK_IS_BASIC,
+ .clkflags = CLK_IS_BASIC,
.typeflags = NA_TYPE_FLAGS,
.mult = NA_MULT,
.div = NA_DIV,
@@ -1442,8 +1429,8 @@
.nodes = &generic_mux_div_unused_gate_nodes,
.num_nodes = ARRAY_SIZE(generic_mux_div_unused_gate_nodes),
},
- [CLK_GEM0_REF] = {
- .name = "gem0_ref",
+ [CLK_GEM0_REF_UNGATED] = {
+ .name = "gem0_ref_ung",
.control_reg = CRL_APB_GEM0_REF_CTRL,
.status_reg = 0,
.parents = &((int32_t []) {
@@ -1453,11 +1440,11 @@
CLK_DPLL_TO_LPD,
CLK_NA_PARENT
}),
- .nodes = &gem_nodes,
- .num_nodes = ARRAY_SIZE(gem_nodes),
+ .nodes = &gem_ref_ungated_nodes,
+ .num_nodes = ARRAY_SIZE(gem_ref_ungated_nodes),
},
- [CLK_GEM1_REF] = {
- .name = "gem1_ref",
+ [CLK_GEM1_REF_UNGATED] = {
+ .name = "gem1_ref_ung",
.control_reg = CRL_APB_GEM1_REF_CTRL,
.status_reg = 0,
.parents = &((int32_t []) {
@@ -1467,11 +1454,11 @@
CLK_DPLL_TO_LPD,
CLK_NA_PARENT
}),
- .nodes = &gem_nodes,
- .num_nodes = ARRAY_SIZE(gem_nodes),
+ .nodes = &gem_ref_ungated_nodes,
+ .num_nodes = ARRAY_SIZE(gem_ref_ungated_nodes),
},
- [CLK_GEM2_REF] = {
- .name = "gem2_ref",
+ [CLK_GEM2_REF_UNGATED] = {
+ .name = "gem2_ref_ung",
.control_reg = CRL_APB_GEM2_REF_CTRL,
.status_reg = 0,
.parents = &((int32_t []) {
@@ -1481,11 +1468,11 @@
CLK_DPLL_TO_LPD,
CLK_NA_PARENT
}),
- .nodes = &gem_nodes,
- .num_nodes = ARRAY_SIZE(gem_nodes),
+ .nodes = &gem_ref_ungated_nodes,
+ .num_nodes = ARRAY_SIZE(gem_ref_ungated_nodes),
},
- [CLK_GEM3_REF] = {
- .name = "gem3_ref",
+ [CLK_GEM3_REF_UNGATED] = {
+ .name = "gem3_ref_ung",
.control_reg = CRL_APB_GEM3_REF_CTRL,
.status_reg = 0,
.parents = &((int32_t []) {
@@ -1495,8 +1482,60 @@
CLK_DPLL_TO_LPD,
CLK_NA_PARENT
}),
+ .nodes = &gem_ref_ungated_nodes,
+ .num_nodes = ARRAY_SIZE(gem_ref_ungated_nodes),
+ },
+ [CLK_GEM0_REF] = {
+ .name = "gem0_ref",
+ .control_reg = IOU_SLCR_GEM_CLK_CTRL,
+ .status_reg = 0,
+ .parents = &((int32_t []) {
+ CLK_GEM0_REF_UNGATED |
+ (PARENT_CLK_NODE3 << CLK_PARENTS_ID_LEN),
+ EXT_CLK_GEM0_TX_EMIO | CLK_EXTERNAL_PARENT,
+ CLK_NA_PARENT
+ }),
+ .nodes = &gem0_ref_nodes,
+ .num_nodes = ARRAY_SIZE(gem0_ref_nodes),
+ },
+ [CLK_GEM1_REF] = {
+ .name = "gem1_ref",
+ .control_reg = IOU_SLCR_GEM_CLK_CTRL,
+ .status_reg = 0,
+ .parents = &((int32_t []) {
+ CLK_GEM1_REF_UNGATED |
+ (PARENT_CLK_NODE3 << CLK_PARENTS_ID_LEN),
+ EXT_CLK_GEM1_TX_EMIO | CLK_EXTERNAL_PARENT,
+ CLK_NA_PARENT
+ }),
+ .nodes = &gem1_ref_nodes,
+ .num_nodes = ARRAY_SIZE(gem1_ref_nodes),
+ },
+ [CLK_GEM2_REF] = {
+ .name = "gem2_ref",
+ .control_reg = IOU_SLCR_GEM_CLK_CTRL,
+ .status_reg = 0,
+ .parents = &((int32_t []) {
+ CLK_GEM2_REF_UNGATED |
+ (PARENT_CLK_NODE3 << CLK_PARENTS_ID_LEN),
+ EXT_CLK_GEM2_TX_EMIO | CLK_EXTERNAL_PARENT,
+ CLK_NA_PARENT
+ }),
+ .nodes = &gem2_ref_nodes,
+ .num_nodes = ARRAY_SIZE(gem2_ref_nodes),
+ },
+ [CLK_GEM3_REF] = {
+ .name = "gem3_ref",
+ .control_reg = IOU_SLCR_GEM_CLK_CTRL,
+ .status_reg = 0,
+ .parents = &((int32_t []) {
+ CLK_GEM3_REF_UNGATED |
+ (PARENT_CLK_NODE3 << CLK_PARENTS_ID_LEN),
+ EXT_CLK_GEM3_TX_EMIO | CLK_EXTERNAL_PARENT,
+ CLK_NA_PARENT
+ }),
- .nodes = &gem_nodes,
- .num_nodes = ARRAY_SIZE(gem_nodes),
+ .nodes = &gem3_ref_nodes,
+ .num_nodes = ARRAY_SIZE(gem3_ref_nodes),
},
[CLK_USB0_BUS_REF] = {
.name = "usb0_bus_ref",
@@ -1960,69 +1999,93 @@
.nodes = &generic_domain_crossing_nodes,
.num_nodes = ARRAY_SIZE(generic_domain_crossing_nodes),
},
- /*
- * This clock control requires different registers for mux and gate.
- * Use control and status registers for the same.
- */
[CLK_GEM0_TX] = {
.name = "gem0_tx",
- .control_reg = IOU_SLCR_GEM_CLK_CTRL,
- .status_reg = CRL_APB_GEM0_REF_CTRL,
+ .control_reg = CRL_APB_GEM0_REF_CTRL,
+ .status_reg = 0,
.parents = &((int32_t []) {
- CLK_GEM0_REF | (PARENT_CLK_NODE3 << CLK_PARENTS_ID_LEN),
- EXT_CLK_GEM0_EMIO | CLK_EXTERNAL_PARENT,
+ CLK_GEM0_REF,
CLK_NA_PARENT
}),
- .nodes = &gem0_tx_nodes,
- .num_nodes = ARRAY_SIZE(gem0_tx_nodes),
+ .nodes = &gem_tx_nodes,
+ .num_nodes = ARRAY_SIZE(gem_tx_nodes),
},
- /*
- * This clock control requires different registers for mux and gate.
- * Use control and status registers for the same.
- */
[CLK_GEM1_TX] = {
.name = "gem1_tx",
- .control_reg = IOU_SLCR_GEM_CLK_CTRL,
- .status_reg = CRL_APB_GEM1_REF_CTRL,
+ .control_reg = CRL_APB_GEM1_REF_CTRL,
+ .status_reg = 0,
.parents = &((int32_t []) {
- CLK_GEM1_REF | (PARENT_CLK_NODE3 << CLK_PARENTS_ID_LEN),
- EXT_CLK_GEM1_EMIO | CLK_EXTERNAL_PARENT,
+ CLK_GEM1_REF,
CLK_NA_PARENT
}),
- .nodes = &gem1_tx_nodes,
- .num_nodes = ARRAY_SIZE(gem1_tx_nodes),
+ .nodes = &gem_tx_nodes,
+ .num_nodes = ARRAY_SIZE(gem_tx_nodes),
},
- /*
- * This clock control requires different registers for mux and gate.
- * Use control and status registers for the same.
- */
[CLK_GEM2_TX] = {
.name = "gem2_tx",
- .control_reg = IOU_SLCR_GEM_CLK_CTRL,
- .status_reg = CRL_APB_GEM2_REF_CTRL,
+ .control_reg = CRL_APB_GEM2_REF_CTRL,
+ .status_reg = 0,
.parents = &((int32_t []) {
- CLK_GEM2_REF | (PARENT_CLK_NODE3 << CLK_PARENTS_ID_LEN),
- EXT_CLK_GEM2_EMIO | CLK_EXTERNAL_PARENT,
+ CLK_GEM2_REF,
CLK_NA_PARENT
}),
- .nodes = &gem2_tx_nodes,
- .num_nodes = ARRAY_SIZE(gem2_tx_nodes),
+ .nodes = &gem_tx_nodes,
+ .num_nodes = ARRAY_SIZE(gem_tx_nodes),
},
- /*
- * This clock control requires different registers for mux and gate.
- * Use control and status registers for the same.
- */
[CLK_GEM3_TX] = {
.name = "gem3_tx",
- .control_reg = IOU_SLCR_GEM_CLK_CTRL,
- .status_reg = CRL_APB_GEM3_REF_CTRL,
+ .control_reg = CRL_APB_GEM3_REF_CTRL,
+ .status_reg = 0,
+ .parents = &((int32_t []) {
+ CLK_GEM3_REF,
+ CLK_NA_PARENT
+ }),
+ .nodes = &gem_tx_nodes,
+ .num_nodes = ARRAY_SIZE(gem_tx_nodes),
+ },
+ [CLK_GEM0_RX] = {
+ .name = "gem0_rx",
+ .control_reg = CRL_APB_GEM0_REF_CTRL,
+ .status_reg = 0,
.parents = &((int32_t []) {
- CLK_GEM3_REF | (PARENT_CLK_NODE3 << CLK_PARENTS_ID_LEN),
- EXT_CLK_GEM3_EMIO | CLK_EXTERNAL_PARENT,
+ EXT_CLK_GEM0_RX_EMIO | CLK_EXTERNAL_PARENT,
CLK_NA_PARENT
}),
- .nodes = &gem3_tx_nodes,
- .num_nodes = ARRAY_SIZE(gem3_tx_nodes),
+ .nodes = &gem_rx_nodes,
+ .num_nodes = ARRAY_SIZE(gem_rx_nodes),
+ },
+ [CLK_GEM1_RX] = {
+ .name = "gem1_rx",
+ .control_reg = CRL_APB_GEM1_REF_CTRL,
+ .status_reg = 0,
+ .parents = &((int32_t []) {
+ EXT_CLK_GEM1_RX_EMIO | CLK_EXTERNAL_PARENT,
+ CLK_NA_PARENT
+ }),
+ .nodes = &gem_rx_nodes,
+ .num_nodes = ARRAY_SIZE(gem_rx_nodes),
+ },
+ [CLK_GEM2_RX] = {
+ .name = "gem2_rx",
+ .control_reg = CRL_APB_GEM2_REF_CTRL,
+ .status_reg = 0,
+ .parents = &((int32_t []) {
+ EXT_CLK_GEM2_RX_EMIO | CLK_EXTERNAL_PARENT,
+ CLK_NA_PARENT
+ }),
+ .nodes = &gem_rx_nodes,
+ .num_nodes = ARRAY_SIZE(gem_rx_nodes),
+ },
+ [CLK_GEM3_RX] = {
+ .name = "gem3_rx",
+ .control_reg = CRL_APB_GEM3_REF_CTRL,
+ .status_reg = 0,
+ .parents = &((int32_t []) {
+ EXT_CLK_GEM3_RX_EMIO | CLK_EXTERNAL_PARENT,
+ CLK_NA_PARENT
+ }),
+ .nodes = &gem_rx_nodes,
+ .num_nodes = ARRAY_SIZE(gem_rx_nodes),
},
[CLK_ACPU_HALF] = {
.name = "acpu_half",
@@ -2035,8 +2098,8 @@
.nodes = &acpu_half_nodes,
.num_nodes = ARRAY_SIZE(acpu_half_nodes),
},
- [CLK_WDT] = {
- .name = "wdt",
+ [CLK_FPD_WDT] = {
+ .name = "fpd_wdt",
.control_reg = FPD_SLCR_WDT_CLK_SEL,
.status_reg = 0,
.parents = &((int32_t []) {
@@ -2135,6 +2198,18 @@
.nodes = &can1_nodes,
.num_nodes = ARRAY_SIZE(can1_nodes),
},
+ [CLK_LPD_WDT] = {
+ .name = "lpd_wdt",
+ .control_reg = IOU_SLCR_WDT_CLK_SEL,
+ .status_reg = 0,
+ .parents = &((int32_t []) {
+ CLK_LPD_LSBUS,
+ EXT_CLK_SWDT1 | CLK_EXTERNAL_PARENT,
+ CLK_NA_PARENT
+ }),
+ .nodes = &wdt_nodes,
+ .num_nodes = ARRAY_SIZE(wdt_nodes),
+ },
};
static struct pm_ext_clock ext_clocks[] = {
@@ -2159,17 +2234,29 @@
[EXT_CLK_INDEX(EXT_CLK_SWDT1)] = {
.name = "swdt1_ext_clk",
},
- [EXT_CLK_INDEX(EXT_CLK_GEM0_EMIO)] = {
- .name = "gem0_emio_clk",
+ [EXT_CLK_INDEX(EXT_CLK_GEM0_TX_EMIO)] = {
+ .name = "gem0_tx_ext",
},
- [EXT_CLK_INDEX(EXT_CLK_GEM1_EMIO)] = {
- .name = "gem1_emio_clk",
+ [EXT_CLK_INDEX(EXT_CLK_GEM1_TX_EMIO)] = {
+ .name = "gem1_tx_ext",
},
- [EXT_CLK_INDEX(EXT_CLK_GEM2_EMIO)] = {
- .name = "gem2_emio_clk",
+ [EXT_CLK_INDEX(EXT_CLK_GEM2_TX_EMIO)] = {
+ .name = "gem2_tx_ext",
},
- [EXT_CLK_INDEX(EXT_CLK_GEM3_EMIO)] = {
- .name = "gem3_emio_clk",
+ [EXT_CLK_INDEX(EXT_CLK_GEM3_TX_EMIO)] = {
+ .name = "gem3_tx_ext",
+ },
+ [EXT_CLK_INDEX(EXT_CLK_GEM0_RX_EMIO)] = {
+ .name = "gem0_rx_ext",
+ },
+ [EXT_CLK_INDEX(EXT_CLK_GEM1_RX_EMIO)] = {
+ .name = "gem1_rx_ext",
+ },
+ [EXT_CLK_INDEX(EXT_CLK_GEM2_RX_EMIO)] = {
+ .name = "gem2_rx_ext",
+ },
+ [EXT_CLK_INDEX(EXT_CLK_GEM3_RX_EMIO)] = {
+ .name = "gem3_rx_ext",
},
[EXT_CLK_INDEX(EXT_CLK_MIO50_OR_MIO51)] = {
.name = "mio_clk_50_51",
@@ -2268,7 +2355,6 @@
CLK_TOPSW_LSBUS,
CLK_GTGREF0_REF,
CLK_LPD_SWITCH,
- CLK_LPD_LSBUS,
CLK_CPU_R5,
CLK_CPU_R5_CORE,
CLK_CSU_SPB,
diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_clock.h b/plat/xilinx/zynqmp/pm_service/pm_api_clock.h
index 9717ca8..5bed5a6 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_api_clock.h
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_clock.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -102,14 +102,14 @@
CLK_IOU_SWITCH,
CLK_GEM_TSU_REF,
CLK_GEM_TSU,
- CLK_GEM0_REF,
- CLK_GEM1_REF,
- CLK_GEM2_REF,
- CLK_GEM3_REF,
CLK_GEM0_TX,
CLK_GEM1_TX,
CLK_GEM2_TX,
CLK_GEM3_TX,
+ CLK_GEM0_RX,
+ CLK_GEM1_RX,
+ CLK_GEM2_RX,
+ CLK_GEM3_RX,
CLK_QSPI_REF,
CLK_SDIO0_REF,
CLK_SDIO1_REF,
@@ -132,7 +132,7 @@
CLK_PL1_REF,
CLK_PL2_REF,
CLK_PL3_REF,
- CLK_WDT,
+ CLK_FPD_WDT,
CLK_IOPLL_INT,
CLK_IOPLL_PRE_SRC,
CLK_IOPLL_HALF,
@@ -161,6 +161,15 @@
CLK_CAN0_MIO,
CLK_CAN1_MIO,
CLK_ACPU_FULL,
+ CLK_GEM0_REF,
+ CLK_GEM1_REF,
+ CLK_GEM2_REF,
+ CLK_GEM3_REF,
+ CLK_GEM0_REF_UNGATED,
+ CLK_GEM1_REF_UNGATED,
+ CLK_GEM2_REF_UNGATED,
+ CLK_GEM3_REF_UNGATED,
+ CLK_LPD_WDT,
END_OF_OUTPUT_CLKS,
};
@@ -175,10 +184,14 @@
EXT_CLK_GT_CRX_REF,
EXT_CLK_SWDT0,
EXT_CLK_SWDT1,
- EXT_CLK_GEM0_EMIO,
- EXT_CLK_GEM1_EMIO,
- EXT_CLK_GEM2_EMIO,
- EXT_CLK_GEM3_EMIO,
+ EXT_CLK_GEM0_TX_EMIO,
+ EXT_CLK_GEM1_TX_EMIO,
+ EXT_CLK_GEM2_TX_EMIO,
+ EXT_CLK_GEM3_TX_EMIO,
+ EXT_CLK_GEM0_RX_EMIO,
+ EXT_CLK_GEM1_RX_EMIO,
+ EXT_CLK_GEM2_RX_EMIO,
+ EXT_CLK_GEM3_RX_EMIO,
EXT_CLK_MIO50_OR_MIO51,
EXT_CLK_MIO0,
EXT_CLK_MIO1,