commit 31464055c41e586458afbbe2f566cf0d851f3f33
author Sieu Mun Tang <sieu.mun.tang@intel.com> Fri Oct 25 09:37:42 2024 +0800
committer Sieu Mun Tang <sieu.mun.tang@intel.com> Fri Oct 25 09:38:51 2024 +0800
tree c8027425417e987f74c756b81ce1f8cf1a20ba68
parent 2e60a3b6d54459fc9d6349faee7c7fe42c798491

fix(intel): refactor SDMMC driver for Altera products

Refactor to be more robust. Removed duplicated and not used functions.
Add in ADMA read.

Change-Id: I1a5a00397ece6f9ccc5916225ab5317010b01b52
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

plat/intel/soc/agilex5/bl2_plat_setup.c

diff --git a/plat/intel/soc/agilex5/bl2_plat_setup.c b/plat/intel/soc/agilex5/bl2_plat_setup.c
index 6d0f183..11fecc4 100644
--- a/plat/intel/soc/agilex5/bl2_plat_setup.c
+++ b/plat/intel/soc/agilex5/bl2_plat_setup.c
@@ -103,6 +103,15 @@
 	/* Configure the pinmux */
 	config_pinmux(&reverse_handoff_ptr);
 
+	/* Configure OCRAM to NON SECURE ACCESS */
+	mmio_write_32(OCRAM_REGION_0_REG_BASE, OCRAM_NON_SECURE_ENABLE);
+	mmio_write_32(SOCFPGA_L4_PER_SCR_REG_BASE + SOCFPGA_SDMMC_SECU_BIT,
+		SOCFPGA_SDMMC_SECU_BIT_ENABLE);
+	mmio_write_32(SOCFPGA_L4_SYS_SCR_REG_BASE + SOCFPGA_SDMMC_SECU_BIT,
+		SOCFPGA_SDMMC_SECU_BIT_ENABLE);
+	mmio_write_32(SOCFPGA_LWSOC2FPGA_SCR_REG_BASE,
+		SOCFPGA_LWSOC2FPGA_ENABLE);
+
 	/* Configure the clock manager */
 	if ((config_clkmgr_handoff(&reverse_handoff_ptr)) != 0) {
 		ERROR("SOCFPGA: Failed to initialize the clock manager\n");
@@ -156,7 +165,7 @@
 	switch (boot_source) {
 	case BOOT_SOURCE_SDMMC:
 		NOTICE("SDMMC boot\n");
-		sdmmc_init(&reverse_handoff_ptr, &params, &mmc_info);
+		cdns_mmc_init(&params, &mmc_info);
 		socfpga_io_setup(boot_source, PLAT_SDMMC_DATA_BASE);
 		break;