Do not enable CCI on Foundation FVP
- The Foundation FVP only has one cluster and does not have
CCI.
Change-Id: If91e81ff72c52e448150089c4cfea3e4d6ae1232
diff --git a/plat/fvp/aarch64/bl1_plat_helpers.S b/plat/fvp/aarch64/bl1_plat_helpers.S
index d72dc39..8cdb10e 100644
--- a/plat/fvp/aarch64/bl1_plat_helpers.S
+++ b/plat/fvp/aarch64/bl1_plat_helpers.S
@@ -226,15 +226,6 @@
str x19, [x1, x2]
/* ---------------------------------------------
- * Enable CCI-400 for this cluster. No need
- * for locks as no other cpu is active at the
- * moment
- * ---------------------------------------------
- */
- mov x0, x19
- bl cci_enable_coherency
-
- /* ---------------------------------------------
* Architectural init. can be generic e.g.
* enabling stack alignment and platform spec-
* ific e.g. MMU & page table setup as per the
diff --git a/plat/fvp/aarch64/fvp_common.c b/plat/fvp/aarch64/fvp_common.c
index 762f542..78a44a5 100644
--- a/plat/fvp/aarch64/fvp_common.c
+++ b/plat/fvp/aarch64/fvp_common.c
@@ -576,6 +576,7 @@
platform_config[CONFIG_MAX_AFF1] = 1;
platform_config[CONFIG_CPU_SETUP] = 0;
platform_config[CONFIG_BASE_MMAP] = 0;
+ platform_config[CONFIG_HAS_CCI] = 0;
break;
case HBI_FVP_BASE:
midr_pn = (read_midr() >> MIDR_PN_SHIFT) & MIDR_PN_MASK;
@@ -587,6 +588,7 @@
platform_config[CONFIG_MAX_AFF0] = 4;
platform_config[CONFIG_MAX_AFF1] = 2;
platform_config[CONFIG_BASE_MMAP] = 1;
+ platform_config[CONFIG_HAS_CCI] = 1;
break;
default:
assert(0);
diff --git a/plat/fvp/bl1_plat_setup.c b/plat/fvp/bl1_plat_setup.c
index 7131f7a..7fa3f76 100644
--- a/plat/fvp/bl1_plat_setup.c
+++ b/plat/fvp/bl1_plat_setup.c
@@ -34,6 +34,7 @@
#include <platform.h>
#include <bl1.h>
#include <console.h>
+#include <cci400.h>
/*******************************************************************************
* Declarations of linker defined symbols which will help us find the layout
@@ -126,6 +127,9 @@
bl1_tzram_layout.free_size =
tzram_limit - bl1_coherent_ram_limit;
}
+
+ /* Initialize the platform config for future decision making */
+ platform_config_setup();
}
/*******************************************************************************
@@ -153,11 +157,23 @@
/*******************************************************************************
* Perform the very early platform specific architecture setup here. At the
- * moment this is only intializes the mmu in a quick and dirty way. Later arch-
- * itectural setup (bl1_arch_setup()) does not do anything platform specific.
+ * moment this only does basic initialization. Later architectural setup
+ * (bl1_arch_setup()) does not do anything platform specific.
******************************************************************************/
void bl1_plat_arch_setup(void)
{
+ unsigned long cci_setup;
+
+ /*
+ * Enable CCI-400 for this cluster. No need
+ * for locks as no other cpu is active at the
+ * moment
+ */
+ cci_setup = platform_get_cfgvar(CONFIG_HAS_CCI);
+ if (cci_setup) {
+ cci_enable_coherency(read_mpidr());
+ }
+
configure_mmu(&bl1_tzram_layout,
TZROM_BASE, /* Read_only region start */
TZROM_BASE + TZROM_SIZE, /* Read_only region size */
diff --git a/plat/fvp/fvp_pm.c b/plat/fvp/fvp_pm.c
index 9621319..af8d1b3 100644
--- a/plat/fvp/fvp_pm.c
+++ b/plat/fvp/fvp_pm.c
@@ -111,7 +111,7 @@
{
int rc = PSCI_E_SUCCESS;
unsigned int gicc_base, ectlr;
- unsigned long cpu_setup;
+ unsigned long cpu_setup, cci_setup;
switch (afflvl) {
case MPIDR_AFFLVL1:
@@ -120,7 +120,10 @@
* Disable coherency if this cluster is to be
* turned off
*/
- cci_disable_coherency(mpidr);
+ cci_setup = platform_get_cfgvar(CONFIG_HAS_CCI);
+ if (cci_setup) {
+ cci_disable_coherency(mpidr);
+ }
/*
* Program the power controller to turn the
@@ -187,7 +190,7 @@
{
int rc = PSCI_E_SUCCESS;
unsigned int gicc_base, ectlr;
- unsigned long cpu_setup, linear_id;
+ unsigned long cpu_setup, cci_setup, linear_id;
mailbox *fvp_mboxes;
/* Cannot allow NS world to execute trusted firmware code */
@@ -203,7 +206,10 @@
* Disable coherency if this cluster is to be
* turned off
*/
- cci_disable_coherency(mpidr);
+ cci_setup = platform_get_cfgvar(CONFIG_HAS_CCI);
+ if (cci_setup) {
+ cci_disable_coherency(mpidr);
+ }
/*
* Program the power controller to turn the
@@ -270,7 +276,7 @@
unsigned int state)
{
int rc = PSCI_E_SUCCESS;
- unsigned long linear_id, cpu_setup;
+ unsigned long linear_id, cpu_setup, cci_setup;
mailbox *fvp_mboxes;
unsigned int gicd_base, gicc_base, reg_val, ectlr;
@@ -278,8 +284,12 @@
case MPIDR_AFFLVL1:
/* Enable coherency if this cluster was off */
- if (state == PSCI_STATE_OFF)
- cci_enable_coherency(mpidr);
+ if (state == PSCI_STATE_OFF) {
+ cci_setup = platform_get_cfgvar(CONFIG_HAS_CCI);
+ if (cci_setup) {
+ cci_enable_coherency(mpidr);
+ }
+ }
break;
case MPIDR_AFFLVL0:
diff --git a/plat/fvp/platform.h b/plat/fvp/platform.h
index 21a7912..463c637 100644
--- a/plat/fvp/platform.h
+++ b/plat/fvp/platform.h
@@ -72,7 +72,9 @@
/* Indicate whether the CPUECTLR SMP bit should be enabled. */
#define CONFIG_CPU_SETUP 6
#define CONFIG_BASE_MMAP 7
-#define CONFIG_LIMIT 8
+/* Indicates whether CCI should be enabled on the platform. */
+#define CONFIG_HAS_CCI 8
+#define CONFIG_LIMIT 9
/*******************************************************************************
* Platform memory map related constants