intel: Platform common code refactor
Pull out common code from aarch64 and include
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I4d0f5e1bb01bcdacbedf8e6c359de594239b645f
diff --git a/plat/intel/soc/agilex/include/plat_macros.S b/plat/intel/soc/agilex/include/plat_macros.S
deleted file mode 100644
index 43db9a2..0000000
--- a/plat/intel/soc/agilex/include/plat_macros.S
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright (c) 2019, Intel Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef PLAT_MACROS_S
-#define PLAT_MACROS_S
-
-#include <platform_def.h>
-
- /* ---------------------------------------------
- * The below required platform porting macro
- * prints out relevant platform registers
- * whenever an unhandled exception is taken in
- * BL31.
- * ---------------------------------------------
- */
- .macro plat_crash_print_regs
- .endm
-
-#endif /* PLAT_MACROS_S */
diff --git a/plat/intel/soc/agilex/include/platform_def.h b/plat/intel/soc/agilex/include/platform_def.h
index 10f7338..277862a 100644
--- a/plat/intel/soc/agilex/include/platform_def.h
+++ b/plat/intel/soc/agilex/include/platform_def.h
@@ -15,7 +15,7 @@
#define PLAT_CPUID_RELEASE 0xffe1b000
-#define PLAT_AGX_SEC_ENTRY 0xffe1b008
+#define PLAT_SEC_ENTRY 0xffe1b008
/* Define next boot image name and offset */
#define PLAT_NS_IMAGE_OFFSET 0x50000
diff --git a/plat/intel/soc/agilex/include/socfpga_private.h b/plat/intel/soc/agilex/include/socfpga_private.h
deleted file mode 100644
index 6ab1409..0000000
--- a/plat/intel/soc/agilex/include/socfpga_private.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * Copyright (c) 2019, Intel Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef PLATFORM_PRIVATE_H
-#define PLATFORM_PRIVATE_H
-
-/*******************************************************************************
- * Function and variable prototypes
- ******************************************************************************/
-void socfgpa_configure_mmu_el3(unsigned long total_base,
- unsigned long total_size,
- unsigned long ro_start,
- unsigned long ro_limit,
- unsigned long coh_start,
- unsigned long coh_limit);
-
-
-void socfpga_configure_mmu_el1(unsigned long total_base,
- unsigned long total_size,
- unsigned long ro_start,
- unsigned long ro_limit,
- unsigned long coh_start,
- unsigned long coh_limit);
-
-void socfpga_delay_timer_init(void);
-
-void socfpga_gic_driver_init(void);
-
-uint32_t socfpga_get_spsr_for_bl32_entry(void);
-
-uint32_t socfpga_get_spsr_for_bl33_entry(void);
-
-unsigned long socfpga_get_ns_image_entrypoint(void);
-
-
-#endif /* PLATFORM_PRIVATE_H */