plat/arm: Fix misra warnings in platform code
Change-Id: Ica944acc474a099219d50b041cfaeabd4f3d362f
Signed-off-by: Sathees Balya <sathees.balya@arm.com>
diff --git a/plat/arm/board/fvp/fvp_topology.c b/plat/arm/board/fvp/fvp_topology.c
index a1e3f7f..e21b9d2 100644
--- a/plat/arm/board/fvp/fvp_topology.c
+++ b/plat/arm/board/fvp/fvp_topology.c
@@ -16,7 +16,8 @@
static unsigned char fvp_power_domain_tree_desc[FVP_CLUSTER_COUNT + 2];
-CASSERT(FVP_CLUSTER_COUNT && FVP_CLUSTER_COUNT <= 256, assert_invalid_fvp_cluster_count);
+CASSERT(((FVP_CLUSTER_COUNT > 0) && (FVP_CLUSTER_COUNT <= 256)),
+ assert_invalid_fvp_cluster_count);
/*******************************************************************************
* This function dynamically constructs the topology according to
@@ -24,7 +25,7 @@
******************************************************************************/
const unsigned char *plat_get_power_domain_tree_desc(void)
{
- unsigned int i;
+ int i;
/*
* The highest level is the system level. The next level is constituted
@@ -60,7 +61,7 @@
unsigned int clus_id, cpu_id, thread_id;
/* Validate affinity fields */
- if (arm_config.flags & ARM_CONFIG_FVP_SHIFTED_AFF) {
+ if ((arm_config.flags & ARM_CONFIG_FVP_SHIFTED_AFF) != 0U) {
thread_id = MPIDR_AFFLVL0_VAL(mpidr);
cpu_id = MPIDR_AFFLVL1_VAL(mpidr);
clus_id = MPIDR_AFFLVL2_VAL(mpidr);
@@ -90,5 +91,5 @@
* bit set.
*/
mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK);
- return plat_arm_calc_core_pos(mpidr);
+ return (int) plat_arm_calc_core_pos(mpidr);
}