| /* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) */ |
| /* |
| * Copyright (C) 2020-2024 STMicroelectronics - All Rights Reserved |
| * Copyright (C) 2020 Ahmad Fatoum, Pengutronix |
| */ |
| |
| #include "stm32mp15-pinctrl.dtsi" |
| |
| &i2c4 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&i2c4_pins_a>; |
| clock-frequency = <400000>; |
| i2c-scl-rising-time-ns = <185>; |
| i2c-scl-falling-time-ns = <20>; |
| status = "okay"; |
| |
| pmic: stpmic@33 { |
| compatible = "st,stpmic1"; |
| reg = <0x33>; |
| interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| |
| regulators { |
| compatible = "st,stpmic1-regulators"; |
| |
| ldo1-supply = <&v3v3>; |
| ldo6-supply = <&v3v3>; |
| pwr_sw1-supply = <&bst_out>; |
| |
| vddcore: buck1 { |
| regulator-name = "vddcore"; |
| regulator-min-microvolt = <1200000>; |
| regulator-max-microvolt = <1350000>; |
| regulator-always-on; |
| regulator-initial-mode = <0>; |
| regulator-over-current-protection; |
| }; |
| |
| vdd_ddr: buck2 { |
| regulator-name = "vdd_ddr"; |
| regulator-min-microvolt = <1350000>; |
| regulator-max-microvolt = <1350000>; |
| regulator-always-on; |
| regulator-initial-mode = <0>; |
| regulator-over-current-protection; |
| }; |
| |
| vdd: buck3 { |
| regulator-name = "vdd"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| st,mask-reset; |
| regulator-initial-mode = <0>; |
| regulator-over-current-protection; |
| }; |
| |
| v3v3: buck4 { |
| regulator-name = "v3v3"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| regulator-over-current-protection; |
| regulator-initial-mode = <0>; |
| }; |
| |
| v1v8_audio: ldo1 { |
| regulator-name = "v1v8_audio"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <1800000>; |
| regulator-always-on; |
| }; |
| |
| v3v3_hdmi: ldo2 { |
| regulator-name = "v3v3_hdmi"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| }; |
| |
| vtt_ddr: ldo3 { |
| regulator-name = "vtt_ddr"; |
| regulator-always-on; |
| regulator-over-current-protection; |
| st,regulator-sink-source; |
| }; |
| |
| vdd_usb: ldo4 { |
| regulator-name = "vdd_usb"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| }; |
| |
| vdda: ldo5 { |
| regulator-name = "vdda"; |
| regulator-min-microvolt = <2900000>; |
| regulator-max-microvolt = <2900000>; |
| regulator-boot-on; |
| }; |
| |
| v1v2_hdmi: ldo6 { |
| regulator-name = "v1v2_hdmi"; |
| regulator-min-microvolt = <1200000>; |
| regulator-max-microvolt = <1200000>; |
| regulator-always-on; |
| }; |
| |
| vref_ddr: vref_ddr { |
| regulator-name = "vref_ddr"; |
| regulator-always-on; |
| }; |
| |
| bst_out: boost { |
| regulator-name = "bst_out"; |
| }; |
| |
| vbus_otg: pwr_sw1 { |
| regulator-name = "vbus_otg"; |
| regulator-active-discharge; |
| }; |
| |
| vbus_sw: pwr_sw2 { |
| regulator-name = "vbus_sw"; |
| regulator-active-discharge; |
| }; |
| }; |
| |
| pmic_watchdog: watchdog { |
| compatible = "st,stpmic1-wdt"; |
| status = "disabled"; |
| }; |
| }; |
| }; |
| |
| &rng1 { |
| status = "okay"; |
| }; |
| |
| /* ATF Specific */ |
| #include <dt-bindings/clock/stm32mp1-clksrc.h> |
| |
| / { |
| aliases { |
| gpio0 = &gpioa; |
| gpio1 = &gpiob; |
| gpio2 = &gpioc; |
| gpio3 = &gpiod; |
| gpio4 = &gpioe; |
| gpio5 = &gpiof; |
| gpio6 = &gpiog; |
| gpio7 = &gpioh; |
| gpio8 = &gpioi; |
| gpio25 = &gpioz; |
| i2c3 = &i2c4; |
| }; |
| }; |
| |
| &bsec { |
| board_id: board-id@ec { |
| reg = <0xec 0x4>; |
| st,non-secure-otp; |
| }; |
| }; |
| |
| &clk_hse { |
| st,digbypass; |
| }; |
| |
| &cpu0 { |
| cpu-supply = <&vddcore>; |
| }; |
| |
| &cpu1 { |
| cpu-supply = <&vddcore>; |
| }; |
| |
| &hash1 { |
| status = "okay"; |
| }; |
| |
| /* CLOCK init */ |
| &rcc { |
| st,clksrc = < |
| CLK_MPU_PLL1P |
| CLK_AXI_PLL2P |
| CLK_MCU_PLL3P |
| CLK_RTC_LSE |
| CLK_MCO1_DISABLED |
| CLK_MCO2_DISABLED |
| CLK_CKPER_HSE |
| CLK_FMC_ACLK |
| CLK_QSPI_ACLK |
| CLK_ETH_PLL4P |
| CLK_SDMMC12_PLL4P |
| CLK_DSI_DSIPLL |
| CLK_STGEN_HSE |
| CLK_USBPHY_HSE |
| CLK_SPI2S1_PLL3Q |
| CLK_SPI2S23_PLL3Q |
| CLK_SPI45_HSI |
| CLK_SPI6_HSI |
| CLK_I2C46_HSI |
| CLK_SDMMC3_PLL4P |
| CLK_USBO_USBPHY |
| CLK_ADC_CKPER |
| CLK_CEC_LSE |
| CLK_I2C12_HSI |
| CLK_I2C35_HSI |
| CLK_UART1_HSI |
| CLK_UART24_HSI |
| CLK_UART35_HSI |
| CLK_UART6_HSI |
| CLK_UART78_HSI |
| CLK_SPDIF_PLL4P |
| CLK_FDCAN_PLL4R |
| CLK_SAI1_PLL3Q |
| CLK_SAI2_PLL3Q |
| CLK_SAI3_PLL3Q |
| CLK_SAI4_PLL3Q |
| CLK_RNG1_CSI |
| CLK_RNG2_LSI |
| CLK_LPTIM1_PCLK1 |
| CLK_LPTIM23_PCLK3 |
| CLK_LPTIM45_LSE |
| >; |
| |
| st,clkdiv = < |
| DIV(DIV_MPU, 1) |
| DIV(DIV_AXI, 0) |
| DIV(DIV_MCU, 0) |
| DIV(DIV_APB1, 1) |
| DIV(DIV_APB2, 1) |
| DIV(DIV_APB3, 1) |
| DIV(DIV_APB4, 1) |
| DIV(DIV_APB5, 2) |
| DIV(DIV_RTC, 23) |
| DIV(DIV_MCO1, 0) |
| DIV(DIV_MCO2, 0) |
| >; |
| |
| st,pll_vco { |
| pll2_vco_1066Mhz: pll2-vco-1066Mhz { |
| src = <CLK_PLL12_HSE>; |
| divmn = <2 65>; |
| frac = <0x1400>; |
| }; |
| |
| pll3_vco_417Mhz: pll3-vco-417Mhz { |
| src = <CLK_PLL3_HSE>; |
| divmn = <1 33>; |
| frac = <0x1a04>; |
| }; |
| |
| pll4_vco_594Mhz: pll4-vco-594Mhz { |
| src = <CLK_PLL4_HSE>; |
| divmn = <3 98>; |
| }; |
| }; |
| |
| /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ |
| pll2: st,pll@1 { |
| compatible = "st,stm32mp1-pll"; |
| reg = <1>; |
| |
| st,pll = <&pll2_cfg1>; |
| |
| pll2_cfg1: pll2_cfg1 { |
| st,pll_vco = <&pll2_vco_1066Mhz>; |
| st,pll_div_pqr = <1 0 0>; |
| }; |
| }; |
| |
| /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ |
| pll3: st,pll@2 { |
| compatible = "st,stm32mp1-pll"; |
| reg = <2>; |
| |
| st,pll = <&pll3_cfg1>; |
| |
| pll3_cfg1: pll3_cfg1 { |
| st,pll_vco = <&pll3_vco_417Mhz>; |
| st,pll_div_pqr = <1 16 36>; |
| }; |
| }; |
| |
| /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */ |
| pll4: st,pll@3 { |
| compatible = "st,stm32mp1-pll"; |
| reg = <3>; |
| |
| st,pll = <&pll4_cfg1>; |
| |
| pll4_cfg1: pll4_cfg1 { |
| st,pll_vco = <&pll4_vco_594Mhz>; |
| st,pll_div_pqr = <5 7 7>; |
| }; |
| }; |
| }; |