Merge "feat(mt8188): add support for SMC from OP-TEE" into integration
diff --git a/Makefile b/Makefile
index 46b712e..0c35120 100644
--- a/Makefile
+++ b/Makefile
@@ -624,6 +624,15 @@
# over the sources.
endif #(SPD=none)
+ifeq (${ENABLE_SPMD_LP}, 1)
+ifneq (${SPD},spmd)
+ $(error Error: ENABLE_SPMD_LP requires SPD=spmd.)
+endif
+ifeq ($(SPMC_AT_EL3),1)
+ $(error SPMC at EL3 not supported when enabling SPMD Logical partitions.)
+endif
+endif
+
ifeq (${CTX_INCLUDE_EL2_REGS}, 1)
ifeq (${SPD},none)
ifeq (${ENABLE_RME},0)
@@ -1182,6 +1191,7 @@
SPM_MM \
SPMC_AT_EL3 \
SPMD_SPM_AT_SEL2 \
+ ENABLE_SPMD_LP \
TRUSTED_BOARD_BOOT \
USE_COHERENT_MEM \
USE_DEBUGFS \
@@ -1398,6 +1408,7 @@
CONDITIONAL_CMO \
IMPDEF_SYSREG_TRAP \
SVE_VECTOR_LEN \
+ ENABLE_SPMD_LP \
)))
ifeq (${SANITIZE_UB},trap)
diff --git a/common/feat_detect.c b/common/feat_detect.c
index 2aa0c5c..a1ffc39 100644
--- a/common/feat_detect.c
+++ b/common/feat_detect.c
@@ -203,7 +203,7 @@
check_feature(ENABLE_FEAT_HCX, read_feat_hcx_id_field(), "HCX", 1, 1);
/* v8.9 features */
- check_feature(ENABLE_FEAT_TCR2, read_feat_tcrx_id_field(),
+ check_feature(ENABLE_FEAT_TCR2, read_feat_tcr2_id_field(),
"TCR2", 1, 1);
check_feature(ENABLE_FEAT_S2PIE, read_feat_s2pie_id_field(),
"S2PIE", 1, 1);
diff --git a/docs/design_documents/rss.rst b/docs/design_documents/rss.rst
index 2ad2ee7..18d5436 100644
--- a/docs/design_documents/rss.rst
+++ b/docs/design_documents/rss.rst
@@ -134,12 +134,10 @@
- ``Delegated attestation``: Query the platform attestation token and derive a
delegated attestation key. More info on the delegated attestation service
in RSS can be found in the ``delegated_attestation_integration_guide`` [4]_ .
-- ``OTP assets management``: RSS provides access for AP to assets in OTP.
- These are keys for image signature verification and non-volatile counters
- for anti-rollback protection. Only RSS has direct access to the OTP. Public
- keys used by AP during the trusted boot process can be requested from RSS.
- Furthermore, AP can request RSS to increase a non-volatile counter. Please
- refer to the ``RSS key management`` [5]_ document for more details.
+- ``OTP assets management``: Public keys used by AP during the trusted boot
+ process can be requested from RSS. Furthermore, AP can request RSS to
+ increase a non-volatile counter. Please refer to the
+ ``RSS key management`` [5]_ document for more details.
Runtime service API
^^^^^^^^^^^^^^^^^^^
@@ -625,6 +623,57 @@
"CCA_PLATFORM_VERIFICATION_SERVICE": "www.trustedfirmware.org"
}
+RSS OTP Assets Management
+-------------------------
+
+RSS provides access for AP to assets in OTP, which include keys for image
+signature verification and non-volatile counters for anti-rollback protection.
+
+Non-Volatile Counter API
+^^^^^^^^^^^^^^^^^^^^^^^^
+
+AP/RSS interface for retrieving and incrementing non-volatile counters API is
+as follows.
+
+Defined here:
+
+- ``include/lib/psa/rss_platform_api.h``
+
+.. code-block:: c
+
+ psa_status_t rss_platform_nv_counter_increment(uint32_t counter_id)
+
+ psa_status_t rss_platform_nv_counter_read(uint32_t counter_id,
+ uint32_t size, uint8_t *val)
+
+Through this service, we can read/increment any of the 3 non-volatile
+counters used on an Arm CCA platform:
+
+- ``Non-volatile counter for CCA firmware (BL2, BL31, RMM).``
+- ``Non-volatile counter for secure firmware.``
+- ``Non-volatile counter for non-secure firmware.``
+
+Public Key API
+^^^^^^^^^^^^^^
+
+AP/RSS interface for reading the ROTPK is as follows.
+
+Defined here:
+
+- ``include/lib/psa/rss_platform_api.h``
+
+.. code-block:: c
+
+ psa_status_t rss_platform_key_read(enum rss_key_id_builtin_t key,
+ uint8_t *data, size_t data_size, size_t *data_length)
+
+Through this service, we can read any of the 3 ROTPKs used on an
+Arm CCA platform:
+
+- ``ROTPK for CCA firmware (BL2, BL31, RMM).``
+- ``ROTPK for secure firmware.``
+- ``ROTPK for non-secure firmware.``
+
References
----------
diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst
index 953a92e..2c018c3 100644
--- a/docs/getting_started/build-options.rst
+++ b/docs/getting_started/build-options.rst
@@ -913,6 +913,12 @@
support pre-Armv8.4 platforms (aka not implementing the ``FEAT_SEL2``
extension).
+- ``ENABLE_SPMD_LP`` : This boolean option is used jointly with the SPM
+ Dispatcher option (``SPD=spmd``). When enabled (1) it indicates support
+ for logical partitions in EL3, managed by the SPMD as defined in the FF-A
+ 1.2 specification. This flag is disabled by default. This flag must not be
+ used if ``SPMC_AT_EL3`` is enabled. This is an experimental feature.
+
- ``SPM_MM`` : Boolean option to enable the Management Mode (MM)-based Secure
Partition Manager (SPM) implementation. The default value is ``0``
(disabled). This option cannot be enabled (``1``) when SPM Dispatcher is
diff --git a/fdts/morello-soc.dts b/fdts/morello-soc.dts
index 9f996bd..f207c06 100644
--- a/fdts/morello-soc.dts
+++ b/fdts/morello-soc.dts
@@ -35,6 +35,15 @@
device_type = "cpu";
enable-method = "psci";
clocks = <&scmi_dvfs 0>;
+ operating-points = <
+ /* kHz uV */
+ 2600000 925000
+ 2400000 875000
+ 2200000 825000
+ 2000000 775000
+ 1800000 750000
+ >;
+ #cooling-cells = <2>;
};
cpu1: cpu1@100 {
compatible = "arm,armv8";
@@ -42,6 +51,15 @@
device_type = "cpu";
enable-method = "psci";
clocks = <&scmi_dvfs 0>;
+ operating-points = <
+ /* kHz uV */
+ 2600000 925000
+ 2400000 875000
+ 2200000 825000
+ 2000000 775000
+ 1800000 750000
+ >;
+ #cooling-cells = <2>;
};
cpu2: cpu2@10000 {
compatible = "arm,armv8";
@@ -49,6 +67,15 @@
device_type = "cpu";
enable-method = "psci";
clocks = <&scmi_dvfs 1>;
+ operating-points = <
+ /* kHz uV */
+ 2600000 925000
+ 2400000 875000
+ 2200000 825000
+ 2000000 775000
+ 1800000 750000
+ >;
+ #cooling-cells = <2>;
};
cpu3: cpu3@10100 {
compatible = "arm,armv8";
@@ -56,6 +83,15 @@
device_type = "cpu";
enable-method = "psci";
clocks = <&scmi_dvfs 1>;
+ operating-points = <
+ /* kHz uV */
+ 2600000 925000
+ 2400000 875000
+ 2200000 825000
+ 2000000 775000
+ 1800000 750000
+ >;
+ #cooling-cells = <2>;
};
};
@@ -255,6 +291,92 @@
reg = <0x14>;
#clock-cells = <1>;
};
+ scmi_sensor: protocol@15 {
+ reg = <0x15>;
+ #thermal-sensor-cells = <1>;
+ };
+ };
+ };
+
+ thermal-zones {
+ clus0-thermal {
+ polling-delay-passive = <200>; /* ms */
+ polling-delay = <1000>; /* ms */
+
+ thermal-sensors = <&scmi_sensor 0>;
+
+ trips {
+ clus0_alarm: clus0-alarm {
+ temperature = <85000>; /* millicelsius */
+ hysteresis = <1000>; /* millicelsius */
+ type = "passive";
+ };
+ clus0_shutdown: clus0-shutdown {
+ temperature = <90000>; /* millicelsius */
+ hysteresis = <0>; /* millicelsius */
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&clus0_alarm>;
+ cooling-device = <&cpu0 4 4>, <&cpu1 4 4>;
+ };
+ };
+ };
+ clus1-thermal {
+ polling-delay-passive = <200>; /* ms */
+ polling-delay = <1000>; /* ms */
+
+ thermal-sensors = <&scmi_sensor 1>;
+ trips {
+ clus1_alarm: clus1-alarm {
+ temperature = <85000>; /* millicelsius */
+ hysteresis = <1000>; /* millicelsius */
+ type = "passive";
+ };
+ clus1_shutdown: clus1-shutdown {
+ temperature = <90000>; /* millicelsius */
+ hysteresis = <0>; /* millicelsius */
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&clus1_alarm>;
+ cooling-device = <&cpu2 4 4>, <&cpu3 4 4>;
+ };
+ };
+ };
+ sys-thermal {
+ polling-delay-passive = <200>; /* ms */
+ polling-delay = <1000>; /* ms */
+
+ thermal-sensors = <&scmi_sensor 2>;
+ trips {
+ sys_alarm: sys-alarm {
+ temperature = <85000>; /* millicelsius */
+ hysteresis = <1000>; /* millicelsius */
+ type = "passive";
+ };
+ sys_shutdown: sys-shutdown {
+ temperature = <90000>; /* millicelsius */
+ hysteresis = <0>; /* millicelsius */
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&sys_alarm>;
+ cooling-device = <&cpu0 4 4>,
+ <&cpu1 4 4>,
+ <&cpu2 4 4>,
+ <&cpu3 4 4>;
+ };
+ };
};
};
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h
index b19e8af..bc37c94 100644
--- a/include/arch/aarch64/arch.h
+++ b/include/arch/aarch64/arch.h
@@ -157,6 +157,8 @@
#define DCCSW U(0x2)
#endif
+#define ID_REG_FIELD_MASK ULL(0xf)
+
/* ID_AA64PFR0_EL1 definitions */
#define ID_AA64PFR0_EL0_SHIFT U(0)
#define ID_AA64PFR0_EL1_SHIFT U(4)
diff --git a/include/arch/aarch64/arch_features.h b/include/arch/aarch64/arch_features.h
index 9f11f15..bd41fef 100644
--- a/include/arch/aarch64/arch_features.h
+++ b/include/arch/aarch64/arch_features.h
@@ -13,49 +13,37 @@
#include <common/feat_detect.h>
#define ISOLATE_FIELD(reg, feat) \
- ((unsigned int)(((reg) >> (feat ## _SHIFT)) & (feat ## _MASK)))
+ ((unsigned int)(((reg) >> (feat)) & ID_REG_FIELD_MASK))
-static inline bool is_armv7_gentimer_present(void)
-{
- /* The Generic Timer is always present in an ARMv8-A implementation */
- return true;
+#define CREATE_FEATURE_FUNCS_VER(name, read_func, idvalue, guard) \
+static inline bool is_ ## name ## _supported(void) \
+{ \
+ if ((guard) == FEAT_STATE_DISABLED) { \
+ return false; \
+ } \
+ if ((guard) == FEAT_STATE_ALWAYS) { \
+ return true; \
+ } \
+ return read_func() >= (idvalue); \
}
-static inline unsigned int read_feat_pan_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_PAN);
-}
-
-static inline bool is_feat_pan_supported(void)
-{
- if (ENABLE_FEAT_PAN == FEAT_STATE_DISABLED) {
- return false;
- }
+#define CREATE_FEATURE_FUNCS(name, idreg, idfield, guard) \
+static unsigned int read_ ## name ## _id_field(void) \
+{ \
+ return ISOLATE_FIELD(read_ ## idreg(), idfield); \
+} \
+CREATE_FEATURE_FUNCS_VER(name, read_ ## name ## _id_field, 1U, guard)
- if (ENABLE_FEAT_PAN == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_pan_id_field() != 0U;
-}
-
-static inline unsigned int read_feat_vhe_id_field(void)
+static inline bool is_armv7_gentimer_present(void)
{
- return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_VHE);
+ /* The Generic Timer is always present in an ARMv8-A implementation */
+ return true;
}
-static inline bool is_feat_vhe_supported(void)
-{
- if (ENABLE_FEAT_VHE == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_FEAT_VHE == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_vhe_id_field() != 0U;
-}
+CREATE_FEATURE_FUNCS(feat_pan, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_PAN_SHIFT,
+ ENABLE_FEAT_PAN)
+CREATE_FEATURE_FUNCS(feat_vhe, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_VHE_SHIFT,
+ ENABLE_FEAT_VHE)
static inline bool is_armv8_2_ttcnp_present(void)
{
@@ -107,278 +95,51 @@
ID_AA64PFR1_EL1_MTE_MASK);
}
-static inline unsigned int read_feat_sel2_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_SEL2);
-}
-
-static inline bool is_feat_sel2_supported(void)
-{
- if (ENABLE_FEAT_SEL2 == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_FEAT_SEL2 == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_sel2_id_field() != 0U;
-}
-
-static inline unsigned int read_feat_twed_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_TWED);
-}
-
-static inline bool is_feat_twed_supported(void)
-{
- if (ENABLE_FEAT_TWED == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_FEAT_TWED == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_twed_id_field() != 0U;
-}
-
-static unsigned int read_feat_fgt_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64mmfr0_el1(), ID_AA64MMFR0_EL1_FGT);
-}
-
-static unsigned int read_feat_mte_perm_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64pfr2_el1(), ID_AA64PFR2_EL1_MTEPERM);
-}
-
-static inline bool is_feat_fgt_supported(void)
-{
- if (ENABLE_FEAT_FGT == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_FEAT_FGT == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_fgt_id_field() != 0U;
-}
-
-static inline bool is_feat_mte_perm_supported(void)
-{
- if (ENABLE_FEAT_MTE_PERM == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_FEAT_MTE_PERM == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_mte_perm_id_field() != 0U;
-}
-
-static unsigned int read_feat_ecv_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64mmfr0_el1(), ID_AA64MMFR0_EL1_ECV);
-}
-
-static inline bool is_feat_ecv_supported(void)
-{
- if (ENABLE_FEAT_ECV == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_FEAT_ECV == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_ecv_id_field() != 0U;
-}
-
-static inline bool is_feat_ecv_v2_supported(void)
-{
- if (ENABLE_FEAT_ECV == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_FEAT_ECV == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_ecv_id_field() >= ID_AA64MMFR0_EL1_ECV_SELF_SYNCH;
-}
-
-static unsigned int read_feat_rng_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64isar0_el1(), ID_AA64ISAR0_RNDR);
-}
-
-static inline bool is_feat_rng_supported(void)
-{
- if (ENABLE_FEAT_RNG == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_FEAT_RNG == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_rng_id_field() != 0U;
-}
-
-static unsigned int read_feat_tcrx_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_TCRX);
-}
-
-static inline bool is_feat_tcr2_supported(void)
-{
- if (ENABLE_FEAT_TCR2 == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_FEAT_TCR2 == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_tcrx_id_field() != 0U;
-}
+CREATE_FEATURE_FUNCS(feat_sel2, id_aa64pfr0_el1, ID_AA64PFR0_SEL2_SHIFT,
+ ENABLE_FEAT_SEL2)
+CREATE_FEATURE_FUNCS(feat_twed, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_TWED_SHIFT,
+ ENABLE_FEAT_TWED)
+CREATE_FEATURE_FUNCS(feat_fgt, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_FGT_SHIFT,
+ ENABLE_FEAT_FGT)
+CREATE_FEATURE_FUNCS(feat_mte_perm, id_aa64pfr2_el1,
+ ID_AA64PFR2_EL1_MTEPERM_SHIFT, ENABLE_FEAT_MTE_PERM)
+CREATE_FEATURE_FUNCS(feat_ecv, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_ECV_SHIFT,
+ ENABLE_FEAT_ECV)
+CREATE_FEATURE_FUNCS_VER(feat_ecv_v2, read_feat_ecv_id_field,
+ ID_AA64MMFR0_EL1_ECV_SELF_SYNCH, ENABLE_FEAT_ECV)
-static unsigned int read_feat_s2poe_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_S2POE);
-}
-
-static inline bool is_feat_s2poe_supported(void)
-{
- if (ENABLE_FEAT_S2POE == FEAT_STATE_DISABLED) {
- return false;
- }
+CREATE_FEATURE_FUNCS(feat_rng, id_aa64isar0_el1, ID_AA64ISAR0_RNDR_SHIFT,
+ ENABLE_FEAT_RNG)
+CREATE_FEATURE_FUNCS(feat_tcr2, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_TCRX_SHIFT,
+ ENABLE_FEAT_TCR2)
- if (ENABLE_FEAT_S2POE == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_s2poe_id_field() != 0U;
-}
-
-static unsigned int read_feat_s1poe_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_S1POE);
-}
-
-static inline bool is_feat_s1poe_supported(void)
-{
- if (ENABLE_FEAT_S1POE == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_FEAT_S1POE == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_s1poe_id_field() != 0U;
-}
-
+CREATE_FEATURE_FUNCS(feat_s2poe, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S2POE_SHIFT,
+ ENABLE_FEAT_S2POE)
+CREATE_FEATURE_FUNCS(feat_s1poe, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S1POE_SHIFT,
+ ENABLE_FEAT_S1POE)
static inline bool is_feat_sxpoe_supported(void)
{
return is_feat_s1poe_supported() || is_feat_s2poe_supported();
}
-static unsigned int read_feat_s2pie_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_S2PIE);
-}
-
-static inline bool is_feat_s2pie_supported(void)
-{
- if (ENABLE_FEAT_S2PIE == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_FEAT_S2PIE == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_s2pie_id_field() != 0U;
-}
-
-static unsigned int read_feat_s1pie_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_S1PIE);
-}
-
-static inline bool is_feat_s1pie_supported(void)
-{
- if (ENABLE_FEAT_S1PIE == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_FEAT_S1PIE == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_s1pie_id_field() != 0U;
-}
-
+CREATE_FEATURE_FUNCS(feat_s2pie, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S2PIE_SHIFT,
+ ENABLE_FEAT_S2PIE)
+CREATE_FEATURE_FUNCS(feat_s1pie, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S1PIE_SHIFT,
+ ENABLE_FEAT_S1PIE)
static inline bool is_feat_sxpie_supported(void)
{
return is_feat_s1pie_supported() || is_feat_s2pie_supported();
}
-static unsigned int read_feat_gcs_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_GCS);
-}
-
-static inline bool is_feat_gcs_supported(void)
-{
- if (ENABLE_FEAT_GCS == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_FEAT_GCS == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_gcs_id_field() != 0U;
-}
-
-/*******************************************************************************
- * Functions to identify the presence of the Activity Monitors Extension
- ******************************************************************************/
-static unsigned int read_feat_amu_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_AMU);
-}
-
-static inline bool is_feat_amu_supported(void)
-{
- if (ENABLE_FEAT_AMU == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_FEAT_AMU == FEAT_STATE_ALWAYS) {
- return true;
- }
+/* FEAT_GCS: Guarded Control Stack */
+CREATE_FEATURE_FUNCS(feat_gcs, id_aa64pfr1_el1, ID_AA64PFR1_EL1_GCS_SHIFT,
+ ENABLE_FEAT_GCS)
- return read_feat_amu_id_field() >= ID_AA64PFR0_AMU_V1;
-}
-
-static inline bool is_feat_amuv1p1_supported(void)
-{
- if (ENABLE_FEAT_AMUv1p1 == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_FEAT_AMUv1p1 == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_amu_id_field() >= ID_AA64PFR0_AMU_V1P1;
-}
+/* FEAT_AMU: Activity Monitors Extension */
+CREATE_FEATURE_FUNCS(feat_amu, id_aa64pfr0_el1, ID_AA64PFR0_AMU_SHIFT,
+ ENABLE_FEAT_AMU)
+CREATE_FEATURE_FUNCS_VER(feat_amuv1p1, read_feat_amu_id_field,
+ ID_AA64PFR0_AMU_V1P1, ENABLE_FEAT_AMUv1p1)
/*
* Return MPAM version:
@@ -397,36 +158,12 @@
ID_AA64PFR1_MPAM_FRAC_SHIFT) & ID_AA64PFR1_MPAM_FRAC_MASK));
}
-static inline bool is_feat_mpam_supported(void)
-{
- if (ENABLE_MPAM_FOR_LOWER_ELS == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_MPAM_FOR_LOWER_ELS == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_mpam_version() != 0U;
-}
-
-static inline unsigned int read_feat_hcx_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_HCX);
-}
-
-static inline bool is_feat_hcx_supported(void)
-{
- if (ENABLE_FEAT_HCX == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_FEAT_HCX == FEAT_STATE_ALWAYS) {
- return true;
- }
+CREATE_FEATURE_FUNCS_VER(feat_mpam, read_feat_mpam_version, 1U,
+ ENABLE_MPAM_FOR_LOWER_ELS)
- return read_feat_hcx_id_field() != 0U;
-}
+/* FEAT_HCX: Extended Hypervisor Configuration Register */
+CREATE_FEATURE_FUNCS(feat_hcx, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_HCX_SHIFT,
+ ENABLE_FEAT_HCX)
static inline bool is_feat_rng_trap_present(void)
{
@@ -451,251 +188,60 @@
********************************************************************************/
static inline unsigned int read_feat_sb_id_field(void)
{
- return ISOLATE_FIELD(read_id_aa64isar1_el1(), ID_AA64ISAR1_SB);
-}
-
-/*********************************************************************************
- * Function to identify the presence of FEAT_CSV2_2 (Cache Speculation Variant 2)
- ********************************************************************************/
-static inline unsigned int read_feat_csv2_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_CSV2);
-}
-
-static inline bool is_feat_csv2_2_supported(void)
-{
- if (ENABLE_FEAT_CSV2_2 == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_FEAT_CSV2_2 == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_csv2_id_field() >= ID_AA64PFR0_CSV2_2_SUPPORTED;
-}
-
-/**********************************************************************************
- * Function to identify the presence of FEAT_SPE (Statistical Profiling Extension)
- *********************************************************************************/
-static inline unsigned int read_feat_spe_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_PMS);
-}
-
-static inline bool is_feat_spe_supported(void)
-{
- if (ENABLE_SPE_FOR_NS == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_SPE_FOR_NS == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_spe_id_field() != 0U;
-}
-
-/*******************************************************************************
- * Function to identify the presence of FEAT_SVE (Scalable Vector Extension)
- ******************************************************************************/
-static inline unsigned int read_feat_sve_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_SVE);
-}
-
-static inline bool is_feat_sve_supported(void)
-{
- if (ENABLE_SVE_FOR_NS == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_SVE_FOR_NS == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_sve_id_field() >= ID_AA64PFR0_SVE_SUPPORTED;
-}
-
-static unsigned int read_feat_ras_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_RAS);
-}
-
-static inline bool is_feat_ras_supported(void)
-{
- if (ENABLE_FEAT_RAS == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_FEAT_RAS == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_ras_id_field() != 0U;
-}
-
-static unsigned int read_feat_dit_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_DIT);
-}
-
-static inline bool is_feat_dit_supported(void)
-{
- if (ENABLE_FEAT_DIT == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_FEAT_DIT == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_dit_id_field() != 0U;
-}
-
-static inline unsigned int read_feat_tracever_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_TRACEVER);
-}
-
-static inline bool is_feat_sys_reg_trace_supported(void)
-{
- if (ENABLE_SYS_REG_TRACE_FOR_NS == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_SYS_REG_TRACE_FOR_NS == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_tracever_id_field() != 0U;
-}
-
-/*************************************************************************
- * Function to identify the presence of FEAT_TRF (TraceLift)
- ************************************************************************/
-static inline unsigned int read_feat_trf_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_TRACEFILT);
+ return ISOLATE_FIELD(read_id_aa64isar1_el1(), ID_AA64ISAR1_SB_SHIFT);
}
-static inline bool is_feat_trf_supported(void)
-{
- if (ENABLE_TRF_FOR_NS == FEAT_STATE_DISABLED) {
- return false;
- }
+/* FEAT_CSV2_2: Cache Speculation Variant 2 */
+CREATE_FEATURE_FUNCS(feat_csv2, id_aa64pfr0_el1, ID_AA64PFR0_CSV2_SHIFT, 0)
+CREATE_FEATURE_FUNCS_VER(feat_csv2_2, read_feat_csv2_id_field,
+ ID_AA64PFR0_CSV2_2_SUPPORTED, ENABLE_FEAT_CSV2_2)
- if (ENABLE_TRF_FOR_NS == FEAT_STATE_ALWAYS) {
- return true;
- }
+/* FEAT_SPE: Statistical Profiling Extension */
+CREATE_FEATURE_FUNCS(feat_spe, id_aa64dfr0_el1, ID_AA64DFR0_PMS_SHIFT,
+ ENABLE_SPE_FOR_NS)
- return read_feat_trf_id_field() != 0U;
-}
+/* FEAT_SVE: Scalable Vector Extension */
+CREATE_FEATURE_FUNCS(feat_sve, id_aa64pfr0_el1, ID_AA64PFR0_SVE_SHIFT,
+ ENABLE_SVE_FOR_NS)
-/********************************************************************************
- * Function to identify the presence of FEAT_NV2 (Enhanced Nested Virtualization
- * Support)
- *******************************************************************************/
-static inline unsigned int read_feat_nv_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64mmfr2_el1(), ID_AA64MMFR2_EL1_NV);
-}
+/* FEAT_RAS: Reliability, Accessibility, Serviceability */
+CREATE_FEATURE_FUNCS(feat_ras, id_aa64pfr0_el1,
+ ID_AA64PFR0_RAS_SHIFT, ENABLE_FEAT_RAS)
-static inline bool is_feat_nv2_supported(void)
-{
- if (CTX_INCLUDE_NEVE_REGS == FEAT_STATE_DISABLED) {
- return false;
- }
+/* FEAT_DIT: Data Independent Timing instructions */
+CREATE_FEATURE_FUNCS(feat_dit, id_aa64pfr0_el1,
+ ID_AA64PFR0_DIT_SHIFT, ENABLE_FEAT_DIT)
- if (CTX_INCLUDE_NEVE_REGS == FEAT_STATE_ALWAYS) {
- return true;
- }
+CREATE_FEATURE_FUNCS(feat_sys_reg_trace, id_aa64dfr0_el1,
+ ID_AA64DFR0_TRACEVER_SHIFT, ENABLE_SYS_REG_TRACE_FOR_NS)
- return read_feat_nv_id_field() >= ID_AA64MMFR2_EL1_NV2_SUPPORTED;
-}
+/* FEAT_TRF: TraceFilter */
+CREATE_FEATURE_FUNCS(feat_trf, id_aa64dfr0_el1, ID_AA64DFR0_TRACEFILT_SHIFT,
+ ENABLE_TRF_FOR_NS)
-/*******************************************************************************
- * Function to identify the presence of FEAT_BRBE (Branch Record Buffer
- * Extension)
- ******************************************************************************/
-static inline unsigned int read_feat_brbe_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_BRBE);
-}
+/* FEAT_NV2: Enhanced Nested Virtualization */
+CREATE_FEATURE_FUNCS(feat_nv, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_NV_SHIFT, 0)
+CREATE_FEATURE_FUNCS_VER(feat_nv2, read_feat_nv_id_field,
+ ID_AA64MMFR2_EL1_NV2_SUPPORTED, CTX_INCLUDE_NEVE_REGS)
-static inline bool is_feat_brbe_supported(void)
-{
- if (ENABLE_BRBE_FOR_NS == FEAT_STATE_DISABLED) {
- return false;
- }
+/* FEAT_BRBE: Branch Record Buffer Extension */
+CREATE_FEATURE_FUNCS(feat_brbe, id_aa64dfr0_el1, ID_AA64DFR0_BRBE_SHIFT,
+ ENABLE_BRBE_FOR_NS)
- if (ENABLE_BRBE_FOR_NS == FEAT_STATE_ALWAYS) {
- return true;
- }
+/* FEAT_TRBE: Trace Buffer Extension */
+CREATE_FEATURE_FUNCS(feat_trbe, id_aa64dfr0_el1, ID_AA64DFR0_TRACEBUFFER_SHIFT,
+ ENABLE_TRBE_FOR_NS)
- return read_feat_brbe_id_field() != 0U;
-}
-
-/*******************************************************************************
- * Function to identify the presence of FEAT_TRBE (Trace Buffer Extension)
- ******************************************************************************/
-static inline unsigned int read_feat_trbe_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_TRACEBUFFER);
-}
-
-static inline bool is_feat_trbe_supported(void)
-{
- if (ENABLE_TRBE_FOR_NS == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_TRBE_FOR_NS == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_trbe_id_field() != 0U;
-
-}
-
-/*******************************************************************************
- * Function to identify the presence of FEAT_SMEx (Scalar Matrix Extension)
- ******************************************************************************/
static inline unsigned int read_feat_sme_fa64_id_field(void)
{
- return ISOLATE_FIELD(read_id_aa64smfr0_el1(), ID_AA64SMFR0_EL1_SME_FA64);
+ return ISOLATE_FIELD(read_id_aa64smfr0_el1(),
+ ID_AA64SMFR0_EL1_SME_FA64_SHIFT);
}
-
-static inline unsigned int read_feat_sme_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_SME);
-}
-
-static inline bool is_feat_sme_supported(void)
-{
- if (ENABLE_SME_FOR_NS == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_SME_FOR_NS == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_sme_id_field() >= ID_AA64PFR1_EL1_SME_SUPPORTED;
-}
-
-static inline bool is_feat_sme2_supported(void)
-{
- if (ENABLE_SME2_FOR_NS == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_SME2_FOR_NS == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_sme_id_field() >= ID_AA64PFR1_EL1_SME2_SUPPORTED;
-}
+/* FEAT_SMEx: Scalar Matrix Extension */
+CREATE_FEATURE_FUNCS(feat_sme, id_aa64pfr1_el1, ID_AA64PFR1_EL1_SME_SHIFT,
+ ENABLE_SME_FOR_NS)
+CREATE_FEATURE_FUNCS_VER(feat_sme2, read_feat_sme_id_field,
+ ID_AA64PFR1_EL1_SME2_SUPPORTED, ENABLE_SME2_FOR_NS)
/*******************************************************************************
* Function to get hardware granularity support
@@ -703,29 +249,30 @@
static inline unsigned int read_id_aa64mmfr0_el0_tgran4_field(void)
{
- return ISOLATE_FIELD(read_id_aa64mmfr0_el1(), ID_AA64MMFR0_EL1_TGRAN4);
+ return ISOLATE_FIELD(read_id_aa64mmfr0_el1(),
+ ID_AA64MMFR0_EL1_TGRAN4_SHIFT);
}
static inline unsigned int read_id_aa64mmfr0_el0_tgran16_field(void)
{
return ISOLATE_FIELD(read_id_aa64mmfr0_el1(),
- ID_AA64MMFR0_EL1_TGRAN16);
+ ID_AA64MMFR0_EL1_TGRAN16_SHIFT);
}
static inline unsigned int read_id_aa64mmfr0_el0_tgran64_field(void)
{
return ISOLATE_FIELD(read_id_aa64mmfr0_el1(),
- ID_AA64MMFR0_EL1_TGRAN64);
+ ID_AA64MMFR0_EL1_TGRAN64_SHIFT);
}
static inline unsigned int read_feat_pmuv3_id_field(void)
{
- return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_PMUVER);
+ return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_PMUVER_SHIFT);
}
static inline unsigned int read_feat_mtpmu_id_field(void)
{
- return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_MTPMU);
+ return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_MTPMU_SHIFT);
}
static inline bool is_feat_mtpmu_supported(void)
diff --git a/include/arch/aarch64/arch_helpers.h b/include/arch/aarch64/arch_helpers.h
index 3121079..6fdc7e8 100644
--- a/include/arch/aarch64/arch_helpers.h
+++ b/include/arch/aarch64/arch_helpers.h
@@ -487,6 +487,13 @@
DEFINE_SYSREG_RW_FUNCS(vpidr_el2)
DEFINE_SYSREG_RW_FUNCS(vmpidr_el2)
+DEFINE_SYSREG_RW_FUNCS(hacr_el2)
+DEFINE_SYSREG_RW_FUNCS(hpfar_el2)
+DEFINE_SYSREG_RW_FUNCS(tpidr_el2)
+DEFINE_SYSREG_RW_FUNCS(dbgvcr32_el2)
+DEFINE_RENAME_SYSREG_RW_FUNCS(ich_hcr_el2, ICH_HCR_EL2)
+DEFINE_RENAME_SYSREG_RW_FUNCS(ich_vmcr_el2, ICH_VMCR_EL2)
+
DEFINE_SYSREG_READ_FUNC(isr_el1)
DEFINE_SYSREG_RW_FUNCS(mdcr_el2)
@@ -585,6 +592,7 @@
DEFINE_RENAME_SYSREG_RW_FUNCS(tfsr_el1, TFSR_EL1)
DEFINE_RENAME_SYSREG_RW_FUNCS(rgsr_el1, RGSR_EL1)
DEFINE_RENAME_SYSREG_RW_FUNCS(gcr_el1, GCR_EL1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(tfsr_el2, TFSR_EL2)
/* Armv8.5 FEAT_RNG Registers */
DEFINE_RENAME_SYSREG_READ_FUNC(rndr, RNDR)
diff --git a/include/common/bl_common.h b/include/common/bl_common.h
index 539280e..4c8a17c 100644
--- a/include/common/bl_common.h
+++ b/include/common/bl_common.h
@@ -85,6 +85,10 @@
#define __EL3_LP_DESCS_START__ Load$$__EL3_LP_DESCS__$$Base
#define __EL3_LP_DESCS_END__ Load$$__EL3_LP_DESCS__$$Limit
#endif
+#if ENABLE_SPMD_LP
+#define __SPMD_LP_DESCS_START__ Load$$__SPMD_LP_DESCS__$$Base
+#define __SPMD_LP_DESCS_END__ Load$$__SPMD_LP_DESCS__$$Limit
+#endif
#define __RW_START__ Load$$LR$$LR_RW_DATA$$Base
#define __RW_END__ Load$$LR$$LR_END$$Base
#define __SPM_SHIM_EXCEPTIONS_START__ Load$$__SPM_SHIM_EXCEPTIONS__$$Base
diff --git a/include/common/bl_common.ld.h b/include/common/bl_common.ld.h
index c9bed1a..b6dd0f0 100644
--- a/include/common/bl_common.ld.h
+++ b/include/common/bl_common.ld.h
@@ -49,6 +49,15 @@
#define EL3_LP_DESCS
#endif
+#if ENABLE_SPMD_LP
+#define SPMD_LP_DESCS \
+ . = ALIGN(STRUCT_ALIGN); \
+ __SPMD_LP_DESCS_START__ = .; \
+ KEEP(*(.spmd_lp_descs)) \
+ __SPMD_LP_DESCS_END__ = .;
+#else
+#define SPMD_LP_DESCS
+#endif
#define PMF_SVC_DESCS \
. = ALIGN(STRUCT_ALIGN); \
__PMF_SVC_DESCS_START__ = .; \
@@ -100,7 +109,8 @@
CPU_OPS \
GOT \
BASE_XLAT_TABLE_RO \
- EL3_LP_DESCS
+ EL3_LP_DESCS \
+ SPMD_LP_DESCS
/*
* .data must be placed at a lower address than the stacks if the stack
diff --git a/include/lib/cpus/aarch64/cortex_gelas.h b/include/lib/cpus/aarch64/cortex_gelas.h
new file mode 100644
index 0000000..90bb78f
--- /dev/null
+++ b/include/lib/cpus/aarch64/cortex_gelas.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2023, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CORTEX_GELAS_H
+#define CORTEX_GELAS_H
+
+#include <lib/utils_def.h>
+
+#define CORTEX_GELAS_MIDR U(0x410FD8B0)
+
+/*******************************************************************************
+ * CPU Extended Control register specific definitions
+ ******************************************************************************/
+#define CORTEX_GELAS_IMP_CPUECTLR_EL1 S3_0_C15_C1_5
+
+/*******************************************************************************
+ * CPU Power Control register specific definitions
+ ******************************************************************************/
+#define CORTEX_GELAS_CPUPWRCTLR_EL1 S3_0_C15_C2_7
+#define CORTEX_GELAS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
+
+/*******************************************************************************
+ * SME Control registers
+ ******************************************************************************/
+#define CORTEX_GELAS_SVCRSM S0_3_C4_C2_3
+#define CORTEX_GELAS_SVCRZA S0_3_C4_C4_3
+
+#endif /* CORTEX_GELAS_H */
diff --git a/include/lib/el3_runtime/aarch64/context.h b/include/lib/el3_runtime/aarch64/context.h
index e6af43e..ebd0e30 100644
--- a/include/lib/el3_runtime/aarch64/context.h
+++ b/include/lib/el3_runtime/aarch64/context.h
@@ -516,15 +516,6 @@
void el1_sysregs_context_save(el1_sysregs_t *regs);
void el1_sysregs_context_restore(el1_sysregs_t *regs);
-#if CTX_INCLUDE_EL2_REGS
-void el2_sysregs_context_save_common(el2_sysregs_t *regs);
-void el2_sysregs_context_restore_common(el2_sysregs_t *regs);
-#if CTX_INCLUDE_MTE_REGS
-void el2_sysregs_context_save_mte(el2_sysregs_t *regs);
-void el2_sysregs_context_restore_mte(el2_sysregs_t *regs);
-#endif /* CTX_INCLUDE_MTE_REGS */
-#endif /* CTX_INCLUDE_EL2_REGS */
-
#if CTX_INCLUDE_FPREGS
void fpregs_context_save(fp_regs_t *regs);
void fpregs_context_restore(fp_regs_t *regs);
diff --git a/include/services/el3_spmd_logical_sp.h b/include/services/el3_spmd_logical_sp.h
new file mode 100644
index 0000000..1f9ef0d
--- /dev/null
+++ b/include/services/el3_spmd_logical_sp.h
@@ -0,0 +1,168 @@
+/*
+ * Copyright (c) 2023, ARM Limited and Contributors. All rights reserved.
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef EL3_SPMD_LOGICAL_SP_H
+#define EL3_SPMD_LOGICAL_SP_H
+
+#include <common/bl_common.h>
+#include <lib/cassert.h>
+#include <services/ffa_svc.h>
+
+/*******************************************************************************
+ * Structure definition, typedefs & constants for the SPMD Logical Partitions.
+ ******************************************************************************/
+typedef struct spmd_spm_core_context spmd_spm_core_context_t;
+
+/* Prototype for SPMD logical partition initializing function. */
+typedef int32_t (*ffa_spmd_lp_init_t)(void);
+
+/* SPMD Logical Partition Descriptor. */
+struct spmd_lp_desc {
+ ffa_spmd_lp_init_t init;
+ uint16_t sp_id;
+ uint32_t properties;
+ uint32_t uuid[4]; /* Little Endian. */
+ const char *debug_name;
+};
+
+struct ffa_value {
+ uint64_t func;
+ uint64_t arg1;
+ uint64_t arg2;
+ uint64_t arg3;
+ uint64_t arg4;
+ uint64_t arg5;
+ uint64_t arg6;
+ uint64_t arg7;
+ uint64_t arg8;
+ uint64_t arg9;
+ uint64_t arg10;
+ uint64_t arg11;
+ uint64_t arg12;
+ uint64_t arg13;
+ uint64_t arg14;
+ uint64_t arg15;
+ uint64_t arg16;
+ uint64_t arg17;
+};
+
+/* Convenience macro to declare a SPMD logical partition descriptor. */
+#define DECLARE_SPMD_LOGICAL_PARTITION(_name, _init, _sp_id, _uuid, _properties) \
+ static const struct spmd_lp_desc __partition_desc_ ## _name \
+ __section(".spmd_lp_descs") __used = { \
+ .debug_name = #_name, \
+ .init = (_init), \
+ .sp_id = (_sp_id), \
+ .uuid = _uuid, \
+ .properties = (_properties), \
+ }
+
+IMPORT_SYM(uintptr_t, __SPMD_LP_DESCS_START__, SPMD_LP_DESCS_START);
+IMPORT_SYM(uintptr_t, __SPMD_LP_DESCS_END__, SPMD_LP_DESCS_END);
+
+#define SPMD_LP_DESCS_COUNT ((SPMD_LP_DESCS_END - SPMD_LP_DESCS_START) \
+ / sizeof(struct spmd_lp_desc))
+CASSERT(sizeof(struct spmd_lp_desc) == 40, assert_spmd_lp_desc_size_mismatch);
+
+/*
+ * Reserve 63 IDs for SPMD Logical Partitions. Currently, 0xFFC0 to 0xFFFE
+ * is reserved.
+ */
+#define SPMD_LP_ID_END (SPMD_DIRECT_MSG_ENDPOINT_ID - 1)
+#define SPMD_LP_ID_START (SPMD_LP_ID_END - 62)
+
+/*
+ * TODO: Arbitrary number. Can make this platform specific in the future,
+ * no known use cases for more LPs at this point.
+ */
+#define EL3_SPMD_MAX_NUM_LP U(5)
+
+static inline bool is_spmd_lp_id(unsigned int id)
+{
+#if ENABLE_SPMD_LP
+ return (id >= SPMD_LP_ID_START && id <= SPMD_LP_ID_END);
+#else
+ return false;
+#endif
+}
+
+static inline bool is_ffa_error(struct ffa_value *retval)
+{
+ return retval->func == FFA_ERROR;
+}
+
+static inline bool is_ffa_success(struct ffa_value *retval)
+{
+ return (retval->func == FFA_SUCCESS_SMC32) ||
+ (retval->func == FFA_SUCCESS_SMC64);
+}
+
+static inline bool is_ffa_direct_msg_resp(struct ffa_value *retval)
+{
+ return (retval->func == FFA_MSG_SEND_DIRECT_RESP_SMC32) ||
+ (retval->func == FFA_MSG_SEND_DIRECT_RESP_SMC64);
+}
+
+static inline uint16_t ffa_partition_info_regs_get_last_idx(
+ struct ffa_value args)
+{
+ return (uint16_t)(args.arg2 & 0xFFFFU);
+}
+
+static inline uint16_t ffa_partition_info_regs_get_curr_idx(
+ struct ffa_value args)
+{
+ return (uint16_t)((args.arg2 >> 16) & 0xFFFFU);
+}
+
+static inline uint16_t ffa_partition_info_regs_get_tag(struct ffa_value args)
+{
+ return (uint16_t)((args.arg2 >> 32) & 0xFFFFU);
+}
+
+static inline uint16_t ffa_partition_info_regs_get_desc_size(
+ struct ffa_value args)
+{
+ return (uint16_t)(args.arg2 >> 48);
+}
+
+uint64_t spmd_el3_populate_logical_partition_info(void *handle, uint64_t x1,
+ uint64_t x2, uint64_t x3);
+
+bool ffa_partition_info_regs_get_part_info(
+ struct ffa_value args, uint8_t idx,
+ struct ffa_partition_info_v1_1 *partition_info);
+
+bool spmd_el3_invoke_partition_info_get(
+ const uint32_t target_uuid[4],
+ const uint16_t start_index,
+ const uint16_t tag,
+ struct ffa_value *retval);
+void spmd_logical_sp_set_spmc_initialized(void);
+void spmc_logical_sp_set_spmc_failure(void);
+
+int32_t spmd_logical_sp_init(void);
+bool is_spmd_logical_sp_dir_req_in_progress(
+ spmd_spm_core_context_t *ctx);
+
+bool is_spmd_logical_sp_info_regs_req_in_progress(
+ spmd_spm_core_context_t *ctx);
+
+bool spmd_el3_ffa_msg_direct_req(uint64_t x1,
+ uint64_t x2,
+ uint64_t x3,
+ uint64_t x4,
+ void *handle,
+ struct ffa_value *retval);
+
+uintptr_t plat_spmd_logical_sp_smc_handler(unsigned int smc_fid,
+ u_register_t x1,
+ u_register_t x2,
+ u_register_t x3,
+ u_register_t x4,
+ void *cookie,
+ void *handle,
+ u_register_t flags);
+
+#endif /* EL3_SPMD_LOGICAL_SP_H */
diff --git a/include/services/ffa_svc.h b/include/services/ffa_svc.h
index 64af437..de56638 100644
--- a/include/services/ffa_svc.h
+++ b/include/services/ffa_svc.h
@@ -343,4 +343,28 @@
uint64_t reserved;
};
+/* FF-A Partition Info Get related macros. */
+#define FFA_PARTITION_INFO_GET_PROPERTIES_V1_0_MASK U(0x7)
+#define FFA_PARTITION_INFO_GET_EXEC_STATE_SHIFT U(8)
+#define FFA_PARTITION_INFO_GET_AARCH32_STATE U(0)
+#define FFA_PARTITION_INFO_GET_AARCH64_STATE U(1)
+
+/**
+ * Holds information returned for each partition by the FFA_PARTITION_INFO_GET
+ * interface.
+ */
+struct ffa_partition_info_v1_0 {
+ uint16_t ep_id;
+ uint16_t execution_ctx_count;
+ uint32_t properties;
+};
+
+/* Extended structure for FF-A v1.1. */
+struct ffa_partition_info_v1_1 {
+ uint16_t ep_id;
+ uint16_t execution_ctx_count;
+ uint32_t properties;
+ uint32_t uuid[4];
+};
+
#endif /* FFA_SVC_H */
diff --git a/lib/cpus/aarch64/cortex_gelas.S b/lib/cpus/aarch64/cortex_gelas.S
new file mode 100644
index 0000000..e0d20a9
--- /dev/null
+++ b/lib/cpus/aarch64/cortex_gelas.S
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2023, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <common/bl_common.h>
+#include <cortex_gelas.h>
+#include <cpu_macros.S>
+#include <plat_macros.S>
+
+/* Hardware handled coherency */
+#if HW_ASSISTED_COHERENCY == 0
+#error "Gelas must be compiled with HW_ASSISTED_COHERENCY enabled"
+#endif
+
+/* 64-bit only core */
+#if CTX_INCLUDE_AARCH32_REGS == 1
+#error "Gelas supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
+#endif
+
+cpu_reset_func_start cortex_gelas
+ /* ----------------------------------------------------
+ * Disable speculative loads
+ * ----------------------------------------------------
+ */
+ msr SSBS, xzr
+cpu_reset_func_end cortex_gelas
+
+ /* ----------------------------------------------------
+ * HW will do the cache maintenance while powering down
+ * ----------------------------------------------------
+ */
+func cortex_gelas_core_pwr_dwn
+ /* ---------------------------------------------------
+ * Disable SME
+ * ---------------------------------------------------
+ */
+ msr CORTEX_GELAS_SVCRSM, xzr
+ msr CORTEX_GELAS_SVCRZA, xzr
+
+ /* ---------------------------------------------------
+ * Enable CPU power down bit in power control register
+ * ---------------------------------------------------
+ */
+ sysreg_bit_set CORTEX_GELAS_CPUPWRCTLR_EL1, \
+ CORTEX_GELAS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+ isb
+ ret
+endfunc cortex_gelas_core_pwr_dwn
+
+errata_report_shim cortex_gelas
+
+ /* ---------------------------------------------
+ * This function provides Gelas specific
+ * register information for crash reporting.
+ * It needs to return with x6 pointing to
+ * a list of register names in ascii and
+ * x8 - x15 having values of registers to be
+ * reported.
+ * ---------------------------------------------
+ */
+.section .rodata.cortex_gelas_regs, "aS"
+cortex_gelas_regs: /* The ASCII list of register names to be reported */
+ .asciz "imp_cpuectlr_el1", ""
+
+func cortex_gelas_cpu_reg_dump
+ adr x6, cortex_gelas_regs
+ mrs x8, CORTEX_GELAS_IMP_CPUECTLR_EL1
+ ret
+endfunc cortex_gelas_cpu_reg_dump
+
+declare_cpu_ops cortex_gelas, CORTEX_GELAS_MIDR, \
+ cortex_gelas_reset_func, \
+ cortex_gelas_core_pwr_dwn
diff --git a/lib/el3_runtime/aarch64/context.S b/lib/el3_runtime/aarch64/context.S
index 771fcdc..f47e779 100644
--- a/lib/el3_runtime/aarch64/context.S
+++ b/lib/el3_runtime/aarch64/context.S
@@ -10,15 +10,6 @@
#include <context.h>
#include <el3_common_macros.S>
-#if CTX_INCLUDE_EL2_REGS
- .global el2_sysregs_context_save_common
- .global el2_sysregs_context_restore_common
-#if CTX_INCLUDE_MTE_REGS
- .global el2_sysregs_context_save_mte
- .global el2_sysregs_context_restore_mte
-#endif /* CTX_INCLUDE_MTE_REGS */
-#endif /* CTX_INCLUDE_EL2_REGS */
-
.global el1_sysregs_context_save
.global el1_sysregs_context_restore
#if CTX_INCLUDE_FPREGS
@@ -30,183 +21,6 @@
.global save_and_update_ptw_el1_sys_regs
.global el3_exit
-#if CTX_INCLUDE_EL2_REGS
-
-/* -----------------------------------------------------
- * The following functions strictly follow the AArch64
- * PCS to use x9-x16 (temporary caller-saved registers)
- * to save/restore EL2 system register context.
- * el2_sysregs_context_save/restore_common functions
- * save and restore registers that are common to all
- * configurations. The rest of the functions save and
- * restore EL2 system registers that are present when a
- * particular feature is enabled. All functions assume
- * that 'x0' is pointing to a 'el2_sys_regs' structure
- * where the register context will be saved/restored.
- *
- * The following registers are not added.
- * AMEVCNTVOFF0<n>_EL2
- * AMEVCNTVOFF1<n>_EL2
- * ICH_AP0R<n>_EL2
- * ICH_AP1R<n>_EL2
- * ICH_LR<n>_EL2
- * -----------------------------------------------------
- */
-func el2_sysregs_context_save_common
- mrs x9, actlr_el2
- mrs x10, afsr0_el2
- stp x9, x10, [x0, #CTX_ACTLR_EL2]
-
- mrs x11, afsr1_el2
- mrs x12, amair_el2
- stp x11, x12, [x0, #CTX_AFSR1_EL2]
-
- mrs x13, cnthctl_el2
- mrs x14, cntvoff_el2
- stp x13, x14, [x0, #CTX_CNTHCTL_EL2]
-
- mrs x15, cptr_el2
- str x15, [x0, #CTX_CPTR_EL2]
-
-#if CTX_INCLUDE_AARCH32_REGS
- mrs x16, dbgvcr32_el2
- str x16, [x0, #CTX_DBGVCR32_EL2]
-#endif /* CTX_INCLUDE_AARCH32_REGS */
-
- mrs x9, elr_el2
- mrs x10, esr_el2
- stp x9, x10, [x0, #CTX_ELR_EL2]
-
- mrs x11, far_el2
- mrs x12, hacr_el2
- stp x11, x12, [x0, #CTX_FAR_EL2]
-
- mrs x13, hcr_el2
- mrs x14, hpfar_el2
- stp x13, x14, [x0, #CTX_HCR_EL2]
-
- mrs x15, hstr_el2
- mrs x16, ICC_SRE_EL2
- stp x15, x16, [x0, #CTX_HSTR_EL2]
-
- mrs x9, ICH_HCR_EL2
- mrs x10, ICH_VMCR_EL2
- stp x9, x10, [x0, #CTX_ICH_HCR_EL2]
-
- mrs x11, mair_el2
- mrs x12, mdcr_el2
- stp x11, x12, [x0, #CTX_MAIR_EL2]
-
- mrs x14, sctlr_el2
- str x14, [x0, #CTX_SCTLR_EL2]
-
- mrs x15, spsr_el2
- mrs x16, sp_el2
- stp x15, x16, [x0, #CTX_SPSR_EL2]
-
- mrs x9, tcr_el2
- mrs x10, tpidr_el2
- stp x9, x10, [x0, #CTX_TCR_EL2]
-
- mrs x11, ttbr0_el2
- mrs x12, vbar_el2
- stp x11, x12, [x0, #CTX_TTBR0_EL2]
-
- mrs x13, vmpidr_el2
- mrs x14, vpidr_el2
- stp x13, x14, [x0, #CTX_VMPIDR_EL2]
-
- mrs x15, vtcr_el2
- mrs x16, vttbr_el2
- stp x15, x16, [x0, #CTX_VTCR_EL2]
- ret
-endfunc el2_sysregs_context_save_common
-
-func el2_sysregs_context_restore_common
- ldp x9, x10, [x0, #CTX_ACTLR_EL2]
- msr actlr_el2, x9
- msr afsr0_el2, x10
-
- ldp x11, x12, [x0, #CTX_AFSR1_EL2]
- msr afsr1_el2, x11
- msr amair_el2, x12
-
- ldp x13, x14, [x0, #CTX_CNTHCTL_EL2]
- msr cnthctl_el2, x13
- msr cntvoff_el2, x14
-
- ldr x15, [x0, #CTX_CPTR_EL2]
- msr cptr_el2, x15
-
-#if CTX_INCLUDE_AARCH32_REGS
- ldr x16, [x0, #CTX_DBGVCR32_EL2]
- msr dbgvcr32_el2, x16
-#endif /* CTX_INCLUDE_AARCH32_REGS */
-
- ldp x9, x10, [x0, #CTX_ELR_EL2]
- msr elr_el2, x9
- msr esr_el2, x10
-
- ldp x11, x12, [x0, #CTX_FAR_EL2]
- msr far_el2, x11
- msr hacr_el2, x12
-
- ldp x13, x14, [x0, #CTX_HCR_EL2]
- msr hcr_el2, x13
- msr hpfar_el2, x14
-
- ldp x15, x16, [x0, #CTX_HSTR_EL2]
- msr hstr_el2, x15
- msr ICC_SRE_EL2, x16
-
- ldp x9, x10, [x0, #CTX_ICH_HCR_EL2]
- msr ICH_HCR_EL2, x9
- msr ICH_VMCR_EL2, x10
-
- ldp x11, x12, [x0, #CTX_MAIR_EL2]
- msr mair_el2, x11
- msr mdcr_el2, x12
-
- ldr x14, [x0, #CTX_SCTLR_EL2]
- msr sctlr_el2, x14
-
- ldp x15, x16, [x0, #CTX_SPSR_EL2]
- msr spsr_el2, x15
- msr sp_el2, x16
-
- ldp x9, x10, [x0, #CTX_TCR_EL2]
- msr tcr_el2, x9
- msr tpidr_el2, x10
-
- ldp x11, x12, [x0, #CTX_TTBR0_EL2]
- msr ttbr0_el2, x11
- msr vbar_el2, x12
-
- ldp x13, x14, [x0, #CTX_VMPIDR_EL2]
- msr vmpidr_el2, x13
- msr vpidr_el2, x14
-
- ldp x15, x16, [x0, #CTX_VTCR_EL2]
- msr vtcr_el2, x15
- msr vttbr_el2, x16
- ret
-endfunc el2_sysregs_context_restore_common
-
-#if CTX_INCLUDE_MTE_REGS
-func el2_sysregs_context_save_mte
- mrs x9, TFSR_EL2
- str x9, [x0, #CTX_TFSR_EL2]
- ret
-endfunc el2_sysregs_context_save_mte
-
-func el2_sysregs_context_restore_mte
- ldr x9, [x0, #CTX_TFSR_EL2]
- msr TFSR_EL2, x9
- ret
-endfunc el2_sysregs_context_restore_mte
-#endif /* CTX_INCLUDE_MTE_REGS */
-
-#endif /* CTX_INCLUDE_EL2_REGS */
/* ------------------------------------------------------------------
* The following function strictly follows the AArch64 PCS to use
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index 9d717bb..0ac2d6e 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -971,6 +971,89 @@
}
}
+/* -----------------------------------------------------
+ * The following registers are not added:
+ * AMEVCNTVOFF0<n>_EL2
+ * AMEVCNTVOFF1<n>_EL2
+ * ICH_AP0R<n>_EL2
+ * ICH_AP1R<n>_EL2
+ * ICH_LR<n>_EL2
+ * -----------------------------------------------------
+ */
+static void el2_sysregs_context_save_common(el2_sysregs_t *ctx)
+{
+ write_ctx_reg(ctx, CTX_ACTLR_EL2, read_actlr_el2());
+ write_ctx_reg(ctx, CTX_AFSR0_EL2, read_afsr0_el2());
+ write_ctx_reg(ctx, CTX_AFSR1_EL2, read_afsr1_el2());
+ write_ctx_reg(ctx, CTX_AMAIR_EL2, read_amair_el2());
+ write_ctx_reg(ctx, CTX_CNTHCTL_EL2, read_cnthctl_el2());
+ write_ctx_reg(ctx, CTX_CNTVOFF_EL2, read_cntvoff_el2());
+ write_ctx_reg(ctx, CTX_CPTR_EL2, read_cptr_el2());
+ if (CTX_INCLUDE_AARCH32_REGS) {
+ write_ctx_reg(ctx, CTX_DBGVCR32_EL2, read_dbgvcr32_el2());
+ }
+ write_ctx_reg(ctx, CTX_ELR_EL2, read_elr_el2());
+ write_ctx_reg(ctx, CTX_ESR_EL2, read_esr_el2());
+ write_ctx_reg(ctx, CTX_FAR_EL2, read_far_el2());
+ write_ctx_reg(ctx, CTX_HACR_EL2, read_hacr_el2());
+ write_ctx_reg(ctx, CTX_HCR_EL2, read_hcr_el2());
+ write_ctx_reg(ctx, CTX_HPFAR_EL2, read_hpfar_el2());
+ write_ctx_reg(ctx, CTX_HSTR_EL2, read_hstr_el2());
+ write_ctx_reg(ctx, CTX_ICC_SRE_EL2, read_icc_sre_el2());
+ write_ctx_reg(ctx, CTX_ICH_HCR_EL2, read_ich_hcr_el2());
+ write_ctx_reg(ctx, CTX_ICH_VMCR_EL2, read_ich_vmcr_el2());
+ write_ctx_reg(ctx, CTX_MAIR_EL2, read_mair_el2());
+ write_ctx_reg(ctx, CTX_MDCR_EL2, read_mdcr_el2());
+ write_ctx_reg(ctx, CTX_SCTLR_EL2, read_sctlr_el2());
+ write_ctx_reg(ctx, CTX_SPSR_EL2, read_spsr_el2());
+ write_ctx_reg(ctx, CTX_SP_EL2, read_sp_el2());
+ write_ctx_reg(ctx, CTX_TCR_EL2, read_tcr_el2());
+ write_ctx_reg(ctx, CTX_TPIDR_EL2, read_tpidr_el2());
+ write_ctx_reg(ctx, CTX_TTBR0_EL2, read_ttbr0_el2());
+ write_ctx_reg(ctx, CTX_VBAR_EL2, read_vbar_el2());
+ write_ctx_reg(ctx, CTX_VMPIDR_EL2, read_vmpidr_el2());
+ write_ctx_reg(ctx, CTX_VPIDR_EL2, read_vpidr_el2());
+ write_ctx_reg(ctx, CTX_VTCR_EL2, read_vtcr_el2());
+ write_ctx_reg(ctx, CTX_VTTBR_EL2, read_vttbr_el2());
+}
+
+static void el2_sysregs_context_restore_common(el2_sysregs_t *ctx)
+{
+ write_actlr_el2(read_ctx_reg(ctx, CTX_ACTLR_EL2));
+ write_afsr0_el2(read_ctx_reg(ctx, CTX_AFSR0_EL2));
+ write_afsr1_el2(read_ctx_reg(ctx, CTX_AFSR1_EL2));
+ write_amair_el2(read_ctx_reg(ctx, CTX_AMAIR_EL2));
+ write_cnthctl_el2(read_ctx_reg(ctx, CTX_CNTHCTL_EL2));
+ write_cntvoff_el2(read_ctx_reg(ctx, CTX_CNTVOFF_EL2));
+ write_cptr_el2(read_ctx_reg(ctx, CTX_CPTR_EL2));
+ if (CTX_INCLUDE_AARCH32_REGS) {
+ write_dbgvcr32_el2(read_ctx_reg(ctx, CTX_DBGVCR32_EL2));
+ }
+ write_elr_el2(read_ctx_reg(ctx, CTX_ELR_EL2));
+ write_esr_el2(read_ctx_reg(ctx, CTX_ESR_EL2));
+ write_far_el2(read_ctx_reg(ctx, CTX_FAR_EL2));
+ write_hacr_el2(read_ctx_reg(ctx, CTX_HACR_EL2));
+ write_hcr_el2(read_ctx_reg(ctx, CTX_HCR_EL2));
+ write_hpfar_el2(read_ctx_reg(ctx, CTX_HPFAR_EL2));
+ write_hstr_el2(read_ctx_reg(ctx, CTX_HSTR_EL2));
+ write_icc_sre_el2(read_ctx_reg(ctx, CTX_ICC_SRE_EL2));
+ write_ich_hcr_el2(read_ctx_reg(ctx, CTX_ICH_HCR_EL2));
+ write_ich_vmcr_el2(read_ctx_reg(ctx, CTX_ICH_VMCR_EL2));
+ write_mair_el2(read_ctx_reg(ctx, CTX_MAIR_EL2));
+ write_mdcr_el2(read_ctx_reg(ctx, CTX_MDCR_EL2));
+ write_sctlr_el2(read_ctx_reg(ctx, CTX_SCTLR_EL2));
+ write_spsr_el2(read_ctx_reg(ctx, CTX_SPSR_EL2));
+ write_sp_el2(read_ctx_reg(ctx, CTX_SP_EL2));
+ write_tcr_el2(read_ctx_reg(ctx, CTX_TCR_EL2));
+ write_tpidr_el2(read_ctx_reg(ctx, CTX_TPIDR_EL2));
+ write_ttbr0_el2(read_ctx_reg(ctx, CTX_TTBR0_EL2));
+ write_vbar_el2(read_ctx_reg(ctx, CTX_VBAR_EL2));
+ write_vmpidr_el2(read_ctx_reg(ctx, CTX_VMPIDR_EL2));
+ write_vpidr_el2(read_ctx_reg(ctx, CTX_VPIDR_EL2));
+ write_vtcr_el2(read_ctx_reg(ctx, CTX_VTCR_EL2));
+ write_vttbr_el2(read_ctx_reg(ctx, CTX_VTTBR_EL2));
+}
+
/*******************************************************************************
* Save EL2 sysreg context
******************************************************************************/
@@ -994,7 +1077,7 @@
el2_sysregs_context_save_common(el2_sysregs_ctx);
#if CTX_INCLUDE_MTE_REGS
- el2_sysregs_context_save_mte(el2_sysregs_ctx);
+ write_ctx_reg(el2_sysregs_ctx, CTX_TFSR_EL2, read_tfsr_el2());
#endif
if (is_feat_mpam_supported()) {
el2_sysregs_context_save_mpam(el2_sysregs_ctx);
@@ -1083,7 +1166,7 @@
el2_sysregs_context_restore_common(el2_sysregs_ctx);
#if CTX_INCLUDE_MTE_REGS
- el2_sysregs_context_restore_mte(el2_sysregs_ctx);
+ write_tfsr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TFSR_EL2));
#endif
if (is_feat_mpam_supported()) {
el2_sysregs_context_restore_mpam(el2_sysregs_ctx);
diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk
index a065039..964e0f9 100644
--- a/make_helpers/defaults.mk
+++ b/make_helpers/defaults.mk
@@ -508,3 +508,6 @@
# Check platform if cache management operations should be performed.
# Disabled by default.
CONDITIONAL_CMO := 0
+
+# By default, disable SPMD Logical partitions
+ENABLE_SPMD_LP := 0
diff --git a/plat/arm/board/fvp/fvp_spmd_logical_sp.c b/plat/arm/board/fvp/fvp_spmd_logical_sp.c
new file mode 100644
index 0000000..37b4466
--- /dev/null
+++ b/plat/arm/board/fvp/fvp_spmd_logical_sp.c
@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2023, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <common/debug.h>
+#include <services/el3_spmd_logical_sp.h>
+#include <services/ffa_svc.h>
+#include <smccc_helpers.h>
+
+#define SPMD_LP_PARTITION_ID SPMD_LP_ID_START
+#define SPMD_LP_UUID {0xe98e43ad, 0xb7db524f, 0x47a3bf57, 0x1588f4e3}
+
+/* SPMD Logical SP currently only supports sending direct message. */
+#define SPMD_PARTITION_PROPERTIES FFA_PARTITION_DIRECT_REQ_SEND
+
+#define SPMD_LP_MAX_SUPPORTED_SP 10
+static void fvp_get_partition_info(void)
+{
+ struct ffa_value ret = { 0 };
+ uint32_t target_uuid[4] = { 0 };
+ static struct ffa_partition_info_v1_1
+ part_info[SPMD_LP_MAX_SUPPORTED_SP] = { 0 };
+
+ uint16_t num_partitions = 0;
+
+ if (!spmd_el3_invoke_partition_info_get(target_uuid, 0, 0, &ret)) {
+ panic();
+ }
+
+ if (is_ffa_error(&ret)) {
+ panic();
+ }
+
+ num_partitions = ffa_partition_info_regs_get_last_idx(ret) + 1;
+ if (num_partitions > SPMD_LP_MAX_SUPPORTED_SP) {
+ panic();
+ }
+
+ INFO("Number of secure partitions = %d\n", num_partitions);
+
+ for (uint16_t i = 0; i < num_partitions; i++) {
+ INFO("***Start Partition***\n");
+ if (!ffa_partition_info_regs_get_part_info(ret, i, &part_info[i]))
+ panic();
+ INFO("\tPartition ID: 0x%x\n", part_info[i].ep_id);
+ INFO("\tvCPU count:0x%x\n", part_info[i].execution_ctx_count);
+ INFO("\tProperties: 0x%x\n", part_info[i].properties);
+ INFO("\tUUID: 0x%x 0x%x 0x%x 0x%x\n", part_info[i].uuid[0],
+ part_info[i].uuid[1], part_info[i].uuid[2],
+ part_info[i].uuid[3]);
+ INFO("***End Partition***\n");
+ }
+
+}
+
+static int32_t fvp_spmd_logical_partition_init(void)
+{
+ INFO("FVP SPMD LSP: Init function called.\n");
+
+ fvp_get_partition_info();
+ return 0;
+}
+
+/*
+ * Platform specific SMC handler used to translate SIP SMCs or other platform
+ * specific SMCs into FF-A direct messages.
+ */
+uintptr_t plat_spmd_logical_sp_smc_handler(unsigned int smc_fid,
+ u_register_t x1,
+ u_register_t x2,
+ u_register_t x3,
+ u_register_t x4,
+ void *cookie,
+ void *handle,
+ u_register_t flags)
+{
+ struct ffa_value retval = { 0 };
+ uint64_t send_recv_id = SPMD_LP_PARTITION_ID << 16 | 0x8001;
+
+ /*
+ * Forward the SMC as direct request.
+ */
+ if (!spmd_el3_ffa_msg_direct_req(send_recv_id, x2, x3, x4, handle, &retval)) {
+ panic();
+ }
+
+ SMC_RET8(handle, retval.func, retval.arg1, retval.arg2, retval.arg3,
+ retval.arg4, retval.arg5, retval.arg6, retval.arg7);
+}
+
+/* Register SPMD logical partition */
+DECLARE_SPMD_LOGICAL_PARTITION(
+ fvp_spmd_logical_partition,
+ fvp_spmd_logical_partition_init,/* Init Function */
+ SPMD_LP_PARTITION_ID, /* FF-A Partition ID */
+ SPMD_LP_UUID, /* UUID */
+ SPMD_PARTITION_PROPERTIES /* Partition Properties. */
+);
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index e790f92..6ac4e09 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -213,7 +213,8 @@
lib/cpus/aarch64/neoverse_n2.S \
lib/cpus/aarch64/neoverse_v1.S \
lib/cpus/aarch64/neoverse_e1.S \
- lib/cpus/aarch64/cortex_x2.S
+ lib/cpus/aarch64/cortex_x2.S \
+ lib/cpus/aarch64/cortex_gelas.S
endif
# AArch64/AArch32 cores
FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \
diff --git a/plat/arm/board/juno/platform.mk b/plat/arm/board/juno/platform.mk
index 19091f3..a00bf26 100644
--- a/plat/arm/board/juno/platform.mk
+++ b/plat/arm/board/juno/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2013-2023, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -63,6 +63,10 @@
ifneq (${ARCH}, aarch32)
override BL32_SOURCES =
endif
+else
+ ifeq (${ARCH}, aarch32)
+ $(error JUNO_AARCH32_EL3_RUNTIME has to be enabled to build BL32 for AArch32)
+ endif
endif
ifeq (${ARCH},aarch64)
diff --git a/plat/arm/common/arm_sip_svc.c b/plat/arm/common/arm_sip_svc.c
index 6af23a7..352d477 100644
--- a/plat/arm/common/arm_sip_svc.c
+++ b/plat/arm/common/arm_sip_svc.c
@@ -13,6 +13,9 @@
#include <lib/pmf/pmf.h>
#include <plat/arm/common/arm_sip_svc.h>
#include <plat/arm/common/plat_arm.h>
+#if ENABLE_SPMD_LP
+#include <services/el3_spmd_logical_sp.h>
+#endif
#include <tools_share/uuid.h>
/* ARM SiP Service UUID */
@@ -133,8 +136,13 @@
SMC_RET2(handle, ARM_SIP_SVC_VERSION_MAJOR, ARM_SIP_SVC_VERSION_MINOR);
default:
+#if ENABLE_SPMD_LP
+ return plat_spmd_logical_sp_smc_handler(smc_fid, x1, x2, x3, x4,
+ cookie, handle, flags);
+#else
WARN("Unimplemented ARM SiP Service Call: 0x%x \n", smc_fid);
SMC_RET1(handle, SMC_UNK);
+#endif
}
}
diff --git a/plat/qemu/common/common.mk b/plat/qemu/common/common.mk
new file mode 100644
index 0000000..b8b57d2
--- /dev/null
+++ b/plat/qemu/common/common.mk
@@ -0,0 +1,112 @@
+#
+# Copyright (c) 2023, Linaro Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+include lib/libfdt/libfdt.mk
+include common/fdt_wrappers.mk
+
+PLAT_INCLUDES := -Iinclude/plat/arm/common/ \
+ -I${PLAT_QEMU_COMMON_PATH}/include \
+ -I${PLAT_QEMU_PATH}/include \
+ -Iinclude/common/tbbr
+
+ifeq (${ARCH},aarch32)
+QEMU_CPU_LIBS := lib/cpus/${ARCH}/cortex_a15.S
+else
+QEMU_CPU_LIBS := lib/cpus/aarch64/aem_generic.S \
+ lib/cpus/aarch64/cortex_a53.S \
+ lib/cpus/aarch64/cortex_a57.S \
+ lib/cpus/aarch64/cortex_a72.S \
+ lib/cpus/aarch64/cortex_a76.S \
+ lib/cpus/aarch64/neoverse_n_common.S \
+ lib/cpus/aarch64/neoverse_n1.S \
+ lib/cpus/aarch64/neoverse_v1.S \
+ lib/cpus/aarch64/qemu_max.S
+
+PLAT_INCLUDES += -Iinclude/plat/arm/common/${ARCH}
+endif
+
+PLAT_BL_COMMON_SOURCES := ${PLAT_QEMU_COMMON_PATH}/qemu_common.c \
+ ${PLAT_QEMU_COMMON_PATH}/qemu_console.c \
+ drivers/arm/pl011/${ARCH}/pl011_console.S
+
+include lib/xlat_tables_v2/xlat_tables.mk
+PLAT_BL_COMMON_SOURCES += ${XLAT_TABLES_LIB_SRCS}
+
+ifneq ($(ENABLE_STACK_PROTECTOR), 0)
+ PLAT_BL_COMMON_SOURCES += ${PLAT_QEMU_COMMON_PATH}/qemu_stack_protector.c
+endif
+
+BL1_SOURCES += drivers/io/io_semihosting.c \
+ drivers/io/io_storage.c \
+ drivers/io/io_fip.c \
+ drivers/io/io_memmap.c \
+ lib/semihosting/semihosting.c \
+ lib/semihosting/${ARCH}/semihosting_call.S \
+ ${PLAT_QEMU_COMMON_PATH}/qemu_io_storage.c \
+ ${PLAT_QEMU_COMMON_PATH}/${ARCH}/plat_helpers.S \
+ ${PLAT_QEMU_COMMON_PATH}/qemu_bl1_setup.c \
+ ${QEMU_CPU_LIBS}
+
+BL2_SOURCES += drivers/io/io_semihosting.c \
+ drivers/io/io_storage.c \
+ drivers/io/io_fip.c \
+ drivers/io/io_memmap.c \
+ lib/semihosting/semihosting.c \
+ lib/semihosting/${ARCH}/semihosting_call.S \
+ ${PLAT_QEMU_COMMON_PATH}/qemu_io_storage.c \
+ ${PLAT_QEMU_COMMON_PATH}/${ARCH}/plat_helpers.S \
+ ${PLAT_QEMU_COMMON_PATH}/qemu_bl2_setup.c \
+ ${PLAT_QEMU_COMMON_PATH}/qemu_bl2_mem_params_desc.c \
+ ${PLAT_QEMU_COMMON_PATH}/qemu_image_load.c \
+ common/desc_image_load.c \
+ common/fdt_fixup.c
+
+BL31_SOURCES += ${QEMU_CPU_LIBS} \
+ lib/semihosting/semihosting.c \
+ lib/semihosting/${ARCH}/semihosting_call.S \
+ plat/common/plat_psci_common.c \
+ ${PLAT_QEMU_COMMON_PATH}/aarch64/plat_helpers.S \
+ ${PLAT_QEMU_COMMON_PATH}/qemu_bl31_setup.c \
+ common/fdt_fixup.c \
+ ${QEMU_GIC_SOURCES}
+
+# CPU flag enablement
+ifeq (${ARCH},aarch64)
+
+# Later QEMU versions support SME and SVE.
+# SPM_MM is not compatible with ENABLE_SVE_FOR_NS (build breaks)
+ifeq (${SPM_MM},1)
+ ENABLE_SVE_FOR_NS := 0
+ ENABLE_SME_FOR_NS := 0
+else
+ ENABLE_SVE_FOR_NS := 2
+ ENABLE_SME_FOR_NS := 2
+endif
+
+# QEMU will use the RNDR instruction for the stack protector canary.
+ENABLE_FEAT_RNG := 2
+
+# QEMU 7.2+ has support for FGT and Linux needs it enabled to boot on max
+ENABLE_FEAT_FGT := 2
+
+# Treating this as a memory-constrained port for now
+USE_COHERENT_MEM := 0
+
+# This can be overridden depending on CPU(s) used in the QEMU image
+HW_ASSISTED_COHERENCY := 1
+
+CTX_INCLUDE_AARCH32_REGS := 0
+ifeq (${CTX_INCLUDE_AARCH32_REGS}, 1)
+$(error "This is an AArch64-only port; CTX_INCLUDE_AARCH32_REGS must be disabled")
+endif
+
+# Pointer Authentication sources
+ifeq (${ENABLE_PAUTH}, 1)
+PLAT_BL_COMMON_SOURCES += plat/arm/common/aarch64/arm_pauth.c
+CTX_INCLUDE_PAUTH_REGS := 1
+endif
+
+endif
diff --git a/plat/qemu/qemu/platform.mk b/plat/qemu/qemu/platform.mk
index a10ab65..16e89c1 100644
--- a/plat/qemu/qemu/platform.mk
+++ b/plat/qemu/qemu/platform.mk
@@ -4,6 +4,14 @@
# SPDX-License-Identifier: BSD-3-Clause
#
+PLAT_QEMU_PATH := plat/qemu/qemu
+PLAT_QEMU_COMMON_PATH := plat/qemu/common
+
+SEPARATE_CODE_AND_RODATA := 1
+ENABLE_STACK_PROTECTOR := 0
+
+include plat/qemu/common/common.mk
+
# Use the GICv2 driver on QEMU by default
QEMU_USE_GIC_DRIVER := QEMU_GICV2
@@ -18,17 +26,6 @@
$(eval $(call add_define,ARMV7_SUPPORTS_VFP))
# Qemu expects a BL32 boot stage.
NEED_BL32 := yes
-else
-CTX_INCLUDE_AARCH32_REGS := 0
-ifeq (${CTX_INCLUDE_AARCH32_REGS}, 1)
-$(error "This is an AArch64-only port; CTX_INCLUDE_AARCH32_REGS must be disabled")
-endif
-
-# Treating this as a memory-constrained port for now
-USE_COHERENT_MEM := 0
-
-# This can be overridden depending on CPU(s) used in the QEMU image
-HW_ASSISTED_COHERENCY := 1
endif # ARMv7
ifeq (${SPD},opteed)
@@ -42,42 +39,10 @@
add-lib-optee := yes
endif
-include lib/libfdt/libfdt.mk
-
ifeq ($(NEED_BL32),yes)
$(eval $(call add_define,QEMU_LOAD_BL32))
endif
-PLAT_QEMU_PATH := plat/qemu/qemu
-PLAT_QEMU_COMMON_PATH := plat/qemu/common
-PLAT_INCLUDES := -Iinclude/plat/arm/common/ \
- -I${PLAT_QEMU_COMMON_PATH}/include \
- -I${PLAT_QEMU_PATH}/include \
- -Iinclude/common/tbbr
-
-ifeq (${ARM_ARCH_MAJOR},8)
-PLAT_INCLUDES += -Iinclude/plat/arm/common/${ARCH}
-
-QEMU_CPU_LIBS := lib/cpus/aarch64/aem_generic.S \
- lib/cpus/aarch64/cortex_a53.S \
- lib/cpus/aarch64/cortex_a57.S \
- lib/cpus/aarch64/cortex_a72.S \
- lib/cpus/aarch64/cortex_a76.S \
- lib/cpus/aarch64/neoverse_n_common.S \
- lib/cpus/aarch64/neoverse_n1.S \
- lib/cpus/aarch64/neoverse_v1.S \
- lib/cpus/aarch64/qemu_max.S
-else
-QEMU_CPU_LIBS := lib/cpus/${ARCH}/cortex_a15.S
-endif
-
-PLAT_BL_COMMON_SOURCES := ${PLAT_QEMU_COMMON_PATH}/qemu_common.c \
- ${PLAT_QEMU_COMMON_PATH}/qemu_console.c \
- drivers/arm/pl011/${ARCH}/pl011_console.S
-
-include lib/xlat_tables_v2/xlat_tables.mk
-PLAT_BL_COMMON_SOURCES += ${XLAT_TABLES_LIB_SRCS}
-
ifneq (${TRUSTED_BOARD_BOOT},0)
AUTH_SOURCES := drivers/auth/auth_mod.c \
@@ -150,42 +115,7 @@
include drivers/auth/mbedtls/mbedtls_crypto.mk
endif
-BL1_SOURCES += drivers/io/io_semihosting.c \
- drivers/io/io_storage.c \
- drivers/io/io_fip.c \
- drivers/io/io_memmap.c \
- lib/semihosting/semihosting.c \
- lib/semihosting/${ARCH}/semihosting_call.S \
- ${PLAT_QEMU_COMMON_PATH}/qemu_io_storage.c \
- ${PLAT_QEMU_COMMON_PATH}/${ARCH}/plat_helpers.S \
- ${PLAT_QEMU_COMMON_PATH}/qemu_bl1_setup.c \
- ${QEMU_CPU_LIBS}
-
-ifeq (${ARM_ARCH_MAJOR},8)
-BL1_SOURCES += lib/cpus/${ARCH}/aem_generic.S \
- lib/cpus/${ARCH}/cortex_a53.S \
- lib/cpus/${ARCH}/cortex_a57.S \
- lib/cpus/${ARCH}/cortex_a72.S \
- lib/cpus/${ARCH}/qemu_max.S \
-
-else
-BL1_SOURCES += lib/cpus/${ARCH}/cortex_a15.S
-endif
-
-BL2_SOURCES += drivers/io/io_semihosting.c \
- drivers/io/io_storage.c \
- drivers/io/io_fip.c \
- drivers/io/io_memmap.c \
- lib/semihosting/semihosting.c \
- lib/semihosting/${ARCH}/semihosting_call.S \
- ${PLAT_QEMU_COMMON_PATH}/qemu_io_storage.c \
- ${PLAT_QEMU_COMMON_PATH}/${ARCH}/plat_helpers.S \
- ${PLAT_QEMU_COMMON_PATH}/qemu_bl2_setup.c \
- ${PLAT_QEMU_COMMON_PATH}/qemu_bl2_mem_params_desc.c \
- ${PLAT_QEMU_COMMON_PATH}/qemu_image_load.c \
- common/fdt_fixup.c \
- common/fdt_wrappers.c \
- common/desc_image_load.c \
+BL2_SOURCES += ${FDT_WRAPPERS_SOURCES} \
common/uuid.c
ifeq ($(add-lib-optee),yes)
@@ -218,29 +148,16 @@
$(error "Incorrect GIC driver chosen for QEMU platform")
endif
-ifeq (${ARM_ARCH_MAJOR},8)
-BL31_SOURCES += ${QEMU_CPU_LIBS} \
- lib/semihosting/semihosting.c \
- lib/semihosting/${ARCH}/semihosting_call.S \
- plat/common/plat_psci_common.c \
- drivers/arm/pl061/pl061_gpio.c \
+ifeq (${ARCH},aarch64)
+BL31_SOURCES += drivers/arm/pl061/pl061_gpio.c \
drivers/gpio/gpio.c \
- ${PLAT_QEMU_COMMON_PATH}/qemu_pm.c \
- ${PLAT_QEMU_COMMON_PATH}/topology.c \
- ${PLAT_QEMU_COMMON_PATH}/aarch64/plat_helpers.S \
- ${PLAT_QEMU_COMMON_PATH}/qemu_bl31_setup.c \
- ${QEMU_GIC_SOURCES}
+ ${PLAT_QEMU_COMMON_PATH}/qemu_pm.c \
+ ${PLAT_QEMU_COMMON_PATH}/topology.c
ifeq (${SDEI_SUPPORT}, 1)
BL31_SOURCES += plat/qemu/common/qemu_sdei.c
endif
-# Pointer Authentication sources
-ifeq (${ENABLE_PAUTH}, 1)
-PLAT_BL_COMMON_SOURCES += plat/arm/common/aarch64/arm_pauth.c \
- lib/extensions/pauth/pauth_helpers.S
-endif
-
ifeq (${SPD},spmd)
BL31_SOURCES += plat/common/plat_spmd_manifest.c \
common/uuid.c \
@@ -280,12 +197,6 @@
$(eval $(call TOOL_ADD_PAYLOAD,${QEMU_TOS_FW_CONFIG},--tos-fw-config,${QEMU_TOS_FW_CONFIG}))
endif
-SEPARATE_CODE_AND_RODATA := 1
-ENABLE_STACK_PROTECTOR := 0
-ifneq ($(ENABLE_STACK_PROTECTOR), 0)
- PLAT_BL_COMMON_SOURCES += ${PLAT_QEMU_COMMON_PATH}/qemu_stack_protector.c
-endif
-
BL32_RAM_LOCATION := tdram
ifeq (${BL32_RAM_LOCATION}, tsram)
BL32_RAM_LOCATION_ID = SEC_SRAM_ID
@@ -306,15 +217,6 @@
ARM_PRELOADED_DTB_BASE := PLAT_QEMU_DT_BASE
$(eval $(call add_define,ARM_PRELOADED_DTB_BASE))
-# QEMU will use the RNDR instruction for the stack protector canary.
-ENABLE_FEAT_RNG := 2
-
-# Later QEMU versions support SME and SVE.
-ifneq (${ARCH},aarch32)
- ENABLE_SVE_FOR_NS := 2
- ENABLE_SME_FOR_NS := 2
-endif
-
qemu_fw.bios: bl1 fip
$(ECHO) " DD $@"
$(Q)cp ${BUILD_PLAT}/bl1.bin ${BUILD_PLAT}/$@
diff --git a/plat/qemu/qemu_sbsa/platform.mk b/plat/qemu/qemu_sbsa/platform.mk
index 3dfefd0..4a8df46 100644
--- a/plat/qemu/qemu_sbsa/platform.mk
+++ b/plat/qemu/qemu_sbsa/platform.mk
@@ -4,11 +4,17 @@
# SPDX-License-Identifier: BSD-3-Clause
#
-include common/fdt_wrappers.mk
+PLAT_QEMU_PATH := plat/qemu/qemu_sbsa
+PLAT_QEMU_COMMON_PATH := plat/qemu/common
+
+MULTI_CONSOLE_API := 1
+CRASH_REPORTING := 1
-CRASH_REPORTING := 1
+# Disable the PSCI platform compatibility layer
+ENABLE_PLAT_COMPAT := 0
-include lib/libfdt/libfdt.mk
+SEPARATE_CODE_AND_RODATA := 1
+ENABLE_STACK_PROTECTOR := 0
ifeq (${SPM_MM},1)
NEED_BL32 := yes
@@ -16,75 +22,16 @@
GICV2_G0_FOR_EL3 := 1
endif
+include plat/qemu/common/common.mk
+
# Enable new version of image loading on QEMU platforms
LOAD_IMAGE_V2 := 1
-CTX_INCLUDE_AARCH32_REGS := 0
-ifeq (${CTX_INCLUDE_AARCH32_REGS}, 1)
-$(error "This is an AArch64-only port; CTX_INCLUDE_AARCH32_REGS must be disabled")
-endif
-
ifeq ($(NEED_BL32),yes)
$(eval $(call add_define,QEMU_LOAD_BL32))
endif
-PLAT_QEMU_PATH := plat/qemu/qemu_sbsa
-PLAT_QEMU_COMMON_PATH := plat/qemu/common
-PLAT_INCLUDES := -Iinclude/plat/arm/common/ \
- -I${PLAT_QEMU_COMMON_PATH}/include \
- -I${PLAT_QEMU_PATH}/include \
- -Iinclude/common/tbbr
-
-PLAT_INCLUDES += -Iinclude/plat/arm/common/${ARCH}
-
-PLAT_BL_COMMON_SOURCES := ${PLAT_QEMU_COMMON_PATH}/qemu_common.c \
- ${PLAT_QEMU_COMMON_PATH}/qemu_console.c \
- drivers/arm/pl011/${ARCH}/pl011_console.S
-
-# Treating this as a memory-constrained port for now
-USE_COHERENT_MEM := 0
-
-# This can be overridden depending on CPU(s) used in the QEMU image
-HW_ASSISTED_COHERENCY := 1
-
-QEMU_CPU_LIBS := lib/cpus/aarch64/cortex_a57.S \
- lib/cpus/aarch64/cortex_a72.S \
- lib/cpus/aarch64/neoverse_n_common.S \
- lib/cpus/aarch64/neoverse_n1.S \
- lib/cpus/aarch64/neoverse_v1.S \
- lib/cpus/aarch64/qemu_max.S
-
-include lib/xlat_tables_v2/xlat_tables.mk
-PLAT_BL_COMMON_SOURCES += ${XLAT_TABLES_LIB_SRCS}
-
-BL1_SOURCES += drivers/io/io_semihosting.c \
- drivers/io/io_storage.c \
- drivers/io/io_fip.c \
- drivers/io/io_memmap.c \
- lib/semihosting/semihosting.c \
- lib/semihosting/${ARCH}/semihosting_call.S \
- ${PLAT_QEMU_COMMON_PATH}/qemu_io_storage.c \
- ${PLAT_QEMU_COMMON_PATH}/${ARCH}/plat_helpers.S \
- ${PLAT_QEMU_COMMON_PATH}/qemu_bl1_setup.c
-
-BL1_SOURCES += ${QEMU_CPU_LIBS}
-
-BL2_SOURCES += drivers/io/io_semihosting.c \
- drivers/io/io_storage.c \
- drivers/io/io_fip.c \
- drivers/io/io_memmap.c \
- lib/semihosting/semihosting.c \
- lib/semihosting/${ARCH}/semihosting_call.S \
- ${PLAT_QEMU_COMMON_PATH}/qemu_io_storage.c \
- ${PLAT_QEMU_COMMON_PATH}/${ARCH}/plat_helpers.S \
- ${PLAT_QEMU_COMMON_PATH}/qemu_bl2_setup.c \
- common/fdt_fixup.c \
- $(LIBFDT_SRCS)
-ifeq (${LOAD_IMAGE_V2},1)
-BL2_SOURCES += ${PLAT_QEMU_COMMON_PATH}/qemu_bl2_mem_params_desc.c \
- ${PLAT_QEMU_COMMON_PATH}/qemu_image_load.c \
- common/desc_image_load.c
-endif
+BL2_SOURCES += $(LIBFDT_SRCS)
# Include GICv3 driver files
include drivers/arm/gic/v3/gicv3.mk
@@ -92,18 +39,10 @@
QEMU_GIC_SOURCES := ${GICV3_SOURCES} \
plat/common/plat_gicv3.c
-BL31_SOURCES += ${QEMU_CPU_LIBS} \
- lib/semihosting/semihosting.c \
- lib/semihosting/${ARCH}/semihosting_call.S \
- plat/common/plat_psci_common.c \
- ${PLAT_QEMU_PATH}/sbsa_gic.c \
+BL31_SOURCES += ${PLAT_QEMU_PATH}/sbsa_gic.c \
${PLAT_QEMU_PATH}/sbsa_pm.c \
${PLAT_QEMU_PATH}/sbsa_sip_svc.c \
- ${PLAT_QEMU_PATH}/sbsa_topology.c \
- ${PLAT_QEMU_COMMON_PATH}/aarch64/plat_helpers.S \
- ${PLAT_QEMU_COMMON_PATH}/qemu_bl31_setup.c \
- common/fdt_fixup.c \
- ${QEMU_GIC_SOURCES}
+ ${PLAT_QEMU_PATH}/sbsa_topology.c
BL31_SOURCES += ${FDT_WRAPPERS_SOURCES}
@@ -111,17 +50,6 @@
BL31_SOURCES += ${PLAT_QEMU_COMMON_PATH}/qemu_spm.c
endif
-SEPARATE_CODE_AND_RODATA := 1
-ENABLE_STACK_PROTECTOR := 0
-ifneq ($(ENABLE_STACK_PROTECTOR), 0)
- PLAT_BL_COMMON_SOURCES += ${PLAT_QEMU_COMMON_PATH}/qemu_stack_protector.c
-endif
-
-MULTI_CONSOLE_API := 1
-
-# Disable the PSCI platform compatibility layer
-ENABLE_PLAT_COMPAT := 0
-
# Use known base for UEFI if not given from command line
# By default BL33 is at FLASH1 base
PRELOADED_BL33_BASE ?= 0x10000000
@@ -137,10 +65,3 @@
ARM_PRELOADED_DTB_BASE := PLAT_QEMU_DT_BASE
$(eval $(call add_define,ARM_PRELOADED_DTB_BASE))
-
-# Later QEMU versions support SME and SVE.
-ENABLE_SVE_FOR_NS := 2
-ENABLE_SME_FOR_NS := 2
-
-# QEMU 7.2+ has support for FGT and Linux needs it enabled to boot on max
-ENABLE_FEAT_FGT := 2
diff --git a/plat/xilinx/versal_net/pm_service/pm_client.c b/plat/xilinx/versal_net/pm_service/pm_client.c
index 626611c..cff400c 100644
--- a/plat/xilinx/versal_net/pm_service/pm_client.c
+++ b/plat/xilinx/versal_net/pm_service/pm_client.c
@@ -321,15 +321,9 @@
isb();
- /* Clear power down interrupt status before enabling */
- mmio_write_32(APU_PCIL_CORE_X_ISR_POWER_REG(cpu_id),
- APU_PCIL_CORE_X_ISR_POWER_MASK);
/* Enable power down interrupt */
mmio_write_32(APU_PCIL_CORE_X_IEN_POWER_REG(cpu_id),
APU_PCIL_CORE_X_IEN_POWER_MASK);
- /* Clear wakeup interrupt status before enabling */
- mmio_write_32(APU_PCIL_CORE_X_ISR_WAKE_REG(cpu_id),
- APU_PCIL_CORE_X_ISR_WAKE_MASK);
/* Enable wake interrupt */
mmio_write_32(APU_PCIL_CORE_X_IEN_WAKE_REG(cpu_id),
APU_PCIL_CORE_X_IEN_WAKE_MASK);
@@ -383,9 +377,6 @@
/* Disabled power down interrupt */
mmio_write_32(APU_PCIL_CORE_X_IDS_POWER_REG(cpuid),
APU_PCIL_CORE_X_IDS_POWER_MASK);
- /* Clear wakeup interrupt status before disabling */
- mmio_write_32(APU_PCIL_CORE_X_ISR_WAKE_REG(cpuid),
- APU_PCIL_CORE_X_ISR_WAKE_MASK);
/* Disable wake interrupt */
mmio_write_32(APU_PCIL_CORE_X_IDS_WAKE_REG(cpuid),
APU_PCIL_CORE_X_IDS_WAKE_MASK);
diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_clock.c b/plat/xilinx/zynqmp/pm_service/pm_api_clock.c
index 2041541..9682e59 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_api_clock.c
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_clock.c
@@ -2458,7 +2458,7 @@
if (clock_id == CLK_MAX) {
memcpy(name, END_OF_CLK, sizeof(END_OF_CLK) > CLK_NAME_LEN ?
CLK_NAME_LEN : sizeof(END_OF_CLK));
- } else if (!pm_clock_valid(clock_id)) {
+ } else if ((clock_id > CLK_MAX) || (!pm_clock_valid(clock_id))) {
memset(name, 0, CLK_NAME_LEN);
} else if (clock_id < CLK_MAX_OUTPUT_CLK) {
memcpy(name, clocks[clock_id].name, CLK_NAME_LEN);
diff --git a/services/std_svc/spm/el3_spmc/spmc.h b/services/std_svc/spm/el3_spmc/spmc.h
index 13875b9..48644ac 100644
--- a/services/std_svc/spm/el3_spmc/spmc.h
+++ b/services/std_svc/spm/el3_spmc/spmc.h
@@ -213,30 +213,6 @@
uint32_t ffa_version;
};
-/**
- * Holds information returned for each partition by the FFA_PARTITION_INFO_GET
- * interface.
- */
-struct ffa_partition_info_v1_0 {
- uint16_t ep_id;
- uint16_t execution_ctx_count;
- uint32_t properties;
-};
-
-/* Extended structure for v1.1. */
-struct ffa_partition_info_v1_1 {
- uint16_t ep_id;
- uint16_t execution_ctx_count;
- uint32_t properties;
- uint32_t uuid[4];
-};
-
-/* FF-A Partition Info Get related macros. */
-#define FFA_PARTITION_INFO_GET_PROPERTIES_V1_0_MASK U(0x7)
-#define FFA_PARTITION_INFO_GET_EXEC_STATE_SHIFT U(8)
-#define FFA_PARTITION_INFO_GET_AARCH32_STATE U(0)
-#define FFA_PARTITION_INFO_GET_AARCH64_STATE U(1)
-
/* Reference to power management hooks */
extern const spd_pm_ops_t spmc_pm;
diff --git a/services/std_svc/spmd/spmd.mk b/services/std_svc/spmd/spmd.mk
index 6f451c8..72376f7 100644
--- a/services/std_svc/spmd/spmd.mk
+++ b/services/std_svc/spmd/spmd.mk
@@ -15,7 +15,18 @@
SPMD_SOURCES += $(addprefix services/std_svc/spmd/, \
${ARCH}/spmd_helpers.S \
spmd_pm.c \
- spmd_main.c)
+ spmd_main.c \
+ spmd_logical_sp.c)
+
+# Specify platform specific SPMD logical partition implementation.
+SPMD_LP_SOURCES := $(wildcard $(addprefix ${PLAT_DIR}/, \
+ ${PLAT}_spmd_logical_sp*.c))
+
+ifeq (${ENABLE_SPMD_LP}, 1)
+ifneq ($(wildcard $(SPMD_LP_SOURCES)),)
+SPMD_SOURCES += $(SPMD_LP_SOURCES)
+endif
+endif
# Let the top-level Makefile know that we intend to include a BL32 image
NEED_BL32 := yes
diff --git a/services/std_svc/spmd/spmd_logical_sp.c b/services/std_svc/spmd/spmd_logical_sp.c
new file mode 100644
index 0000000..964b36b
--- /dev/null
+++ b/services/std_svc/spmd/spmd_logical_sp.c
@@ -0,0 +1,742 @@
+/*
+ * Copyright (c) 2023, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <errno.h>
+#include <string.h>
+#include "spmd_private.h"
+
+#include <common/debug.h>
+#include <common/uuid.h>
+#include <lib/el3_runtime/context_mgmt.h>
+#include <services/el3_spmd_logical_sp.h>
+#include <services/spmc_svc.h>
+#include <smccc_helpers.h>
+
+
+/*
+ * Maximum ffa_partition_info entries that can be returned by an invocation
+ * of FFA_PARTITION_INFO_GET_REGS_64 is size in bytes, of available
+ * registers/args in struct ffa_value divided by size of struct
+ * ffa_partition_info. For this ABI, arg3-arg17 in ffa_value can be used, i.e.
+ * 15 uint64_t fields. For FF-A v1.1, this value should be 5.
+ */
+#define MAX_INFO_REGS_ENTRIES_PER_CALL \
+ (uint8_t)((15 * sizeof(uint64_t)) / \
+ sizeof(struct ffa_partition_info_v1_1))
+CASSERT(MAX_INFO_REGS_ENTRIES_PER_CALL == 5, assert_too_many_info_reg_entries);
+
+#if ENABLE_SPMD_LP
+static bool is_spmd_lp_inited;
+static bool is_spmc_inited;
+
+/*
+ * Helper function to obtain the array storing the EL3
+ * SPMD Logical Partition descriptors.
+ */
+static struct spmd_lp_desc *get_spmd_el3_lp_array(void)
+{
+ return (struct spmd_lp_desc *) SPMD_LP_DESCS_START;
+}
+
+/*******************************************************************************
+ * Validate any logical partition descriptors before we initialize.
+ * Initialization of said partitions will be taken care of during SPMD boot.
+ ******************************************************************************/
+static int el3_spmd_sp_desc_validate(struct spmd_lp_desc *lp_array)
+{
+ /* Check the array bounds are valid. */
+ assert(SPMD_LP_DESCS_END > SPMD_LP_DESCS_START);
+
+ /*
+ * No support for SPMD logical partitions when SPMC is at EL3.
+ */
+ assert(!is_spmc_at_el3());
+
+ /* If no SPMD logical partitions are implemented then simply bail out. */
+ if (SPMD_LP_DESCS_COUNT == 0U) {
+ return -1;
+ }
+
+ for (uint32_t index = 0U; index < SPMD_LP_DESCS_COUNT; index++) {
+ struct spmd_lp_desc *lp_desc = &lp_array[index];
+
+ /* Validate our logical partition descriptors. */
+ if (lp_desc == NULL) {
+ ERROR("Invalid SPMD Logical SP Descriptor\n");
+ return -EINVAL;
+ }
+
+ /*
+ * Ensure the ID follows the convention to indicate it resides
+ * in the secure world.
+ */
+ if (!ffa_is_secure_world_id(lp_desc->sp_id)) {
+ ERROR("Invalid SPMD Logical SP ID (0x%x)\n",
+ lp_desc->sp_id);
+ return -EINVAL;
+ }
+
+ /* Ensure SPMD logical partition is in valid range. */
+ if (!is_spmd_lp_id(lp_desc->sp_id)) {
+ ERROR("Invalid SPMD Logical Partition ID (0x%x)\n",
+ lp_desc->sp_id);
+ return -EINVAL;
+ }
+
+ /* Ensure the UUID is not the NULL UUID. */
+ if (lp_desc->uuid[0] == 0 && lp_desc->uuid[1] == 0 &&
+ lp_desc->uuid[2] == 0 && lp_desc->uuid[3] == 0) {
+ ERROR("Invalid UUID for SPMD Logical SP (0x%x)\n",
+ lp_desc->sp_id);
+ return -EINVAL;
+ }
+
+ /* Ensure init function callback is registered. */
+ if (lp_desc->init == NULL) {
+ ERROR("Missing init function for Logical SP(0x%x)\n",
+ lp_desc->sp_id);
+ return -EINVAL;
+ }
+
+ /* Ensure that SPMD LP only supports sending direct requests. */
+ if (lp_desc->properties != FFA_PARTITION_DIRECT_REQ_SEND) {
+ ERROR("Invalid SPMD logical partition properties (0x%x)\n",
+ lp_desc->properties);
+ return -EINVAL;
+ }
+
+ /* Ensure that all partition IDs are unique. */
+ for (uint32_t inner_idx = index + 1;
+ inner_idx < SPMD_LP_DESCS_COUNT; inner_idx++) {
+ if (lp_desc->sp_id == lp_array[inner_idx].sp_id) {
+ ERROR("Duplicate SPMD logical SP ID Detected (0x%x)\n",
+ lp_desc->sp_id);
+ return -EINVAL;
+ }
+ }
+ }
+ return 0;
+}
+
+static void spmd_encode_ffa_error(struct ffa_value *retval, int32_t error_code)
+{
+ retval->func = FFA_ERROR;
+ retval->arg1 = FFA_TARGET_INFO_MBZ;
+ retval->arg2 = (uint32_t)error_code;
+ retval->arg3 = FFA_TARGET_INFO_MBZ;
+ retval->arg4 = FFA_TARGET_INFO_MBZ;
+ retval->arg5 = FFA_TARGET_INFO_MBZ;
+ retval->arg6 = FFA_TARGET_INFO_MBZ;
+ retval->arg7 = FFA_TARGET_INFO_MBZ;
+}
+
+static void spmd_build_direct_message_req(spmd_spm_core_context_t *ctx,
+ uint64_t x1, uint64_t x2,
+ uint64_t x3, uint64_t x4)
+{
+ gp_regs_t *gpregs = get_gpregs_ctx(&ctx->cpu_ctx);
+
+ write_ctx_reg(gpregs, CTX_GPREG_X0, FFA_MSG_SEND_DIRECT_REQ_SMC32);
+ write_ctx_reg(gpregs, CTX_GPREG_X1, x1);
+ write_ctx_reg(gpregs, CTX_GPREG_X2, x2);
+ write_ctx_reg(gpregs, CTX_GPREG_X3, x3);
+ write_ctx_reg(gpregs, CTX_GPREG_X4, x4);
+ write_ctx_reg(gpregs, CTX_GPREG_X5, 0U);
+ write_ctx_reg(gpregs, CTX_GPREG_X6, 0U);
+ write_ctx_reg(gpregs, CTX_GPREG_X7, 0U);
+}
+
+static void spmd_encode_ctx_to_ffa_value(spmd_spm_core_context_t *ctx,
+ struct ffa_value *retval)
+{
+ gp_regs_t *gpregs = get_gpregs_ctx(&ctx->cpu_ctx);
+
+ retval->func = read_ctx_reg(gpregs, CTX_GPREG_X0);
+ retval->arg1 = read_ctx_reg(gpregs, CTX_GPREG_X1);
+ retval->arg2 = read_ctx_reg(gpregs, CTX_GPREG_X2);
+ retval->arg3 = read_ctx_reg(gpregs, CTX_GPREG_X3);
+ retval->arg4 = read_ctx_reg(gpregs, CTX_GPREG_X4);
+ retval->arg5 = read_ctx_reg(gpregs, CTX_GPREG_X5);
+ retval->arg6 = read_ctx_reg(gpregs, CTX_GPREG_X6);
+ retval->arg7 = read_ctx_reg(gpregs, CTX_GPREG_X7);
+ retval->arg8 = read_ctx_reg(gpregs, CTX_GPREG_X8);
+ retval->arg9 = read_ctx_reg(gpregs, CTX_GPREG_X9);
+ retval->arg10 = read_ctx_reg(gpregs, CTX_GPREG_X10);
+ retval->arg11 = read_ctx_reg(gpregs, CTX_GPREG_X11);
+ retval->arg12 = read_ctx_reg(gpregs, CTX_GPREG_X12);
+ retval->arg13 = read_ctx_reg(gpregs, CTX_GPREG_X13);
+ retval->arg14 = read_ctx_reg(gpregs, CTX_GPREG_X14);
+ retval->arg15 = read_ctx_reg(gpregs, CTX_GPREG_X15);
+ retval->arg16 = read_ctx_reg(gpregs, CTX_GPREG_X16);
+ retval->arg17 = read_ctx_reg(gpregs, CTX_GPREG_X17);
+}
+
+static void spmd_logical_sp_set_dir_req_ongoing(spmd_spm_core_context_t *ctx)
+{
+ ctx->spmd_lp_sync_req_ongoing |= SPMD_LP_FFA_DIR_REQ_ONGOING;
+}
+
+static void spmd_logical_sp_reset_dir_req_ongoing(spmd_spm_core_context_t *ctx)
+{
+ ctx->spmd_lp_sync_req_ongoing &= ~SPMD_LP_FFA_DIR_REQ_ONGOING;
+}
+
+static void spmd_build_ffa_info_get_regs(spmd_spm_core_context_t *ctx,
+ const uint32_t uuid[4],
+ const uint16_t start_index,
+ const uint16_t tag)
+{
+ gp_regs_t *gpregs = get_gpregs_ctx(&ctx->cpu_ctx);
+
+ uint64_t arg1 = (uint64_t)uuid[1] << 32 | uuid[0];
+ uint64_t arg2 = (uint64_t)uuid[3] << 32 | uuid[2];
+ uint64_t arg3 = start_index | (uint64_t)tag << 16;
+
+ write_ctx_reg(gpregs, CTX_GPREG_X0, FFA_PARTITION_INFO_GET_REGS_SMC64);
+ write_ctx_reg(gpregs, CTX_GPREG_X1, arg1);
+ write_ctx_reg(gpregs, CTX_GPREG_X2, arg2);
+ write_ctx_reg(gpregs, CTX_GPREG_X3, arg3);
+ write_ctx_reg(gpregs, CTX_GPREG_X4, 0U);
+ write_ctx_reg(gpregs, CTX_GPREG_X5, 0U);
+ write_ctx_reg(gpregs, CTX_GPREG_X6, 0U);
+ write_ctx_reg(gpregs, CTX_GPREG_X7, 0U);
+ write_ctx_reg(gpregs, CTX_GPREG_X8, 0U);
+ write_ctx_reg(gpregs, CTX_GPREG_X9, 0U);
+ write_ctx_reg(gpregs, CTX_GPREG_X10, 0U);
+ write_ctx_reg(gpregs, CTX_GPREG_X11, 0U);
+ write_ctx_reg(gpregs, CTX_GPREG_X12, 0U);
+ write_ctx_reg(gpregs, CTX_GPREG_X13, 0U);
+ write_ctx_reg(gpregs, CTX_GPREG_X14, 0U);
+ write_ctx_reg(gpregs, CTX_GPREG_X15, 0U);
+ write_ctx_reg(gpregs, CTX_GPREG_X16, 0U);
+ write_ctx_reg(gpregs, CTX_GPREG_X17, 0U);
+}
+
+static void spmd_logical_sp_set_info_regs_ongoing(spmd_spm_core_context_t *ctx)
+{
+ ctx->spmd_lp_sync_req_ongoing |= SPMD_LP_FFA_INFO_GET_REG_ONGOING;
+}
+
+static void spmd_logical_sp_reset_info_regs_ongoing(
+ spmd_spm_core_context_t *ctx)
+{
+ ctx->spmd_lp_sync_req_ongoing &= ~SPMD_LP_FFA_INFO_GET_REG_ONGOING;
+}
+
+static void spmd_fill_lp_info_array(
+ struct ffa_partition_info_v1_1 (*partitions)[EL3_SPMD_MAX_NUM_LP],
+ uint32_t uuid[4], uint16_t *lp_count_out)
+{
+ uint16_t lp_count = 0;
+ struct spmd_lp_desc *lp_array;
+ bool uuid_is_null = is_null_uuid(uuid);
+
+ if (SPMD_LP_DESCS_COUNT == 0U) {
+ *lp_count_out = 0;
+ return;
+ }
+
+ lp_array = get_spmd_el3_lp_array();
+ for (uint16_t index = 0; index < SPMD_LP_DESCS_COUNT; ++index) {
+ struct spmd_lp_desc *lp = &lp_array[index];
+
+ if (uuid_is_null || uuid_match(uuid, lp->uuid)) {
+ uint16_t array_index = lp_count;
+
+ ++lp_count;
+
+ (*partitions)[array_index].ep_id = lp->sp_id;
+ (*partitions)[array_index].execution_ctx_count = 1;
+ (*partitions)[array_index].properties = lp->properties;
+ (*partitions)[array_index].properties |=
+ (FFA_PARTITION_INFO_GET_AARCH64_STATE <<
+ FFA_PARTITION_INFO_GET_EXEC_STATE_SHIFT);
+ if (uuid_is_null) {
+ memcpy(&((*partitions)[array_index].uuid),
+ &lp->uuid, sizeof(lp->uuid));
+ }
+ }
+ }
+
+ *lp_count_out = lp_count;
+}
+
+static inline void spmd_pack_lp_count_props(
+ uint64_t *xn, uint16_t ep_id, uint16_t vcpu_count,
+ uint32_t properties)
+{
+ *xn = (uint64_t)ep_id;
+ *xn |= (uint64_t)vcpu_count << 16;
+ *xn |= (uint64_t)properties << 32;
+}
+
+static inline void spmd_pack_lp_uuid(uint64_t *xn_1, uint64_t *xn_2,
+ uint32_t uuid[4])
+{
+ *xn_1 = (uint64_t)uuid[0];
+ *xn_1 |= (uint64_t)uuid[1] << 32;
+ *xn_2 = (uint64_t)uuid[2];
+ *xn_2 |= (uint64_t)uuid[3] << 32;
+}
+#endif
+
+/*
+ * Initialize SPMD logical partitions. This function assumes that it is called
+ * only after the SPMC has successfully initialized.
+ */
+int32_t spmd_logical_sp_init(void)
+{
+#if ENABLE_SPMD_LP
+ int32_t rc = 0;
+ struct spmd_lp_desc *spmd_lp_descs;
+
+ assert(SPMD_LP_DESCS_COUNT <= EL3_SPMD_MAX_NUM_LP);
+
+ if (is_spmd_lp_inited == true) {
+ return 0;
+ }
+
+ if (is_spmc_inited == false) {
+ return -1;
+ }
+
+ spmd_lp_descs = get_spmd_el3_lp_array();
+
+ /* Perform initial validation of the SPMD Logical Partitions. */
+ rc = el3_spmd_sp_desc_validate(spmd_lp_descs);
+ if (rc != 0) {
+ ERROR("Logical SPMD Partition validation failed!\n");
+ return rc;
+ }
+
+ VERBOSE("SPMD Logical Secure Partition init start.\n");
+ for (unsigned int i = 0U; i < SPMD_LP_DESCS_COUNT; i++) {
+ rc = spmd_lp_descs[i].init();
+ if (rc != 0) {
+ ERROR("SPMD Logical SP (0x%x) failed to initialize\n",
+ spmd_lp_descs[i].sp_id);
+ return rc;
+ }
+ VERBOSE("SPMD Logical SP (0x%x) Initialized\n",
+ spmd_lp_descs[i].sp_id);
+ }
+
+ INFO("SPMD Logical Secure Partition init completed.\n");
+ if (rc == 0) {
+ is_spmd_lp_inited = true;
+ }
+ return rc;
+#else
+ return 0;
+#endif
+}
+
+void spmd_logical_sp_set_spmc_initialized(void)
+{
+#if ENABLE_SPMD_LP
+ is_spmc_inited = true;
+#endif
+}
+
+void spmd_logical_sp_set_spmc_failure(void)
+{
+#if ENABLE_SPMD_LP
+ is_spmc_inited = false;
+#endif
+}
+
+/*
+ * This function takes an ffa_value structure populated with partition
+ * information from an FFA_PARTITION_INFO_GET_REGS ABI call, extracts
+ * the values and writes it into a ffa_partition_info_v1_1 structure for
+ * other code to consume.
+ */
+bool ffa_partition_info_regs_get_part_info(
+ struct ffa_value args, uint8_t idx,
+ struct ffa_partition_info_v1_1 *partition_info)
+{
+ uint64_t *arg_ptrs;
+ uint64_t info, uuid_lo, uuid_high;
+
+ /*
+ * Each partition information is encoded in 3 registers, so there can be
+ * a maximum of 5 entries.
+ */
+ if (idx >= 5 || partition_info == NULL) {
+ return false;
+ }
+
+ /*
+ * List of pointers to args in return value. arg0/func encodes ff-a
+ * function, arg1 is reserved, arg2 encodes indices. arg3 and greater
+ * values reflect partition properties.
+ */
+ arg_ptrs = (uint64_t *)&args + ((idx * 3) + 3);
+ info = *arg_ptrs;
+
+ arg_ptrs++;
+ uuid_lo = *arg_ptrs;
+
+ arg_ptrs++;
+ uuid_high = *arg_ptrs;
+
+ partition_info->ep_id = (uint16_t)(info & 0xFFFFU);
+ partition_info->execution_ctx_count = (uint16_t)((info >> 16) & 0xFFFFU);
+ partition_info->properties = (uint32_t)(info >> 32);
+ partition_info->uuid[0] = (uint32_t)(uuid_lo & 0xFFFFFFFFU);
+ partition_info->uuid[1] = (uint32_t)((uuid_lo >> 32) & 0xFFFFFFFFU);
+ partition_info->uuid[2] = (uint32_t)(uuid_high & 0xFFFFFFFFU);
+ partition_info->uuid[3] = (uint32_t)((uuid_high >> 32) & 0xFFFFFFFFU);
+
+ return true;
+}
+
+/*
+ * This function is called by the SPMD in response to
+ * an FFA_PARTITION_INFO_GET_REG ABI invocation by the SPMC. Secure partitions
+ * are allowed to discover the presence of EL3 SPMD logical partitions by
+ * invoking the aforementioned ABI and this function populates the required
+ * information about EL3 SPMD logical partitions.
+ */
+uint64_t spmd_el3_populate_logical_partition_info(void *handle, uint64_t x1,
+ uint64_t x2, uint64_t x3)
+{
+#if ENABLE_SPMD_LP
+ uint32_t target_uuid[4] = { 0 };
+ uint32_t w0;
+ uint32_t w1;
+ uint32_t w2;
+ uint32_t w3;
+ uint16_t start_index;
+ uint16_t tag;
+ static struct ffa_partition_info_v1_1 partitions[EL3_SPMD_MAX_NUM_LP];
+ uint16_t lp_count = 0;
+ uint16_t max_idx = 0;
+ uint16_t curr_idx = 0;
+ uint8_t num_entries_to_ret = 0;
+ struct ffa_value ret = { 0 };
+ uint64_t *arg_ptrs = (uint64_t *)&ret + 3;
+
+ w0 = (uint32_t)(x1 & 0xFFFFFFFFU);
+ w1 = (uint32_t)(x1 >> 32);
+ w2 = (uint32_t)(x2 & 0xFFFFFFFFU);
+ w3 = (uint32_t)(x2 >> 32);
+
+ target_uuid[0] = w0;
+ target_uuid[1] = w1;
+ target_uuid[2] = w2;
+ target_uuid[3] = w3;
+
+ start_index = (uint16_t)(x3 & 0xFFFFU);
+ tag = (uint16_t)((x3 >> 16) & 0xFFFFU);
+
+ assert(handle == cm_get_context(SECURE));
+
+ if (tag != 0) {
+ VERBOSE("Tag is not 0. Cannot return partition info.\n");
+ return spmd_ffa_error_return(handle, FFA_ERROR_RETRY);
+ }
+
+ memset(&partitions, 0, sizeof(partitions));
+
+ spmd_fill_lp_info_array(&partitions, target_uuid, &lp_count);
+
+ if (lp_count == 0) {
+ VERBOSE("No SPDM EL3 logical partitions exist.\n");
+ return spmd_ffa_error_return(handle, FFA_ERROR_NOT_SUPPORTED);
+ }
+
+ if (start_index >= lp_count) {
+ VERBOSE("start_index = %d, lp_count = %d (start index must be"
+ " less than partition count.\n",
+ start_index, lp_count);
+ return spmd_ffa_error_return(handle,
+ FFA_ERROR_INVALID_PARAMETER);
+ }
+
+ max_idx = lp_count - 1;
+ num_entries_to_ret = (max_idx - start_index) + 1;
+ num_entries_to_ret =
+ MIN(num_entries_to_ret, MAX_INFO_REGS_ENTRIES_PER_CALL);
+ curr_idx = start_index + num_entries_to_ret - 1;
+ assert(curr_idx <= max_idx);
+
+ ret.func = FFA_SUCCESS_SMC64;
+ ret.arg2 = (uint64_t)((sizeof(struct ffa_partition_info_v1_1) & 0xFFFFU) << 48);
+ ret.arg2 |= (uint64_t)(curr_idx << 16);
+ ret.arg2 |= (uint64_t)max_idx;
+
+ for (uint16_t idx = start_index; idx <= curr_idx; ++idx) {
+ spmd_pack_lp_count_props(arg_ptrs, partitions[idx].ep_id,
+ partitions[idx].execution_ctx_count,
+ partitions[idx].properties);
+ arg_ptrs++;
+ if (is_null_uuid(target_uuid)) {
+ spmd_pack_lp_uuid(arg_ptrs, (arg_ptrs + 1),
+ partitions[idx].uuid);
+ }
+ arg_ptrs += 2;
+ }
+
+ SMC_RET18(handle, ret.func, ret.arg1, ret.arg2, ret.arg3, ret.arg4,
+ ret.arg5, ret.arg6, ret.arg7, ret.arg8, ret.arg9, ret.arg10,
+ ret.arg11, ret.arg12, ret.arg13, ret.arg14, ret.arg15,
+ ret.arg16, ret.arg17);
+#else
+ return spmd_ffa_error_return(handle, FFA_ERROR_NOT_SUPPORTED);
+#endif
+}
+
+/* This function can be used by an SPMD logical partition to invoke the
+ * FFA_PARTITION_INFO_GET_REGS ABI to the SPMC, to discover the secure
+ * partitions in the system. The function takes a UUID, start index and
+ * tag and the partition information are returned in an ffa_value structure
+ * and can be consumed by using appropriate helper functions.
+ */
+bool spmd_el3_invoke_partition_info_get(
+ const uint32_t target_uuid[4],
+ const uint16_t start_index,
+ const uint16_t tag,
+ struct ffa_value *retval)
+{
+#if ENABLE_SPMD_LP
+ uint64_t rc = UINT64_MAX;
+ spmd_spm_core_context_t *ctx = spmd_get_context();
+
+ if (retval == NULL) {
+ return false;
+ }
+
+ memset(retval, 0, sizeof(*retval));
+
+ if (!is_spmc_inited) {
+ VERBOSE("Cannot discover partition before,"
+ " SPMC is initialized.\n");
+ spmd_encode_ffa_error(retval, FFA_ERROR_DENIED);
+ return true;
+ }
+
+ if (tag != 0) {
+ VERBOSE("Tag must be zero. other tags unsupported\n");
+ spmd_encode_ffa_error(retval,
+ FFA_ERROR_INVALID_PARAMETER);
+ return true;
+ }
+
+ /* Save the non-secure context before entering SPMC */
+ cm_el1_sysregs_context_save(NON_SECURE);
+#if SPMD_SPM_AT_SEL2
+ cm_el2_sysregs_context_save(NON_SECURE);
+#endif
+
+ spmd_build_ffa_info_get_regs(ctx, target_uuid, start_index, tag);
+ spmd_logical_sp_set_info_regs_ongoing(ctx);
+
+ rc = spmd_spm_core_sync_entry(ctx);
+ if (rc != 0ULL) {
+ ERROR("%s failed (%lx) on CPU%u\n", __func__, rc,
+ plat_my_core_pos());
+ panic();
+ }
+
+ spmd_logical_sp_reset_info_regs_ongoing(ctx);
+ spmd_encode_ctx_to_ffa_value(ctx, retval);
+
+ assert(is_ffa_error(retval) || is_ffa_success(retval));
+
+ cm_el1_sysregs_context_restore(NON_SECURE);
+#if SPMD_SPM_AT_SEL2
+ cm_el2_sysregs_context_restore(NON_SECURE);
+#endif
+ cm_set_next_eret_context(NON_SECURE);
+ return true;
+#else
+ return false;
+#endif
+}
+
+/*******************************************************************************
+ * This function sends an FF-A Direct Request from a partition in EL3 to a
+ * partition that may reside under an SPMC (only lower ELs supported). The main
+ * use of this API is for SPMD logical partitions.
+ * The API is expected to be used when there are platform specific SMCs that
+ * need to be routed to a secure partition that is FF-A compliant or when
+ * there are group 0 interrupts that need to be handled first in EL3 and then
+ * forwarded to an FF-A compliant secure partition. Therefore, it is expected
+ * that the handle to the context provided belongs to the non-secure context.
+ * This also means that interrupts/SMCs that trap to EL3 during secure execution
+ * cannot use this API.
+ * x1, x2, x3 and x4 are encoded as specified in the FF-A specification.
+ * retval is used to pass the direct response values to the caller.
+ * The function returns true if retval has valid values, and false otherwise.
+ ******************************************************************************/
+bool spmd_el3_ffa_msg_direct_req(uint64_t x1,
+ uint64_t x2,
+ uint64_t x3,
+ uint64_t x4,
+ void *handle,
+ struct ffa_value *retval)
+{
+#if ENABLE_SPMD_LP
+
+ uint64_t rc = UINT64_MAX;
+ spmd_spm_core_context_t *ctx = spmd_get_context();
+
+ if (retval == NULL) {
+ return false;
+ }
+
+ memset(retval, 0, sizeof(*retval));
+
+ if (!is_spmd_lp_inited || !is_spmc_inited) {
+ VERBOSE("Cannot send SPMD logical partition direct message,"
+ " Partitions not initialized or SPMC not initialized.\n");
+ spmd_encode_ffa_error(retval, FFA_ERROR_DENIED);
+ return true;
+ }
+
+ /*
+ * x2 must be zero, since there is no support for framework message via
+ * an SPMD logical partition. This is sort of a useless check and it is
+ * possible to not take parameter. However, as the framework extends it
+ * may be useful to have x2 and extend this function later with
+ * functionality based on x2.
+ */
+ if (x2 != 0) {
+ VERBOSE("x2 must be zero. Cannot send framework message.\n");
+ spmd_encode_ffa_error(retval, FFA_ERROR_DENIED);
+ return true;
+ }
+
+ /*
+ * Current context must be non-secure. API is expected to be used
+ * when entry into EL3 and the SPMD logical partition is via an
+ * interrupt that occurs when execution is in normal world and
+ * SMCs from normal world. FF-A compliant SPMCs are expected to
+ * trap interrupts during secure execution in lower ELs since they
+ * are usually not re-entrant and SMCs from secure world can be
+ * handled synchronously. There is no known use case for an SPMD
+ * logical partition to send a direct message to another partition
+ * in response to a secure interrupt or SMCs from secure world.
+ */
+ if (handle != cm_get_context(NON_SECURE)) {
+ VERBOSE("Handle must be for the non-secure context.\n");
+ spmd_encode_ffa_error(retval, FFA_ERROR_DENIED);
+ return true;
+ }
+
+ if (!is_spmd_lp_id(ffa_endpoint_source(x1))) {
+ VERBOSE("Source ID must be valid SPMD logical partition"
+ " ID.\n");
+ spmd_encode_ffa_error(retval,
+ FFA_ERROR_INVALID_PARAMETER);
+ return true;
+ }
+
+ if (is_spmd_lp_id(ffa_endpoint_destination(x1))) {
+ VERBOSE("Destination ID must not be SPMD logical partition"
+ " ID.\n");
+ spmd_encode_ffa_error(retval,
+ FFA_ERROR_INVALID_PARAMETER);
+ return true;
+ }
+
+ if (!ffa_is_secure_world_id(ffa_endpoint_destination(x1))) {
+ VERBOSE("Destination ID must be secure world ID.\n");
+ spmd_encode_ffa_error(retval,
+ FFA_ERROR_INVALID_PARAMETER);
+ return true;
+ }
+
+ if (ffa_endpoint_destination(x1) == SPMD_DIRECT_MSG_ENDPOINT_ID) {
+ VERBOSE("Destination ID must not be SPMD ID.\n");
+ spmd_encode_ffa_error(retval,
+ FFA_ERROR_INVALID_PARAMETER);
+ return true;
+ }
+
+ if (ffa_endpoint_destination(x1) == spmd_spmc_id_get()) {
+ VERBOSE("Destination ID must not be SPMC ID.\n");
+ spmd_encode_ffa_error(retval,
+ FFA_ERROR_INVALID_PARAMETER);
+ return true;
+ }
+
+ /* Save the non-secure context before entering SPMC */
+ cm_el1_sysregs_context_save(NON_SECURE);
+#if SPMD_SPM_AT_SEL2
+ cm_el2_sysregs_context_save(NON_SECURE);
+#endif
+
+ /*
+ * Perform synchronous entry into the SPMC. Synchronous entry is
+ * required because the spec requires that a direct message request
+ * from an SPMD LP look like a function call from it's perspective.
+ */
+ spmd_build_direct_message_req(ctx, x1, x2, x3, x4);
+ spmd_logical_sp_set_dir_req_ongoing(ctx);
+
+ rc = spmd_spm_core_sync_entry(ctx);
+
+ spmd_logical_sp_reset_dir_req_ongoing(ctx);
+
+ if (rc != 0ULL) {
+ ERROR("%s failed (%lx) on CPU%u\n", __func__, rc,
+ plat_my_core_pos());
+ panic();
+ } else {
+ spmd_encode_ctx_to_ffa_value(ctx, retval);
+
+ /*
+ * Only expect error or direct response,
+ * spmd_spm_core_sync_exit should not be called on other paths.
+ * Checks are asserts since the LSP can fail gracefully if the
+ * source or destination ids are not the same. Panic'ing would
+ * not provide any benefit.
+ */
+ assert(is_ffa_error(retval) || is_ffa_direct_msg_resp(retval));
+ assert(is_ffa_error(retval) ||
+ (ffa_endpoint_destination(retval->arg1) ==
+ ffa_endpoint_source(x1)));
+ assert(is_ffa_error(retval) ||
+ (ffa_endpoint_source(retval->arg1) ==
+ ffa_endpoint_destination(x1)));
+ }
+
+ cm_el1_sysregs_context_restore(NON_SECURE);
+#if SPMD_SPM_AT_SEL2
+ cm_el2_sysregs_context_restore(NON_SECURE);
+#endif
+ cm_set_next_eret_context(NON_SECURE);
+
+ return true;
+#else
+ return false;
+#endif
+}
+
+bool is_spmd_logical_sp_info_regs_req_in_progress(
+ spmd_spm_core_context_t *ctx)
+{
+#if ENABLE_SPMD_LP
+ return ((ctx->spmd_lp_sync_req_ongoing & SPMD_LP_FFA_INFO_GET_REG_ONGOING)
+ == SPMD_LP_FFA_INFO_GET_REG_ONGOING);
+#else
+ return false;
+#endif
+}
+
+bool is_spmd_logical_sp_dir_req_in_progress(
+ spmd_spm_core_context_t *ctx)
+{
+#if ENABLE_SPMD_LP
+ return ((ctx->spmd_lp_sync_req_ongoing & SPMD_LP_FFA_DIR_REQ_ONGOING)
+ == SPMD_LP_FFA_DIR_REQ_ONGOING);
+#else
+ return false;
+#endif
+}
diff --git a/services/std_svc/spmd/spmd_main.c b/services/std_svc/spmd/spmd_main.c
index 587e60f..d830403 100644
--- a/services/std_svc/spmd/spmd_main.c
+++ b/services/std_svc/spmd/spmd_main.c
@@ -27,6 +27,7 @@
#include <plat/common/common_def.h>
#include <plat/common/platform.h>
#include <platform_def.h>
+#include <services/el3_spmd_logical_sp.h>
#include <services/ffa_svc.h>
#include <services/spmc_svc.h>
#include <services/spmd_svc.h>
@@ -86,8 +87,7 @@
******************************************************************************/
static int32_t spmd_init(void);
static int spmd_spmc_init(void *pm_addr);
-static uint64_t spmd_ffa_error_return(void *handle,
- int error_code);
+
static uint64_t spmd_smc_forward(uint32_t smc_fid,
bool secure_origin,
uint64_t x1,
@@ -190,6 +190,12 @@
VERBOSE("SPM Core init end.\n");
+ spmd_logical_sp_set_spmc_initialized();
+ rc = spmd_logical_sp_init();
+ if (rc != 0) {
+ WARN("SPMD Logical partitions failed init.\n");
+ }
+
return 1;
}
@@ -742,7 +748,7 @@
/*******************************************************************************
* Return FFA_ERROR with specified error code
******************************************************************************/
-static uint64_t spmd_ffa_error_return(void *handle, int error_code)
+uint64_t spmd_ffa_error_return(void *handle, int error_code)
{
SMC_RET8(handle, (uint32_t) FFA_ERROR,
FFA_TARGET_INFO_MBZ, (uint32_t)error_code,
@@ -845,6 +851,16 @@
SMC_GET_GP(handle, CTX_GPREG_X6),
SMC_GET_GP(handle, CTX_GPREG_X7));
+ /*
+ * If there is an on-going info regs from EL3 SPMD LP, unconditionally
+ * return, we don't expect any other FF-A ABIs to be called between
+ * calls to FFA_PARTITION_INFO_GET_REGS.
+ */
+ if (is_spmd_logical_sp_info_regs_req_in_progress(ctx)) {
+ assert(secure_origin);
+ spmd_spm_core_sync_exit(0ULL);
+ }
+
switch (smc_fid) {
case FFA_ERROR:
/*
@@ -856,6 +872,16 @@
spmd_spm_core_sync_exit(x2);
}
+ /*
+ * If there was an SPMD logical partition direct request on-going,
+ * return back to the SPMD logical partition so the error can be
+ * consumed.
+ */
+ if (is_spmd_logical_sp_dir_req_in_progress(ctx)) {
+ assert(secure_origin);
+ spmd_spm_core_sync_exit(0ULL);
+ }
+
return spmd_smc_forward(smc_fid, secure_origin,
x1, x2, x3, x4, cookie,
handle, flags);
@@ -1045,6 +1071,31 @@
case FFA_MSG_SEND_DIRECT_REQ_SMC32:
case FFA_MSG_SEND_DIRECT_REQ_SMC64:
+ /*
+ * Regardless of secure_origin, SPMD logical partitions cannot
+ * handle direct messages. They can only initiate direct
+ * messages and consume direct responses or errors.
+ */
+ if (is_spmd_lp_id(ffa_endpoint_source(x1)) ||
+ is_spmd_lp_id(ffa_endpoint_destination(x1))) {
+ return spmd_ffa_error_return(handle,
+ FFA_ERROR_INVALID_PARAMETER
+ );
+ }
+
+ /*
+ * When there is an ongoing SPMD logical partition direct
+ * request, there cannot be another direct request. Return
+ * error in this case. Panic'ing is an option but that does
+ * not provide the opportunity for caller to abort based on
+ * error codes.
+ */
+ if (is_spmd_logical_sp_dir_req_in_progress(ctx)) {
+ assert(secure_origin);
+ return spmd_ffa_error_return(handle,
+ FFA_ERROR_DENIED);
+ }
+
if (!secure_origin) {
/* Validate source endpoint is non-secure for non-secure caller. */
if (ffa_is_secure_world_id(ffa_endpoint_source(x1))) {
@@ -1072,7 +1123,9 @@
break; /* Not reached */
case FFA_MSG_SEND_DIRECT_RESP_SMC32:
- if (secure_origin && spmd_is_spmc_message(x1)) {
+ case FFA_MSG_SEND_DIRECT_RESP_SMC64:
+ if (secure_origin && (spmd_is_spmc_message(x1) ||
+ is_spmd_logical_sp_dir_req_in_progress(ctx))) {
spmd_spm_core_sync_exit(0ULL);
} else {
/* Forward direct message to the other world */
@@ -1112,7 +1165,6 @@
/* Forward the call to the other world */
/* fallthrough */
case FFA_MSG_SEND:
- case FFA_MSG_SEND_DIRECT_RESP_SMC64:
case FFA_MEM_DONATE_SMC32:
case FFA_MEM_DONATE_SMC64:
case FFA_MEM_LEND_SMC32:
@@ -1129,11 +1181,14 @@
case FFA_SUCCESS_SMC32:
case FFA_SUCCESS_SMC64:
/*
- * TODO: Assume that no requests originate from EL3 at the
- * moment. This will change if a SP service is required in
- * response to secure interrupts targeted to EL3. Until then
- * simply forward the call to the Normal world.
+ * If there is an ongoing direct request from an SPMD logical
+ * partition, return an error.
*/
+ if (is_spmd_logical_sp_dir_req_in_progress(ctx)) {
+ assert(secure_origin);
+ return spmd_ffa_error_return(handle,
+ FFA_ERROR_DENIED);
+ }
return spmd_smc_forward(smc_fid, secure_origin,
x1, x2, x3, x4, cookie,
@@ -1160,6 +1215,12 @@
FFA_ERROR_NOT_SUPPORTED);
}
+ if (is_spmd_logical_sp_dir_req_in_progress(ctx)) {
+ assert(secure_origin);
+ return spmd_ffa_error_return(handle,
+ FFA_ERROR_DENIED);
+ }
+
return spmd_smc_forward(smc_fid, secure_origin,
x1, x2, x3, x4, cookie,
handle, flags);
@@ -1175,8 +1236,8 @@
#if MAKE_FFA_VERSION(1, 1) <= FFA_VERSION_COMPILED
case FFA_PARTITION_INFO_GET_REGS_SMC64:
if (secure_origin) {
- /* TODO: Future patches to enable support for this */
- return spmd_ffa_error_return(handle, FFA_ERROR_NOT_SUPPORTED);
+ return spmd_el3_populate_logical_partition_info(handle, x1,
+ x2, x3);
}
/* Call only supported with SMCCC 1.2+ */
diff --git a/services/std_svc/spmd/spmd_private.h b/services/std_svc/spmd/spmd_private.h
index ff6942e..fef7ef6 100644
--- a/services/std_svc/spmd/spmd_private.h
+++ b/services/std_svc/spmd/spmd_private.h
@@ -52,8 +52,15 @@
cpu_context_t cpu_ctx;
spmc_state_t state;
bool secure_interrupt_ongoing;
+#if ENABLE_SPMD_LP
+ uint8_t spmd_lp_sync_req_ongoing;
+#endif
} spmd_spm_core_context_t;
+/* Flags to indicate ongoing requests for SPMD EL3 logical partitions */
+#define SPMD_LP_FFA_DIR_REQ_ONGOING U(0x1)
+#define SPMD_LP_FFA_INFO_GET_REG_ONGOING U(0x2)
+
/*
* Reserve ID for NS physical FFA Endpoint.
*/
@@ -100,6 +107,9 @@
* otherwise it returns a negative value
*/
int plat_spmd_handle_group0_interrupt(uint32_t id);
+
+uint64_t spmd_ffa_error_return(void *handle, int error_code);
+
#endif /* __ASSEMBLER__ */
#endif /* SPMD_PRIVATE_H */