TF-A GICv3 driver: Separate GICD and GICR accessor functions
This patch provides separation of GICD, GICR accessor
functions and adds new macros for GICv3 registers access
as a preparation for GICv3.1 and GICv4 support.
NOTE: Platforms need to modify to include both
'gicdv3_helpers.c' and 'gicrv3_helpers.c' instead of the
single helper file previously.
Change-Id: I1641bd6d217d6eb7d1228be3c4177b2d556da60a
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
diff --git a/drivers/arm/gic/v3/gicdv3_helpers.c b/drivers/arm/gic/v3/gicdv3_helpers.c
new file mode 100644
index 0000000..3f5ff45
--- /dev/null
+++ b/drivers/arm/gic/v3/gicdv3_helpers.c
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+
+#include "gicv3_private.h"
+
+/*******************************************************************************
+ * GIC Distributor interface accessors for bit operations
+ ******************************************************************************/
+
+/*
+ * Accessor to read the GIC Distributor IGRPMODR corresponding to the
+ * interrupt `id`, 32 interrupt IDs at a time.
+ */
+uint32_t gicd_read_igrpmodr(uintptr_t base, unsigned int id)
+{
+ return GICD_READ(IGRPMODR, base, id);
+}
+
+/*
+ * Accessor to write the GIC Distributor IGRPMODR corresponding to the
+ * interrupt `id`, 32 interrupt IDs at a time.
+ */
+void gicd_write_igrpmodr(uintptr_t base, unsigned int id, uint32_t val)
+{
+ GICD_WRITE(IGRPMODR, base, id, val);
+}
+
+/*
+ * Accessor to get the bit corresponding to interrupt ID
+ * in GIC Distributor IGRPMODR.
+ */
+unsigned int gicd_get_igrpmodr(uintptr_t base, unsigned int id)
+{
+ return GICD_GET_BIT(IGRPMODR, base, id);
+}
+
+/*
+ * Accessor to set the bit corresponding to interrupt ID
+ * in GIC Distributor IGRPMODR.
+ */
+void gicd_set_igrpmodr(uintptr_t base, unsigned int id)
+{
+ GICD_SET_BIT(IGRPMODR, base, id);
+}
+
+/*
+ * Accessor to clear the bit corresponding to interrupt ID
+ * in GIC Distributor IGRPMODR.
+ */
+void gicd_clr_igrpmodr(uintptr_t base, unsigned int id)
+{
+ GICD_CLR_BIT(IGRPMODR, base, id);
+}
diff --git a/drivers/arm/gic/v3/gicrv3_helpers.c b/drivers/arm/gic/v3/gicrv3_helpers.c
new file mode 100644
index 0000000..294acda
--- /dev/null
+++ b/drivers/arm/gic/v3/gicrv3_helpers.c
@@ -0,0 +1,215 @@
+/*
+ * Copyright (c) 2015-2020, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <arch_helpers.h>
+#include <common/debug.h>
+#include <common/interrupt_props.h>
+#include <drivers/arm/gicv3.h>
+#include "gicv3_private.h"
+
+/*******************************************************************************
+ * GIC Redistributor functions
+ * Note: The raw register values correspond to multiple interrupt IDs and
+ * the number of interrupt IDs involved depends on the register accessed.
+ ******************************************************************************/
+
+/*
+ * Accessor to read the GIC Redistributor IPRIORITYR corresponding to the
+ * interrupt `id`, 4 interrupts IDs at a time.
+ */
+unsigned int gicr_read_ipriorityr(uintptr_t base, unsigned int id)
+{
+ unsigned int n = id >> IPRIORITYR_SHIFT;
+
+ return mmio_read_32(base + GICR_IPRIORITYR + (n << 2));
+}
+
+/*
+ * Accessor to write the GIC Redistributor IPRIORITYR corresponding to the
+ * interrupt `id`, 4 interrupts IDs at a time.
+ */
+void gicr_write_ipriorityr(uintptr_t base, unsigned int id, unsigned int val)
+{
+ unsigned int n = id >> IPRIORITYR_SHIFT;
+
+ mmio_write_32(base + GICR_IPRIORITYR + (n << 2), val);
+}
+
+/*
+ * Accessor to set the byte corresponding to interrupt ID
+ * in GIC Redistributor IPRIORITYR.
+ */
+void gicr_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri)
+{
+ GICR_WRITE_8(IPRIORITYR, base, id, pri & GIC_PRI_MASK);
+}
+
+/*
+ * Accessor to get the bit corresponding to interrupt ID
+ * from GIC Redistributor IGROUPR0.
+ */
+unsigned int gicr_get_igroupr0(uintptr_t base, unsigned int id)
+{
+ unsigned int bit_num = id & ((1U << IGROUPR_SHIFT) - 1U);
+ unsigned int reg_val = gicr_read_igroupr0(base);
+
+ return (reg_val >> bit_num) & 0x1U;
+}
+
+/*
+ * Accessor to set the bit corresponding to interrupt ID
+ * in GIC Redistributor IGROUPR0.
+ */
+void gicr_set_igroupr0(uintptr_t base, unsigned int id)
+{
+ unsigned int bit_num = id & ((1U << IGROUPR_SHIFT) - 1U);
+ unsigned int reg_val = gicr_read_igroupr0(base);
+
+ gicr_write_igroupr0(base, reg_val | (1U << bit_num));
+}
+
+/*
+ * Accessor to clear the bit corresponding to interrupt ID
+ * in GIC Redistributor IGROUPR0.
+ */
+void gicr_clr_igroupr0(uintptr_t base, unsigned int id)
+{
+ unsigned int bit_num = id & ((1U << IGROUPR_SHIFT) - 1U);
+ unsigned int reg_val = gicr_read_igroupr0(base);
+
+ gicr_write_igroupr0(base, reg_val & ~(1U << bit_num));
+}
+
+/*
+ * Accessor to get the bit corresponding to interrupt ID
+ * from GIC Redistributor IGRPMODR0.
+ */
+unsigned int gicr_get_igrpmodr0(uintptr_t base, unsigned int id)
+{
+ unsigned int bit_num = id & ((1U << IGRPMODR_SHIFT) - 1U);
+ unsigned int reg_val = gicr_read_igrpmodr0(base);
+
+ return (reg_val >> bit_num) & 0x1U;
+}
+
+/*
+ * Accessor to set the bit corresponding to interrupt ID
+ * in GIC Redistributor IGRPMODR0.
+ */
+void gicr_set_igrpmodr0(uintptr_t base, unsigned int id)
+{
+ unsigned int bit_num = id & ((1U << IGRPMODR_SHIFT) - 1U);
+ unsigned int reg_val = gicr_read_igrpmodr0(base);
+
+ gicr_write_igrpmodr0(base, reg_val | (1U << bit_num));
+}
+
+/*
+ * Accessor to clear the bit corresponding to interrupt ID
+ * in GIC Redistributor IGRPMODR0.
+ */
+void gicr_clr_igrpmodr0(uintptr_t base, unsigned int id)
+{
+ unsigned int bit_num = id & ((1U << IGRPMODR_SHIFT) - 1U);
+ unsigned int reg_val = gicr_read_igrpmodr0(base);
+
+ gicr_write_igrpmodr0(base, reg_val & ~(1U << bit_num));
+}
+
+/*
+ * Accessor to set the bit corresponding to interrupt ID
+ * in GIC Redistributor ISENABLER0.
+ */
+void gicr_set_isenabler0(uintptr_t base, unsigned int id)
+{
+ unsigned int bit_num = id & ((1U << ISENABLER_SHIFT) - 1U);
+
+ gicr_write_isenabler0(base, (1U << bit_num));
+}
+
+/*
+ * Accessor to set the bit corresponding to interrupt ID in GIC Redistributor
+ * ICENABLER0.
+ */
+void gicr_set_icenabler0(uintptr_t base, unsigned int id)
+{
+ unsigned int bit_num = id & ((1U << ICENABLER_SHIFT) - 1U);
+
+ gicr_write_icenabler0(base, (1U << bit_num));
+}
+
+/*
+ * Accessor to set the bit corresponding to interrupt ID in GIC Redistributor
+ * ISACTIVER0.
+ */
+unsigned int gicr_get_isactiver0(uintptr_t base, unsigned int id)
+{
+ unsigned int bit_num = id & ((1U << ISACTIVER_SHIFT) - 1U);
+ unsigned int reg_val = gicr_read_isactiver0(base);
+
+ return (reg_val >> bit_num) & 0x1U;
+}
+
+/*
+ * Accessor to clear the bit corresponding to interrupt ID in GIC Redistributor
+ * ICPENDRR0.
+ */
+void gicr_set_icpendr0(uintptr_t base, unsigned int id)
+{
+ unsigned int bit_num = id & ((1U << ICPENDR_SHIFT) - 1U);
+
+ gicr_write_icpendr0(base, (1U << bit_num));
+}
+
+/*
+ * Accessor to set the bit corresponding to interrupt ID in GIC Redistributor
+ * ISPENDR0.
+ */
+void gicr_set_ispendr0(uintptr_t base, unsigned int id)
+{
+ unsigned int bit_num = id & ((1U << ISPENDR_SHIFT) - 1U);
+
+ gicr_write_ispendr0(base, (1U << bit_num));
+}
+
+/*
+ * Accessor to set the bit fields corresponding to interrupt ID
+ * in GIC Redistributor ICFGR0.
+ */
+void gicr_set_icfgr0(uintptr_t base, unsigned int id, unsigned int cfg)
+{
+ /* Interrupt configuration is a 2-bit field */
+ unsigned int bit_num = id & ((1U << ICFGR_SHIFT) - 1U);
+ unsigned int bit_shift = bit_num << 1U;
+
+ uint32_t reg_val = gicr_read_icfgr0(base);
+
+ /* Clear the field, and insert required configuration */
+ reg_val &= ~(GIC_CFG_MASK << bit_shift);
+ reg_val |= ((cfg & GIC_CFG_MASK) << bit_shift);
+
+ gicr_write_icfgr0(base, reg_val);
+}
+
+/*
+ * Accessor to set the bit fields corresponding to interrupt ID
+ * in GIC Redistributor ICFGR1.
+ */
+void gicr_set_icfgr1(uintptr_t base, unsigned int id, unsigned int cfg)
+{
+ /* Interrupt configuration is a 2-bit field */
+ unsigned int bit_num = id & ((1U << ICFGR_SHIFT) - 1U);
+ unsigned int bit_shift = bit_num << 1U;
+
+ uint32_t reg_val = gicr_read_icfgr1(base);
+
+ /* Clear the field, and insert required configuration */
+ reg_val &= ~(GIC_CFG_MASK << bit_shift);
+ reg_val |= ((cfg & GIC_CFG_MASK) << bit_shift);
+
+ gicr_write_icfgr1(base, reg_val);
+}
diff --git a/drivers/arm/gic/v3/gicv3_helpers.c b/drivers/arm/gic/v3/gicv3_helpers.c
index 710532e..d5aaf96 100644
--- a/drivers/arm/gic/v3/gicv3_helpers.c
+++ b/drivers/arm/gic/v3/gicv3_helpers.c
@@ -15,263 +15,6 @@
#include "../common/gic_common_private.h"
#include "gicv3_private.h"
-/*
- * Accessor to read the GIC Distributor IGRPMODR corresponding to the
- * interrupt `id`, 32 interrupt IDs at a time.
- */
-unsigned int gicd_read_igrpmodr(uintptr_t base, unsigned int id)
-{
- unsigned int n = id >> IGRPMODR_SHIFT;
-
- return mmio_read_32(base + GICD_IGRPMODR + (n << 2));
-}
-
-/*
- * Accessor to write the GIC Distributor IGRPMODR corresponding to the
- * interrupt `id`, 32 interrupt IDs at a time.
- */
-void gicd_write_igrpmodr(uintptr_t base, unsigned int id, unsigned int val)
-{
- unsigned int n = id >> IGRPMODR_SHIFT;
-
- mmio_write_32(base + GICD_IGRPMODR + (n << 2), val);
-}
-
-/*
- * Accessor to get the bit corresponding to interrupt ID
- * in GIC Distributor IGRPMODR.
- */
-unsigned int gicd_get_igrpmodr(uintptr_t base, unsigned int id)
-{
- unsigned int bit_num = id & ((1U << IGRPMODR_SHIFT) - 1U);
- unsigned int reg_val = gicd_read_igrpmodr(base, id);
-
- return (reg_val >> bit_num) & 0x1U;
-}
-
-/*
- * Accessor to set the bit corresponding to interrupt ID
- * in GIC Distributor IGRPMODR.
- */
-void gicd_set_igrpmodr(uintptr_t base, unsigned int id)
-{
- unsigned int bit_num = id & ((1U << IGRPMODR_SHIFT) - 1U);
- unsigned int reg_val = gicd_read_igrpmodr(base, id);
-
- gicd_write_igrpmodr(base, id, reg_val | (1U << bit_num));
-}
-
-/*
- * Accessor to clear the bit corresponding to interrupt ID
- * in GIC Distributor IGRPMODR.
- */
-void gicd_clr_igrpmodr(uintptr_t base, unsigned int id)
-{
- unsigned int bit_num = id & ((1U << IGRPMODR_SHIFT) - 1U);
- unsigned int reg_val = gicd_read_igrpmodr(base, id);
-
- gicd_write_igrpmodr(base, id, reg_val & ~(1U << bit_num));
-}
-
-/*
- * Accessor to read the GIC Re-distributor IPRIORITYR corresponding to the
- * interrupt `id`, 4 interrupts IDs at a time.
- */
-unsigned int gicr_read_ipriorityr(uintptr_t base, unsigned int id)
-{
- unsigned int n = id >> IPRIORITYR_SHIFT;
-
- return mmio_read_32(base + GICR_IPRIORITYR + (n << 2));
-}
-
-/*
- * Accessor to write the GIC Re-distributor IPRIORITYR corresponding to the
- * interrupt `id`, 4 interrupts IDs at a time.
- */
-void gicr_write_ipriorityr(uintptr_t base, unsigned int id, unsigned int val)
-{
- unsigned int n = id >> IPRIORITYR_SHIFT;
-
- mmio_write_32(base + GICR_IPRIORITYR + (n << 2), val);
-}
-
-/*
- * Accessor to get the bit corresponding to interrupt ID
- * from GIC Re-distributor IGROUPR0.
- */
-unsigned int gicr_get_igroupr0(uintptr_t base, unsigned int id)
-{
- unsigned int bit_num = id & ((1U << IGROUPR_SHIFT) - 1U);
- unsigned int reg_val = gicr_read_igroupr0(base);
-
- return (reg_val >> bit_num) & 0x1U;
-}
-
-/*
- * Accessor to set the bit corresponding to interrupt ID
- * in GIC Re-distributor IGROUPR0.
- */
-void gicr_set_igroupr0(uintptr_t base, unsigned int id)
-{
- unsigned int bit_num = id & ((1U << IGROUPR_SHIFT) - 1U);
- unsigned int reg_val = gicr_read_igroupr0(base);
-
- gicr_write_igroupr0(base, reg_val | (1U << bit_num));
-}
-
-/*
- * Accessor to clear the bit corresponding to interrupt ID
- * in GIC Re-distributor IGROUPR0.
- */
-void gicr_clr_igroupr0(uintptr_t base, unsigned int id)
-{
- unsigned int bit_num = id & ((1U << IGROUPR_SHIFT) - 1U);
- unsigned int reg_val = gicr_read_igroupr0(base);
-
- gicr_write_igroupr0(base, reg_val & ~(1U << bit_num));
-}
-
-/*
- * Accessor to get the bit corresponding to interrupt ID
- * from GIC Re-distributor IGRPMODR0.
- */
-unsigned int gicr_get_igrpmodr0(uintptr_t base, unsigned int id)
-{
- unsigned int bit_num = id & ((1U << IGRPMODR_SHIFT) - 1U);
- unsigned int reg_val = gicr_read_igrpmodr0(base);
-
- return (reg_val >> bit_num) & 0x1U;
-}
-
-/*
- * Accessor to set the bit corresponding to interrupt ID
- * in GIC Re-distributor IGRPMODR0.
- */
-void gicr_set_igrpmodr0(uintptr_t base, unsigned int id)
-{
- unsigned int bit_num = id & ((1U << IGRPMODR_SHIFT) - 1U);
- unsigned int reg_val = gicr_read_igrpmodr0(base);
-
- gicr_write_igrpmodr0(base, reg_val | (1U << bit_num));
-}
-
-/*
- * Accessor to clear the bit corresponding to interrupt ID
- * in GIC Re-distributor IGRPMODR0.
- */
-void gicr_clr_igrpmodr0(uintptr_t base, unsigned int id)
-{
- unsigned int bit_num = id & ((1U << IGRPMODR_SHIFT) - 1U);
- unsigned int reg_val = gicr_read_igrpmodr0(base);
-
- gicr_write_igrpmodr0(base, reg_val & ~(1U << bit_num));
-}
-
-/*
- * Accessor to set the bit corresponding to interrupt ID
- * in GIC Re-distributor ISENABLER0.
- */
-void gicr_set_isenabler0(uintptr_t base, unsigned int id)
-{
- unsigned int bit_num = id & ((1U << ISENABLER_SHIFT) - 1U);
-
- gicr_write_isenabler0(base, (1U << bit_num));
-}
-
-/*
- * Accessor to set the bit corresponding to interrupt ID in GIC Re-distributor
- * ICENABLER0.
- */
-void gicr_set_icenabler0(uintptr_t base, unsigned int id)
-{
- unsigned int bit_num = id & ((1U << ICENABLER_SHIFT) - 1U);
-
- gicr_write_icenabler0(base, (1U << bit_num));
-}
-
-/*
- * Accessor to set the bit corresponding to interrupt ID in GIC Re-distributor
- * ISACTIVER0.
- */
-unsigned int gicr_get_isactiver0(uintptr_t base, unsigned int id)
-{
- unsigned int bit_num = id & ((1U << ISACTIVER_SHIFT) - 1U);
- unsigned int reg_val = gicr_read_isactiver0(base);
-
- return (reg_val >> bit_num) & 0x1U;
-}
-
-/*
- * Accessor to clear the bit corresponding to interrupt ID in GIC Re-distributor
- * ICPENDRR0.
- */
-void gicr_set_icpendr0(uintptr_t base, unsigned int id)
-{
- unsigned int bit_num = id & ((1U << ICPENDR_SHIFT) - 1U);
-
- gicr_write_icpendr0(base, (1U << bit_num));
-}
-
-/*
- * Accessor to set the bit corresponding to interrupt ID in GIC Re-distributor
- * ISPENDR0.
- */
-void gicr_set_ispendr0(uintptr_t base, unsigned int id)
-{
- unsigned int bit_num = id & ((1U << ISPENDR_SHIFT) - 1U);
-
- gicr_write_ispendr0(base, (1U << bit_num));
-}
-
-/*
- * Accessor to set the byte corresponding to interrupt ID
- * in GIC Re-distributor IPRIORITYR.
- */
-void gicr_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri)
-{
- uint8_t val = pri & GIC_PRI_MASK;
-
- mmio_write_8(base + GICR_IPRIORITYR + id, val);
-}
-
-/*
- * Accessor to set the bit fields corresponding to interrupt ID
- * in GIC Re-distributor ICFGR0.
- */
-void gicr_set_icfgr0(uintptr_t base, unsigned int id, unsigned int cfg)
-{
- /* Interrupt configuration is a 2-bit field */
- unsigned int bit_num = id & ((1U << ICFGR_SHIFT) - 1U);
- unsigned int bit_shift = bit_num << 1U;
-
- uint32_t reg_val = gicr_read_icfgr0(base);
-
- /* Clear the field, and insert required configuration */
- reg_val &= ~(GIC_CFG_MASK << bit_shift);
- reg_val |= ((cfg & GIC_CFG_MASK) << bit_shift);
-
- gicr_write_icfgr0(base, reg_val);
-}
-
-/*
- * Accessor to set the bit fields corresponding to interrupt ID
- * in GIC Re-distributor ICFGR1.
- */
-void gicr_set_icfgr1(uintptr_t base, unsigned int id, unsigned int cfg)
-{
- /* Interrupt configuration is a 2-bit field */
- unsigned int bit_num = id & ((1U << ICFGR_SHIFT) - 1U);
- unsigned int bit_shift = bit_num << 1U;
-
- uint32_t reg_val = gicr_read_icfgr1(base);
-
- /* Clear the field, and insert required configuration */
- reg_val &= ~(GIC_CFG_MASK << bit_shift);
- reg_val |= ((cfg & GIC_CFG_MASK) << bit_shift);
-
- gicr_write_icfgr1(base, reg_val);
-}
-
/******************************************************************************
* This function marks the core as awake in the re-distributor and
* ensures that the interface is active.
@@ -292,7 +35,6 @@
;
}
-
/******************************************************************************
* This function marks the core as asleep in the re-distributor and ensures
* that the interface is quiescent.
diff --git a/drivers/arm/gic/v3/gicv3_private.h b/drivers/arm/gic/v3/gicv3_private.h
index 327a9a1..dae01cb 100644
--- a/drivers/arm/gic/v3/gicv3_private.h
+++ b/drivers/arm/gic/v3/gicv3_private.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -24,6 +24,100 @@
#define RWP_TRUE U(1)
#define RWP_FALSE U(0)
+/* Calculate GIC register bit number corresponding to its interrupt ID */
+#define BIT_NUM(REG, id) \
+ ((id) & ((1U << REG##_SHIFT) - 1U))
+
+/* Calculate 8-bit GICD register offset corresponding to its interrupt ID */
+#define GICD_OFFSET_8(REG, id) \
+ GICD_##REG + (id)
+
+/* Calculate 32-bit GICD register offset corresponding to its interrupt ID */
+#define GICD_OFFSET(REG, id) \
+ GICD_##REG + (((id) >> REG##_SHIFT) << 2)
+
+/* Calculate 64-bit GICD register offset corresponding to its interrupt ID */
+#define GICD_OFFSET_64(REG, id) \
+ GICD_##REG + (((id) >> REG##_SHIFT) << 3)
+
+/* Read 32-bit GIC Distributor register corresponding to its interrupt ID */
+#define GICD_READ(REG, base, id) \
+ mmio_read_32((base) + GICD_OFFSET(REG, (id)))
+
+/* Read 64-bit GIC Distributor register corresponding to its interrupt ID */
+#define GICD_READ_64(REG, base, id) \
+ mmio_read_64((base) + GICD_OFFSET_64(REG, (id)))
+
+/* Write to 64-bit GIC Distributor register corresponding to its interrupt ID */
+#define GICD_WRITE_64(REG, base, id, val) \
+ mmio_write_64((base) + GICD_OFFSET_64(REG, (id)), (val))
+
+/* Write to 32-bit GIC Distributor register corresponding to its interrupt ID */
+#define GICD_WRITE(REG, base, id, val) \
+ mmio_write_32((base) + GICD_OFFSET(REG, (id)), (val))
+
+/* Write to 8-bit GIC Distributor register corresponding to its interrupt ID */
+#define GICD_WRITE_8(REG, base, id, val) \
+ mmio_write_8((base) + GICD_OFFSET_8(REG, (id)), (val))
+
+/*
+ * Bit operations on GIC Distributor register corresponding
+ * to its interrupt ID
+ */
+/* Get bit in GIC Distributor register */
+#define GICD_GET_BIT(REG, base, id) \
+ ((mmio_read_32((base) + GICD_OFFSET(REG, (id))) >> \
+ BIT_NUM(REG, (id))) & 1U)
+
+/* Set bit in GIC Distributor register */
+#define GICD_SET_BIT(REG, base, id) \
+ mmio_setbits_32((base) + GICD_OFFSET(REG, (id)), \
+ ((uint32_t)1 << BIT_NUM(REG, (id))))
+
+/* Clear bit in GIC Distributor register */
+#define GICD_CLR_BIT(REG, base, id) \
+ mmio_clrbits_32((base) + GICD_OFFSET(REG, (id)), \
+ ((uint32_t)1 << BIT_NUM(REG, (id))))
+
+/* Write bit in GIC Distributor register */
+#define GICD_WRITE_BIT(REG, base, id) \
+ mmio_write_32((base) + GICD_OFFSET(REG, (id)), \
+ ((uint32_t)1 << BIT_NUM(REG, (id))))
+
+/*
+ * Calculate GICv3 GICR register offset
+ */
+#define GICR_OFFSET(REG, id) \
+ GICR_##REG + (((id) >> REG##_SHIFT) << 2)
+
+/* Write to GIC Redistributor register corresponding to its interrupt ID */
+#define GICR_WRITE_8(REG, base, id, val) \
+ mmio_write_8((base) + GICR_##REG + (id), (val))
+
+/*
+ * Bit operations on GIC Redistributor register
+ * corresponding to its interrupt ID
+ */
+/* Get bit in GIC Redistributor register */
+#define GICR_GET_BIT(REG, base, id) \
+ ((mmio_read_32((base) + GICR_OFFSET(REG, (id))) >> \
+ BIT_NUM(REG, (id))) & 1U)
+
+/* Write bit in GIC Redistributor register */
+#define GICR_WRITE_BIT(REG, base, id) \
+ mmio_write_32((base) + GICR_OFFSET(REG, (id)), \
+ ((uint32_t)1 << BIT_NUM(REG, (id))))
+
+/* Set bit in GIC Redistributor register */
+#define GICR_SET_BIT(REG, base, id) \
+ mmio_setbits_32((base) + GICR_OFFSET(REG, (id)), \
+ ((uint32_t)1 << BIT_NUM(REG, (id))))
+
+/* Clear bit in GIC Redistributor register */
+#define GICR_CLR_BIT(REG, base, id) \
+ mmio_clrbits_32((base) + GICR_OFFSET(REG, (id)), \
+ ((uint32_t)1 << BIT_NUM(REG, (id))))
+
/*
* Macro to convert an mpidr to a value suitable for programming into a
* GICD_IROUTER. Bits[31:24] in the MPIDR are cleared as they are not relevant
@@ -63,9 +157,9 @@
* Note: The raw register values correspond to multiple interrupt IDs and
* the number of interrupt IDs involved depends on the register accessed.
******************************************************************************/
-unsigned int gicd_read_igrpmodr(uintptr_t base, unsigned int id);
+uint32_t gicd_read_igrpmodr(uintptr_t base, unsigned int id);
unsigned int gicr_read_ipriorityr(uintptr_t base, unsigned int id);
-void gicd_write_igrpmodr(uintptr_t base, unsigned int id, unsigned int val);
+void gicd_write_igrpmodr(uintptr_t base, unsigned int id, uint32_t val);
void gicr_write_ipriorityr(uintptr_t base, unsigned int id, unsigned int val);
/*******************************************************************************
@@ -121,27 +215,27 @@
*/
static inline void gicd_wait_for_pending_write(uintptr_t gicd_base)
{
- while ((gicd_read_ctlr(gicd_base) & GICD_CTLR_RWP_BIT) != 0U)
- ;
+ while ((gicd_read_ctlr(gicd_base) & GICD_CTLR_RWP_BIT) != 0U) {
+ }
}
-static inline unsigned int gicd_read_pidr2(uintptr_t base)
+static inline uint32_t gicd_read_pidr2(uintptr_t base)
{
return mmio_read_32(base + GICD_PIDR2_GICV3);
}
-static inline unsigned long long gicd_read_irouter(uintptr_t base, unsigned int id)
+static inline uint64_t gicd_read_irouter(uintptr_t base, unsigned int id)
{
assert(id >= MIN_SPI_ID);
- return mmio_read_64(base + GICD_IROUTER + (id << 3));
+ return GICD_READ_64(IROUTER, base, id);
}
static inline void gicd_write_irouter(uintptr_t base,
unsigned int id,
- unsigned long long affinity)
+ uint64_t affinity)
{
assert(id >= MIN_SPI_ID);
- mmio_write_64(base + GICD_IROUTER + (id << 3), affinity);
+ GICD_WRITE_64(IROUTER, base, id, affinity);
}
static inline void gicd_clr_ctlr(uintptr_t base,
@@ -149,8 +243,9 @@
unsigned int rwp)
{
gicd_write_ctlr(base, gicd_read_ctlr(base) & ~bitmap);
- if (rwp != 0U)
+ if (rwp != 0U) {
gicd_wait_for_pending_write(base);
+ }
}
static inline void gicd_set_ctlr(uintptr_t base,
@@ -158,8 +253,9 @@
unsigned int rwp)
{
gicd_write_ctlr(base, gicd_read_ctlr(base) | bitmap);
- if (rwp != 0U)
+ if (rwp != 0U) {
gicd_wait_for_pending_write(base);
+ }
}
/*******************************************************************************
@@ -175,17 +271,17 @@
mmio_write_32(base + GICR_CTLR, val);
}
-static inline unsigned long long gicr_read_typer(uintptr_t base)
+static inline uint64_t gicr_read_typer(uintptr_t base)
{
return mmio_read_64(base + GICR_TYPER);
}
-static inline unsigned int gicr_read_waker(uintptr_t base)
+static inline uint32_t gicr_read_waker(uintptr_t base)
{
return mmio_read_32(base + GICR_WAKER);
}
-static inline void gicr_write_waker(uintptr_t base, unsigned int val)
+static inline void gicr_write_waker(uintptr_t base, uint32_t val)
{
mmio_write_32(base + GICR_WAKER, val);
}
@@ -199,14 +295,14 @@
*/
static inline void gicr_wait_for_pending_write(uintptr_t gicr_base)
{
- while ((gicr_read_ctlr(gicr_base) & GICR_CTLR_RWP_BIT) != 0U)
- ;
+ while ((gicr_read_ctlr(gicr_base) & GICR_CTLR_RWP_BIT) != 0U) {
+ }
}
static inline void gicr_wait_for_upstream_pending_write(uintptr_t gicr_base)
{
- while ((gicr_read_ctlr(gicr_base) & GICR_CTLR_UWP_BIT) != 0U)
- ;
+ while ((gicr_read_ctlr(gicr_base) & GICR_CTLR_UWP_BIT) != 0U) {
+ }
}
/* Private implementation of Distributor power control hooks */
@@ -214,7 +310,7 @@
void arm_gicv3_distif_post_restore(unsigned int rdist_proc_num);
/*******************************************************************************
- * GIC Re-distributor functions for accessing entire registers.
+ * GIC Redistributor functions for accessing entire registers.
* Note: The raw register values correspond to multiple interrupt IDs and
* the number of interrupt IDs involved depends on the register accessed.
******************************************************************************/
@@ -341,7 +437,7 @@
return mmio_read_32(base + GITS_CTLR);
}
-static inline void gits_write_ctlr(uintptr_t base, unsigned int val)
+static inline void gits_write_ctlr(uintptr_t base, uint32_t val)
{
mmio_write_32(base + GITS_CTLR, val);
}
@@ -366,13 +462,15 @@
mmio_write_64(base + GITS_CWRITER, val);
}
-static inline uint64_t gits_read_baser(uintptr_t base, unsigned int its_table_id)
+static inline uint64_t gits_read_baser(uintptr_t base,
+ unsigned int its_table_id)
{
assert(its_table_id < 8U);
return mmio_read_64(base + GITS_BASER + (8U * its_table_id));
}
-static inline void gits_write_baser(uintptr_t base, unsigned int its_table_id, uint64_t val)
+static inline void gits_write_baser(uintptr_t base, unsigned int its_table_id,
+ uint64_t val)
{
assert(its_table_id < 8U);
mmio_write_64(base + GITS_BASER + (8U * its_table_id), val);
@@ -384,9 +482,8 @@
static inline void gits_wait_for_quiescent_bit(uintptr_t gits_base)
{
assert((gits_read_ctlr(gits_base) & GITS_CTLR_ENABLED_BIT) == 0U);
- while ((gits_read_ctlr(gits_base) & GITS_CTLR_QUIESCENT_BIT) == 0U)
- ;
+ while ((gits_read_ctlr(gits_base) & GITS_CTLR_QUIESCENT_BIT) == 0U) {
+ }
}
-
#endif /* GICV3_PRIVATE_H */
diff --git a/include/drivers/arm/gicv3.h b/include/drivers/arm/gicv3.h
index c4f42d0..e6339bc 100644
--- a/include/drivers/arm/gicv3.h
+++ b/include/drivers/arm/gicv3.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -32,7 +32,7 @@
#define GICD_SETSPI_NSR U(0x40)
#define GICD_CLRSPI_NSR U(0x48)
#define GICD_SETSPI_SR U(0x50)
-#define GICD_CLRSPI_SR U(0x50)
+#define GICD_CLRSPI_SR U(0x58)
#define GICD_IGRPMODR U(0xd00)
/*
* GICD_IROUTER<n> register is at 0x6000 + 8n, where n is the interrupt id and
@@ -79,7 +79,7 @@
#define NUM_OF_DIST_REGS 30
/*******************************************************************************
- * GICv3 Re-distributor interface registers & constants
+ * GICv3 Redistributor interface registers & constants
******************************************************************************/
#define GICR_PCPUBASE_SHIFT 0x11
#define GICR_SGIBASE_OFFSET U(65536) /* 64 KB */
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index 05c11ce..c32b302 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -56,6 +56,8 @@
FVP_GICV3_SOURCES := drivers/arm/gic/common/gic_common.c \
drivers/arm/gic/v3/gicv3_main.c \
drivers/arm/gic/v3/gicv3_helpers.c \
+ drivers/arm/gic/v3/gicdv3_helpers.c \
+ drivers/arm/gic/v3/gicrv3_helpers.c \
plat/common/plat_gicv3.c \
plat/arm/common/arm_gicv3.c
diff --git a/plat/arm/board/n1sdp/platform.mk b/plat/arm/board/n1sdp/platform.mk
index 8816670..da780a3 100644
--- a/plat/arm/board/n1sdp/platform.mk
+++ b/plat/arm/board/n1sdp/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -18,6 +18,8 @@
N1SDP_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
drivers/arm/gic/v3/gicv3_main.c \
drivers/arm/gic/v3/gicv3_helpers.c \
+ drivers/arm/gic/v3/gicdv3_helpers.c \
+ drivers/arm/gic/v3/gicrv3_helpers.c \
drivers/arm/gic/v3/gic600_multichip.c \
plat/common/plat_gicv3.c \
plat/arm/common/arm_gicv3.c \
diff --git a/plat/arm/css/sgi/sgi-common.mk b/plat/arm/css/sgi/sgi-common.mk
index 40a7fd8..ea5a563 100644
--- a/plat/arm/css/sgi/sgi-common.mk
+++ b/plat/arm/css/sgi/sgi-common.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -25,6 +25,8 @@
ENT_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
drivers/arm/gic/v3/gicv3_main.c \
drivers/arm/gic/v3/gicv3_helpers.c \
+ drivers/arm/gic/v3/gicdv3_helpers.c \
+ drivers/arm/gic/v3/gicrv3_helpers.c \
plat/common/plat_gicv3.c \
plat/arm/common/arm_gicv3.c \
drivers/arm/gic/v3/gic600.c
diff --git a/plat/arm/css/sgm/sgm-common.mk b/plat/arm/css/sgm/sgm-common.mk
index ac34450..49fc717 100644
--- a/plat/arm/css/sgm/sgm-common.mk
+++ b/plat/arm/css/sgm/sgm-common.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -25,6 +25,8 @@
SGM_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
drivers/arm/gic/v3/gicv3_main.c \
drivers/arm/gic/v3/gicv3_helpers.c \
+ drivers/arm/gic/v3/gicdv3_helpers.c \
+ drivers/arm/gic/v3/gicrv3_helpers.c \
plat/common/plat_gicv3.c \
plat/arm/common/arm_gicv3.c \
drivers/arm/gic/v3/gic600.c \
diff --git a/plat/imx/imx8m/imx8mm/platform.mk b/plat/imx/imx8m/imx8mm/platform.mk
index c0cb6c2..1ff576d 100644
--- a/plat/imx/imx8m/imx8mm/platform.mk
+++ b/plat/imx/imx8m/imx8mm/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -9,6 +9,8 @@
-Iplat/imx/imx8m/imx8mm/include
IMX_GIC_SOURCES := drivers/arm/gic/v3/gicv3_helpers.c \
+ drivers/arm/gic/v3/gicdv3_helpers.c \
+ drivers/arm/gic/v3/gicrv3_helpers.c \
drivers/arm/gic/v3/arm_gicv3_common.c \
drivers/arm/gic/v3/gic500.c \
drivers/arm/gic/v3/gicv3_main.c \
diff --git a/plat/imx/imx8m/imx8mq/platform.mk b/plat/imx/imx8m/imx8mq/platform.mk
index 80ebe40..e419f05 100644
--- a/plat/imx/imx8m/imx8mq/platform.mk
+++ b/plat/imx/imx8m/imx8mq/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -9,6 +9,8 @@
-Iplat/imx/imx8m/imx8mq/include
IMX_GIC_SOURCES := drivers/arm/gic/v3/gicv3_helpers.c \
+ drivers/arm/gic/v3/gicdv3_helpers.c \
+ drivers/arm/gic/v3/gicrv3_helpers.c \
drivers/arm/gic/v3/arm_gicv3_common.c \
drivers/arm/gic/v3/gic500.c \
drivers/arm/gic/v3/gicv3_main.c \
diff --git a/plat/imx/imx8qm/platform.mk b/plat/imx/imx8qm/platform.mk
index 3a772e5..5ba9c3f 100644
--- a/plat/imx/imx8qm/platform.mk
+++ b/plat/imx/imx8qm/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -8,6 +8,8 @@
-Iplat/imx/common/include \
IMX_GIC_SOURCES := drivers/arm/gic/v3/gicv3_helpers.c \
+ drivers/arm/gic/v3/gicdv3_helpers.c \
+ drivers/arm/gic/v3/gicrv3_helpers.c \
drivers/arm/gic/v3/arm_gicv3_common.c \
drivers/arm/gic/v3/gic500.c \
drivers/arm/gic/v3/gicv3_main.c \
diff --git a/plat/imx/imx8qx/platform.mk b/plat/imx/imx8qx/platform.mk
index d5629d1..5e8ba06 100644
--- a/plat/imx/imx8qx/platform.mk
+++ b/plat/imx/imx8qx/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -8,6 +8,8 @@
-Iplat/imx/common/include \
IMX_GIC_SOURCES := drivers/arm/gic/v3/gicv3_helpers.c \
+ drivers/arm/gic/v3/gicdv3_helpers.c \
+ drivers/arm/gic/v3/gicrv3_helpers.c \
drivers/arm/gic/v3/arm_gicv3_common.c \
drivers/arm/gic/v3/gic500.c \
drivers/arm/gic/v3/gicv3_main.c \
diff --git a/plat/marvell/a3700/common/a3700_common.mk b/plat/marvell/a3700/common/a3700_common.mk
index 1e27567..fd2b7ed 100644
--- a/plat/marvell/a3700/common/a3700_common.mk
+++ b/plat/marvell/a3700/common/a3700_common.mk
@@ -81,6 +81,8 @@
MARVELL_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
drivers/arm/gic/v3/gicv3_main.c \
drivers/arm/gic/v3/gicv3_helpers.c \
+ drivers/arm/gic/v3/gicdv3_helpers.c \
+ drivers/arm/gic/v3/gicrv3_helpers.c \
drivers/arm/gic/v3/arm_gicv3_common.c \
plat/common/plat_gicv3.c \
drivers/arm/gic/v3/gic500.c
diff --git a/plat/mediatek/mt8183/platform.mk b/plat/mediatek/mt8183/platform.mk
index 597e18b..59ffe5d 100644
--- a/plat/mediatek/mt8183/platform.mk
+++ b/plat/mediatek/mt8183/platform.mk
@@ -31,6 +31,8 @@
drivers/arm/gic/common/gic_common.c \
drivers/arm/gic/v3/arm_gicv3_common.c \
drivers/arm/gic/v3/gicv3_helpers.c \
+ drivers/arm/gic/v3/gicdv3_helpers.c \
+ drivers/arm/gic/v3/gicrv3_helpers.c \
drivers/arm/gic/v3/gic500.c \
drivers/arm/gic/v3/gicv3_main.c \
drivers/delay_timer/delay_timer.c \
diff --git a/plat/qemu/qemu/platform.mk b/plat/qemu/qemu/platform.mk
index 928d69a..6aa198c 100644
--- a/plat/qemu/qemu/platform.mk
+++ b/plat/qemu/qemu/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -140,6 +140,8 @@
${PLAT_QEMU_COMMON_PATH}/qemu_gicv2.c
QEMU_GICV3_SOURCES := drivers/arm/gic/v3/gicv3_helpers.c \
+ drivers/arm/gic/v3/gicdv3_helpers.c \
+ drivers/arm/gic/v3/gicrv3_helpers.c \
drivers/arm/gic/v3/gicv3_main.c \
drivers/arm/gic/common/gic_common.c \
plat/common/plat_gicv3.c \
diff --git a/plat/qemu/qemu_sbsa/platform.mk b/plat/qemu/qemu_sbsa/platform.mk
index 51832d0..6ad3d8b 100644
--- a/plat/qemu/qemu_sbsa/platform.mk
+++ b/plat/qemu/qemu_sbsa/platform.mk
@@ -63,6 +63,8 @@
endif
QEMU_GIC_SOURCES := drivers/arm/gic/v3/gicv3_helpers.c \
+ drivers/arm/gic/v3/gicdv3_helpers.c \
+ drivers/arm/gic/v3/gicrv3_helpers.c \
drivers/arm/gic/v3/gicv3_main.c \
drivers/arm/gic/common/gic_common.c \
plat/common/plat_gicv3.c \
diff --git a/plat/rockchip/rk3399/platform.mk b/plat/rockchip/rk3399/platform.mk
index 5a23d3c..0dc1840 100644
--- a/plat/rockchip/rk3399/platform.mk
+++ b/plat/rockchip/rk3399/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -29,6 +29,8 @@
drivers/arm/gic/v3/gic500.c \
drivers/arm/gic/v3/gicv3_main.c \
drivers/arm/gic/v3/gicv3_helpers.c \
+ drivers/arm/gic/v3/gicdv3_helpers.c \
+ drivers/arm/gic/v3/gicrv3_helpers.c \
plat/common/plat_gicv3.c \
${RK_PLAT}/common/rockchip_gicv3.c
diff --git a/plat/socionext/synquacer/platform.mk b/plat/socionext/synquacer/platform.mk
index ab1f69e..0d9071b 100644
--- a/plat/socionext/synquacer/platform.mk
+++ b/plat/socionext/synquacer/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -33,6 +33,8 @@
BL31_SOURCES += drivers/arm/ccn/ccn.c \
drivers/arm/gic/common/gic_common.c \
drivers/arm/gic/v3/gicv3_helpers.c \
+ drivers/arm/gic/v3/gicdv3_helpers.c \
+ drivers/arm/gic/v3/gicrv3_helpers.c \
drivers/arm/gic/v3/gicv3_main.c \
lib/cpus/aarch64/cortex_a53.S \
plat/common/plat_gicv3.c \
diff --git a/plat/socionext/uniphier/platform.mk b/plat/socionext/uniphier/platform.mk
index 8e96b68..a014f52 100644
--- a/plat/socionext/uniphier/platform.mk
+++ b/plat/socionext/uniphier/platform.mk
@@ -58,6 +58,8 @@
BL31_SOURCES += drivers/arm/cci/cci.c \
drivers/arm/gic/common/gic_common.c \
drivers/arm/gic/v3/gicv3_helpers.c \
+ drivers/arm/gic/v3/gicdv3_helpers.c \
+ drivers/arm/gic/v3/gicrv3_helpers.c \
drivers/arm/gic/v3/gicv3_main.c \
lib/cpus/aarch64/cortex_a53.S \
lib/cpus/aarch64/cortex_a72.S \
diff --git a/plat/ti/k3/common/plat_common.mk b/plat/ti/k3/common/plat_common.mk
index 7956497..587b44b 100644
--- a/plat/ti/k3/common/plat_common.mk
+++ b/plat/ti/k3/common/plat_common.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -57,6 +57,8 @@
drivers/arm/gic/common/gic_common.c \
drivers/arm/gic/v3/gicv3_main.c \
drivers/arm/gic/v3/gicv3_helpers.c \
+ drivers/arm/gic/v3/gicdv3_helpers.c \
+ drivers/arm/gic/v3/gicrv3_helpers.c \
plat/common/plat_gicv3.c \
${PLAT_PATH}/common/k3_gicv3.c \
diff --git a/plat/xilinx/versal/platform.mk b/plat/xilinx/versal/platform.mk
index 1e231cc..5d7fd69 100644
--- a/plat/xilinx/versal/platform.mk
+++ b/plat/xilinx/versal/platform.mk
@@ -52,6 +52,8 @@
drivers/arm/gic/v3/gic500.c \
drivers/arm/gic/v3/gicv3_main.c \
drivers/arm/gic/v3/gicv3_helpers.c \
+ drivers/arm/gic/v3/gicdv3_helpers.c \
+ drivers/arm/gic/v3/gicrv3_helpers.c \
drivers/arm/pl011/aarch64/pl011_console.S \
plat/common/aarch64/crash_console_helpers.S \
plat/arm/common/arm_cci.c \