mvebu: cp110: introduce COMPHY porting layer
Some of COMPHY parameters depends on the hw connection between the SoC
and the PHY, which can vary on different boards e.g. due to different
wires length. Define the "porting layer" with some defaults
parameters. It ease updating static values which needs to be updated due
to board differences, which are now grouped in one place.
Example porting layer for a8k-db is under:
plat/marvell/a8k/a80x0/board/phy-porting-layer.h
If for some boards parameters are not defined (missing
phy-porting-layer.h), the default values are used
(drivers/marvell/comphy/phy-default-porting-layer.h)
and the following compilation warning is show:
"Using default comphy params - you may need to suit them to your board".
The common COMPHY driver code is extracted in order to be shared with
future COMPHY driver for A3700 SoC platforms
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Igal Liberman <igall@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
diff --git a/drivers/marvell/comphy/phy-comphy-cp110.h b/drivers/marvell/comphy/phy-comphy-cp110.h
index 2461e5c..70dbfbf 100644
--- a/drivers/marvell/comphy/phy-comphy-cp110.h
+++ b/drivers/marvell/comphy/phy-comphy-cp110.h
@@ -5,7 +5,79 @@
* https://spdx.org/licenses
*/
-/* Marvell CP110 SoC COMPHY unit driver */
+/* Those are parameters for xfi mode, which need to be tune for each board type.
+ * For known DB boards the parameters was already calibrated and placed under
+ * the plat/marvell/a8k/<board_type>/board/phy-porting-layer.h
+ */
+struct xfi_params {
+ uint8_t g1_ffe_res_sel;
+ uint8_t g1_ffe_cap_sel;
+ uint8_t align90;
+ uint8_t g1_dfe_res;
+ uint8_t g1_amp;
+ uint8_t g1_emph;
+ uint8_t g1_emph_en;
+ uint8_t g1_tx_amp_adj;
+ uint8_t g1_tx_emph_en;
+ uint8_t g1_tx_emph;
+ uint8_t g1_rx_selmuff;
+ uint8_t g1_rx_selmufi;
+ uint8_t g1_rx_selmupf;
+ uint8_t g1_rx_selmupi;
+ _Bool valid;
+};
+
+struct sata_params {
+ uint8_t g1_amp;
+ uint8_t g2_amp;
+ uint8_t g3_amp;
+
+ uint8_t g1_emph;
+ uint8_t g2_emph;
+ uint8_t g3_emph;
+
+ uint8_t g1_emph_en;
+ uint8_t g2_emph_en;
+ uint8_t g3_emph_en;
+
+ uint8_t g1_tx_amp_adj;
+ uint8_t g2_tx_amp_adj;
+ uint8_t g3_tx_amp_adj;
+
+ uint8_t g1_tx_emph_en;
+ uint8_t g2_tx_emph_en;
+ uint8_t g3_tx_emph_en;
+
+ uint8_t g1_tx_emph;
+ uint8_t g2_tx_emph;
+ uint8_t g3_tx_emph;
+
+ uint8_t g3_dfe_res;
+
+ uint8_t g3_ffe_res_sel;
+
+ uint8_t g3_ffe_cap_sel;
+
+ uint8_t align90;
+
+ uint8_t g1_rx_selmuff;
+ uint8_t g2_rx_selmuff;
+ uint8_t g3_rx_selmuff;
+
+ uint8_t g1_rx_selmufi;
+ uint8_t g2_rx_selmufi;
+ uint8_t g3_rx_selmufi;
+
+ uint8_t g1_rx_selmupf;
+ uint8_t g2_rx_selmupf;
+ uint8_t g3_rx_selmupf;
+
+ uint8_t g1_rx_selmupi;
+ uint8_t g2_rx_selmupi;
+ uint8_t g3_rx_selmupi;
+
+ _Bool valid;
+};
int mvebu_cp110_comphy_is_pll_locked(uint64_t comphy_base,
uint8_t comphy_index);