fix(versal-net): setup counter frequency
Refactor the system counter configuration into the
syscnt_freq_config_setup() function as it involves timestamp and
system counter configuration, which requires early configuration for
clock setup and read the value of the IOU_SCNTRS_BASE_FREQ register
using mmio_read_32() to determine the counter frequency.
If the counter frequency is zero, the system will set the default CPU
clocks constants in TF-A and displays message. However, if the counter
frequency is non-zero, the program will return the value stored in the
IOU_SCNTRS_BASE_FREQ register.
The issue lies in dcc_status_timeout(),function verifying timeout
status, particularly within timeout_cnt_us2cnt(), converting
microseconds to counter ticks using read_cntfrq_el0(), which returns
zero. timeout_elapsed() then checks if the current counter from
read_cntpct_el0() exceeds the expiration count, reached to timeout.
After the function set_cnt_freq() writes into the counter frequency
register, the function timeout_cnt_us2cnt() is used to obtain the
appropriate counter ticks. Subsequently, the function timeout_elapsed()
checks whether the current counter value read_cntpct_el0() has
exceeded the specified expiration count. If it has, this indicates
that the timeout has lapsed.
Change-Id: Ib9ed3493d22f23c832f8bb7d11c4f727fe1ebe3c
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
diff --git a/plat/xilinx/versal_net/aarch64/versal_net_common.c b/plat/xilinx/versal_net/aarch64/versal_net_common.c
index 69c5c87..f0cbec1 100644
--- a/plat/xilinx/versal_net/aarch64/versal_net_common.c
+++ b/plat/xilinx/versal_net/aarch64/versal_net_common.c
@@ -114,6 +114,16 @@
void versal_net_config_setup(void)
{
+ generic_delay_timer_init();
+
+#if (TFA_NO_PM == 0)
+ /* Configure IPI data for versal_net */
+ versal_net_ipi_config_table_init();
+#endif
+}
+
+void syscnt_freq_config_setup(void)
+{
uint32_t val;
uintptr_t crl_base, iou_scntrs_base, psx_base;
@@ -137,16 +147,22 @@
cpu_clock);
mmio_write_32(iou_scntrs_base + VERSAL_NET_IOU_SCNTRS_COUNTER_CONTROL_REG_OFFSET,
VERSAL_NET_IOU_SCNTRS_CONTROL_EN);
-
- generic_delay_timer_init();
-
-#if (TFA_NO_PM == 0)
- /* Configure IPI data for versal_net */
- versal_net_ipi_config_table_init();
-#endif
}
uint32_t plat_get_syscnt_freq2(void)
{
- return cpu_clock;
+ uint32_t counter_freq = 0;
+ uint32_t ret = 0;
+
+ counter_freq = mmio_read_32(VERSAL_NET_IOU_SCNTRS +
+ VERSAL_NET_IOU_SCNTRS_BASE_FREQ_OFFSET);
+ if (counter_freq != 0U) {
+ ret = counter_freq;
+ } else {
+ INFO("Indicates counter frequency %dHz setting to %dHz\n",
+ counter_freq, cpu_clock);
+ ret = cpu_clock;
+ }
+
+ return ret;
}