refactor(tc): clarify msc0 DT node
This node specifies the location of the MPAM registers for the DSU.
Rename the node to clarify this.
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>
Change-Id: Ie870a7f31acbc44dd943e76896219b9bbdd7d5b4
diff --git a/fdts/tc-base.dtsi b/fdts/tc-base.dtsi
index 691a3b8..4623790 100644
--- a/fdts/tc-base.dtsi
+++ b/fdts/tc-base.dtsi
@@ -615,9 +615,9 @@
* L3 cache in the DSU is the Memory System Component (MSC)
* The MPAM registers are accessed through utility bus in the DSU
*/
- msc0 {
+ dsu-msc0 {
compatible = "arm,mpam-msc";
- reg = <MPAM_ADDR 0x0 0x2000>;
+ reg = <DSU_MPAM_ADDR 0x0 0x2000>;
};
ete0 {
diff --git a/fdts/tc2.dts b/fdts/tc2.dts
index 003efdc..8aa77ce 100644
--- a/fdts/tc2.dts
+++ b/fdts/tc2.dts
@@ -35,7 +35,7 @@
#define MID_CPU_PMU_COMPATIBLE "arm,cortex-a720-pmu"
#define BIG_CPU_PMU_COMPATIBLE "arm,cortex-x4-pmu"
-#define MPAM_ADDR 0x1 0x00010000 /* 0x1_0001_0000 */
+#define DSU_MPAM_ADDR 0x1 0x00010000 /* 0x1_0001_0000 */
#define DPU_ADDR 2cc00000
#define DPU_IRQ 69
diff --git a/fdts/tc3-4-base.dtsi b/fdts/tc3-4-base.dtsi
index 049a4c6..ef8713a 100644
--- a/fdts/tc3-4-base.dtsi
+++ b/fdts/tc3-4-base.dtsi
@@ -17,7 +17,7 @@
#define MHU_RX_INT_NUM 300
#define MHU_RX_INT_NAME "combined"
-#define MPAM_ADDR 0x0 0x5f010000 /* 0x5f01_0000 */
+#define DSU_MPAM_ADDR 0x0 0x5f010000 /* 0x5f01_0000 */
#if TARGET_FLAVOUR_FVP
#define DPU_ADDR 4000000000