Merge "feat(intel): update BL2 platform specific functions" into integration
diff --git a/plat/intel/soc/agilex5/bl2_plat_setup.c b/plat/intel/soc/agilex5/bl2_plat_setup.c
index b75c78c..6d0f183 100644
--- a/plat/intel/soc/agilex5/bl2_plat_setup.c
+++ b/plat/intel/soc/agilex5/bl2_plat_setup.c
@@ -68,8 +68,10 @@
boot_source_type boot_source = BOOT_SOURCE;
-void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1,
- u_register_t x2, u_register_t x4)
+void bl2_el3_early_platform_setup(u_register_t x0 __unused,
+ u_register_t x1 __unused,
+ u_register_t x2 __unused,
+ u_register_t x3 __unused)
{
static console_t console;
handoff reverse_handoff_ptr;
@@ -94,22 +96,41 @@
/* Get the handoff data */
if ((socfpga_get_handoff(&reverse_handoff_ptr)) != 0) {
- ERROR("BL2: Failed to get the correct handoff data\n");
+ ERROR("SOCFPGA: Failed to get the correct handoff data\n");
panic();
}
- config_clkmgr_handoff(&reverse_handoff_ptr);
+ /* Configure the pinmux */
+ config_pinmux(&reverse_handoff_ptr);
+
+ /* Configure the clock manager */
+ if ((config_clkmgr_handoff(&reverse_handoff_ptr)) != 0) {
+ ERROR("SOCFPGA: Failed to initialize the clock manager\n");
+ panic();
+ }
+
/* Configure power manager PSS SRAM power gate */
config_pwrmgr_handoff(&reverse_handoff_ptr);
/* Initialize the mailbox to enable communication between HPS and SDM */
mailbox_init();
+ /* Perform a handshake with certain peripherals before issuing a reset */
+ config_hps_hs_before_warm_reset();
+
+ /* TODO: watchdog init */
+ //watchdog_init(clkmgr_get_rate(CLKMGR_WDT_CLK_ID));
+
+ /* Initialize the CCU module for hardware cache coherency */
+ init_ncore_ccu();
+
+ socfpga_emac_init();
+
/* DDR and IOSSM driver init */
agilex5_ddr_init(&reverse_handoff_ptr);
if (combo_phy_init(&reverse_handoff_ptr) != 0) {
- ERROR("Combo Phy initialization failed\n");
+ ERROR("SOCFPGA: Combo Phy initialization failed\n");
}
/* Enable FPGA bridges as required */
diff --git a/plat/intel/soc/agilex5/include/agilex5_clock_manager.h b/plat/intel/soc/agilex5/include/agilex5_clock_manager.h
index 566a80d..91e21f7 100644
--- a/plat/intel/soc/agilex5/include/agilex5_clock_manager.h
+++ b/plat/intel/soc/agilex5/include/agilex5_clock_manager.h
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
+ * Copyright (c) 2024, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -142,7 +143,7 @@
uint32_t clk_freq_of_cb_intosc_ls;
} CLOCK_SOURCE_CONFIG;
-void config_clkmgr_handoff(handoff *hoff_ptr);
+int config_clkmgr_handoff(handoff *hoff_ptr);
uint32_t get_wdt_clk(void);
uint32_t get_uart_clk(void);
uint32_t get_mmc_clk(void);
diff --git a/plat/intel/soc/agilex5/soc/agilex5_clock_manager.c b/plat/intel/soc/agilex5/soc/agilex5_clock_manager.c
index fdf1a82..0bc7497 100644
--- a/plat/intel/soc/agilex5/soc/agilex5_clock_manager.c
+++ b/plat/intel/soc/agilex5/soc/agilex5_clock_manager.c
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
+ * Copyright (c) 2024, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -93,7 +94,7 @@
return rdata;
}
-void config_clkmgr_handoff(handoff *hoff_ptr)
+int config_clkmgr_handoff(handoff *hoff_ptr)
{
/* Take both PLL out of reset and power up */
@@ -129,6 +130,8 @@
CLKMGR_MAINPLL_EN_RESET);
mmio_write_32(CLKMGR_PERPLL + CLKMGR_PERPLL_EN,
CLKMGR_PERPLL_EN_RESET);
+
+ return 0;
}
/* Extract reference clock from platform clock source */