Merge "refactor(st): change method to get GIC base addresses" into integration
diff --git a/changelog.yaml b/changelog.yaml
index fd2a8ec..6a235cd 100644
--- a/changelog.yaml
+++ b/changelog.yaml
@@ -1146,6 +1146,9 @@
- title: TRDC
scope: imx-trdc
+ - title: Clock
+ scope: nxp-clk
+
- title: Renesas
scope: renesas-drivers
@@ -1413,6 +1416,9 @@
- title: Certificate Creation Tool
scope: cert-create
+ - title: Firmware Encryption Tool
+ scope: encrypt-fw
+
- title: Memory Mapping Tool
scope: memmap
diff --git a/common/feat_detect.c b/common/feat_detect.c
index 09088c9..8e3e3dd 100644
--- a/common/feat_detect.c
+++ b/common/feat_detect.c
@@ -289,7 +289,7 @@
* revisions so that we catch them as they come along
*/
check_feature(FEAT_STATE_ALWAYS, read_feat_pmuv3_id_field(),
- "PMUv3", 1, ID_AA64DFR0_PMUVER_PMUV3P7);
+ "PMUv3", 1, ID_AA64DFR0_PMUVER_PMUV3P8);
/* v8.1 features */
check_feature(ENABLE_FEAT_PAN, read_feat_pan_id_field(), "PAN", 1, 3);
diff --git a/docs/about/maintainers.rst b/docs/about/maintainers.rst
index 85cc612..cbed72f 100644
--- a/docs/about/maintainers.rst
+++ b/docs/about/maintainers.rst
@@ -767,6 +767,7 @@
:|M|: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
:|G|: `gprocopciucnxp`_
:|F|: docs/plat/s32g274a.rst
+:|F|: drivers/nxp/clk/s32cc
:|F|: drivers/nxp/console/linflex_console.S
:|F|: include/drivers/nxp/console/linflex.h
:|F|: plat/nxp/s32
diff --git a/docs/plat/arm/fvp/fvp-support.rst b/docs/plat/arm/fvp/fvp-support.rst
index c805c78..5292d68 100644
--- a/docs/plat/arm/fvp/fvp-support.rst
+++ b/docs/plat/arm/fvp/fvp-support.rst
@@ -9,25 +9,21 @@
(64-bit host machine only).
.. note::
- The FVP models used are Version 11.22 Build 14, unless otherwise stated.
+ The FVP models used are Version 11.26 Build 11, unless otherwise stated.
-- ``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502`` (Version 11.17/21)
-- ``FVP_Base_AEMv8A-GIC600AE`` (Version 11.17/21)
- ``FVP_Base_AEMvA``
- ``FVP_Base_AEMvA-AEMvA``
- ``FVP_Base_Cortex-A32x4``
- ``FVP_Base_Cortex-A35x4``
- ``FVP_Base_Cortex-A53x4``
- ``FVP_Base_Cortex-A55``
-- ``FVP_Base_Cortex-A55x4+Cortex-A75x4``
-- ``FVP_Base_Cortex-A55x4+Cortex-A76x2``
- ``FVP_Base_Cortex-A57x1-A53x1``
- ``FVP_Base_Cortex-A57x2-A53x4``
- ``FVP_Base_Cortex-A57x4``
- ``FVP_Base_Cortex-A57x4-A53x4``
-- ``FVP_Base_Cortex-A65``
-- ``FVP_Base_Cortex-A65AE``
-- ``FVP_Base_Cortex-A710x4`` (Version 11.17/21)
+- ``FVP_Base_Cortex-A65`` (Version 11.24/24)
+- ``FVP_Base_Cortex-A65AE`` (Version 11.24/24)
+- ``FVP_Base_Cortex-A710``
- ``FVP_Base_Cortex-A72x4``
- ``FVP_Base_Cortex-A72x4-A53x4``
- ``FVP_Base_Cortex-A73x4``
@@ -39,15 +35,15 @@
- ``FVP_Base_Cortex-A78``
- ``FVP_Base_Cortex-A78AE``
- ``FVP_Base_Cortex-A78C``
-- ``FVP_Base_Cortex-X2x4`` (Version 11.17/21)
-- ``FVP_Base_Neoverse-E1``
+- ``FVP_Base_Cortex-X2``
+- ``FVP_Base_Neoverse-E1`` (Version 11.24/24)
- ``FVP_Base_Neoverse-N1``
+- ``FVP_Base_Neoverse-N2``
- ``FVP_Base_Neoverse-V1``
- ``FVP_Base_RevC-2xAEMv8A``
- ``FVP_BaseR_AEMv8R``
- ``FVP_Morello`` (Version 0.11/33)
- ``FVP_RD_V1``
-- ``FVP_TC1``
- ``FVP_TC2`` (Version 11.23/17)
The latest version of the AArch32 build of TF-A has been tested on the
diff --git a/drivers/arm/mhu/mhu_wrapper_v3_x.c b/drivers/arm/mhu/mhu_wrapper_v3_x.c
index b3d51e3..3efd701 100644
--- a/drivers/arm/mhu/mhu_wrapper_v3_x.c
+++ b/drivers/arm/mhu/mhu_wrapper_v3_x.c
@@ -445,7 +445,7 @@
size_t mhu_get_max_message_size(void)
{
- enum mhu_v3_x_error_t err;
+ enum mhu_v3_x_error_t err __maybe_unused;
uint8_t num_channels;
err = mhu_v3_x_get_num_channel_implemented(&mhu_seh_dev,
diff --git a/drivers/auth/mbedtls/mbedtls_psa_crypto.c b/drivers/auth/mbedtls/mbedtls_psa_crypto.c
index 99242e3..2da97dc 100644
--- a/drivers/auth/mbedtls/mbedtls_psa_crypto.c
+++ b/drivers/auth/mbedtls/mbedtls_psa_crypto.c
@@ -446,7 +446,9 @@
*/
if (pk_alg == MBEDTLS_PK_RSASSA_PSS) {
rc = pk_bytes_from_subpubkey((unsigned char **) &pk_ptr, &pk_len);
- goto end2;
+ if (rc != 0) {
+ goto end2;
+ }
}
/* Get the key_id using import API */
diff --git a/drivers/nxp/clk/s32cc/s32cc_clk.mk b/drivers/nxp/clk/s32cc/s32cc_clk.mk
new file mode 100644
index 0000000..d1f940a
--- /dev/null
+++ b/drivers/nxp/clk/s32cc/s32cc_clk.mk
@@ -0,0 +1,12 @@
+#
+# Copyright 2024 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+CLK_SOURCES := \
+ ${PLAT_DRIVERS_PATH}/clk/s32cc/s32cc_clk_drv.c \
+
+ifeq (${BL_COMM_CLK_NEEDED},yes)
+BL2_SOURCES += ${CLK_SOURCES}
+endif
diff --git a/drivers/nxp/clk/s32cc/s32cc_clk_drv.c b/drivers/nxp/clk/s32cc/s32cc_clk_drv.c
new file mode 100644
index 0000000..8453000
--- /dev/null
+++ b/drivers/nxp/clk/s32cc/s32cc_clk_drv.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <errno.h>
+
+#include <drivers/clk.h>
+
+static int s32cc_clk_enable(unsigned long id)
+{
+ return -ENOTSUP;
+}
+
+static void s32cc_clk_disable(unsigned long id)
+{
+}
+
+static bool s32cc_clk_is_enabled(unsigned long id)
+{
+ return false;
+}
+
+static unsigned long s32cc_clk_get_rate(unsigned long id)
+{
+ return 0;
+}
+
+static int s32cc_clk_set_rate(unsigned long id, unsigned long rate,
+ unsigned long *orate)
+{
+ return -ENOTSUP;
+}
+
+static int s32cc_clk_get_parent(unsigned long id)
+{
+ return -ENOTSUP;
+}
+
+static int s32cc_clk_set_parent(unsigned long id, unsigned long parent_id)
+{
+ return -ENOTSUP;
+}
+
+void s32cc_clk_register_drv(void)
+{
+ static const struct clk_ops s32cc_clk_ops = {
+ .enable = s32cc_clk_enable,
+ .disable = s32cc_clk_disable,
+ .is_enabled = s32cc_clk_is_enabled,
+ .get_rate = s32cc_clk_get_rate,
+ .set_rate = s32cc_clk_set_rate,
+ .get_parent = s32cc_clk_get_parent,
+ .set_parent = s32cc_clk_set_parent,
+ };
+
+ clk_register(&s32cc_clk_ops);
+}
+
diff --git a/drivers/nxp/drivers.mk b/drivers/nxp/drivers.mk
index d77e985..761571d 100644
--- a/drivers/nxp/drivers.mk
+++ b/drivers/nxp/drivers.mk
@@ -97,3 +97,7 @@
ifeq (${IFC_NAND_NEEDED},yes)
include ${PLAT_DRIVERS_PATH}/ifc/nand/ifc_nand.mk
endif
+
+ifeq (${CLK_NEEDED},yes)
+include ${PLAT_DRIVERS_PATH}/clk/s32cc/s32cc_clk.mk
+endif
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h
index 4eb54ed..df0dcc3 100644
--- a/include/arch/aarch64/arch.h
+++ b/include/arch/aarch64/arch.h
@@ -238,7 +238,7 @@
#define ID_AA64DFR0_PMUVER_SHIFT U(8)
#define ID_AA64DFR0_PMUVER_MASK U(0xf)
#define ID_AA64DFR0_PMUVER_PMUV3 U(1)
-#define ID_AA64DFR0_PMUVER_PMUV3P7 U(7)
+#define ID_AA64DFR0_PMUVER_PMUV3P8 U(8)
#define ID_AA64DFR0_PMUVER_IMP_DEF U(0xf)
/* ID_AA64DFR0_EL1.SEBEP definitions */
diff --git a/include/arch/aarch64/el3_common_macros.S b/include/arch/aarch64/el3_common_macros.S
index 1a3e9b6..b4c5c1b 100644
--- a/include/arch/aarch64/el3_common_macros.S
+++ b/include/arch/aarch64/el3_common_macros.S
@@ -88,21 +88,8 @@
* MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug.
* Debug exceptions, other than Breakpoint Instruction exceptions, are
* disabled from all ELs in Secure state.
- *
- * MDCR_EL3.SPD32: Set to 0b10 to disable AArch32 Secure self-hosted
- * privileged debug from S-EL1.
- *
- * MDCR_EL3.TDOSA: Set to zero so that EL2 and EL2 System register
- * access to the powerdown debug registers do not trap to EL3.
- *
- * MDCR_EL3.TDA: Set to zero to allow EL0, EL1 and EL2 access to the
- * debug registers, other than those registers that are controlled by
- * MDCR_EL3.TDOSA.
*/
- mov_imm x0, ((MDCR_EL3_RESET_VAL | MDCR_SDD_BIT | \
- MDCR_SPD32(MDCR_SPD32_DISABLE)) & \
- ~(MDCR_TDOSA_BIT | MDCR_TDA_BIT))
-
+ mov_imm x0, (MDCR_EL3_RESET_VAL | MDCR_SDD_BIT)
msr mdcr_el3, x0
/* ---------------------------------------------------------------------
diff --git a/include/drivers/cadence/cdns_sdmmc.h b/include/drivers/cadence/cdns_sdmmc.h
index 6452725..8bf3b78 100644
--- a/include/drivers/cadence/cdns_sdmmc.h
+++ b/include/drivers/cadence/cdns_sdmmc.h
@@ -280,9 +280,6 @@
#define SDMMC_CDN(_reg) (SDMMC_CDN_REG_BASE + \
(SDMMC_CDN_##_reg))
-/* Refer to atf/tools/cert_create/include/debug.h */
-#define BIT_32(nr) (U(1) << (nr))
-
/* MMC Peripheral Definition */
#define SOCFPGA_MMC_BLOCK_SIZE U(8192)
#define SOCFPGA_MMC_BLOCK_MASK (SOCFPGA_MMC_BLOCK_SIZE - U(1))
diff --git a/include/lib/el3_runtime/aarch64/context.h b/include/lib/el3_runtime/aarch64/context.h
index 6f97bed..acf111b 100644
--- a/include/lib/el3_runtime/aarch64/context.h
+++ b/include/lib/el3_runtime/aarch64/context.h
@@ -63,19 +63,20 @@
#define CTX_ELR_EL3 U(0x20)
#define CTX_PMCR_EL0 U(0x28)
#define CTX_IS_IN_EL3 U(0x30)
+#define CTX_MDCR_EL3 U(0x38)
/* Constants required in supporting nested exception in EL3 */
-#define CTX_SAVED_ELR_EL3 U(0x38)
+#define CTX_SAVED_ELR_EL3 U(0x40)
/*
* General purpose flag, to save various EL3 states
* FFH mode : Used to identify if handling nested exception
* KFH mode : Used as counter value
*/
-#define CTX_NESTED_EA_FLAG U(0x40)
+#define CTX_NESTED_EA_FLAG U(0x48)
#if FFH_SUPPORT
- #define CTX_SAVED_ESR_EL3 U(0x48)
- #define CTX_SAVED_SPSR_EL3 U(0x50)
- #define CTX_SAVED_GPREG_LR U(0x58)
- #define CTX_EL3STATE_END U(0x60) /* Align to the next 16 byte boundary */
+ #define CTX_SAVED_ESR_EL3 U(0x50)
+ #define CTX_SAVED_SPSR_EL3 U(0x58)
+ #define CTX_SAVED_GPREG_LR U(0x60)
+ #define CTX_EL3STATE_END U(0x70) /* Align to the next 16 byte boundary */
#else
#define CTX_EL3STATE_END U(0x50) /* Align to the next 16 byte boundary */
#endif /* FFH_SUPPORT */
diff --git a/include/lib/extensions/brbe.h b/include/lib/extensions/brbe.h
index 194efba..425a037 100644
--- a/include/lib/extensions/brbe.h
+++ b/include/lib/extensions/brbe.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022-2023, Arm Limited. All rights reserved.
+ * Copyright (c) 2022-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,10 +7,12 @@
#ifndef BRBE_H
#define BRBE_H
+#include <context.h>
+
#if ENABLE_BRBE_FOR_NS
-void brbe_init_el3(void);
+void brbe_enable(cpu_context_t *ctx);
#else
-static inline void brbe_init_el3(void)
+static inline void brbe_enable(cpu_context_t *ctx)
{
}
#endif /* ENABLE_BRBE_FOR_NS */
diff --git a/include/lib/extensions/spe.h b/include/lib/extensions/spe.h
index 7b39037..c6e44f9 100644
--- a/include/lib/extensions/spe.h
+++ b/include/lib/extensions/spe.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -8,13 +8,14 @@
#define SPE_H
#include <stdbool.h>
+#include <context.h>
#if ENABLE_SPE_FOR_NS
-void spe_init_el3(void);
+void spe_enable(cpu_context_t *ctx);
void spe_init_el2_unused(void);
void spe_disable(void);
#else
-static inline void spe_init_el3(void)
+static inline void spe_enable(cpu_context_t *ctx)
{
}
static inline void spe_init_el2_unused(void)
diff --git a/include/lib/extensions/trbe.h b/include/lib/extensions/trbe.h
index 0bed433..5db3316 100644
--- a/include/lib/extensions/trbe.h
+++ b/include/lib/extensions/trbe.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,11 +7,13 @@
#ifndef TRBE_H
#define TRBE_H
+#include <context.h>
+
#if ENABLE_TRBE_FOR_NS
-void trbe_init_el3(void);
+void trbe_enable(cpu_context_t *ctx);
void trbe_init_el2_unused(void);
#else
-static inline void trbe_init_el3(void)
+static inline void trbe_enable(cpu_context_t *ctx)
{
}
static inline void trbe_init_el2_unused(void)
diff --git a/include/lib/extensions/trf.h b/include/lib/extensions/trf.h
index 1ac7cda..f0a946b 100644
--- a/include/lib/extensions/trf.h
+++ b/include/lib/extensions/trf.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,16 +7,32 @@
#ifndef TRF_H
#define TRF_H
+#include <context.h>
+
#if ENABLE_TRF_FOR_NS
-void trf_init_el3(void);
+
+#if __aarch64__
+void trf_enable(cpu_context_t *ctx);
void trf_init_el2_unused(void);
-#else
-static inline void trf_init_el3(void)
+#else /* !__aarch64 */
+void trf_init_el3(void);
+#endif /* __aarch64__ */
+
+#else /* ENABLE_TRF_FOR_NS=0 */
+
+#if __aarch64__
+static inline void trf_enable(cpu_context_t *ctx)
{
}
static inline void trf_init_el2_unused(void)
{
}
+#else /* !__aarch64 */
+static inline void trf_init_el3(void)
+{
+}
+#endif /* __aarch64__*/
+
#endif /* ENABLE_TRF_FOR_NS */
#endif /* TRF_H */
diff --git a/include/lib/utils_def.h b/include/lib/utils_def.h
index 8a03c7d..c3f767e 100644
--- a/include/lib/utils_def.h
+++ b/include/lib/utils_def.h
@@ -19,8 +19,13 @@
#define SIZE_FROM_LOG2_WORDS(n) (U(4) << (n))
+#if defined(__LINKER__) || defined(__ASSEMBLER__)
#define BIT_32(nr) (U(1) << (nr))
#define BIT_64(nr) (ULL(1) << (nr))
+#else
+#define BIT_32(nr) (((uint32_t)(1U)) << (nr))
+#define BIT_64(nr) (((uint64_t)(1ULL)) << (nr))
+#endif
#ifdef __aarch64__
#define BIT BIT_64
@@ -29,22 +34,22 @@
#endif
/*
- * Create a contiguous bitmask starting at bit position @l and ending at
- * position @h. For example
+ * Create a contiguous bitmask starting at bit position @low and ending at
+ * position @high. For example
* GENMASK_64(39, 21) gives us the 64bit vector 0x000000ffffe00000.
*/
#if defined(__LINKER__) || defined(__ASSEMBLER__)
-#define GENMASK_32(h, l) \
- (((0xFFFFFFFF) << (l)) & (0xFFFFFFFF >> (32 - 1 - (h))))
+#define GENMASK_32(high, low) \
+ (((0xFFFFFFFF) << (low)) & (0xFFFFFFFF >> (32 - 1 - (high))))
-#define GENMASK_64(h, l) \
- ((~0 << (l)) & (~0 >> (64 - 1 - (h))))
+#define GENMASK_64(high, low) \
+ ((~0 << (low)) & (~0 >> (64 - 1 - (high))))
#else
-#define GENMASK_32(h, l) \
- (((~UINT32_C(0)) << (l)) & (~UINT32_C(0) >> (32 - 1 - (h))))
+#define GENMASK_32(high, low) \
+ ((~UINT32_C(0) >> (32U - 1U - (high))) ^ ((BIT_32(low) - 1U)))
-#define GENMASK_64(h, l) \
- (((~UINT64_C(0)) << (l)) & (~UINT64_C(0) >> (64 - 1 - (h))))
+#define GENMASK_64(high, low) \
+ ((~UINT64_C(0) >> (64U - 1U - (high))) ^ ((BIT_64(low) - 1U)))
#endif
#ifdef __aarch64__
diff --git a/lib/el3_runtime/aarch64/context.S b/lib/el3_runtime/aarch64/context.S
index 76aebf9..1fce1bf 100644
--- a/lib/el3_runtime/aarch64/context.S
+++ b/lib/el3_runtime/aarch64/context.S
@@ -454,15 +454,17 @@
synchronize_errors
#endif /* IMAGE_BL31 */
- /* ----------------------------------------------------------
- * Restore SPSR_EL3, ELR_EL3 and SCR_EL3 prior to ERET
- * ----------------------------------------------------------
+ /* --------------------------------------------------------------
+ * Restore MDCR_EL3, SPSR_EL3, ELR_EL3 and SCR_EL3 prior to ERET
+ * --------------------------------------------------------------
*/
- ldr x18, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3]
ldp x16, x17, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
- msr scr_el3, x18
+ ldr x18, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3]
+ ldr x19, [sp, #CTX_EL3STATE_OFFSET + CTX_MDCR_EL3]
msr spsr_el3, x16
msr elr_el3, x17
+ msr scr_el3, x18
+ msr mdcr_el3, x19
restore_ptw_el1_sys_regs
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index 1937c30..981fddc 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -42,6 +42,7 @@
per_world_context_t per_world_context[CPU_DATA_CONTEXT_NUM];
static bool has_secure_perworld_init;
+static void manage_extensions_common(cpu_context_t *ctx);
static void manage_extensions_nonsecure(cpu_context_t *ctx);
static void manage_extensions_secure(cpu_context_t *ctx);
static void manage_extensions_secure_per_world(void);
@@ -261,13 +262,9 @@
#if CTX_INCLUDE_EL2_REGS
/*
- * Initialize SCTLR_EL2 context register using Endianness value
- * taken from the entrypoint attribute.
+ * Initialize SCTLR_EL2 context register with reset value.
*/
- u_register_t sctlr_el2_val = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL;
- sctlr_el2_val |= SCTLR_EL2_RES1;
- write_el2_ctx_common(get_el2_sysregs_ctx(ctx), sctlr_el2, sctlr_el2_val);
-
+ write_el2_ctx_common(get_el2_sysregs_ctx(ctx), sctlr_el2, SCTLR_EL2_RES1);
if (is_feat_hcx_supported()) {
/*
@@ -312,6 +309,7 @@
static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep)
{
u_register_t scr_el3;
+ u_register_t mdcr_el3;
el3_state_t *state;
gp_regs_t *gp_regs;
@@ -484,6 +482,37 @@
write_ctx_reg(state, CTX_ELR_EL3, ep->pc);
write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr);
+ /* Start with a clean MDCR_EL3 copy as all relevant values are set */
+ mdcr_el3 = MDCR_EL3_RESET_VAL;
+
+ /* ---------------------------------------------------------------------
+ * Initialise MDCR_EL3, setting all fields rather than relying on hw.
+ * Some fields are architecturally UNKNOWN on reset.
+ *
+ * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug.
+ * Debug exceptions, other than Breakpoint Instruction exceptions, are
+ * disabled from all ELs in Secure state.
+ *
+ * MDCR_EL3.SPD32: Set to 0b10 to disable AArch32 Secure self-hosted
+ * privileged debug from S-EL1.
+ *
+ * MDCR_EL3.TDOSA: Set to zero so that EL2 and EL2 System register
+ * access to the powerdown debug registers do not trap to EL3.
+ *
+ * MDCR_EL3.TDA: Set to zero to allow EL0, EL1 and EL2 access to the
+ * debug registers, other than those registers that are controlled by
+ * MDCR_EL3.TDOSA.
+ */
+ mdcr_el3 |= ((MDCR_SDD_BIT | MDCR_SPD32(MDCR_SPD32_DISABLE))
+ & ~(MDCR_TDA_BIT | MDCR_TDOSA_BIT)) ;
+ write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3);
+
+ /*
+ * Configure MDCR_EL3 register as applicable for each world
+ * (NS/Secure/Realm) context.
+ */
+ manage_extensions_common(ctx);
+
/*
* Store the X0-X7 value from the entrypoint into the context
* Use memcpy as we are in control of the layout of the structures
@@ -560,10 +589,6 @@
#if IMAGE_BL31
void cm_manage_extensions_el3(void)
{
- if (is_feat_spe_supported()) {
- spe_init_el3();
- }
-
if (is_feat_amu_supported()) {
amu_init_el3();
}
@@ -572,18 +597,6 @@
sme_init_el3();
}
- if (is_feat_trbe_supported()) {
- trbe_init_el3();
- }
-
- if (is_feat_brbe_supported()) {
- brbe_init_el3();
- }
-
- if (is_feat_trf_supported()) {
- trf_init_el3();
- }
-
pmuv3_init_el3();
}
#endif /* IMAGE_BL31 */
@@ -704,6 +717,48 @@
}
/*******************************************************************************
+ * Enable architecture extensions on first entry to Non-secure world only
+ * and disable for secure world.
+ *
+ * NOTE: Arch features which have been provided with the capability of getting
+ * enabled only for non-secure world and being disabled for secure world are
+ * grouped here, as the MDCR_EL3 context value remains same across the worlds.
+ ******************************************************************************/
+static void manage_extensions_common(cpu_context_t *ctx)
+{
+#if IMAGE_BL31
+ if (is_feat_spe_supported()) {
+ /*
+ * Enable FEAT_SPE for Non-Secure and prohibit for Secure state.
+ */
+ spe_enable(ctx);
+ }
+
+ if (is_feat_trbe_supported()) {
+ /*
+ * Enable FEAT_SPE for Non-Secure and prohibit for Secure and
+ * Realm state.
+ */
+ trbe_enable(ctx);
+ }
+
+ if (is_feat_trf_supported()) {
+ /*
+ * Enable FEAT_SPE for Non-Secure and prohibit for Secure state.
+ */
+ trf_enable(ctx);
+ }
+
+ if (is_feat_brbe_supported()) {
+ /*
+ * Enable FEAT_SPE for Non-Secure and prohibit for Secure state.
+ */
+ brbe_enable(ctx);
+ }
+#endif /* IMAGE_BL31 */
+}
+
+/*******************************************************************************
* Enable architecture extensions on first entry to Non-secure world.
******************************************************************************/
static void manage_extensions_nonsecure(cpu_context_t *ctx)
@@ -952,7 +1007,7 @@
******************************************************************************/
void cm_prepare_el3_exit(uint32_t security_state)
{
- u_register_t sctlr_elx, scr_el3;
+ u_register_t sctlr_el2, scr_el3;
cpu_context_t *ctx = cm_get_context(security_state);
assert(ctx != NULL);
@@ -993,20 +1048,17 @@
/* Condition to ensure EL2 is being used. */
if ((scr_el3 & SCR_HCE_BIT) != 0U) {
- /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */
- sctlr_elx = read_ctx_reg(get_el1_sysregs_ctx(ctx),
- CTX_SCTLR_EL1);
- sctlr_elx &= SCTLR_EE_BIT;
- sctlr_elx |= SCTLR_EL2_RES1;
+ /* Initialize SCTLR_EL2 register with reset value. */
+ sctlr_el2 = SCTLR_EL2_RES1;
#if ERRATA_A75_764081
/*
* If workaround of errata 764081 for Cortex-A75
* is used then set SCTLR_EL2.IESB to enable
* Implicit Error Synchronization Barrier.
*/
- sctlr_elx |= SCTLR_IESB_BIT;
-#endif /* ERRATA_A75_764081 */
- write_sctlr_el2(sctlr_elx);
+ sctlr_el2 |= SCTLR_IESB_BIT;
+#endif
+ write_sctlr_el2(sctlr_el2);
} else {
/*
* (scr_el3 & SCR_HCE_BIT==0)
diff --git a/lib/extensions/brbe/brbe.c b/lib/extensions/brbe/brbe.c
index 37bd834..dde0266 100644
--- a/lib/extensions/brbe/brbe.c
+++ b/lib/extensions/brbe/brbe.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022-2023, Arm Limited. All rights reserved.
+ * Copyright (c) 2022-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -9,9 +9,10 @@
#include <arch_helpers.h>
#include <lib/extensions/brbe.h>
-void brbe_init_el3(void)
+void brbe_enable(cpu_context_t *ctx)
{
- uint64_t val;
+ el3_state_t *state = get_el3state_ctx(ctx);
+ u_register_t mdcr_el3_val = read_ctx_reg(state, CTX_MDCR_EL3);
/*
* MDCR_EL3.SBRBE = 0b01
@@ -19,8 +20,7 @@
* Allows BRBE usage in non-secure world and prohibited in
* secure world.
*/
- val = read_mdcr_el3();
- val &= ~(MDCR_SBRBE_MASK << MDCR_SBRBE_SHIFT);
- val |= (0x1UL << MDCR_SBRBE_SHIFT);
- write_mdcr_el3(val);
+ mdcr_el3_val &= ~(MDCR_SBRBE_MASK << MDCR_SBRBE_SHIFT);
+ mdcr_el3_val |= (0x1UL << MDCR_SBRBE_SHIFT);
+ write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3_val);
}
diff --git a/lib/extensions/spe/spe.c b/lib/extensions/spe/spe.c
index d1fb182..c6076fe 100644
--- a/lib/extensions/spe/spe.c
+++ b/lib/extensions/spe/spe.c
@@ -29,9 +29,10 @@
__asm__ volatile("hint #17");
}
-void spe_init_el3(void)
+void spe_enable(cpu_context_t *ctx)
{
- uint64_t v;
+ el3_state_t *state = get_el3state_ctx(ctx);
+ u_register_t mdcr_el3_val = read_ctx_reg(state, CTX_MDCR_EL3);
/*
* MDCR_EL3.NSPB (ARM v8.2): SPE enabled in Non-secure state
@@ -46,10 +47,9 @@
* Setting this bit to 1 doesn't have any effect on it when
* FEAT_SPEv1p2 not implemented.
*/
- v = read_mdcr_el3();
- v |= MDCR_NSPB(MDCR_NSPB_EL1) | MDCR_EnPMSN_BIT;
- v &= ~(MDCR_NSPBE_BIT);
- write_mdcr_el3(v);
+ mdcr_el3_val |= MDCR_NSPB(MDCR_NSPB_EL1) | MDCR_EnPMSN_BIT;
+ mdcr_el3_val &= ~(MDCR_NSPBE_BIT);
+ write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3_val);
}
void spe_init_el2_unused(void)
diff --git a/lib/extensions/trbe/trbe.c b/lib/extensions/trbe/trbe.c
index d4fbdfb..9157734 100644
--- a/lib/extensions/trbe/trbe.c
+++ b/lib/extensions/trbe/trbe.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -19,9 +19,10 @@
__asm__ volatile("hint #18");
}
-void trbe_init_el3(void)
+void trbe_enable(cpu_context_t *ctx)
{
- u_register_t val;
+ el3_state_t *state = get_el3state_ctx(ctx);
+ u_register_t mdcr_el3_val = read_ctx_reg(state, CTX_MDCR_EL3);
/*
* MDCR_EL3.NSTBE = 0b0
@@ -33,10 +34,9 @@
* NS-EL2, tracing is prohibited in Secure and Realm state (if
* implemented).
*/
- val = read_mdcr_el3();
- val |= MDCR_NSTB(MDCR_NSTB_EL1);
- val &= ~(MDCR_NSTBE_BIT);
- write_mdcr_el3(val);
+ mdcr_el3_val |= MDCR_NSTB(MDCR_NSTB_EL1);
+ mdcr_el3_val &= ~(MDCR_NSTBE_BIT);
+ write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3_val);
}
void trbe_init_el2_unused(void)
diff --git a/lib/extensions/trf/aarch64/trf.c b/lib/extensions/trf/aarch64/trf.c
index 83fbf85..d36853a 100644
--- a/lib/extensions/trf/aarch64/trf.c
+++ b/lib/extensions/trf/aarch64/trf.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -9,9 +9,10 @@
#include <arch_helpers.h>
#include <lib/extensions/trf.h>
-void trf_init_el3(void)
+void trf_enable(cpu_context_t *ctx)
{
- u_register_t val;
+ el3_state_t *state = get_el3state_ctx(ctx);
+ u_register_t mdcr_el3_val = read_ctx_reg(state, CTX_MDCR_EL3);
/*
* MDCR_EL3.STE = b0
@@ -22,9 +23,8 @@
* Allow access of trace filter control registers from NS-EL2
* and NS-EL1 when NS-EL2 is implemented but not used
*/
- val = read_mdcr_el3();
- val &= ~(MDCR_STE_BIT | MDCR_TTRF_BIT);
- write_mdcr_el3(val);
+ mdcr_el3_val &= ~(MDCR_STE_BIT | MDCR_TTRF_BIT);
+ write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3_val);
}
void trf_init_el2_unused(void)
diff --git a/lib/gpt_rme/gpt_rme.c b/lib/gpt_rme/gpt_rme.c
index ee502de..d028fce 100644
--- a/lib/gpt_rme/gpt_rme.c
+++ b/lib/gpt_rme/gpt_rme.c
@@ -847,7 +847,7 @@
assert(GPT_L0_IDX(first) == GPT_L0_IDX(last));
#if (RME_GPT_MAX_BLOCK != 0)
- while (first < last) {
+ while (first <= last) {
/* Region length */
size_t length = last - first + GPT_PGS_ACTUAL_SIZE(gpt_config.p);
diff --git a/plat/arm/board/arm_fpga/platform.mk b/plat/arm/board/arm_fpga/platform.mk
index bf7c59b..82401db 100644
--- a/plat/arm/board/arm_fpga/platform.mk
+++ b/plat/arm/board/arm_fpga/platform.mk
@@ -41,8 +41,12 @@
ENABLE_FEAT_ECV := 2
ENABLE_FEAT_FGT := 2
ENABLE_FEAT_HCX := 2
+ENABLE_FEAT_MTE2 := 2
+ENABLE_FEAT_TCR2 := 2
ENABLE_SYS_REG_TRACE_FOR_NS := 2
ENABLE_TRF_FOR_NS := 2
+ENABLE_SME_FOR_NS := 2
+ENABLE_SME2_FOR_NS := 2
# Treating this as a memory-constrained port for now
USE_COHERENT_MEM := 0
diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk
index 7377a01..f5919ab 100644
--- a/plat/arm/common/arm_common.mk
+++ b/plat/arm/common/arm_common.mk
@@ -26,7 +26,7 @@
else ifeq (${ARM_TSP_RAM_LOCATION}, dram)
ARM_TSP_RAM_LOCATION_ID = ARM_DRAM_ID
else
- $(error "Unsupported ARM_TSP_RAM_LOCATION value")
+ $(error Unsupported ARM_TSP_RAM_LOCATION value)
endif
# Process flags
@@ -83,7 +83,7 @@
# memory. This means we must not run BL31 from TZC-protected DRAM.
ifeq (${ARM_BL31_IN_DRAM},1)
ifeq (${ENABLE_RME},1)
- $(error "BL31 must not run from DRAM on RME-systems. Please set ARM_BL31_IN_DRAM to 0")
+ $(error BL31 must not run from DRAM on RME-systems. Please set ARM_BL31_IN_DRAM to 0)
endif
endif
@@ -105,16 +105,15 @@
ifeq (${ARM_LINUX_KERNEL_AS_BL33},1)
ifneq (${ARCH},aarch64)
ifneq (${RESET_TO_SP_MIN},1)
- $(error "ARM_LINUX_KERNEL_AS_BL33 is only available if RESET_TO_SP_MIN=1.")
+ $(error ARM_LINUX_KERNEL_AS_BL33 is only available if RESET_TO_SP_MIN=1.)
endif
endif
ifndef PRELOADED_BL33_BASE
- $(error "PRELOADED_BL33_BASE must be set if ARM_LINUX_KERNEL_AS_BL33 is used.")
+ $(error PRELOADED_BL33_BASE must be set if ARM_LINUX_KERNEL_AS_BL33 is used.)
endif
ifeq (${RESET_TO_BL31},1)
ifndef ARM_PRELOADED_DTB_BASE
- $(error "ARM_PRELOADED_DTB_BASE must be set if ARM_LINUX_KERNEL_AS_BL33 is
- used with RESET_TO_BL31.")
+ $(error ARM_PRELOADED_DTB_BASE must be set if ARM_LINUX_KERNEL_AS_BL33 is used with RESET_TO_BL31.)
endif
$(eval $(call add_define,ARM_PRELOADED_DTB_BASE))
endif
@@ -456,6 +455,6 @@
ifeq (${RECLAIM_INIT_CODE}, 1)
ifeq (${ARM_XLAT_TABLES_LIB_V1}, 1)
- $(error "To reclaim init code xlat tables v2 must be used")
+ $(error To reclaim init code xlat tables v2 must be used)
endif
endif
diff --git a/plat/aspeed/ast2700/include/platform_def.h b/plat/aspeed/ast2700/include/platform_def.h
index 8be26c3..e668115 100644
--- a/plat/aspeed/ast2700/include/platform_def.h
+++ b/plat/aspeed/ast2700/include/platform_def.h
@@ -21,9 +21,6 @@
#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \
PLATFORM_CORE_COUNT_PER_CLUSTER)
-/* arch timer */
-#define PLAT_SYSCNT_CLKIN_HZ U(1600000000)
-
/* power domain */
#define PLAT_MAX_PWR_LVL U(1)
#define PLAT_NUM_PWR_DOMAINS U(5)
@@ -55,4 +52,12 @@
#define CONSOLE_UART_CLKIN_HZ U(1846153)
#define CONSOLE_UART_BAUDRATE U(115200)
+/* CLK information */
+#define CLKIN_25M UL(25000000)
+
+#define PLAT_CLK_GATE_NUM U(29)
+#define PLAT_CLK_HPLL (PLAT_CLK_GATE_NUM + 5)
+#define PLAT_CLK_DPLL (PLAT_CLK_GATE_NUM + 6)
+#define PLAT_CLK_MPLL (PLAT_CLK_GATE_NUM + 7)
+
#endif /* PLATFORM_DEF_H */
diff --git a/plat/aspeed/ast2700/include/platform_reg.h b/plat/aspeed/ast2700/include/platform_reg.h
index 7f26865..3c164a4 100644
--- a/plat/aspeed/ast2700/include/platform_reg.h
+++ b/plat/aspeed/ast2700/include/platform_reg.h
@@ -19,6 +19,10 @@
/* CPU-die SCU */
#define SCU_CPU_BASE U(0x12c02000)
+#define SCU_CPU_HW_STRAP1 (SCU_CPU_BASE + 0x010)
+#define SCU_CPU_HPLL (SCU_CPU_BASE + 0x300)
+#define SCU_CPU_DPLL (SCU_CPU_BASE + 0x308)
+#define SCU_CPU_MPLL (SCU_CPU_BASE + 0x310)
#define SCU_CPU_SMP_EP0 (SCU_CPU_BASE + 0x780)
#define SCU_CPU_SMP_EP1 (SCU_CPU_BASE + 0x788)
#define SCU_CPU_SMP_EP2 (SCU_CPU_BASE + 0x790)
diff --git a/plat/aspeed/ast2700/plat_bl31_setup.c b/plat/aspeed/ast2700/plat_bl31_setup.c
index 92a48ff..9fec3e8 100644
--- a/plat/aspeed/ast2700/plat_bl31_setup.c
+++ b/plat/aspeed/ast2700/plat_bl31_setup.c
@@ -4,6 +4,7 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
+#include <errno.h>
#include <arch.h>
#include <common/debug.h>
#include <common/desc_image_load.h>
@@ -112,3 +113,90 @@
return ep_info;
}
+
+/*
+ * Clock divider/multiplier configuration struct.
+ * For H-PLL and M-PLL the formula is
+ * (Output Frequency) = CLKIN * ((M + 1) / (N + 1)) / (P + 1)
+ * M - Numerator
+ * N - Denumerator
+ * P - Post Divider
+ * They have the same layout in their control register.
+ *
+ */
+union plat_pll_reg {
+ uint32_t w;
+ struct {
+ uint16_t m : 13; /* bit[12:0] */
+ uint8_t n : 6; /* bit[18:13] */
+ uint8_t p : 4; /* bit[22:19] */
+ uint8_t off : 1; /* bit[23] */
+ uint8_t bypass : 1; /* bit[24] */
+ uint8_t reset : 1; /* bit[25] */
+ uint8_t reserved : 6; /* bit[31:26] */
+ } b;
+};
+
+static uint32_t plat_get_pll_rate(int pll_idx)
+{
+ union plat_pll_reg pll_reg;
+ uint32_t mul = 1, div = 1;
+ uint32_t rate = 0;
+
+ switch (pll_idx) {
+ case PLAT_CLK_HPLL:
+ pll_reg.w = mmio_read_32(SCU_CPU_HPLL);
+ break;
+ case PLAT_CLK_DPLL:
+ pll_reg.w = mmio_read_32(SCU_CPU_DPLL);
+ break;
+ case PLAT_CLK_MPLL:
+ pll_reg.w = mmio_read_32(SCU_CPU_MPLL);
+ break;
+ default:
+ ERROR("%s: invalid PSP clock source (%d)\n", __func__, pll_idx);
+ return -EINVAL;
+ }
+
+ if (pll_idx == PLAT_CLK_HPLL && ((mmio_read_32(SCU_CPU_HW_STRAP1) & GENMASK(3, 2)) != 0U)) {
+ switch ((mmio_read_32(SCU_CPU_HW_STRAP1) & GENMASK(3, 2)) >> 2) {
+ case 1U:
+ rate = 1900000000;
+ break;
+ case 2U:
+ rate = 1800000000;
+ break;
+ case 3U:
+ rate = 1700000000;
+ break;
+ default:
+ rate = 2000000000;
+ break;
+ }
+ } else {
+ if (pll_reg.b.bypass != 0U) {
+ if (pll_idx == PLAT_CLK_MPLL) {
+ /* F = 25Mhz * [M / (n + 1)] / (p + 1) */
+ mul = (pll_reg.b.m) / ((pll_reg.b.n + 1));
+ div = (pll_reg.b.p + 1);
+ } else {
+ /* F = 25Mhz * [(M + 2) / 2 * (n + 1)] / (p + 1) */
+ mul = (pll_reg.b.m + 1) / ((pll_reg.b.n + 1) * 2);
+ div = (pll_reg.b.p + 1);
+ }
+ }
+
+ rate = ((CLKIN_25M * mul) / div);
+ }
+
+ return rate;
+}
+
+unsigned int plat_get_syscnt_freq2(void)
+{
+ if (mmio_read_32(SCU_CPU_HW_STRAP1) & BIT(4)) {
+ return plat_get_pll_rate(PLAT_CLK_HPLL);
+ } else {
+ return plat_get_pll_rate(PLAT_CLK_MPLL);
+ }
+}
diff --git a/plat/aspeed/ast2700/plat_helpers.S b/plat/aspeed/ast2700/plat_helpers.S
index c6d987e..e4a283c 100644
--- a/plat/aspeed/ast2700/plat_helpers.S
+++ b/plat/aspeed/ast2700/plat_helpers.S
@@ -59,12 +59,6 @@
br x0
endfunc plat_secondary_cold_boot_setup
-/* unsigned int plat_get_syscnt_freq2(void); */
-func plat_get_syscnt_freq2
- mov_imm w0, PLAT_SYSCNT_CLKIN_HZ
- ret
-endfunc plat_get_syscnt_freq2
-
/* int plat_crash_console_init(void); */
func plat_crash_console_init
mov_imm x0, CONSOLE_UART_BASE
diff --git a/plat/mediatek/drivers/gic600/mt_gic_v3.c b/plat/mediatek/drivers/gic600/mt_gic_v3.c
index 85f9e37..2f9765c 100644
--- a/plat/mediatek/drivers/gic600/mt_gic_v3.c
+++ b/plat/mediatek/drivers/gic600/mt_gic_v3.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2020-2024, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -27,6 +27,10 @@
/* we save and restore the GICv3 context on system suspend */
gicv3_dist_ctx_t dist_ctx;
+static const interrupt_prop_t mtk_interrupt_props[] = {
+ PLAT_MTK_G1S_IRQ_PROPS(INTR_GROUP1S)
+};
+
static unsigned int mt_mpidr_to_core_pos(u_register_t mpidr)
{
return plat_core_pos_by_mpidr(mpidr);
@@ -35,6 +39,8 @@
gicv3_driver_data_t mt_gicv3_data = {
.gicd_base = MT_GIC_BASE,
.gicr_base = MT_GIC_RDIST_BASE,
+ .interrupt_props = mtk_interrupt_props,
+ .interrupt_props_num = ARRAY_SIZE(mtk_interrupt_props),
.rdistif_num = PLATFORM_CORE_COUNT,
.rdistif_base_addrs = rdistif_base_addrs,
.mpidr_to_core_pos = mt_mpidr_to_core_pos,
diff --git a/plat/mediatek/mt8186/include/platform_def.h b/plat/mediatek/mt8186/include/platform_def.h
index 850ce2f..98b88bd 100644
--- a/plat/mediatek/mt8186/include/platform_def.h
+++ b/plat/mediatek/mt8186/include/platform_def.h
@@ -1,6 +1,6 @@
/*
- * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved.
- * Copyright (c) 2021-2022, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2021-2024, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2024, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -83,6 +83,8 @@
#define BASE_GICD_BASE MT_GIC_BASE
#define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000)
+#define PLAT_MTK_G1S_IRQ_PROPS(grp)
+
#define SYS_CIRQ_BASE (IO_PHYS + 0x204000)
#define CIRQ_REG_NUM (11)
#define CIRQ_IRQ_NUM (326)
diff --git a/plat/mediatek/mt8188/include/platform_def.h b/plat/mediatek/mt8188/include/platform_def.h
index 71a4e97..8e0f5f9 100644
--- a/plat/mediatek/mt8188/include/platform_def.h
+++ b/plat/mediatek/mt8188/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2022-2024, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -96,6 +96,11 @@
/* Base MTK_platform compatible GIC memory map */
#define BASE_GICD_BASE (MT_GIC_BASE)
#define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000)
+#define DEV_IRQ_ID 580
+
+#define PLAT_MTK_G1S_IRQ_PROPS(grp) \
+ INTR_PROP_DESC(DEV_IRQ_ID, GIC_HIGHEST_SEC_PRIORITY, grp, \
+ GIC_INTR_CFG_LEVEL)
/*******************************************************************************
* CIRQ related constants
diff --git a/plat/mediatek/mt8192/include/platform_def.h b/plat/mediatek/mt8192/include/platform_def.h
index ec377b5..1b25e00 100644
--- a/plat/mediatek/mt8192/include/platform_def.h
+++ b/plat/mediatek/mt8192/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020-2024, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -82,6 +82,8 @@
#define BASE_GICD_BASE MT_GIC_BASE
#define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000)
+#define PLAT_MTK_G1S_IRQ_PROPS(grp)
+
#define SYS_CIRQ_BASE (IO_PHYS + 0x204000)
#define CIRQ_REG_NUM 14
#define CIRQ_IRQ_NUM 439
diff --git a/plat/mediatek/mt8195/include/platform_def.h b/plat/mediatek/mt8195/include/platform_def.h
index 8696f2a..a70abec 100644
--- a/plat/mediatek/mt8195/include/platform_def.h
+++ b/plat/mediatek/mt8195/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2024, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -95,6 +95,11 @@
/* Base MTK_platform compatible GIC memory map */
#define BASE_GICD_BASE MT_GIC_BASE
#define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000)
+#define DEV_IRQ_ID 580
+
+#define PLAT_MTK_G1S_IRQ_PROPS(grp) \
+ INTR_PROP_DESC(DEV_IRQ_ID, GIC_HIGHEST_SEC_PRIORITY, grp, \
+ GIC_INTR_CFG_LEVEL)
#define SYS_CIRQ_BASE (IO_PHYS + 0x204000)
#define CIRQ_REG_NUM 23
diff --git a/plat/nxp/s32/s32g274ardb2/platform.mk b/plat/nxp/s32/s32g274ardb2/platform.mk
index ee1507e..316ed2c 100644
--- a/plat/nxp/s32/s32g274ardb2/platform.mk
+++ b/plat/nxp/s32/s32g274ardb2/platform.mk
@@ -35,6 +35,7 @@
# Selecting Drivers for SoC
$(eval $(call SET_NXP_MAKE_FLAG,CONSOLE_NEEDED,BL_COMM))
+$(eval $(call SET_NXP_MAKE_FLAG,CLK_NEEDED,BL_COMM))
include ${PLAT_DRIVERS_PATH}/drivers.mk
diff --git a/plat/qemu/qemu_sbsa/sbsa_sip_svc.c b/plat/qemu/qemu_sbsa/sbsa_sip_svc.c
index 535f0eb..83e66f3 100644
--- a/plat/qemu/qemu_sbsa/sbsa_sip_svc.c
+++ b/plat/qemu/qemu_sbsa/sbsa_sip_svc.c
@@ -30,6 +30,7 @@
#define SIP_SVC_GET_GIC_ITS SIP_FUNCTION_ID(101)
#define SIP_SVC_GET_CPU_COUNT SIP_FUNCTION_ID(200)
#define SIP_SVC_GET_CPU_NODE SIP_FUNCTION_ID(201)
+#define SIP_SVC_GET_CPU_TOPOLOGY SIP_FUNCTION_ID(202)
#define SIP_SVC_GET_MEMORY_NODE_COUNT SIP_FUNCTION_ID(300)
#define SIP_SVC_GET_MEMORY_NODE SIP_FUNCTION_ID(301)
@@ -46,10 +47,24 @@
uint64_t addr_size;
} memory_data;
+/*
+ * sockets: the number of sockets on sbsa-ref platform.
+ * clusters: the number of clusters in one socket.
+ * cores: the number of cores in one cluster.
+ * threads: the number of threads in one core.
+ */
+typedef struct {
+ uint32_t sockets;
+ uint32_t clusters;
+ uint32_t cores;
+ uint32_t threads;
+} cpu_topology;
+
static struct {
uint32_t num_cpus;
uint32_t num_memnodes;
cpu_data cpu[PLATFORM_CORE_COUNT];
+ cpu_topology cpu_topo;
memory_data memory[PLAT_MAX_MEM_NODES];
} dynamic_platform_info;
@@ -71,12 +86,46 @@
* cope.
*/
+static void read_cpu_topology_from_dt(void *dtb)
+{
+ int node;
+
+ /*
+ * QEMU gives us this DeviceTree node when we config:
+ * -smp 16,sockets=2,clusters=2,cores=2,threads=2
+ *
+ * topology {
+ * threads = <0x02>;
+ * cores = <0x02>;
+ * clusters = <0x02>;
+ * sockets = <0x02>;
+ * };
+ */
+
+ node = fdt_path_offset(dtb, "/cpus/topology");
+ if (node > 0) {
+ dynamic_platform_info.cpu_topo.sockets =
+ fdt_read_uint32_default(dtb, node, "sockets", 0);
+ dynamic_platform_info.cpu_topo.clusters =
+ fdt_read_uint32_default(dtb, node, "clusters", 0);
+ dynamic_platform_info.cpu_topo.cores =
+ fdt_read_uint32_default(dtb, node, "cores", 0);
+ dynamic_platform_info.cpu_topo.threads =
+ fdt_read_uint32_default(dtb, node, "threads", 0);
+ }
+
+ INFO("Cpu topology: sockets: %d, clusters: %d, cores: %d, threads: %d\n",
+ dynamic_platform_info.cpu_topo.sockets,
+ dynamic_platform_info.cpu_topo.clusters,
+ dynamic_platform_info.cpu_topo.cores,
+ dynamic_platform_info.cpu_topo.threads);
+}
+
void read_cpuinfo_from_dt(void *dtb)
{
int node;
int prev;
int cpu = 0;
- uint32_t nodeid = 0;
uintptr_t mpidr;
/*
@@ -118,14 +167,12 @@
panic();
}
- if (fdt_getprop(dtb, node, "numa-node-id", NULL)) {
- fdt_read_uint32(dtb, node, "numa-node-id", &nodeid);
- }
-
- dynamic_platform_info.cpu[cpu].nodeid = nodeid;
dynamic_platform_info.cpu[cpu].mpidr = mpidr;
+ dynamic_platform_info.cpu[cpu].nodeid =
+ fdt_read_uint32_default(dtb, node, "numa-node-id", 0);
- INFO("CPU %d: node-id: %d, mpidr: %ld\n", cpu, nodeid, mpidr);
+ INFO("CPU %d: node-id: %d, mpidr: %ld\n", cpu,
+ dynamic_platform_info.cpu[cpu].nodeid, mpidr);
cpu++;
@@ -135,6 +182,8 @@
dynamic_platform_info.num_cpus = cpu;
INFO("Found %d cpus\n", dynamic_platform_info.num_cpus);
+
+ read_cpu_topology_from_dt(dtb);
}
void read_meminfo_from_dt(void *dtb)
@@ -143,7 +192,6 @@
const char *type;
int prev, node;
int len;
- uint32_t nodeid = 0;
uint32_t memnode = 0;
uint32_t higher_value, lower_value;
uint64_t cur_base, cur_size;
@@ -172,11 +220,8 @@
type = fdt_getprop(dtb, node, "device_type", &len);
if (type && strncmp(type, "memory", len) == 0) {
- if (fdt_getprop(dtb, node, "numa-node-id", NULL)) {
- fdt_read_uint32(dtb, node, "numa-node-id", &nodeid);
- }
-
- dynamic_platform_info.memory[memnode].nodeid = nodeid;
+ dynamic_platform_info.memory[memnode].nodeid =
+ fdt_read_uint32_default(dtb, node, "numa-node-id", 0);
/*
* Get the 'reg' property of this node and
@@ -274,10 +319,10 @@
node = fdt_path_offset(dtb, "/");
if (node >= 0) {
- platform_version_major = fdt32_ld(fdt_getprop(dtb, node,
- "machine-version-major", NULL));
- platform_version_minor = fdt32_ld(fdt_getprop(dtb, node,
- "machine-version-minor", NULL));
+ platform_version_major =
+ fdt_read_uint32_default(dtb, node, "machine-version-major", 0);
+ platform_version_minor =
+ fdt_read_uint32_default(dtb, node, "machine-version-minor", 0);
}
}
@@ -354,6 +399,18 @@
SMC_RET1(handle, SMC_ARCH_CALL_INVAL_PARAM);
}
+ case SIP_SVC_GET_CPU_TOPOLOGY:
+ if (dynamic_platform_info.cpu_topo.cores > 0) {
+ SMC_RET5(handle, NULL,
+ dynamic_platform_info.cpu_topo.sockets,
+ dynamic_platform_info.cpu_topo.clusters,
+ dynamic_platform_info.cpu_topo.cores,
+ dynamic_platform_info.cpu_topo.threads);
+ } else {
+ /* we do not know topology so we report SMC as unknown */
+ SMC_RET1(handle, SMC_UNK);
+ }
+
case SIP_SVC_GET_MEMORY_NODE_COUNT:
SMC_RET2(handle, NULL, dynamic_platform_info.num_memnodes);
diff --git a/plat/xilinx/versal/bl31_versal_setup.c b/plat/xilinx/versal/bl31_versal_setup.c
index 08c0205..594784f 100644
--- a/plat/xilinx/versal/bl31_versal_setup.c
+++ b/plat/xilinx/versal/bl31_versal_setup.c
@@ -118,19 +118,6 @@
panic();
} else {
INFO("BL31: PLM to TF-A handover success %u\n", ret);
-
- /*
- * The BL32 load address is indicated as 0x0 in the handoff
- * parameters, which is different from the default/user-provided
- * load address of 0x60000000 but the flags are correctly
- * configured. Consequently, in this scenario, set the PC
- * to the requested BL32_BASE address.
- */
-
- /* TODO: Remove the following check once this is fixed from PLM */
- if (bl32_image_ep_info.pc == 0 && bl32_image_ep_info.spsr != 0) {
- bl32_image_ep_info.pc = (uintptr_t)BL32_BASE;
- }
}
NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc);
diff --git a/plat/xilinx/versal_net/bl31_versal_net_setup.c b/plat/xilinx/versal_net/bl31_versal_net_setup.c
index d6390e2..5af2b1d 100644
--- a/plat/xilinx/versal_net/bl31_versal_net_setup.c
+++ b/plat/xilinx/versal_net/bl31_versal_net_setup.c
@@ -153,18 +153,6 @@
INFO("BL31: PLM to TF-A handover success\n");
- /*
- * The BL32 load address is indicated as 0x0 in the handoff
- * parameters, which is different from the default/user-provided
- * load address of 0x60000000 but the flags are correctly
- * configured. Consequently, in this scenario, set the PC
- * to the requested BL32_BASE address.
- */
-
- /* TODO: Remove the following check once this is fixed from PLM */
- if (bl32_image_ep_info.pc == 0 && bl32_image_ep_info.spsr != 0) {
- bl32_image_ep_info.pc = (uintptr_t)BL32_BASE;
- }
} else {
INFO("BL31: setting up default configs\n");
diff --git a/plat/xilinx/zynqmp/platform.mk b/plat/xilinx/zynqmp/platform.mk
index e266615..3a752b2 100644
--- a/plat/xilinx/zynqmp/platform.mk
+++ b/plat/xilinx/zynqmp/platform.mk
@@ -2,7 +2,7 @@
# Copyright (c) 2013-2021, Arm Limited and Contributors. All rights reserved.
# Portions copyright (c) 2021-2022, ProvenRun S.A.S. All rights reserved.
# Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved.
-# Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
@@ -16,6 +16,7 @@
IPI_CRC_CHECK := 0
override RESET_TO_BL31 := 1
override WARMBOOT_ENABLE_DCACHE_EARLY := 1
+ENABLE_LTO := 1
EL3_EXCEPTION_HANDLING := $(SDEI_SUPPORT)
diff --git a/tools/cert_create/Makefile b/tools/cert_create/Makefile
index 7670939..16f4aa3 100644
--- a/tools/cert_create/Makefile
+++ b/tools/cert_create/Makefile
@@ -18,6 +18,7 @@
include ${MAKE_HELPERS_DIRECTORY}common.mk
include ${MAKE_HELPERS_DIRECTORY}defaults.mk
include ${MAKE_HELPERS_DIRECTORY}toolchain.mk
+include ${MAKE_HELPERS_DIRECTORY}utilities.mk
ifneq (${PLAT},none)
TF_PLATFORM_ROOT := ../../plat/
@@ -60,7 +61,7 @@
HOSTCCFLAGS += -O2 -DLOG_LEVEL=20
endif
-HOSTCCFLAGS += ${DEFINES}
+HOSTCCFLAGS += ${DEFINES} -DPLAT_MSG=$(call escape-shell,"$(PLAT_MSG)")
# USING_OPENSSL3 flag will be added to the HOSTCCFLAGS variable with the proper
# computed value.
HOSTCCFLAGS += -DUSING_OPENSSL3=$(USING_OPENSSL3)
@@ -84,10 +85,7 @@
${BINARY}: ${OBJECTS} Makefile
$(s)echo " HOSTLD $@"
- $(q)echo 'const char build_msg[] = "Built : "__TIME__", "__DATE__; \
- const char platform_msg[] = "${PLAT_MSG}";' | \
- $(host-cc) -c ${HOSTCCFLAGS} -xc - -o src/build_msg.o
- $(q)$(host-cc) src/build_msg.o ${OBJECTS} ${LIB_DIR} ${LIB} -o $@
+ $(q)$(host-cc) ${OBJECTS} ${LIB_DIR} ${LIB} -o $@
%.o: %.c
$(s)echo " HOSTCC $<"
@@ -99,7 +97,7 @@
endif
clean:
- $(call SHELL_DELETE_ALL, src/build_msg.o ${OBJECTS})
+ $(call SHELL_DELETE_ALL,${OBJECTS})
realclean: clean
$(call SHELL_DELETE,${BINARY})
diff --git a/tools/cert_create/src/main.c b/tools/cert_create/src/main.c
index 14610ed..edc2d68 100644
--- a/tools/cert_create/src/main.c
+++ b/tools/cert_create/src/main.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -66,10 +66,8 @@
static int save_keys;
static int print_cert;
-/* Info messages created in the Makefile */
-extern const char build_msg[];
-extern const char platform_msg[];
-
+static const char build_msg[] = "Built : " __TIME__ ", " __DATE__;
+static const char platform_msg[] = PLAT_MSG;
static char *strdup(const char *str)
{
diff --git a/tools/encrypt_fw/Makefile b/tools/encrypt_fw/Makefile
index 21309f7..0210c36 100644
--- a/tools/encrypt_fw/Makefile
+++ b/tools/encrypt_fw/Makefile
@@ -1,4 +1,5 @@
#
+# Copyright (c) 2024, Arm Limited. All rights reserved.
# Copyright (c) 2019-2022, Linaro Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
@@ -64,9 +65,7 @@
${BINARY}: ${OBJECTS} Makefile
$(s)echo " HOSTLD $@"
- $(q)echo 'const char build_msg[] = "Built : "__TIME__", "__DATE__;' | \
- $(host-cc) -c ${HOSTCCFLAGS} -xc - -o src/build_msg.o
- $(q)$(host-cc) src/build_msg.o ${OBJECTS} ${LIB_DIR} ${LIB} -o $@
+ $(q)$(host-cc) ${OBJECTS} ${LIB_DIR} ${LIB} -o $@
%.o: %.c
$(s)echo " HOSTCC $<"
@@ -78,7 +77,7 @@
endif
clean:
- $(call SHELL_DELETE_ALL, src/build_msg.o ${OBJECTS})
+ $(call SHELL_DELETE_ALL,${OBJECTS})
realclean: clean
$(call SHELL_DELETE,${BINARY})
diff --git a/tools/encrypt_fw/src/main.c b/tools/encrypt_fw/src/main.c
index 39b7af7..6e43e73 100644
--- a/tools/encrypt_fw/src/main.c
+++ b/tools/encrypt_fw/src/main.c
@@ -1,4 +1,5 @@
/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2019, Linaro Limited. All rights reserved.
* Author: Sumit Garg <sumit.garg@linaro.org>
*
@@ -25,8 +26,7 @@
/* Global options */
-/* Info messages created in the Makefile */
-extern const char build_msg[];
+static const char build_msg[] = "Built : " __TIME__ ", " __DATE__;
static char *key_algs_str[] = {
[KEY_ALG_GCM] = "gcm",