Merge "feat(common): add SZ_* macros" into integration
diff --git a/Makefile b/Makefile
index a238ee4..1baacf0 100644
--- a/Makefile
+++ b/Makefile
@@ -277,6 +277,10 @@
ENABLE_FEAT_ECV = 1
endif
+ifeq "8.4" "$(word 1, $(sort 8.4 $(ARM_ARCH_MAJOR).$(ARM_ARCH_MINOR)))"
+ENABLE_FEAT_DIT = 1
+endif
+
ifneq ($(findstring armclang,$(notdir $(CC))),)
TF_CFLAGS_aarch32 = -target arm-arm-none-eabi $(march32-directive)
TF_CFLAGS_aarch64 = -target aarch64-arm-none-eabi $(march64-directive)
@@ -1040,6 +1044,7 @@
USE_SP804_TIMER \
ENABLE_FEAT_RNG \
ENABLE_FEAT_SB \
+ ENABLE_FEAT_DIT \
PSA_FWU_SUPPORT \
ENABLE_TRBE_FOR_NS \
ENABLE_SYS_REG_TRACE_FOR_NS \
@@ -1154,6 +1159,7 @@
USE_SP804_TIMER \
ENABLE_FEAT_RNG \
ENABLE_FEAT_SB \
+ ENABLE_FEAT_DIT \
NR_OF_FW_BANKS \
NR_OF_IMAGES_IN_FW_BANK \
PSA_FWU_SUPPORT \
diff --git a/bl1/aarch64/bl1_exceptions.S b/bl1/aarch64/bl1_exceptions.S
index 9dc9e6c..c54219f 100644
--- a/bl1/aarch64/bl1_exceptions.S
+++ b/bl1/aarch64/bl1_exceptions.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -224,7 +224,7 @@
* TODO: Revisit to store only SMCCC specified registers.
* -----------------------------------------------------
*/
- bl save_gp_pmcr_pauth_regs
+ bl prepare_el3_entry
#if ENABLE_PAUTH
/* -----------------------------------------------------
diff --git a/bl31/aarch64/ea_delegate.S b/bl31/aarch64/ea_delegate.S
index f9c789f..fa6ede8 100644
--- a/bl31/aarch64/ea_delegate.S
+++ b/bl31/aarch64/ea_delegate.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -92,8 +92,9 @@
* Save general purpose and ARMv8.3-PAuth registers (if enabled).
* If Secure Cycle Counter is not disabled in MDCR_EL3 when
* ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter.
+ * Also set the PSTATE to a known state.
*/
- bl save_gp_pmcr_pauth_regs
+ bl prepare_el3_entry
#if ENABLE_PAUTH
/* Load and program APIAKey firmware key */
@@ -139,8 +140,9 @@
* Save general purpose and ARMv8.3-PAuth registers (if enabled).
* If Secure Cycle Counter is not disabled in MDCR_EL3 when
* ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter.
+ * Also set the PSTATE to a known state.
*/
- bl save_gp_pmcr_pauth_regs
+ bl prepare_el3_entry
#if ENABLE_PAUTH
/* Load and program APIAKey firmware key */
diff --git a/bl31/aarch64/runtime_exceptions.S b/bl31/aarch64/runtime_exceptions.S
index 0d0a12d..bf5bd8d 100644
--- a/bl31/aarch64/runtime_exceptions.S
+++ b/bl31/aarch64/runtime_exceptions.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -71,8 +71,9 @@
* Save general purpose and ARMv8.3-PAuth registers (if enabled).
* If Secure Cycle Counter is not disabled in MDCR_EL3 when
* ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter.
+ * Also set the PSTATE to a known state.
*/
- bl save_gp_pmcr_pauth_regs
+ bl prepare_el3_entry
bl handle_lower_el_ea_esb
@@ -209,8 +210,9 @@
* Save general purpose and ARMv8.3-PAuth registers (if enabled).
* If Secure Cycle Counter is not disabled in MDCR_EL3 when
* ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter.
+ * Also set the PSTATE to a known state.
*/
- bl save_gp_pmcr_pauth_regs
+ bl prepare_el3_entry
#if ENABLE_PAUTH
/* Load and program APIAKey firmware key */
@@ -462,8 +464,9 @@
* Save general purpose and ARMv8.3-PAuth registers (if enabled).
* If Secure Cycle Counter is not disabled in MDCR_EL3 when
* ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter.
+ * Also set the PSTATE to a known state.
*/
- bl save_gp_pmcr_pauth_regs
+ bl prepare_el3_entry
#if ENABLE_PAUTH
/* Load and program APIAKey firmware key */
diff --git a/bl32/tsp/tsp_main.c b/bl32/tsp/tsp_main.c
index 55e1532..522c1b4 100644
--- a/bl32/tsp/tsp_main.c
+++ b/bl32/tsp/tsp_main.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -370,6 +370,7 @@
uint64_t service_arg1;
uint64_t results[2];
uint32_t linear_id = plat_my_core_pos();
+ u_register_t dit;
/* Update this cpu's statistics */
tsp_stats[linear_id].smc_count++;
@@ -424,6 +425,23 @@
results[0] /= service_arg0 ? service_arg0 : 1;
results[1] /= service_arg1 ? service_arg1 : 1;
break;
+ case TSP_CHECK_DIT:
+ if (!is_armv8_4_dit_present()) {
+#if LOG_LEVEL >= LOG_LEVEL_ERROR
+ spin_lock(&console_lock);
+ ERROR("DIT not supported\n");
+ spin_unlock(&console_lock);
+#endif
+ results[0] = 0;
+ results[1] = 0xffff;
+ break;
+ }
+ dit = read_dit();
+ results[0] = dit == service_arg0;
+ results[1] = dit;
+ /* Toggle the dit bit */
+ write_dit(service_arg0 != 0U ? 0 : DIT_BIT);
+ break;
default:
break;
}
diff --git a/changelog.yaml b/changelog.yaml
index c4ed59b..9a4a8a7 100644
--- a/changelog.yaml
+++ b/changelog.yaml
@@ -113,6 +113,9 @@
- title: Self-hosted Trace Extensions (FEAT_TRF)
scope: trf
+ - title: Statistical profiling Extension (FEAT_SPE)
+ scope: spe
+
- title: Platforms
subsections:
diff --git a/docs/process/contributing.rst b/docs/process/contributing.rst
index d6f61d6..f80389d 100644
--- a/docs/process/contributing.rst
+++ b/docs/process/contributing.rst
@@ -1,8 +1,8 @@
Contributor's Guide
-===================
+*******************
Getting Started
----------------
+===============
- Make sure you have a Github account and you are logged on both
`developer.trustedfirmware.org`_ and `review.trustedfirmware.org`_.
@@ -24,7 +24,7 @@
branch.
Making Changes
---------------
+==============
- Ensure commits adhere to the the project's :ref:`Commit Style`.
@@ -91,7 +91,7 @@
block a patch, depending on how critical they are.
Submitting Changes
-------------------
+==================
- Submit your changes for review at https://review.trustedfirmware.org
targeting the ``integration`` branch.
@@ -164,13 +164,17 @@
revert your patches and ask you to resubmit a reworked version of them or
they may ask you to provide a fix-up patch.
-Add Build Configurations
-------------------------
+Add CI Configurations
+=====================
- TF-A uses Jenkins tool for Continuous Integration and testing activities.
Various CI Jobs are deployed which run tests on every patch before being
merged. So each of your patches go through a series of checks before they
- get merged on to the master branch.
+ get merged on to the master branch. Kindly ensure, that everytime you add
+ new files under your platform, they are covered under the following two sections:
+
+Coverity Scan
+-------------
- ``Coverity Scan analysis`` is one of the tests we perform on our source code
at regular intervals. We maintain a build script ``tf-cov-make`` which contains the
@@ -182,7 +186,7 @@
respective build configurations in the ``tf-cov-make`` build script.
- In this section you find the details on how to append your new build
- configurations for Coverity Scan analysis:
+ configurations for Coverity scan analysis illustrated with examples:
#. We maintain a separate repository named `tf-a-ci-scripts repository`_
for placing all the test scripts which will be executed by the CI Jobs.
@@ -223,8 +227,51 @@
of various other platforms listed in the ``tf-cov-make`` script. Kindly refer
them and append your build configurations respectively.
+Test Build Configuration (``tf-l1-build-plat``)
+-----------------------------------------------
+
+- Coverity Scan analysis, runs on a daily basis and will not be triggered for
+ every individual trusted-firmware patch.
+
+- Considering this, we have other distinguished CI jobs which run a set of test
+ configurations on every patch, before they are being passed to ``Coverity scan analysis``.
+
+- ``tf-l1-build-plat`` is the test group, which holds the test configurations
+ to build all the platforms. So be kind enough to verify that your newly added
+ files are built as part of one of the existing platform configurations present
+ in ``tf-l1-build-plat`` test group.
+
+- In this section you find the details on how to add the appropriate files,
+ needed to build your newly introduced platform as part of ``tf-l1-build-plat``
+ test group, illustrated with an example:
+
+- Lets consider ``Hikey`` platform:
+ In the `tf-a-ci-scripts repository`_ we need to add a build configuration file ``hikey-default``
+ under tf_config folder, ``tf_config/hikey-default`` listing all the build parameters
+ relevant to it.
+
+.. code:: shell
+
+ #Hikey Build Parameters
+ CROSS_COMPILE=aarch64-none-elf-
+ PLAT=hikey
+
+- Further a test-configuration file ``hikey-default:nil`` need to be added under the
+ test group, ``tf-l1-build-plat`` located at ``tf-a-ci-scripts/group/tf-l1-build-plat``,
+ to allow the platform to be built as part of this group.
+
+.. code:: shell
+
+ #
+ # Copyright (c) 2019-2022 Arm Limited. All rights reserved.
+ #
+ # SPDX-License-Identifier: BSD-3-Clause
+ #
+
+- As illustrated above, you need to add the similar files supporting your platform.
+
Binary Components
------------------
+=================
- Platforms may depend on binary components submitted to the `Trusted Firmware
binary repository`_ if they require code that the contributor is unable or
@@ -242,7 +289,7 @@
--------------
-*Copyright (c) 2013-2021, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.*
.. _developer.trustedfirmware.org: https://developer.trustedfirmware.org
.. _review.trustedfirmware.org: https://review.trustedfirmware.org
diff --git a/include/arch/aarch64/arch_features.h b/include/arch/aarch64/arch_features.h
index 46cd1c9..a260f03 100644
--- a/include/arch/aarch64/arch_features.h
+++ b/include/arch/aarch64/arch_features.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2021, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2022, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -46,6 +46,12 @@
return (read_id_aa64isar1_el1() & mask) != 0U;
}
+static inline bool is_armv8_4_dit_present(void)
+{
+ return ((read_id_aa64pfr0_el1() >> ID_AA64PFR0_DIT_SHIFT) &
+ ID_AA64PFR0_DIT_MASK) == 1U;
+}
+
static inline bool is_armv8_4_ttst_present(void)
{
return ((read_id_aa64mmfr2_el1() >> ID_AA64MMFR2_EL1_ST_SHIFT) &
diff --git a/include/arch/aarch64/arch_helpers.h b/include/arch/aarch64/arch_helpers.h
index 733bb23..009eb90 100644
--- a/include/arch/aarch64/arch_helpers.h
+++ b/include/arch/aarch64/arch_helpers.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2021, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -529,6 +529,9 @@
DEFINE_RENAME_SYSREG_RW_FUNCS(apiakeyhi_el1, APIAKeyHi_EL1)
DEFINE_RENAME_SYSREG_RW_FUNCS(apiakeylo_el1, APIAKeyLo_EL1)
+/* Armv8.4 Data Independent Timing Register */
+DEFINE_RENAME_SYSREG_RW_FUNCS(dit, DIT)
+
/* Armv8.5 MTE Registers */
DEFINE_RENAME_SYSREG_RW_FUNCS(tfsre0_el1, TFSRE0_EL1)
DEFINE_RENAME_SYSREG_RW_FUNCS(tfsr_el1, TFSR_EL1)
diff --git a/include/arch/aarch64/el3_common_macros.S b/include/arch/aarch64/el3_common_macros.S
index f29def7..d47244e 100644
--- a/include/arch/aarch64/el3_common_macros.S
+++ b/include/arch/aarch64/el3_common_macros.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2021, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -9,6 +9,7 @@
#include <arch.h>
#include <asm_macros.S>
+#include <assert_macros.S>
#include <context.h>
#include <lib/xlat_tables/xlat_tables_defs.h>
@@ -237,15 +238,20 @@
/*
* If Data Independent Timing (DIT) functionality is implemented,
- * always enable DIT in EL3
+ * always enable DIT in EL3.
+ * First assert that the FEAT_DIT build flag matches the feature id
+ * register value for DIT.
*/
+#if ENABLE_FEAT_DIT
+#if ENABLE_ASSERTIONS
mrs x0, id_aa64pfr0_el1
ubfx x0, x0, #ID_AA64PFR0_DIT_SHIFT, #ID_AA64PFR0_DIT_LENGTH
cmp x0, #ID_AA64PFR0_DIT_SUPPORTED
- bne 1f
+ ASM_ASSERT(eq)
+#endif /* ENABLE_ASSERTIONS */
mov x0, #DIT_BIT
msr DIT, x0
-1:
+#endif
.endm
/* -----------------------------------------------------------------------------
diff --git a/include/bl32/tsp/tsp.h b/include/bl32/tsp/tsp.h
index 637e14a..285bfbe 100644
--- a/include/bl32/tsp/tsp.h
+++ b/include/bl32/tsp/tsp.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -41,6 +41,7 @@
#define TSP_MUL 0x2002
#define TSP_DIV 0x2003
#define TSP_HANDLE_SEL1_INTR_AND_RETURN 0x2004
+#define TSP_CHECK_DIT 0x2005
/*
* Identify a TSP service from function ID filtering the last 16 bits from the
diff --git a/lib/el3_runtime/aarch64/context.S b/lib/el3_runtime/aarch64/context.S
index c9035e8..c1c0612 100644
--- a/lib/el3_runtime/aarch64/context.S
+++ b/lib/el3_runtime/aarch64/context.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -21,7 +21,7 @@
.global fpregs_context_save
.global fpregs_context_restore
#endif
- .global save_gp_pmcr_pauth_regs
+ .global prepare_el3_entry
.global restore_gp_pmcr_pauth_regs
.global save_and_update_ptw_el1_sys_regs
.global el3_exit
@@ -682,8 +682,24 @@
endfunc fpregs_context_restore
#endif /* CTX_INCLUDE_FPREGS */
+ /*
+ * Set the PSTATE bits not set when the exception was taken as
+ * described in the AArch64.TakeException() pseudocode function
+ * in ARM DDI 0487F.c page J1-7635 to a default value.
+ */
+ .macro set_unset_pstate_bits
+ /*
+ * If Data Independent Timing (DIT) functionality is implemented,
+ * always enable DIT in EL3
+ */
+#if ENABLE_FEAT_DIT
+ mov x8, #DIT_BIT
+ msr DIT, x8
+#endif /* ENABLE_FEAT_DIT */
+ .endm /* set_unset_pstate_bits */
+
/* ------------------------------------------------------------------
- * The following function is used to save and restore all the general
+ * The following macro is used to save and restore all the general
* purpose and ARMv8.3-PAuth (if enabled) registers.
* It also checks if Secure Cycle Counter is not disabled in MDCR_EL3
* when ARMv8.5-PMU is implemented, and if called from Non-secure
@@ -693,12 +709,10 @@
* when a world switch occurs but that type of implementation is more
* complex. So currently we will always save and restore these
* registers on entry and exit of EL3.
- * These are not macros to ensure their invocation fits within the 32
- * instructions per exception vector.
* clobbers: x18
* ------------------------------------------------------------------
*/
-func save_gp_pmcr_pauth_regs
+ .macro save_gp_pmcr_pauth_regs
stp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
stp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
@@ -769,9 +783,28 @@
stp x26, x27, [x19, #CTX_PACDBKEY_LO]
stp x28, x29, [x19, #CTX_PACGAKEY_LO]
#endif /* CTX_INCLUDE_PAUTH_REGS */
+ .endm /* save_gp_pmcr_pauth_regs */
+/* -----------------------------------------------------------------
+ * This function saves the context and sets the PSTATE to a known
+ * state, preparing entry to el3.
+ * Save all the general purpose and ARMv8.3-PAuth (if enabled)
+ * registers.
+ * Then set any of the PSTATE bits that are not set by hardware
+ * according to the Aarch64.TakeException pseudocode in the Arm
+ * Architecture Reference Manual to a default value for EL3.
+ * clobbers: x17
+ * -----------------------------------------------------------------
+ */
+func prepare_el3_entry
+ save_gp_pmcr_pauth_regs
+ /*
+ * Set the PSTATE bits not described in the Aarch64.TakeException
+ * pseudocode to their default values.
+ */
+ set_unset_pstate_bits
ret
-endfunc save_gp_pmcr_pauth_regs
+endfunc prepare_el3_entry
/* ------------------------------------------------------------------
* This function restores ARMv8.3-PAuth (if enabled) and all general
diff --git a/lib/extensions/spe/spe.c b/lib/extensions/spe/spe.c
index f0d7342..d747efc 100644
--- a/lib/extensions/spe/spe.c
+++ b/lib/extensions/spe/spe.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2022, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -54,9 +54,14 @@
* MDCR_EL2.NSPB (ARM v8.2): SPE enabled in Non-secure state
* and disabled in secure state. Accesses to SPE registers at
* S-EL1 generate trap exceptions to EL3.
+ *
+ * MDCR_EL3.EnPMSN (ARM v8.7): Do not trap access to PMSNEVFR_EL1
+ * register at NS-EL1 or NS-EL2 to EL3 if FEAT_SPEv1p2 is implemented.
+ * Setting this bit to 1 doesn't have any effect on it when
+ * FEAT_SPEv1p2 not implemented.
*/
v = read_mdcr_el3();
- v |= MDCR_NSPB(MDCR_NSPB_EL1);
+ v |= MDCR_NSPB(MDCR_NSPB_EL1) | MDCR_EnPMSN_BIT;
write_mdcr_el3(v);
}
diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk
index 551b689..b39dcf4 100644
--- a/make_helpers/defaults.mk
+++ b/make_helpers/defaults.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2016-2021, Arm Limited. All rights reserved.
+# Copyright (c) 2016-2022, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -145,6 +145,9 @@
# Flag to enable access to the CNTPOFF_EL2 register
ENABLE_FEAT_ECV := 0
+# Flag to enable use of the DIT feature.
+ENABLE_FEAT_DIT := 0
+
# By default BL31 encryption disabled
ENCRYPT_BL31 := 0
diff --git a/plat/st/stm32mp1/stm32mp1_def.h b/plat/st/stm32mp1/stm32mp1_def.h
index fd12159..aabe81f 100644
--- a/plat/st/stm32mp1/stm32mp1_def.h
+++ b/plat/st/stm32mp1/stm32mp1_def.h
@@ -429,7 +429,7 @@
#define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100))
#if !(defined(__LINKER__) || defined(__ASSEMBLER__))
-static inline uint32_t tamp_bkpr(uint32_t idx)
+static inline uintptr_t tamp_bkpr(uint32_t idx)
{
return TAMP_BKP_REGISTER_BASE + (idx << 2);
}
diff --git a/plat/st/stm32mp1/stm32mp1_pm.c b/plat/st/stm32mp1/stm32mp1_pm.c
index ed4d5e5..3892151 100644
--- a/plat/st/stm32mp1/stm32mp1_pm.c
+++ b/plat/st/stm32mp1/stm32mp1_pm.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,8 +7,6 @@
#include <assert.h>
#include <errno.h>
-#include <platform_def.h>
-
#include <arch_helpers.h>
#include <bl32/sp_min/platform_sp_min.h>
#include <common/debug.h>
@@ -20,6 +18,8 @@
#include <lib/psci/psci.h>
#include <plat/common/platform.h>
+#include <platform_def.h>
+
static uintptr_t stm32_sec_entrypoint;
static uint32_t cntfrq_core0;
@@ -60,9 +60,9 @@
static int stm32_pwr_domain_on(u_register_t mpidr)
{
unsigned long current_cpu_mpidr = read_mpidr_el1();
- uint32_t bkpr_core1_addr =
+ uintptr_t bkpr_core1_addr =
tamp_bkpr(BOOT_API_CORE1_BRANCH_ADDRESS_TAMP_BCK_REG_IDX);
- uint32_t bkpr_core1_magic =
+ uintptr_t bkpr_core1_magic =
tamp_bkpr(BOOT_API_CORE1_MAGIC_NUMBER_TAMP_BCK_REG_IDX);
if (mpidr == current_cpu_mpidr) {
diff --git a/plat/st/stm32mp1/stm32mp1_private.c b/plat/st/stm32mp1/stm32mp1_private.c
index 9b39b9d..1125a69 100644
--- a/plat/st/stm32mp1/stm32mp1_private.c
+++ b/plat/st/stm32mp1/stm32mp1_private.c
@@ -568,7 +568,7 @@
void stm32_save_boot_interface(uint32_t interface, uint32_t instance)
{
- uint32_t bkpr_itf_idx = tamp_bkpr(TAMP_BOOT_MODE_BACKUP_REG_ID);
+ uintptr_t bkpr_itf_idx = tamp_bkpr(TAMP_BOOT_MODE_BACKUP_REG_ID);
clk_enable(RTCAPB);
@@ -585,7 +585,7 @@
static uint32_t itf;
if (itf == 0U) {
- uint32_t bkpr = tamp_bkpr(TAMP_BOOT_MODE_BACKUP_REG_ID);
+ uintptr_t bkpr = tamp_bkpr(TAMP_BOOT_MODE_BACKUP_REG_ID);
clk_enable(RTCAPB);
diff --git a/services/spd/tspd/tspd_main.c b/services/spd/tspd/tspd_main.c
index 29fc238..6cb4992 100644
--- a/services/spd/tspd/tspd_main.c
+++ b/services/spd/tspd/tspd_main.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -570,6 +570,11 @@
case TSP_YIELD_FID(TSP_SUB):
case TSP_YIELD_FID(TSP_MUL):
case TSP_YIELD_FID(TSP_DIV):
+ /*
+ * Request from non-secure client to perform a check
+ * of the DIT PSTATE bit.
+ */
+ case TSP_YIELD_FID(TSP_CHECK_DIT):
if (ns) {
/*
* This is a fresh request from the non-secure client.