Merge "feat(fiptool): handle FIP in a disk partition" into integration
diff --git a/Makefile b/Makefile
index 1ddb7b8..f4d623e 100644
--- a/Makefile
+++ b/Makefile
@@ -350,27 +350,53 @@
# General warnings
WARNINGS := -Wall -Wmissing-include-dirs -Wunused \
-Wdisabled-optimization -Wvla -Wshadow \
- -Wno-unused-parameter -Wredundant-decls
+ -Wredundant-decls
+# stricter warnings
+WARNINGS += -Wextra -Wno-trigraphs
+# too verbose for generic build
+WARNINGS += -Wno-missing-field-initializers \
+ -Wno-type-limits -Wno-sign-compare \
+# on clang this flag gets reset if -Wextra is set after it. No difference on gcc
+WARNINGS += -Wno-unused-parameter
# Additional warnings
-# Level 1
-WARNING1 := -Wextra
-WARNING1 += -Wmissing-format-attribute
-WARNING1 += -Wmissing-prototypes
-WARNING1 += -Wold-style-definition
+# Level 1 - infrequent warnings we should have none of
+# full -Wextra
+WARNING1 += -Wsign-compare
+WARNING1 += -Wtype-limits
+WARNING1 += -Wmissing-field-initializers
-# Level 2
-WARNING2 := -Waggregate-return
-WARNING2 += -Wcast-align
-WARNING2 += -Wnested-externs
+# Level 2 - problematic warnings that we want
+# zlib, compiler-rt, coreboot, and mbdedtls blow up with these
+# TODO: disable just for them and move into default build
+WARNING2 += -Wold-style-definition
+WARNING2 += -Wmissing-prototypes
+WARNING2 += -Wmissing-format-attribute
+# TF-A aims to comply with this eventually. Effort too large at present
+WARNING2 += -Wundef
+# currently very involved and many platforms set this off
+WARNING2 += -Wunused-const-variable=2
+# Level 3 - very pedantic, frequently ignored
WARNING3 := -Wbad-function-cast
+WARNING3 += -Waggregate-return
+WARNING3 += -Wnested-externs
+WARNING3 += -Wcast-align
WARNING3 += -Wcast-qual
WARNING3 += -Wconversion
WARNING3 += -Wpacked
WARNING3 += -Wpointer-arith
WARNING3 += -Wswitch-default
+# Setting W is quite verbose and most warnings will be pre-existing issues
+# outside of the contributor's control. Don't fail the build on them so warnings
+# can be seen and hopefully addressed
+ifdef W
+ifneq (${W},0)
+E ?= 0
+endif
+endif
+
ifeq (${W},1)
WARNINGS += $(WARNING1)
else ifeq (${W},2)
@@ -526,9 +552,7 @@
SPD_DIR := std_svc
ifeq ($(SPMD_SPM_AT_SEL2),1)
- ifeq ($(CTX_INCLUDE_EL2_REGS),0)
- $(error SPMD with SPM at S-EL2 requires CTX_INCLUDE_EL2_REGS option)
- endif
+ CTX_INCLUDE_EL2_REGS := 1
ifeq ($(SPMC_AT_EL3),1)
$(error SPM cannot be enabled in both S-EL2 and EL3.)
endif
@@ -574,6 +598,14 @@
# over the sources.
endif
+ifeq (${CTX_INCLUDE_EL2_REGS}, 1)
+ifeq (${SPD},none)
+ifeq (${ENABLE_RME},0)
+ $(error CTX_INCLUDE_EL2_REGS is available only when SPD or RME is enabled)
+endif
+endif
+endif
+
################################################################################
# Include rmmd Makefile if RME is enabled
################################################################################
diff --git a/bl31/aarch64/runtime_exceptions.S b/bl31/aarch64/runtime_exceptions.S
index 0283553..0c60859 100644
--- a/bl31/aarch64/runtime_exceptions.S
+++ b/bl31/aarch64/runtime_exceptions.S
@@ -10,6 +10,7 @@
#include <asm_macros.S>
#include <bl31/ea_handle.h>
#include <bl31/interrupt_mgmt.h>
+#include <bl31/sync_handle.h>
#include <common/runtime_svc.h>
#include <context.h>
#include <el3_common_macros.S>
@@ -82,31 +83,6 @@
1:
#else
/*
- * For SoCs which do not implement RAS, use DSB as a barrier to
- * synchronize pending external aborts.
- */
- dsb sy
-
- /* Unmask the SError interrupt */
- msr daifclr, #DAIF_ABT_BIT
-
- /* Use ISB for the above unmask operation to take effect immediately */
- isb
-
- /*
- * Refer Note 1. No need to restore X30 as both handle_sync_exception
- * and handle_interrupt_exception macro which follow this macro modify
- * X30 anyway.
- */
- str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
- mov x30, #1
- str x30, [sp, #CTX_EL3STATE_OFFSET + CTX_IS_IN_EL3]
- dmb sy
-#endif
- .endm
-
-#if !RAS_EXTENSION
- /*
* Note 1: The explicit DSB at the entry of various exception vectors
* for handling exceptions from lower ELs can inadvertently trigger an
* SError exception in EL3 due to pending asynchronous aborts in lower
@@ -120,13 +96,9 @@
* flag execute without causing further exceptions.
*/
- /* ---------------------------------------------------------------------
- * This macro handles Asynchronous External Aborts.
- * ---------------------------------------------------------------------
- */
- .macro handle_async_ea
/*
- * Use a barrier to synchronize pending external aborts.
+ * For SoCs which do not implement RAS, use DSB as a barrier to
+ * synchronize pending external aborts.
*/
dsb sy
@@ -136,33 +108,16 @@
/* Use ISB for the above unmask operation to take effect immediately */
isb
- /* Refer Note 1 */
+ /*
+ * Refer Note 1.
+ * No need to restore X30 as macros following this modify x30 anyway.
+ */
str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
mov x30, #1
str x30, [sp, #CTX_EL3STATE_OFFSET + CTX_IS_IN_EL3]
dmb sy
-
- b handle_lower_el_async_ea
- .endm
-
- /*
- * This macro checks if the exception was taken due to SError in EL3 or
- * because of pending asynchronous external aborts from lower EL that got
- * triggered due to explicit synchronization in EL3. Refer Note 1.
- */
- .macro check_if_serror_from_EL3
- /* Assumes SP_EL3 on entry */
- str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
- ldr x30, [sp, #CTX_EL3STATE_OFFSET + CTX_IS_IN_EL3]
- cbnz x30, exp_from_EL3
-
- /* Handle asynchronous external abort from lower EL */
- b handle_lower_el_async_ea
-
-exp_from_EL3:
- /* Jump to plat_handle_el3_ea which does not return */
- .endm
#endif
+ .endm
/* ---------------------------------------------------------------------
* This macro handles Synchronous exceptions.
@@ -191,7 +146,10 @@
b.eq smc_handler32
cmp x30, #EC_AARCH64_SMC
- b.eq smc_handler64
+ b.eq sync_handler64
+
+ cmp x30, #EC_AARCH64_SYS
+ b.eq sync_handler64
/* Synchronous exceptions other than the above are assumed to be EA */
ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
@@ -352,7 +310,19 @@
vector_entry serror_sp_elx
#if !RAS_EXTENSION
- check_if_serror_from_EL3
+ /*
+ * This will trigger if the exception was taken due to SError in EL3 or
+ * because of pending asynchronous external aborts from lower EL that got
+ * triggered due to explicit synchronization in EL3. Refer Note 1.
+ */
+ /* Assumes SP_EL3 on entry */
+ str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
+ ldr x30, [sp, #CTX_EL3STATE_OFFSET + CTX_IS_IN_EL3]
+ cbnz x30, 1f
+
+ /* Handle asynchronous external abort from lower EL */
+ b handle_lower_el_async_ea
+1:
#endif
no_ret plat_handle_el3_ea
end_vector_entry serror_sp_elx
@@ -391,7 +361,8 @@
msr daifclr, #DAIF_ABT_BIT
b enter_lower_el_async_ea
#else
- handle_async_ea
+ check_and_unmask_ea
+ b handle_lower_el_async_ea
#endif
end_vector_entry serror_aarch64
@@ -429,7 +400,8 @@
msr daifclr, #DAIF_ABT_BIT
b enter_lower_el_async_ea
#else
- handle_async_ea
+ check_and_unmask_ea
+ b handle_lower_el_async_ea
#endif
end_vector_entry serror_aarch32
@@ -452,12 +424,12 @@
* Note that x30 has been explicitly saved and can be used here
* ---------------------------------------------------------------------
*/
-func smc_handler
+func sync_exception_handler
smc_handler32:
/* Check whether aarch32 issued an SMC64 */
tbnz x0, #FUNCID_CC_SHIFT, smc_prohibited
-smc_handler64:
+sync_handler64:
/* NOTE: The code below must preserve x0-x4 */
/*
@@ -493,15 +465,22 @@
msr spsel, #MODE_SP_EL0
/*
- * Save the SPSR_EL3, ELR_EL3, & SCR_EL3 in case there is a world
+ * Save the SPSR_EL3 and ELR_EL3 in case there is a world
* switch during SMC handling.
* TODO: Revisit if all system registers can be saved later.
*/
mrs x16, spsr_el3
mrs x17, elr_el3
- mrs x18, scr_el3
stp x16, x17, [x6, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
- str x18, [x6, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3]
+
+ /* Load SCR_EL3 */
+ mrs x18, scr_el3
+
+ /* check for system register traps */
+ mrs x16, esr_el3
+ ubfx x17, x16, #ESR_EC_SHIFT, #ESR_EC_LENGTH
+ cmp x17, #EC_AARCH64_SYS
+ b.eq sysreg_handler64
/* Clear flag register */
mov x7, xzr
@@ -566,6 +545,32 @@
#endif
blr x15
+ b el3_exit
+
+sysreg_handler64:
+ mov x0, x16 /* ESR_EL3, containing syndrome information */
+ mov x1, x6 /* lower EL's context */
+ mov x19, x6 /* save context pointer for after the call */
+ mov sp, x12 /* EL3 runtime stack, as loaded above */
+
+ /* int handle_sysreg_trap(uint64_t esr_el3, cpu_context_t *ctx); */
+ bl handle_sysreg_trap
+ /*
+ * returns:
+ * -1: unhandled trap, panic
+ * 0: handled trap, return to the trapping instruction (repeating it)
+ * 1: handled trap, return to the next instruction
+ */
+
+ tst w0, w0
+ b.mi do_panic /* negative return value: panic */
+ b.eq 1f /* zero: do not change ELR_EL3 */
+
+ /* advance the PC to continue after the instruction */
+ ldr x1, [x19, #CTX_EL3STATE_OFFSET + CTX_ELR_EL3]
+ add x1, x1, #4
+ str x1, [x19, #CTX_EL3STATE_OFFSET + CTX_ELR_EL3]
+1:
b el3_exit
smc_unknown:
@@ -592,7 +597,7 @@
msr spsel, #MODE_SP_ELX
no_ret report_unhandled_exception
#endif
-endfunc smc_handler
+endfunc sync_exception_handler
/* ---------------------------------------------------------------------
* The following code handles exceptions caused by BRK instructions.
diff --git a/bl31/bl31.mk b/bl31/bl31.mk
index 4c93a55..ac15f9f 100644
--- a/bl31/bl31.mk
+++ b/bl31/bl31.mk
@@ -42,6 +42,7 @@
bl31/aarch64/ea_delegate.S \
bl31/aarch64/runtime_exceptions.S \
bl31/bl31_context_mgmt.c \
+ bl31/bl31_traps.c \
common/runtime_svc.c \
lib/cpus/aarch64/dsu_helpers.S \
plat/common/aarch64/platform_mp_stack.S \
diff --git a/bl31/bl31_main.c b/bl31/bl31_main.c
index 2a3d838..e70eb55 100644
--- a/bl31/bl31_main.c
+++ b/bl31/bl31_main.c
@@ -93,15 +93,6 @@
/* Perform late platform-specific setup */
bl31_plat_arch_setup();
-#if ENABLE_FEAT_HCX
- /*
- * Assert that FEAT_HCX is supported on this system, without this check
- * an exception would occur during context save/restore if enabled but
- * not supported.
- */
- assert(is_feat_hcx_present());
-#endif /* ENABLE_FEAT_HCX */
-
#if CTX_INCLUDE_PAUTH_REGS
/*
* Assert that the ARMv8.3-PAuth registers are present or an access
diff --git a/bl31/bl31_traps.c b/bl31/bl31_traps.c
new file mode 100644
index 0000000..b12185d
--- /dev/null
+++ b/bl31/bl31_traps.c
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2022, ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Dispatch synchronous system register traps from lower ELs.
+ */
+
+#include <bl31/sync_handle.h>
+#include <context.h>
+
+int handle_sysreg_trap(uint64_t esr_el3, cpu_context_t *ctx)
+{
+ switch (esr_el3 & ISS_SYSREG_OPCODE_MASK) {
+#if ENABLE_FEAT_RNG_TRAP
+ case ISS_SYSREG_OPCODE_RNDR:
+ case ISS_SYSREG_OPCODE_RNDRRS:
+ return plat_handle_rng_trap(esr_el3, ctx);
+#endif
+ default:
+ return TRAP_RET_UNHANDLED;
+ }
+}
diff --git a/bl32/tsp/ffa_helpers.c b/bl32/tsp/ffa_helpers.c
index 3639c22..ad70c2b 100644
--- a/bl32/tsp/ffa_helpers.c
+++ b/bl32/tsp/ffa_helpers.c
@@ -149,13 +149,15 @@
{
smc_args_t ret;
uint32_t descriptor_size;
- struct ffa_mtd *memory_region = (struct ffa_mtd *)mb->tx_buffer;
+ struct ffa_mtd *memory_region;
if (retrieved == NULL || mb == NULL) {
ERROR("Invalid parameters!\n");
return false;
}
+ memory_region = (struct ffa_mtd *)mb->tx_buffer;
+
/* Clear TX buffer. */
memset(memory_region, 0, PAGE_SIZE);
diff --git a/bl32/tsp/tsp_ffa_main.c b/bl32/tsp/tsp_ffa_main.c
index 53dbd03..2c53977 100644
--- a/bl32/tsp/tsp_ffa_main.c
+++ b/bl32/tsp/tsp_ffa_main.c
@@ -216,10 +216,10 @@
(uint64_t)composite->address_range_array[i].address,
size, mem_attrs);
- /* Remove mappings created in this transaction. */
- for (i--; i >= 0U; i--) {
+ /* Remove mappings previously created in this transaction. */
+ for (i--; i >= 0; i--) {
ret = mmap_remove_dynamic_region(
- (uint64_t)ptr,
+ (uint64_t)composite->address_range_array[i].address,
composite->address_range_array[i].page_count * PAGE_SIZE);
if (ret != 0) {
@@ -227,6 +227,7 @@
panic();
}
}
+
return FFA_ERROR_NO_MEMORY;
}
@@ -298,8 +299,8 @@
tsp_stats[linear_id].eret_count++;
tsp_stats[linear_id].cpu_off_count++;
- INFO("TSP: cpu 0x%lx off request\n", read_mpidr());
- INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu off requests\n",
+ VERBOSE("TSP: cpu 0x%lx off request\n", read_mpidr());
+ VERBOSE("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu off requests\n",
read_mpidr(),
tsp_stats[linear_id].smc_count,
tsp_stats[linear_id].eret_count,
@@ -336,7 +337,7 @@
tsp_stats[linear_id].eret_count++;
tsp_stats[linear_id].cpu_suspend_count++;
- INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu suspend requests\n",
+ VERBOSE("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu suspend requests\n",
read_mpidr(),
tsp_stats[linear_id].smc_count,
tsp_stats[linear_id].eret_count,
@@ -369,9 +370,9 @@
tsp_stats[linear_id].eret_count++;
tsp_stats[linear_id].cpu_resume_count++;
- INFO("TSP: cpu 0x%lx resumed. maximum off power level %" PRId64 "\n",
+ VERBOSE("TSP: cpu 0x%lx resumed. maximum off power level %" PRId64 "\n",
read_mpidr(), max_off_pwrlvl);
- INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu resume requests\n",
+ VERBOSE("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu resume requests\n",
read_mpidr(),
tsp_stats[linear_id].smc_count,
tsp_stats[linear_id].eret_count,
@@ -611,7 +612,7 @@
tsp_stats[linear_id].eret_count++;
tsp_stats[linear_id].cpu_on_count++;
- INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu on requests\n",
+ VERBOSE("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu on requests\n",
read_mpidr(),
tsp_stats[linear_id].smc_count,
tsp_stats[linear_id].eret_count,
@@ -640,8 +641,8 @@
tsp_stats[linear_id].smc_count++;
tsp_stats[linear_id].eret_count++;
tsp_stats[linear_id].cpu_on_count++;
- INFO("TSP: cpu 0x%lx turned on\n", read_mpidr());
- INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu on requests\n",
+ VERBOSE("TSP: cpu 0x%lx turned on\n", read_mpidr());
+ VERBOSE("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu on requests\n",
read_mpidr(),
tsp_stats[linear_id].smc_count,
tsp_stats[linear_id].eret_count,
diff --git a/changelog.yaml b/changelog.yaml
index cfb2bb5..e100f82 100644
--- a/changelog.yaml
+++ b/changelog.yaml
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2021-2022, Arm Limited. All rights reserved.
+# Copyright (c) 2021-2023, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -101,6 +101,9 @@
- title: Extended Cache Index (FEAT_CCIDX)
scope: ccidx
+ - title: CPU feature / ID register handling in general
+ scope: cpufeat
+
- title: Support for the `HCRX_EL2` register (FEAT_HCX)
scope: hcx
@@ -744,6 +747,9 @@
- title: mbedTLS
scope: mbedtls
+ - title: Console
+ scope: console
+
- title: Generic Clock
scope: clk
diff --git a/common/fdt_wrappers.c b/common/fdt_wrappers.c
index 1b065b1..783b660 100644
--- a/common/fdt_wrappers.c
+++ b/common/fdt_wrappers.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2023, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -206,9 +206,9 @@
assert(cells <= 2U);
if (cells == 2U)
- *(uint64_t *)value = cpu_to_fdt64(*(uint64_t *)value);
+ *(fdt64_t *)value = cpu_to_fdt64(*(uint64_t *)value);
else
- *(uint32_t *)value = cpu_to_fdt32(*(uint32_t *)value);
+ *(fdt32_t *)value = cpu_to_fdt32(*(uint32_t *)value);
len = (int)cells * 4;
@@ -392,7 +392,7 @@
* to a global address with help of various helper functions.
******************************************************************************/
-static bool fdtw_xlat_hit(const uint32_t *value, int child_addr_size,
+static bool fdtw_xlat_hit(const fdt32_t *value, int child_addr_size,
int parent_addr_size, int range_size, uint64_t base_address,
uint64_t *translated_addr)
{
@@ -427,7 +427,7 @@
int local_bus, uint64_t base_address)
{
uint64_t translated_addr;
- const uint32_t *next_entry;
+ const fdt32_t *next_entry;
int parent_bus_node, nxlat_entries, length;
int self_addr_cells, parent_addr_cells, self_size_cells, ncells_xlat;
@@ -460,7 +460,7 @@
assert(nxlat_entries > 0);
- next_entry = (const uint32_t *)ranges_prop->data;
+ next_entry = (const fdt32_t *)ranges_prop->data;
/* Iterate over the entries in the "ranges" */
for (int i = 0; i < nxlat_entries; i++) {
diff --git a/common/feat_detect.c b/common/feat_detect.c
index ee34588..a8c40f7 100644
--- a/common/feat_detect.c
+++ b/common/feat_detect.c
@@ -4,24 +4,59 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
+#include <arch_features.h>
+#include <common/debug.h>
#include <common/feat_detect.h>
+static bool tainted;
+
/*******************************************************************************
* This section lists the wrapper modules for each feature to evaluate the
- * feature states (FEAT_STATE_1 and FEAT_STATE_2) and perform necessary action
- * as below:
+ * feature states (FEAT_STATE_ALWAYS and FEAT_STATE_CHECK) and perform
+ * necessary action as below:
*
* It verifies whether the FEAT_XXX (eg: FEAT_SB) is supported by the PE or not.
* Without this check an exception would occur during context save/restore
* routines, if the feature is enabled but not supported by PE.
******************************************************************************/
+
+#define feat_detect_panic(a, b) ((a) ? (void)0 : feature_panic(b))
+
+/*******************************************************************************
+ * Function : feature_panic
+ * Customised panic function with error logging mechanism to list the feature
+ * not supported by the PE.
+ ******************************************************************************/
+static inline void feature_panic(char *feat_name)
+{
+ ERROR("FEAT_%s not supported by the PE\n", feat_name);
+ panic();
+}
+
+/*******************************************************************************
+ * Function : check_feature
+ * Check for a valid combination of build time flags (ENABLE_FEAT_xxx) and
+ * feature availability on the hardware.
+ * Panics if a feature is forcefully enabled, but not available on the PE.
+ *
+ * We force inlining here to let the compiler optimise away the whole check
+ * if the feature is disabled at build time (FEAT_STATE_DISABLED).
+ ******************************************************************************/
+static inline void __attribute((__always_inline__))
+check_feature(int state, unsigned long field, const char *feat_name)
+{
+ if (state == FEAT_STATE_ALWAYS && field == 0U) {
+ ERROR("FEAT_%s not supported by the PE\n", feat_name);
+ tainted = true;
+ }
+}
/******************************************
* Feature : FEAT_SB (Speculation Barrier)
*****************************************/
static void read_feat_sb(void)
{
-#if (ENABLE_FEAT_SB == FEAT_STATE_1)
+#if (ENABLE_FEAT_SB == FEAT_STATE_ALWAYS)
feat_detect_panic(is_armv8_0_feat_sb_present(), "SB");
#endif
}
@@ -31,7 +66,7 @@
*****************************************************/
static void read_feat_csv2_2(void)
{
-#if (ENABLE_FEAT_CSV2_2 == FEAT_STATE_1)
+#if (ENABLE_FEAT_CSV2_2 == FEAT_STATE_ALWAYS)
feat_detect_panic(is_armv8_0_feat_csv2_2_present(), "CSV2_2");
#endif
}
@@ -41,7 +76,7 @@
**********************************************/
static void read_feat_pan(void)
{
-#if (ENABLE_FEAT_PAN == FEAT_STATE_1)
+#if (ENABLE_FEAT_PAN == FEAT_STATE_ALWAYS)
feat_detect_panic(is_armv8_1_pan_present(), "PAN");
#endif
}
@@ -51,7 +86,7 @@
*****************************************************/
static void read_feat_vhe(void)
{
-#if (ENABLE_FEAT_VHE == FEAT_STATE_1)
+#if (ENABLE_FEAT_VHE == FEAT_STATE_ALWAYS)
feat_detect_panic(is_armv8_1_vhe_present(), "VHE");
#endif
}
@@ -61,7 +96,7 @@
******************************************************************************/
static void read_feat_ras(void)
{
-#if (RAS_EXTENSION == FEAT_STATE_1)
+#if (RAS_EXTENSION == FEAT_STATE_ALWAYS)
feat_detect_panic(is_armv8_2_feat_ras_present(), "RAS");
#endif
}
@@ -71,7 +106,7 @@
***********************************************/
static void read_feat_pauth(void)
{
-#if (ENABLE_PAUTH == FEAT_STATE_1) || (CTX_INCLUDE_PAUTH_REGS == FEAT_STATE_1)
+#if (ENABLE_PAUTH == FEAT_STATE_ALWAYS) || (CTX_INCLUDE_PAUTH_REGS == FEAT_STATE_ALWAYS)
feat_detect_panic(is_armv8_3_pauth_present(), "PAUTH");
#endif
}
@@ -81,27 +116,17 @@
***********************************************************/
static void read_feat_dit(void)
{
-#if (ENABLE_FEAT_DIT == FEAT_STATE_1)
+#if (ENABLE_FEAT_DIT == FEAT_STATE_ALWAYS)
feat_detect_panic(is_armv8_4_feat_dit_present(), "DIT");
#endif
}
-/*********************************************************
- * Feature : FEAT_AMUv1 (Activity Monitors Extensions v1)
- ********************************************************/
-static void read_feat_amuv1(void)
-{
-#if (ENABLE_FEAT_AMUv1 == FEAT_STATE_1)
- feat_detect_panic(is_armv8_4_feat_amuv1_present(), "AMUv1");
-#endif
-}
-
/****************************************************************************
* Feature : FEAT_MPAM (Memory Partitioning and Monitoring (MPAM) Extension)
***************************************************************************/
static void read_feat_mpam(void)
{
-#if (ENABLE_MPAM_FOR_LOWER_ELS == FEAT_STATE_1)
+#if (ENABLE_MPAM_FOR_LOWER_ELS == FEAT_STATE_ALWAYS)
feat_detect_panic(get_mpam_version() != 0U, "MPAM");
#endif
}
@@ -111,7 +136,7 @@
*************************************************************/
static void read_feat_nv2(void)
{
-#if (CTX_INCLUDE_NEVE_REGS == FEAT_STATE_1)
+#if (CTX_INCLUDE_NEVE_REGS == FEAT_STATE_ALWAYS)
unsigned int nv = get_armv8_4_feat_nv_support();
feat_detect_panic((nv == ID_AA64MMFR2_EL1_NV2_SUPPORTED), "NV2");
@@ -123,7 +148,7 @@
**********************************/
static void read_feat_sel2(void)
{
-#if (ENABLE_FEAT_SEL2 == FEAT_STATE_1)
+#if (ENABLE_FEAT_SEL2 == FEAT_STATE_ALWAYS)
feat_detect_panic(is_armv8_4_sel2_present(), "SEL2");
#endif
}
@@ -133,7 +158,7 @@
***************************************************/
static void read_feat_trf(void)
{
-#if (ENABLE_TRF_FOR_NS == FEAT_STATE_1)
+#if (ENABLE_TRF_FOR_NS == FEAT_STATE_ALWAYS)
feat_detect_panic(is_arm8_4_feat_trf_present(), "TRF");
#endif
}
@@ -143,7 +168,7 @@
***********************************************/
static void read_feat_mte(void)
{
-#if (CTX_INCLUDE_MTE_REGS == FEAT_STATE_1)
+#if (CTX_INCLUDE_MTE_REGS == FEAT_STATE_ALWAYS)
unsigned int mte = get_armv8_5_mte_support();
feat_detect_panic((mte != MTE_UNIMPLEMENTED), "MTE");
@@ -155,7 +180,7 @@
**********************************************/
static void read_feat_rng(void)
{
-#if (ENABLE_FEAT_RNG == FEAT_STATE_1)
+#if (ENABLE_FEAT_RNG == FEAT_STATE_ALWAYS)
feat_detect_panic(is_armv8_5_rng_present(), "RNG");
#endif
}
@@ -165,27 +190,17 @@
***************************************************/
static void read_feat_bti(void)
{
-#if (ENABLE_BTI == FEAT_STATE_1)
+#if (ENABLE_BTI == FEAT_STATE_ALWAYS)
feat_detect_panic(is_armv8_5_bti_present(), "BTI");
#endif
}
-/****************************************
- * Feature : FEAT_FGT (Fine Grain Traps)
- ***************************************/
-static void read_feat_fgt(void)
-{
-#if (ENABLE_FEAT_FGT == FEAT_STATE_1)
- feat_detect_panic(is_armv8_6_fgt_present(), "FGT");
-#endif
-}
-
/***********************************************
* Feature : FEAT_AMUv1p1 (AMU Extensions v1.1)
**********************************************/
static void read_feat_amuv1p1(void)
{
-#if (ENABLE_FEAT_AMUv1p1 == FEAT_STATE_1)
+#if (ENABLE_FEAT_AMUv1p1 == FEAT_STATE_ALWAYS)
feat_detect_panic(is_armv8_6_feat_amuv1p1_present(), "AMUv1p1");
#endif
}
@@ -195,7 +210,7 @@
******************************************************/
static void read_feat_ecv(void)
{
-#if (ENABLE_FEAT_ECV == FEAT_STATE_1)
+#if (ENABLE_FEAT_ECV == FEAT_STATE_ALWAYS)
unsigned int ecv = get_armv8_6_ecv_support();
feat_detect_panic(((ecv == ID_AA64MMFR0_EL1_ECV_SUPPORTED) ||
@@ -208,27 +223,17 @@
**********************************************************/
static void read_feat_twed(void)
{
-#if (ENABLE_FEAT_TWED == FEAT_STATE_1)
+#if (ENABLE_FEAT_TWED == FEAT_STATE_ALWAYS)
feat_detect_panic(is_armv8_6_twed_present(), "TWED");
#endif
}
-/******************************************************************
- * Feature : FEAT_HCX (Extended Hypervisor Configuration Register)
- *****************************************************************/
-static void read_feat_hcx(void)
-{
-#if (ENABLE_FEAT_HCX == FEAT_STATE_1)
- feat_detect_panic(is_feat_hcx_present(), "HCX");
-#endif
-}
-
/**************************************************
* Feature : FEAT_RME (Realm Management Extension)
*************************************************/
static void read_feat_rme(void)
{
-#if (ENABLE_RME == FEAT_STATE_1)
+#if (ENABLE_RME == FEAT_STATE_ALWAYS)
feat_detect_panic((get_armv9_2_feat_rme_support() !=
ID_AA64PFR0_FEAT_RME_NOT_SUPPORTED), "RME");
#endif
@@ -239,7 +244,7 @@
*****************************************************/
static void read_feat_brbe(void)
{
-#if (ENABLE_BRBE_FOR_NS == FEAT_STATE_1)
+#if (ENABLE_BRBE_FOR_NS == FEAT_STATE_ALWAYS)
feat_detect_panic(is_feat_brbe_present(), "BRBE");
#endif
}
@@ -249,7 +254,7 @@
*****************************************************/
static void read_feat_trbe(void)
{
-#if (ENABLE_TRBE_FOR_NS == FEAT_STATE_1)
+#if (ENABLE_TRBE_FOR_NS == FEAT_STATE_ALWAYS)
feat_detect_panic(is_feat_trbe_present(), "TRBE");
#endif
}
@@ -259,7 +264,7 @@
*****************************************************************/
static void read_feat_rng_trap(void)
{
-#if (ENABLE_FEAT_RNG_TRAP == FEAT_STATE_1)
+#if (ENABLE_FEAT_RNG_TRAP == FEAT_STATE_ALWAYS)
feat_detect_panic(is_feat_rng_trap_present(), "RNG_TRAP");
#endif
}
@@ -283,11 +288,14 @@
* ENABLE_FEAT_xxx = 2 : The feature is enabled but dynamically enabled at runtime
* depending on hardware capability.
*
- * For better readability, state values are defined with macros namely:
- * { FEAT_STATE_0, FEAT_STATE_1, FEAT_STATE_2 } taking values as their naming.
+ * For better readability, state values are defined with macros, namely:
+ * { FEAT_STATE_DISABLED, FEAT_STATE_ALWAYS, FEAT_STATE_CHECK }, taking values
+ * { 0, 1, 2 }, respectively, as their naming.
**********************************************************************************/
void detect_arch_features(void)
{
+ tainted = false;
+
/* v8.0 features */
read_feat_sb();
read_feat_csv2_2();
@@ -304,7 +312,7 @@
/* v8.4 features */
read_feat_dit();
- read_feat_amuv1();
+ check_feature(ENABLE_FEAT_AMUv1, read_feat_amu_id_field(), "AMUv1");
read_feat_mpam();
read_feat_nv2();
read_feat_sel2();
@@ -318,12 +326,12 @@
/* v8.6 features */
read_feat_amuv1p1();
- read_feat_fgt();
+ check_feature(ENABLE_FEAT_FGT, read_feat_fgt_id_field(), "FGT");
read_feat_ecv();
read_feat_twed();
/* v8.7 features */
- read_feat_hcx();
+ check_feature(ENABLE_FEAT_HCX, read_feat_hcx_id_field(), "HCX");
/* v9.0 features */
read_feat_brbe();
@@ -331,4 +339,8 @@
/* v9.2 features */
read_feat_rme();
+
+ if (tainted) {
+ panic();
+ }
}
diff --git a/docs/about/maintainers.rst b/docs/about/maintainers.rst
index 9a2ae73..914c959 100644
--- a/docs/about/maintainers.rst
+++ b/docs/about/maintainers.rst
@@ -506,8 +506,10 @@
Arm Total Compute platform port
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-:|M|: Anders Dellien <anders.dellien@arm.com>
-:|G|: `andersdellien-arm`_
+:|M|: Vishnu Banavath <vishnu.banavath@arm.com>
+:|G|: `vishnu-banavath`_
+:|M|: Rupinderjit Singh <rupinderjit.singh@arm.com>
+:|G|: `rupsin01`_
:|F|: plat/arm/board/tc
HiSilicon HiKey and HiKey960 platform ports
@@ -956,5 +958,6 @@
.. _marcbonnici: https://github.com/marcbonnici
.. _jayanthchidanand-arm: https://github.com/jayanthchidanand-arm
.. _bytefire: https://github.com/bytefire
+.. _rupsin01: https://github.com/rupsin01
.. _Project Maintenance Process: https://developer.trustedfirmware.org/w/collaboration/project-maintenance-process/
diff --git a/docs/about/release-information.rst b/docs/about/release-information.rst
index ddfc081..f99b7ff 100644
--- a/docs/about/release-information.rst
+++ b/docs/about/release-information.rst
@@ -69,6 +69,8 @@
+================================+=============+=========+=========================================================+
| plat_convert_pk() function | Nov'22 | 2.9 | Platform conversion to manage specific PK hash |
+--------------------------------+-------------+---------+---------------------------------------------------------+
+| io_dummy driver | Nov'22 | 2.9 | No more used by any upstream platform |
++--------------------------------+-------------+---------+---------------------------------------------------------+
--------------
diff --git a/docs/components/realm-management-extension.rst b/docs/components/realm-management-extension.rst
index 6fc0c2e..2ea8012 100644
--- a/docs/components/realm-management-extension.rst
+++ b/docs/components/realm-management-extension.rst
@@ -196,7 +196,7 @@
-C bp.refcounter.use_real_time=0 \
-C bp.ve_sysregs.exit_on_shutdown=1 \
-C cache_state_modelled=1 \
- -C bp.dram_size=2 \
+ -C bp.dram_size=4 \
-C bp.secure_memory=1 \
-C pci.pci_smmuv3.mmu.SMMU_ROOT_IDR0=3 \
-C pci.pci_smmuv3.mmu.SMMU_ROOT_IIDR=0x43B \
diff --git a/docs/components/rmm-el3-comms-spec.rst b/docs/components/rmm-el3-comms-spec.rst
index 8070ff4..25c4269 100644
--- a/docs/components/rmm-el3-comms-spec.rst
+++ b/docs/components/rmm-el3-comms-spec.rst
@@ -101,7 +101,7 @@
x2,Maximum number of CPUs to be supported at runtime. RMM should ensure that it can support this maximum number.
x3,Base address for the shared buffer used for communication between EL3 firmware and RMM. This buffer must be of 4KB size (1 page). The boot manifest must be present at the base of this shared buffer during cold boot.
-During cold boot, EL3 firmware needs to allocate a 4K page that will be
+During cold boot, EL3 firmware needs to allocate a 4KB page that will be
passed to RMM in x3. This memory will be used as shared buffer for communication
between EL3 and RMM. It must be assigned to Realm world and must be mapped with
Normal memory attributes (IWB-OWB-ISH) at EL3. At boot, this memory will be
@@ -522,8 +522,8 @@
.. _rmm_el3_manifest_struct:
-RMM-EL3 Boot Manifest Version
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+RMM-EL3 Boot Manifest structure
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
The RMM-EL3 Boot Manifest structure contains platform boot information passed
from EL3 to RMM. The width of the Boot Manifest is 128 bits
diff --git a/docs/components/secure-partition-manager.rst b/docs/components/secure-partition-manager.rst
index cd439ad..f0caf89 100644
--- a/docs/components/secure-partition-manager.rst
+++ b/docs/components/secure-partition-manager.rst
@@ -150,9 +150,6 @@
at EL3.
- If neither ``SPMD_SPM_AT_SEL2`` or ``SPMC_AT_EL3`` are enabled the SPMC
exception level is set to S-EL1.
-- **CTX_INCLUDE_EL2_REGS**: this option permits saving (resp.
- restoring) the EL2 system register context before entering (resp.
- after leaving) the SPMC. It is mandatorily enabled when
``SPMD_SPM_AT_SEL2`` is enabled. The context save/restore routine
and exhaustive list of registers is visible at `[4]`_.
- **SP_LAYOUT_FILE**: this option specifies a text description file
@@ -161,16 +158,16 @@
is required when ``SPMD_SPM_AT_SEL2`` is enabled hence when multiple
secure partitions are to be loaded by BL2 on behalf of the SPMC.
-+---------------+----------------------+------------------+-------------+
-| | CTX_INCLUDE_EL2_REGS | SPMD_SPM_AT_SEL2 | SPMC_AT_EL3 |
-+---------------+----------------------+------------------+-------------+
-| SPMC at S-EL1 | 0 | 0 | 0 |
-+---------------+----------------------+------------------+-------------+
-| SPMC at S-EL2 | 1 | 1 (default when | 0 |
-| | | SPD=spmd) | |
-+---------------+----------------------+------------------+-------------+
-| SPMC at EL3 | 0 | 0 | 1 |
-+---------------+----------------------+------------------+-------------+
++---------------+------------------+-------------+-------------------------+
+| | SPMD_SPM_AT_SEL2 | SPMC_AT_EL3 | CTX_INCLUDE_EL2_REGS(*) |
++---------------+------------------+-------------+-------------------------+
+| SPMC at S-EL1 | 0 | 0 | 0 |
++---------------+------------------+-------------+-------------------------+
+| SPMC at S-EL2 | 1 (default when | 0 | 1 |
+| | SPD=spmd) | | |
++---------------+------------------+-------------+-------------------------+
+| SPMC at EL3 | 0 | 1 | 0 |
++---------------+------------------+-------------+-------------------------+
Other combinations of such build options either break the build or are not
supported.
@@ -181,9 +178,9 @@
stack.
- When ``SPMD_SPM_AT_SEL2=1``, the reference software stack assumes enablement
of FEAT_PAuth, FEAT_BTI and FEAT_MTE architecture extensions.
-- The ``CTX_INCLUDE_EL2_REGS`` option provides the generic support for
- barely saving/restoring EL2 registers from an Arm arch perspective. As such
- it is decoupled from the ``SPD=spmd`` option.
+- ``(*) CTX_INCLUDE_EL2_REGS``, this flag is |TF-A| internal and informational
+ in this table. When set, it provides the generic support for saving/restoring
+ EL2 registers required when S-EL2 firmware is present.
- BL32 option is re-purposed to specify the SPMC image. It can specify either
the Hafnium binary path (built for the secure world) or the path to a TEE
binary implementing FF-A interfaces.
@@ -212,7 +209,6 @@
CROSS_COMPILE=aarch64-none-elf- \
PLAT=fvp \
SPD=spmd \
- CTX_INCLUDE_EL2_REGS=1 \
ARM_ARCH_MINOR=5 \
BRANCH_PROTECTION=1 \
CTX_INCLUDE_PAUTH_REGS=1 \
@@ -230,7 +226,6 @@
CROSS_COMPILE=aarch64-none-elf- \
PLAT=fvp \
SPD=spmd \
- CTX_INCLUDE_EL2_REGS=1 \
ARM_ARCH_MINOR=5 \
BRANCH_PROTECTION=1 \
CTX_INCLUDE_PAUTH_REGS=1 \
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index d48f284..c4a0e15 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -317,6 +317,14 @@
CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and
it is still open.
+- ``ERRATA_A78_2772019``: This applies errata 2772019 workaround to Cortex-A78
+ CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and
+ it is still open.
+
+- ``ERRATA_A78_2779479``: This applies erratum 2779479 workaround to Cortex-A78
+ CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 and
+ it is still open.
+
For Cortex-A78 AE, the following errata build flags are defined :
- ``ERRATA_A78_AE_1941500`` : This applies errata 1941500 workaround to
@@ -460,6 +468,14 @@
CPU. This needs to be enabled for revisions r0p0, r1p0 and r1p1 of the CPU.
It is still open.
+- ``ERRATA_V1_2743093``: This applies errata 2743093 workaround to Neoverse-V1
+ CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 of the
+ CPU. It is still open.
+
+- ``ERRATA_V1_2779461``: This applies erratum 2779461 workaround to Neoverse-V1
+ CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, r1p2 of the
+ CPU. It is still open.
+
For Cortex-A710, the following errata build flags are defined :
- ``ERRATA_A710_1987031``: This applies errata 1987031 workaround to
@@ -503,8 +519,8 @@
of the CPU and is fixed in r2p1.
- ``ERRATA_A710_2282622``: This applies errata 2282622 workaround to
- Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
- of the CPU and is fixed in r2p1.
+ Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and
+ r2p1 of the CPU and is still open.
- ``ERRATA_A710_2291219``: This applies errata 2291219 workaround to
Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
@@ -518,6 +534,10 @@
Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
of the CPU and is fixed in r2p1.
+- ``ERRATA_A710_2768515``: This applies errata 2768515 workaround to
+ Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and
+ r2p1 of the CPU and is still open.
+
For Neoverse N2, the following errata build flags are defined :
- ``ERRATA_N2_2002655``: This applies errata 2002655 workaround to Neoverse-N2
@@ -562,6 +582,10 @@
CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in
r0p1.
+- ``ERRATA_N2_2743089``: This applies errata 2743089 workaround to Neoverse-N2
+ CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed
+ in r0p3.
+
For Cortex-X2, the following errata build flags are defined :
- ``ERRATA_X2_2002765``: This applies errata 2002765 workaround to Cortex-X2
@@ -575,25 +599,33 @@
- ``ERRATA_X2_2083908``: This applies errata 2083908 workaround to Cortex-X2
CPU. This needs to be enabled for revision r2p0 of the CPU, it is still open.
-- ``ERRATA_X2_2017096``: This applies errata 2017096 workaround to
- Cortex-X2 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
- r2p0 of the CPU, it is fixed in r2p1.
+- ``ERRATA_X2_2017096``: This applies errata 2017096 workaround to Cortex-X2
+ CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the
+ CPU, it is fixed in r2p1.
-- ``ERRATA_X2_2081180``: This applies errata 2081180 workaround to
- Cortex-X2 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
- r2p0 of the CPU, it is fixed in r2p1.
+- ``ERRATA_X2_2081180``: This applies errata 2081180 workaround to Cortex-X2
+ CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the
+ CPU, it is fixed in r2p1.
-- ``ERRATA_X2_2216384``: This applies errata 2216384 workaround to
- Cortex-X2 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
- r2p0 of the CPU, it is fixed in r2p1.
+- ``ERRATA_X2_2216384``: This applies errata 2216384 workaround to Cortex-X2
+ CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the
+ CPU, it is fixed in r2p1.
-- ``ERRATA_X2_2147715``: This applies errata 2147715 workaround to
- Cortex-X2 CPU. This needs to be enabled only for revision r2p0 of the CPU,
- it is fixed in r2p1.
+- ``ERRATA_X2_2147715``: This applies errata 2147715 workaround to Cortex-X2
+ CPU. This needs to be enabled only for revision r2p0 of the CPU, it is fixed
+ in r2p1.
-- ``ERRATA_X2_2371105``: This applies errata 2371105 workaround to
- Cortex-X2 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
- of the CPU and is fixed in r2p1.
+- ``ERRATA_X2_2282622``: This applies errata 2282622 workaround to Cortex-X2
+ CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the
+ CPU and is still open.
+
+- ``ERRATA_X2_2371105``: This applies errata 2371105 workaround to Cortex-X2
+ CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 of the CPU
+ and is fixed in r2p1.
+
+- ``ERRATA_X2_2768515``: This applies errata 2768515 workaround to Cortex-X2
+ CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the
+ CPU and is still open.
For Cortex-X3, the following errata build flags are defined :
@@ -734,7 +766,7 @@
--------------
-*Copyright (c) 2014-2022, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2014-2023, Arm Limited and Contributors. All rights reserved.*
.. _CVE-2017-5715: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2017-5715
.. _CVE-2018-3639: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2018-3639
diff --git a/docs/design/trusted-board-boot-build.rst b/docs/design/trusted-board-boot-build.rst
index c3f3a2f..caf367b 100644
--- a/docs/design/trusted-board-boot-build.rst
+++ b/docs/design/trusted-board-boot-build.rst
@@ -42,7 +42,7 @@
are loaded from that path instead of the default OS path. Export this
variable if necessary.
- In the case of Arm platforms, the location of the ROTPK hash must also be
+ In the case of Arm platforms, the location of the ROTPK must also be
specified at build time. The following locations are currently supported (see
``ARM_ROTPK_LOCATION`` build option):
@@ -62,6 +62,9 @@
``plat/arm/board/common/rotpk/arm_rotpk_ecdsa_sha256.bin``. Enforce
generation of the new hash if ``ROT_KEY`` is specified.
+ - ``ARM_ROTPK_LOCATION=devel_full_dev_rsa_key``: use the key located in
+ ``plat/arm/board/common/rotpk/arm_full_dev_rsa_rotpk.S``.
+
Example of command line using RSA development keys:
.. code:: shell
diff --git a/docs/getting_started/build-internals.rst b/docs/getting_started/build-internals.rst
new file mode 100644
index 0000000..a015d71
--- /dev/null
+++ b/docs/getting_started/build-internals.rst
@@ -0,0 +1,14 @@
+Internal Build Options
+======================
+
+|TF-A| internally uses certain options that are not exposed directly through
+:ref:`build-options <build options>` but enabled or disabled indirectly and
+depends on certain options to be enabled or disabled.
+
+.. _build_options_internal:
+
+- ``CTX_INCLUDE_EL2_REGS``: This boolean option provides context save/restore
+ operations when entering/exiting an EL2 execution context. This is of primary
+ interest when Armv8.4-SecEL2 or RME extension is implemented.
+ Default is 0 (disabled). This option will be set to 1 (enabled) when ``SPD=spmd``
+ and ``SPMD_SPM_AT_SEL2`` is set or when ``ENABLE_RME`` is set to 1 (enabled).
diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst
index 402de13..d5ded5e 100644
--- a/docs/getting_started/build-options.rst
+++ b/docs/getting_started/build-options.rst
@@ -164,12 +164,6 @@
is on hardware that does not implement AArch32, or at least not at EL1 and
higher ELs). Default value is 1.
-- ``CTX_INCLUDE_EL2_REGS`` : This boolean option provides context save/restore
- operations when entering/exiting an EL2 execution context. This is of primary
- interest when Armv8.4-SecEL2 extension is implemented. Default is 0 (disabled).
- This option must be equal to 1 (enabled) when ``SPD=spmd`` and
- ``SPMD_SPM_AT_SEL2`` is set.
-
- ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP
registers to be included when saving and restoring the CPU context. Default
is 0.
@@ -219,6 +213,12 @@
- ``E``: Boolean option to make warnings into errors. Default is 1.
+ When specifying higher warnings levels (``W=1`` and higher), this option
+ defaults to 0. This is done to encourage contributors to use them, as they
+ are expected to produce warnings that would otherwise fail the build. New
+ contributions are still expected to build with ``W=0`` and ``E=1`` (the
+ default).
+
- ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of
the normal boot flow. It must specify the entry point address of the EL3
payload. Please refer to the "Booting an EL3 payload" section for more
@@ -824,6 +824,11 @@
disabled). This configuration supports pre-Armv8.4 platforms (aka not
implementing the ``FEAT_SEL2`` extension). This is an experimental feature.
+- ``SPMC_OPTEE`` : This boolean option is used jointly with the SPM
+ Dispatcher option (``SPD=spmd``) and with ``SPMD_SPM_AT_SEL2=0`` to
+ indicate that the SPMC at S-EL1 is OP-TEE and an OP-TEE specific loading
+ mechanism should be used.
+
- ``SPMD_SPM_AT_SEL2`` : This boolean option is used jointly with the SPM
Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC
component runs at the S-EL2 exception level provided by the ``FEAT_SEL2``
@@ -955,6 +960,43 @@
regrouped and put in the root Makefile. This flag can take the values 0 to 3,
each level enabling more warning options. Default is 0.
+ This option is closely related to the ``E`` option, which enables
+ ``-Werror``.
+
+ - ``W=0`` (default)
+
+ Enables a wide assortment of warnings, most notably ``-Wall`` and
+ ``-Wextra``, as well as various bad practices and things that are likely to
+ result in errors. Includes some compiler specific flags. No warnings are
+ expected at this level for any build.
+
+ - ``W=1``
+
+ Enables warnings we want the generic build to include but are too time
+ consuming to fix at the moment. It re-enables warnings taken out for
+ ``W=0`` builds (a few of the ``-Wextra`` additions). This level is expected
+ to eventually be merged into ``W=0``. Some warnings are expected on some
+ builds, but new contributions should not introduce new ones.
+
+ - ``W=2`` (recommended)
+
+ Enables warnings we want the generic build to include but cannot be enabled
+ due to external libraries. This level is expected to eventually be merged
+ into ``W=0``. Lots of warnings are expected, primarily from external
+ libraries like zlib and compiler-rt, but new controbutions should not
+ introduce new ones.
+
+ - ``W=3``
+
+ Enables warnings that are informative but not necessary and generally too
+ verbose and frequently ignored. A very large number of warnings are
+ expected.
+
+ The exact set of warning flags depends on the compiler and TF-A warning
+ level, however they are all succinctly set in the top-level Makefile. Please
+ refer to the `GCC`_ or `Clang`_ documentation for more information on the
+ individual flags.
+
- ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on
the CPU after warm boot. This is applicable for platforms which do not
require interconnect programming to enable cache coherency (eg: single
@@ -1162,3 +1204,5 @@
.. _DEN0115: https://developer.arm.com/docs/den0115/latest
.. _PSA FW update specification: https://developer.arm.com/documentation/den0118/a/
.. _PSA DRTM specification: https://developer.arm.com/documentation/den0113/a
+.. _GCC: https://gcc.gnu.org/onlinedocs/gcc/Warning-Options.html
+.. _Clang: https://clang.llvm.org/docs/DiagnosticsReference.html
diff --git a/docs/getting_started/index.rst b/docs/getting_started/index.rst
index 3fbf48d..5ebabea 100644
--- a/docs/getting_started/index.rst
+++ b/docs/getting_started/index.rst
@@ -10,6 +10,7 @@
initial-build
tools-build
build-options
+ build-internals
image-terminology
porting-guide
psci-lib-integration-guide
diff --git a/docs/getting_started/porting-guide.rst b/docs/getting_started/porting-guide.rst
index aa57e1d..80b72e5 100644
--- a/docs/getting_started/porting-guide.rst
+++ b/docs/getting_started/porting-guide.rst
@@ -2135,7 +2135,7 @@
#. Providing runtime firmware services. Currently, BL31 only implements a
subset of the Power State Coordination Interface (PSCI) API as a runtime
- service. See Section 3.3 below for details of porting the PSCI
+ service. See :ref:`psci_in_bl31` below for details of porting the PSCI
implementation.
#. Optionally passing control to the BL32 image, pre-loaded at a platform-
@@ -2544,6 +2544,8 @@
This function writes entropy into storage provided by the caller. If no entropy
is available, it must return false and the storage must not be written.
+.. _psci_in_bl31:
+
Power State Coordination Interface (in BL31)
--------------------------------------------
@@ -3396,6 +3398,39 @@
The default implementation of this function calls
``report_unhandled_exception``.
+Function : plat_handle_rng_trap
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+::
+
+ Argument : uint64_t
+ Argument : cpu_context_t *
+ Return : int
+
+This function is invoked by BL31's exception handler when there is a synchronous
+system register trap caused by access to the RNDR or RNDRRS registers. It allows
+platforms implementing ``FEAT_RNG_TRAP`` and enabling ``ENABLE_FEAT_RNG_TRAP`` to
+emulate those system registers by returing back some entropy to the lower EL.
+
+The first parameter (``uint64_t esr_el3``) contains the content of the ESR_EL3
+syndrome register, which encodes the instruction that was trapped. The interesting
+information in there is the target register (``get_sysreg_iss_rt()``).
+
+The second parameter (``cpu_context_t *ctx``) represents the CPU state in the
+lower exception level, at the time when the execution of the ``mrs`` instruction
+was trapped. Its content can be changed, to put the entropy into the target
+register.
+
+The return value indicates how to proceed:
+
+- When returning ``TRAP_RET_UNHANDLED`` (-1), the machine will panic.
+- When returning ``TRAP_RET_REPEAT`` (0), the exception handler will return
+ to the same instruction, so its execution will be repeated.
+- When returning ``TRAP_RET_CONTINUE`` (1), the exception handler will return
+ to the next instruction.
+
+This function needs to be implemented by a platform if it enables FEAT_RNG_TRAP.
+
Build flags
-----------
diff --git a/docs/plat/arm/arm-build-options.rst b/docs/plat/arm/arm-build-options.rst
index 407c04b..68eb3ec 100644
--- a/docs/plat/arm/arm-build-options.rst
+++ b/docs/plat/arm/arm-build-options.rst
@@ -49,7 +49,7 @@
field of power-state parameter.
- ``ARM_ROTPK_LOCATION``: used when ``TRUSTED_BOARD_BOOT=1``. It specifies the
- location of the ROTPK hash returned by the function ``plat_get_rotpk_info()``
+ location of the ROTPK returned by the function ``plat_get_rotpk_info()``
for Arm platforms. Depending on the selected option, the proper private key
must be specified using the ``ROT_KEY`` option when building the Trusted
Firmware. This private key will be used by the certificate generation tool
@@ -68,12 +68,16 @@
``arm_rotpk_ecdsa.der``, located in ``plat/arm/board/common/rotpk``. To
use this option, ``arm_rotprivk_ecdsa.pem`` must be specified as
``ROT_KEY`` when creating the certificates.
+ - ``devel_full_dev_rsa_key`` : returns a development public key embedded in
+ the BL1 and BL2 binaries. This key has been obtained from the RSA public
+ key ``arm_rotpk_rsa.der``, located in ``plat/arm/board/common/rotpk``.
-- ``ARM_ROTPK_HASH``: used when ``ARM_ROTPK_LOCATION=devel_*``. Specifies the
- location of the ROTPK hash. Not expected to be a build option. This defaults to
- ``plat/arm/board/common/rotpk/*_sha256.bin`` depending on the specified algorithm.
- Providing ``ROT_KEY`` enforces generation of the hash from the ``ROT_KEY`` and
- overwrites the default hash file.
+- ``ARM_ROTPK_HASH``: used when ``ARM_ROTPK_LOCATION=devel_*``, excluding
+ ``devel_full_dev_rsa_key``. Specifies the location of the ROTPK hash. Not
+ expected to be a build option. This defaults to
+ ``plat/arm/board/common/rotpk/*_sha256.bin`` depending on the specified
+ algorithm. Providing ``ROT_KEY`` enforces generation of the hash from the
+ ``ROT_KEY`` and overwrites the default hash file.
- ``ARM_TSP_RAM_LOCATION``: location of the TSP binary. Options:
diff --git a/docs/process/security-hardening.rst b/docs/process/security-hardening.rst
index 507046f..f9618db 100644
--- a/docs/process/security-hardening.rst
+++ b/docs/process/security-hardening.rst
@@ -131,38 +131,9 @@
overflows.
- The ``W`` build flag can be used to enable a number of compiler warning
- options to detect potentially incorrect code.
-
- - W=0 (default value)
-
- The ``Wunused`` with ``Wno-unused-parameter``, ``Wdisabled-optimization``
- and ``Wvla`` flags are enabled.
-
- The ``Wunused-but-set-variable``, ``Wmaybe-uninitialized`` and
- ``Wpacked-bitfield-compat`` are GCC specific flags that are also enabled.
-
- - W=1
-
- Adds ``Wextra``, ``Wmissing-format-attribute``, ``Wmissing-prototypes``,
- ``Wold-style-definition`` and ``Wunused-const-variable``.
-
- - W=2
-
- Adds ``Waggregate-return``, ``Wcast-align``, ``Wnested-externs``,
- ``Wshadow``, ``Wlogical-op``.
-
- - W=3
-
- Adds ``Wbad-function-cast``, ``Wcast-qual``, ``Wconversion``, ``Wpacked``,
- ``Wpointer-arith``, ``Wredundant-decls`` and
- ``Wswitch-default``.
-
- Refer to the GCC or Clang documentation for more information on the individual
- options: https://gcc.gnu.org/onlinedocs/gcc/Warning-Options.html and
- https://clang.llvm.org/docs/DiagnosticsReference.html.
-
- NB: The ``Werror`` flag is enabled by default in TF-A and can be disabled by
- setting the ``E`` build flag to 0.
+ options to detect potentially incorrect code. TF-A is tested with ``W=0`` but
+ it is recommended to develop against ``W=2`` (which will eventually become the
+ default).
.. rubric:: References
diff --git a/docs/resources/diagrams/plantuml/tfa_rss_dfd.puml b/docs/resources/diagrams/plantuml/tfa_rss_dfd.puml
new file mode 100644
index 0000000..23f5b17
--- /dev/null
+++ b/docs/resources/diagrams/plantuml/tfa_rss_dfd.puml
@@ -0,0 +1,77 @@
+/'
+ ' Copyright (c) 2021-2022, Arm Limited. All rights reserved.
+ '
+ ' SPDX-License-Identifier: BSD-3-Clause
+ '/
+
+/'
+TF-A Data Flow Diagram including RSS
+'/
+
+@startuml
+digraph tfa_dfd {
+
+ # Arrange nodes from left to right
+ rankdir="LR"
+
+ # Allow arrows to end on cluster boundaries
+ compound=true
+
+ # Default settings for edges and nodes
+ edge [minlen=2 color="#8c1b07"]
+ node [fillcolor="#ffb866" style=filled shape=box fixedsize=true width=1.6 height=0.7]
+
+ # Nodes outside of the trust boundary
+ nsec [label="Non-secure\nClients"]
+ sec [label="Secure\nClients"]
+ dbg [label="Debug & Trace"]
+ logs [label="Logs\n(UART)"]
+ nvm [label="Non-volatile\nMemory"]
+
+
+ # Trust boundary cluster
+ subgraph cluster_trusted{
+ graph [style=dashed color="#f22430"]
+
+ # HW IPs cluster
+ subgraph cluster_ip{
+ label ="Hardware IPs";
+ graph [style=filled color="#000000" fillcolor="#ffd29e"]
+
+ rank="same"
+ gic [label="GIC" width=1.2 height=0.5]
+ tzc [label="TZ\nController" width=1.2 height=0.5]
+ etc [label="..." shape=none style=none height=0.5]
+ }
+
+ # TF-A cluster
+ subgraph cluster_tfa{
+ label ="TF-A";
+ graph [style=filled color="#000000" fillcolor="#faf9cd"]
+
+ bl1 [label="Boot ROM\n(BL1)" fillcolor="#ddffb3"];
+ bl2 [label="Trusted Boot\nFirmware\n(BL2)" fillcolor="#ddffb3" height=1]
+ bl31 [label="TF-A Runtime\n(BL31)" fillcolor="#ddffb3"]
+ }
+
+ # RSS cluster
+ subgraph cluster_rss{
+ label ="RSS";
+ graph [style=filled color="#000000" fillcolor="#faf9cd"]
+
+ rss [label="Runtime Security\n\ Subsystem\n\ (RSS)" fillcolor="#ddffb3"]
+ }
+ }
+
+ # Interactions between nodes
+ nvm -> bl31 [lhead=cluster_tfa label="DF1"]
+ logs -> bl31 [dir="back" lhead=cluster_tfa label="DF2"]
+ dbg -> bl2 [dir="both" lhead=cluster_tfa label="DF3"]
+ sec -> bl2 [dir="both" lhead=cluster_tfa label="DF4"]
+ nsec -> bl1 [dir="both" lhead=cluster_tfa, label="DF5"]
+ bl2 -> tzc [dir="both" ltail=cluster_tfa lhead=cluster_ip label="DF6" minlen=1]
+ bl31 -> rss [dir="both" ltail=cluster_tfa lhead=cluster_rss label="DF7" minlen=1]
+
+}
+
+@enduml
diff --git a/docs/security_advisories/index.rst b/docs/security_advisories/index.rst
index b80ba34..c9b0f78 100644
--- a/docs/security_advisories/index.rst
+++ b/docs/security_advisories/index.rst
@@ -14,3 +14,4 @@
security-advisory-tfv-7.rst
security-advisory-tfv-8.rst
security-advisory-tfv-9.rst
+ security-advisory-tfv-10.rst
diff --git a/docs/security_advisories/security-advisory-tfv-10.rst b/docs/security_advisories/security-advisory-tfv-10.rst
new file mode 100644
index 0000000..91dba07
--- /dev/null
+++ b/docs/security_advisories/security-advisory-tfv-10.rst
@@ -0,0 +1,159 @@
+Advisory TFV-10 (CVE-2022-47630)
+================================
+
++----------------+-------------------------------------------------------------+
+| Title | Incorrect validation of X.509 certificate extensions can |
+| | result in an out-of-bounds read. |
++================+=============================================================+
+| CVE ID | `CVE-2022-47630`_ |
++----------------+-------------------------------------------------------------+
+| Date | Reported on 12 Dec 2022 |
++----------------+-------------------------------------------------------------+
+| Versions | v1.2 to v2.8 |
+| Affected | |
++----------------+-------------------------------------------------------------+
+| Configurations | BL1 and BL2 with Trusted Boot enabled with custom, |
+| Affected | downstream usages of ``get_ext()`` and/or ``auth_nvctr()`` |
+| | interfaces. Not exploitable in upstream TF-A code. |
++----------------+-------------------------------------------------------------+
+| Impact | Out-of-bounds read. |
++----------------+-------------------------------------------------------------+
+| Fix Version | - `fd37982a19a4a291`_ "fix(auth): forbid junk after |
+| | extensions" |
+| | |
+| | - `72460f50e2437a85`_ "fix(auth): require at least one |
+| | extension to be present" |
+| | |
+| | - `f5c51855d36e399e`_ "fix(auth): properly validate X.509 |
+| | extensions" |
+| | |
+| | - `abb8f936fd0ad085`_ "fix(auth): avoid out-of-bounds read |
+| | in auth_nvctr()" |
+| | |
+| | Note that `72460f50e2437a85`_ is not fixing any |
+| | vulnerability per se but it is required for |
+| | `f5c51855d36e399e`_ to apply cleanly. |
++----------------+-------------------------------------------------------------+
+| Credit | Demi Marie Obenour, Invisible Things Lab |
++----------------+-------------------------------------------------------------+
+
+This security advisory describes a vulnerability in the X.509 parser used to
+parse boot certificates in TF-A trusted boot: it is possible for a crafted
+certificate to cause an out-of-bounds memory read.
+
+Note that upstream platforms are **not** affected by this. Only downstream
+platforms may be, if (and only if) the interfaces described below are used in a
+different context than seen in upstream code. Details of such context is
+described in the rest of this document.
+
+To fully understand this security advisory, it is recommended to refer to the
+following standards documents:
+
+ - `RFC 5280`_, *Internet X.509 Public Key Infrastructure Certificate and
+ Certificate Revocation List (CRL) Profile*.
+
+ - `ITU-T X.690`_, *ASN.1 encoding rules: Specification of Basic Encoding Rules
+ (BER), Canonical Encoding Rules (CER) and Distinguished Encoding Rules
+ (DER).*
+
+Bug 1: Insufficient certificate validation
+------------------------------------------
+
+The vulnerability lies in the following source file:
+``drivers/auth/mbedtls/mbedtls_x509_parser.c``. By design, ``get_ext()`` does
+not check the return value of the various ``mbedtls_*()`` functions, as
+``cert_parse()`` is assumed to have guaranteed that they will always succeed.
+However, it passes the end of an extension as the end pointer to these
+functions, whereas ``cert_parse()`` passes the end of the ``TBSCertificate``.
+Furthermore, ``cert_parse()`` does not check that the contents of the extension
+have the same length as the extension itself. It also does not check that the
+extension block extends to the end of the ``TBSCertificate``.
+
+This is a problem, as ``mbedtls_asn1_get_tag()`` leaves ``*p`` and ``*len``
+undefined on failure. In practice, this results in ``get_ext()`` continuing to
+parse at different offsets than were used (and validated) by ``cert_parse()``,
+which means that the in-bounds guarantee provided by ``cert_parse()`` no longer
+holds. The result is that it is possible for ``get_ext()`` to read memory past
+the end of the certificate. This could potentially access memory with dangerous
+read side effects, or leak microarchitectural state that could theoretically be
+retrieved through some side-channel attacks as part of a more complex attack.
+
+Bug 2: Missing bounds check in ``auth_nvctr()``
+-----------------------------------------------
+``auth_nvctr()`` does not check that the buffer provided is
+long enough to hold an ``ASN.1 INTEGER``. Since ``auth_nvctr()`` will only ever
+read 6 bytes, it is possible to read up to 6 bytes past the end of the buffer.
+
+Exploitability Analysis
+-----------------------
+
+Upstream TF-A Code
+~~~~~~~~~~~~~~~~~~
+
+In upstream TF-A code, the only caller of ``auth_nvctr()`` takes its input from
+``get_ext()``, which means that the second bug is exploitable, so is the first.
+Therefore, only the first bug need be considered.
+
+All standard chains of trust provided in TF-A source tree (that is, under
+``drivers/auth/``) require that the certificate's signature has already been
+validated prior to calling ``get_ext()``, or any function that calls ``get_ext()``.
+Platforms taking their chain of trust from a dynamic configuration file (such as
+``fdts/cot_descriptors.dtsi``) are also safe, as signature verification will
+always be done prior to any calls to ``get_ext()`` or ``auth_nvctr()`` in this
+case, no matter the order of the properties in the file. Therefore, it is not
+possible to exploit this vulnerability pre-authentication in upstream TF-A.
+
+Furthermore, the data read through ``get_ext()`` only
+ever gets used by the authentication framework (``drivers/auth/auth_mod.c``),
+which greatly reduces the range of inputs it will ever receive and thus the
+impact this has. Specifically, the authentication framework uses ``get_ext()``
+in three cases:
+
+ 1. Retrieving a hash from an X.509 certificate to check the integrity of a
+ child certificate (see ``auth_hash()``).
+
+ 2. Retrieving the signature details from an X.509 certificate to check its
+ authenticity and integrity (see ``auth_signature()``).
+
+ 3. Retrieving the security counter value from an X.509 certificate to protect
+ it from unauthorized rollback to a previous version (see ``auth_nvctr()``).
+
+None of these uses authentication framework write to the out-of-bounds memory,
+so no memory corruption is possible.
+
+In summary, there are 2 separate issues - one in ``get_ext()`` and another one
+in ``auth_nvctr()`` - but neither of these can be exploited in the context of
+TF-A upstream code.
+
+Only in the following 2 cases do we expect this vulnerability to be triggerable
+prior to authentication:
+
+ - The platform uses a custom chain of trust which uses the non-volatile counter
+ authentication method (``AUTH_METHOD_NV_CTR``) before the cryptographic
+ authentication method (``AUTH_METHOD_SIG``).
+
+ - The chain of trust uses a custom authentication method that calls
+ ``get_ext()`` before cryptographic authentication.
+
+Custom Image Parsers
+~~~~~~~~~~~~~~~~~~~~
+
+If the platform uses a custom image parser instead of the certificate parser,
+the bug in the certificate parser is obviously not relevant. The bug in
+``auth_nvctr()`` *may* be relevant, but only if the returned data is:
+
+- Taken from an untrusted source (meaning that it is read prior to
+ authentication).
+
+- Not already checked to be a primitively-encoded ASN.1 tag.
+
+In particular, if the custom image parser implementation wraps a 32-bit integer
+in an ASN.1 ``INTEGER``, it is not affected.
+
+.. _CVE-2022-47630: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2022-47630
+.. _fd37982a19a4a291: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=fd37982a19a4a291
+.. _72460f50e2437a85: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=72460f50e2437a85
+.. _f5c51855d36e399e: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=f5c51855d36e399e
+.. _abb8f936fd0ad085: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=abb8f936fd0ad085
+.. _RFC 5280: https://www.ietf.org/rfc/rfc5280.txt
+.. _ITU-T X.690: https://www.itu.int/ITU-T/studygroups/com10/languages/X.690_1297.pdf
diff --git a/docs/threat_model/index.rst b/docs/threat_model/index.rst
index ad8b82a..9fd55a9 100644
--- a/docs/threat_model/index.rst
+++ b/docs/threat_model/index.rst
@@ -16,7 +16,8 @@
threat_model_spm
threat_model_el3_spm
threat_model_fvp_r
+ threat_model_rss_interface
--------------
-*Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.*
diff --git a/docs/threat_model/threat_model.rst b/docs/threat_model/threat_model.rst
index 38e5c87..99bbb3a 100644
--- a/docs/threat_model/threat_model.rst
+++ b/docs/threat_model/threat_model.rst
@@ -170,7 +170,7 @@
For each threat identified, a risk rating that ranges
from *informational* to *critical* is given based on the likelihood of the
-threat occuring if a mitigation is not in place, and the impact of the
+threat occurring if a mitigation is not in place, and the impact of the
threat (i.e. how severe the consequences could be). Table 4 explains each
rating in terms of score, impact and likelihood.
@@ -778,8 +778,9 @@
+========================+====================================================+
| Threat | | **Misconfiguration of the Memory Management Unit |
| | (MMU) may allow a normal world software to |
-| | access sensitive data or execute arbitrary |
-| | code** |
+| | access sensitive data, execute arbitrary |
+| | code or access otherwise restricted HW |
+| | interface** |
| | |
| | | A misconfiguration of the MMU could |
| | lead to an open door for software running in the |
@@ -853,6 +854,8 @@
+------------------------+-----------------------------------------------------+
| Threat Type | Information Disclosure |
+------------------------+-------------------+----------------+----------------+
+| Application | Server | IoT | Mobile |
++------------------------+-------------------+----------------+----------------+
| Impact | Medium (3) | Medium (3) | Medium (3) |
+------------------------+-------------------+----------------+----------------+
| Likelihood | Low (2) | Low (2) | Low (2) |
@@ -880,6 +883,41 @@
| | mitigated. |
+------------------------+-----------------------------------------------------+
++------------------------+-----------------------------------------------------+
+| ID | 13 |
++========================+=====================================================+
+| Threat | | **Leaving sensitive information in the memory, |
+| | can allow an attacker to retrieve them.** |
+| | |
+| | | Accidentally leaving not-needed sensitive data in |
+| | internal buffers can leak them if an attacker |
+| | gains access to memory due to a vulnerability. |
++------------------------+-----------------------------------------------------+
+| Diagram Elements | DF4, DF5 |
++------------------------+-----------------------------------------------------+
+| Affected TF-A | BL1, BL2, BL31 |
+| Components | |
++------------------------+-----------------------------------------------------+
+| Assets | Sensitive Data |
++------------------------+-----------------------------------------------------+
+| Threat Agent | NSCode, SecCode |
++------------------------+-----------------------------------------------------+
+| Threat Type | Information Disclosure |
++------------------------+-------------------+----------------+----------------+
+| Application | Server | IoT | Mobile |
++------------------------+-------------------+----------------+----------------+
+| Impact | Critical (5) | Critical (5) | Critical (5) |
++------------------------+-------------------+----------------+----------------+
+| Likelihood | Medium (3) | Medium (3) | Medium (3) |
++------------------------+-------------------+----------------+----------------+
+| Total Risk Rating | High (15) | High (15) | High (15) |
++------------------------+-------------------+----------------+----------------+
+| Mitigations | Clear the sensitive data from internal buffers as |
+| | soon as they are not needed anymore. |
++------------------------+-----------------------------------------------------+
+| Mitigations | | Yes / Platform specific |
++------------------------+-----------------------------------------------------+
+
--------------
*Copyright (c) 2021-2022, Arm Limited. All rights reserved.*
diff --git a/docs/threat_model/threat_model_rss_interface.rst b/docs/threat_model/threat_model_rss_interface.rst
new file mode 100644
index 0000000..4bceb63
--- /dev/null
+++ b/docs/threat_model/threat_model_rss_interface.rst
@@ -0,0 +1,59 @@
+Threat Model for RSS - AP interface
+***********************************
+
+************
+Introduction
+************
+This document is an extension for the general TF-A threat-model. It considers
+those platforms where a Runtime Security Subsystem (RSS) is included in the SoC
+next to the Application Processor (AP).
+
+********************
+Target of Evaluation
+********************
+The scope of this threat model only includes the interface between the RSS and
+AP. Otherwise, the TF-A :ref:`Generic Threat Model` document is applicable for
+the AP core. The threat model for the RSS firmware will be provided by the RSS
+firmware project in the future.
+
+
+Data Flow Diagram
+=================
+This diagram is different only from the general TF-A data flow diagram in that
+it includes the RSS and highlights the interface between the AP and the RSS
+cores. The interface description only focuses on the AP-RSS interface the rest
+is the same as in the general TF-A threat-model document.
+
+.. uml:: ../resources/diagrams/plantuml/tfa_rss_dfd.puml
+ :caption: Figure 1: TF-A Data Flow Diagram including RSS
+
+.. table:: Table 1: TF-A - RSS data flow diagram
+
+ +-----------------+--------------------------------------------------------+
+ | Diagram Element | Description |
+ +=================+========================================================+
+ | DF7 | | Boot images interact with RSS over a communication |
+ | | channel to record boot measurements and get image |
+ | | verification keys. At runtime, BL31 obtains the |
+ | | realm world attestation signing key from RSS. |
+ +-----------------+--------------------------------------------------------+
+
+Threat Assessment
+=================
+For this section, please reference the Threat Assessment under the general TF-A
+threat-model document, :ref:`Generic Threat Model`. All the threats listed there
+are applicable for the AP core, here only the differences are highlighted.
+
+ - ID 11: The access to the communication interface between AP and RSS is
+ allowed only for firmware running at EL3. Accidentally exposing this
+ interface to NSCode can allow malicious code to interact with RSS and
+ gain access to sensitive data.
+ - ID 13: Relevant in the context of the realm attestation key, which can be
+ retrieved by BL31 through DF7. The RSS communication protocol layer
+ mitigates against this by clearing its internal buffer when reply is
+ received. The caller of the API must do the same if data is not needed
+ anymore.
+
+--------------
+
+*Copyright (c) 2022, Arm Limited. All rights reserved.*
\ No newline at end of file
diff --git a/drivers/arm/gic/v3/gicv3_main.c b/drivers/arm/gic/v3/gicv3_main.c
index bc93f93..f6c251d 100644
--- a/drivers/arm/gic/v3/gicv3_main.c
+++ b/drivers/arm/gic/v3/gicv3_main.c
@@ -12,6 +12,7 @@
#include <common/interrupt_props.h>
#include <drivers/arm/gicv3.h>
#include <lib/spinlock.h>
+#include <plat/common/platform.h>
#include "gicv3_private.h"
@@ -1287,12 +1288,14 @@
assert(gicv3_driver_data->gicr_base == 0U);
+ if (plat_can_cmo()) {
/* Ensure this function is called with Data Cache enabled */
#ifndef __aarch64__
- assert((read_sctlr() & SCTLR_C_BIT) != 0U);
+ assert((read_sctlr() & SCTLR_C_BIT) != 0U);
#else
- assert((read_sctlr_el3() & SCTLR_C_BIT) != 0U);
+ assert((read_sctlr_el3() & SCTLR_C_BIT) != 0U);
#endif /* !__aarch64__ */
+ }
mpidr_self = read_mpidr_el1() & MPIDR_AFFINITY_MASK;
rdistif_base = gicr_frame;
diff --git a/drivers/arm/rss/rss_comms.c b/drivers/arm/rss/rss_comms.c
index 5e224e1..4622af9 100644
--- a/drivers/arm/rss/rss_comms.c
+++ b/drivers/arm/rss/rss_comms.c
@@ -156,14 +156,22 @@
err = mhu_init_sender(mhu_sender_base);
if (err != MHU_ERR_NONE) {
- ERROR("[RSS-COMMS] Host to RSS MHU driver initialization failed: %d\n", err);
- return -1;
+ if (err == MHU_ERR_ALREADY_INIT) {
+ INFO("[RSS-COMMS] Host to RSS MHU driver already initialized\n");
+ } else {
+ ERROR("[RSS-COMMS] Host to RSS MHU driver initialization failed: %d\n", err);
+ return -1;
+ }
}
err = mhu_init_receiver(mhu_receiver_base);
if (err != MHU_ERR_NONE) {
- ERROR("[RSS-COMMS] RSS to Host MHU driver initialization failed: %d\n", err);
- return -1;
+ if (err == MHU_ERR_ALREADY_INIT) {
+ INFO("[RSS-COMMS] RSS to Host MHU driver already initialized\n");
+ } else {
+ ERROR("[RSS-COMMS] RSS to Host MHU driver initialization failed: %d\n", err);
+ return -1;
+ }
}
return 0;
diff --git a/drivers/auth/auth_mod.c b/drivers/auth/auth_mod.c
index fa9509a..1bf03d4 100644
--- a/drivers/auth/auth_mod.c
+++ b/drivers/auth/auth_mod.c
@@ -243,7 +243,7 @@
unsigned int *cert_nv_ctr,
bool *need_nv_ctr_upgrade)
{
- char *p;
+ unsigned char *p;
void *data_ptr = NULL;
unsigned int data_len, len, i;
unsigned int plat_nv_ctr;
@@ -258,16 +258,24 @@
/* Parse the DER encoded integer */
assert(data_ptr);
- p = (char *)data_ptr;
- if (*p != ASN1_INTEGER) {
+ p = (unsigned char *)data_ptr;
+
+ /*
+ * Integers must be at least 3 bytes: 1 for tag, 1 for length, and 1
+ * for value. The first byte (tag) must be ASN1_INTEGER.
+ */
+ if ((data_len < 3) || (*p != ASN1_INTEGER)) {
/* Invalid ASN.1 integer */
return 1;
}
p++;
- /* NV-counters are unsigned integers up to 32-bit */
- len = (unsigned int)(*p & 0x7f);
- if ((*p & 0x80) || (len > 4)) {
+ /*
+ * NV-counters are unsigned integers up to 31 bits. Trailing
+ * padding is not allowed.
+ */
+ len = (unsigned int)*p;
+ if ((len > 4) || (data_len - 2 != len)) {
return 1;
}
p++;
diff --git a/drivers/auth/mbedtls/mbedtls_common.mk b/drivers/auth/mbedtls/mbedtls_common.mk
index 16ce65f..ae4b067 100644
--- a/drivers/auth/mbedtls/mbedtls_common.mk
+++ b/drivers/auth/mbedtls/mbedtls_common.mk
@@ -22,7 +22,7 @@
MBEDTLS_SOURCES += drivers/auth/mbedtls/mbedtls_common.c
-LIBMBEDTLS_SRCS := $(addprefix ${MBEDTLS_DIR}/library/, \
+LIBMBEDTLS_SRCS += $(addprefix ${MBEDTLS_DIR}/library/, \
aes.c \
asn1parse.c \
asn1write.c \
diff --git a/drivers/auth/mbedtls/mbedtls_crypto.c b/drivers/auth/mbedtls/mbedtls_crypto.c
index d231179..42a0925 100644
--- a/drivers/auth/mbedtls/mbedtls_crypto.c
+++ b/drivers/auth/mbedtls/mbedtls_crypto.c
@@ -115,7 +115,7 @@
end = (unsigned char *)(p + sig_len);
signature.tag = *p;
rc = mbedtls_asn1_get_bitstring_null(&p, end, &signature.len);
- if (rc != 0) {
+ if ((rc != 0) || ((size_t)(end - p) != signature.len)) {
rc = CRYPTO_ERR_SIGNATURE;
goto end1;
}
@@ -170,12 +170,15 @@
size_t len;
int rc;
- /* Digest info should be an MBEDTLS_ASN1_SEQUENCE */
+ /*
+ * Digest info should be an MBEDTLS_ASN1_SEQUENCE
+ * and consume all bytes.
+ */
p = (unsigned char *)digest_info_ptr;
end = p + digest_info_len;
rc = mbedtls_asn1_get_tag(&p, end, &len, MBEDTLS_ASN1_CONSTRUCTED |
MBEDTLS_ASN1_SEQUENCE);
- if (rc != 0) {
+ if (rc != 0 || ((size_t)(end - p) != len)) {
return CRYPTO_ERR_HASH;
}
@@ -195,9 +198,9 @@
return CRYPTO_ERR_HASH;
}
- /* Hash should be octet string type */
+ /* Hash should be octet string type and consume all bytes */
rc = mbedtls_asn1_get_tag(&p, end, &len, MBEDTLS_ASN1_OCTET_STRING);
- if (rc != 0) {
+ if ((rc != 0) || ((size_t)(end - p) != len)) {
return CRYPTO_ERR_HASH;
}
diff --git a/drivers/auth/mbedtls/mbedtls_x509_parser.c b/drivers/auth/mbedtls/mbedtls_x509_parser.c
index 993ef12..bbabd9b 100644
--- a/drivers/auth/mbedtls/mbedtls_x509_parser.c
+++ b/drivers/auth/mbedtls/mbedtls_x509_parser.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -85,9 +85,6 @@
p = v3_ext.p;
end = v3_ext.p + v3_ext.len;
- mbedtls_asn1_get_tag(&p, end, &len, MBEDTLS_ASN1_CONSTRUCTED |
- MBEDTLS_ASN1_SEQUENCE);
-
while (p < end) {
zeromem(&extn_oid, sizeof(extn_oid));
is_critical = 0; /* DEFAULT FALSE */
@@ -144,8 +141,23 @@
{
int ret, is_critical;
size_t len;
- unsigned char *p, *end, *crt_end;
- mbedtls_asn1_buf sig_alg1, sig_alg2;
+ unsigned char *p, *end, *crt_end, *pk_end;
+ mbedtls_asn1_buf sig_alg1;
+ /*
+ * The unique ASN.1 DER encoding of [0] EXPLICIT INTEGER { v3(2} }.
+ */
+ static const char v3[] = {
+ /* The outer CONTEXT SPECIFIC 0 tag */
+ MBEDTLS_ASN1_CONSTRUCTED | MBEDTLS_ASN1_CONTEXT_SPECIFIC | 0,
+ /* The number bytes used to encode the inner INTEGER */
+ 3,
+ /* The tag of the inner INTEGER */
+ MBEDTLS_ASN1_INTEGER,
+ /* The number of bytes needed to represent 2 */
+ 1,
+ /* The actual value 2 */
+ 2,
+ };
p = (unsigned char *)img;
len = img_len;
@@ -163,7 +175,7 @@
return IMG_PARSER_ERR_FORMAT;
}
- if (len > (size_t)(end - p)) {
+ if (len != (size_t)(end - p)) {
return IMG_PARSER_ERR_FORMAT;
}
crt_end = p + len;
@@ -181,15 +193,14 @@
tbs.len = end - tbs.p;
/*
- * Version ::= INTEGER { v1(0), v2(1), v3(2) }
+ * Version ::= [0] EXPLICIT INTEGER { v1(0), v2(1), v3(2) }
+ * -- only v3 accepted
*/
- ret = mbedtls_asn1_get_tag(&p, end, &len,
- MBEDTLS_ASN1_CONTEXT_SPECIFIC |
- MBEDTLS_ASN1_CONSTRUCTED | 0);
- if (ret != 0) {
+ if (((end - p) <= (ptrdiff_t)sizeof(v3)) ||
+ (memcmp(p, v3, sizeof(v3)) != 0)) {
return IMG_PARSER_ERR_FORMAT;
}
- p += len;
+ p += sizeof(v3);
/*
* CertificateSerialNumber ::= INTEGER
@@ -257,9 +268,24 @@
if (ret != 0) {
return IMG_PARSER_ERR_FORMAT;
}
+ pk_end = p + len;
+ pk.len = pk_end - pk.p;
+
+ /* algorithm */
+ ret = mbedtls_asn1_get_tag(&p, pk_end, &len, MBEDTLS_ASN1_CONSTRUCTED |
+ MBEDTLS_ASN1_SEQUENCE);
+ if (ret != 0) {
+ return IMG_PARSER_ERR_FORMAT;
+ }
- pk.len = (p + len) - pk.p;
p += len;
+ /* Key is a BIT STRING and must use all bytes in SubjectPublicKeyInfo */
+ ret = mbedtls_asn1_get_bitstring_null(&p, pk_end, &len);
+ if ((ret != 0) || (p + len != pk_end)) {
+ return IMG_PARSER_ERR_FORMAT;
+ }
+ p = pk_end;
+
/*
* issuerUniqueID [1] IMPLICIT UniqueIdentifier OPTIONAL,
*/
@@ -290,57 +316,79 @@
/*
* extensions [3] EXPLICIT Extensions OPTIONAL
+ * }
+ *
+ * X.509 and RFC5280 allow omitting the extensions entirely.
+ * However, in TF-A, a certificate with no extensions would
+ * always fail later on, as the extensions contain the
+ * information needed to authenticate the next stage in the
+ * boot chain. Furthermore, get_ext() assumes that the
+ * extensions have been parsed into v3_ext, and allowing
+ * there to be no extensions would pointlessly complicate
+ * the code. Therefore, just reject certificates without
+ * extensions. This is also why version 1 and 2 certificates
+ * are rejected above.
*/
ret = mbedtls_asn1_get_tag(&p, end, &len,
MBEDTLS_ASN1_CONTEXT_SPECIFIC |
MBEDTLS_ASN1_CONSTRUCTED | 3);
- if (ret != 0) {
+ if ((ret != 0) || (len != (size_t)(end - p))) {
return IMG_PARSER_ERR_FORMAT;
}
/*
* Extensions ::= SEQUENCE SIZE (1..MAX) OF Extension
+ * -- must use all remaining bytes in TBSCertificate
*/
- v3_ext.p = p;
ret = mbedtls_asn1_get_tag(&p, end, &len, MBEDTLS_ASN1_CONSTRUCTED |
MBEDTLS_ASN1_SEQUENCE);
- if (ret != 0) {
+ if ((ret != 0) || (len != (size_t)(end - p))) {
return IMG_PARSER_ERR_FORMAT;
}
- v3_ext.len = (p + len) - v3_ext.p;
+ v3_ext.p = p;
+ v3_ext.len = len;
/*
- * Check extensions integrity
+ * Check extensions integrity. At least one extension is
+ * required: the ASN.1 specifies a minimum size of 1, and at
+ * least one extension is needed to authenticate the next stage
+ * in the boot chain.
*/
- while (p < end) {
+ do {
+ unsigned char *end_ext_data;
+
ret = mbedtls_asn1_get_tag(&p, end, &len,
MBEDTLS_ASN1_CONSTRUCTED |
MBEDTLS_ASN1_SEQUENCE);
if (ret != 0) {
return IMG_PARSER_ERR_FORMAT;
}
+ end_ext_data = p + len;
/* Get extension ID */
- ret = mbedtls_asn1_get_tag(&p, end, &len, MBEDTLS_ASN1_OID);
+ ret = mbedtls_asn1_get_tag(&p, end_ext_data, &len, MBEDTLS_ASN1_OID);
if (ret != 0) {
return IMG_PARSER_ERR_FORMAT;
}
p += len;
/* Get optional critical */
- ret = mbedtls_asn1_get_bool(&p, end, &is_critical);
+ ret = mbedtls_asn1_get_bool(&p, end_ext_data, &is_critical);
if ((ret != 0) && (ret != MBEDTLS_ERR_ASN1_UNEXPECTED_TAG)) {
return IMG_PARSER_ERR_FORMAT;
}
- /* Data should be octet string type */
- ret = mbedtls_asn1_get_tag(&p, end, &len,
+ /*
+ * Data should be octet string type and must use all bytes in
+ * the Extension.
+ */
+ ret = mbedtls_asn1_get_tag(&p, end_ext_data, &len,
MBEDTLS_ASN1_OCTET_STRING);
- if (ret != 0) {
+ if ((ret != 0) || ((p + len) != end_ext_data)) {
return IMG_PARSER_ERR_FORMAT;
}
- p += len;
- }
+ p = end_ext_data;
+ } while (p < end);
if (p != end) {
return IMG_PARSER_ERR_FORMAT;
@@ -353,33 +401,22 @@
* -- end of TBSCertificate
*
* signatureAlgorithm AlgorithmIdentifier
+ * -- Does not need to be parsed. Ensuring it is bitwise
+ * -- identical (including the tag!) with the first signature
+ * -- algorithm is sufficient.
*/
- sig_alg2.p = p;
- ret = mbedtls_asn1_get_tag(&p, end, &len, MBEDTLS_ASN1_CONSTRUCTED |
- MBEDTLS_ASN1_SEQUENCE);
- if (ret != 0) {
+ if ((sig_alg1.len >= (size_t)(end - p)) ||
+ (0 != memcmp(sig_alg1.p, p, sig_alg1.len))) {
return IMG_PARSER_ERR_FORMAT;
}
- if ((end - p) < 1) {
- return IMG_PARSER_ERR_FORMAT;
- }
- sig_alg2.len = (p + len) - sig_alg2.p;
- p += len;
-
- /* Compare both signature algorithms */
- if (sig_alg1.len != sig_alg2.len) {
- return IMG_PARSER_ERR_FORMAT;
- }
- if (0 != memcmp(sig_alg1.p, sig_alg2.p, sig_alg1.len)) {
- return IMG_PARSER_ERR_FORMAT;
- }
+ p += sig_alg1.len;
memcpy(&sig_alg, &sig_alg1, sizeof(sig_alg));
/*
* signatureValue BIT STRING
*/
signature.p = p;
- ret = mbedtls_asn1_get_tag(&p, end, &len, MBEDTLS_ASN1_BIT_STRING);
+ ret = mbedtls_asn1_get_bitstring_null(&p, end, &len);
if (ret != 0) {
return IMG_PARSER_ERR_FORMAT;
}
@@ -447,7 +484,7 @@
rc = get_ext(type_desc->cookie, param, param_len);
break;
case AUTH_PARAM_PUB_KEY:
- if (type_desc->cookie != 0) {
+ if (type_desc->cookie != NULL) {
/* Get public key from extension */
rc = get_ext(type_desc->cookie, param, param_len);
} else {
diff --git a/drivers/brcm/emmc/emmc_csl_sdcard.c b/drivers/brcm/emmc/emmc_csl_sdcard.c
index 9e2c618..40bc4a0 100644
--- a/drivers/brcm/emmc/emmc_csl_sdcard.c
+++ b/drivers/brcm/emmc/emmc_csl_sdcard.c
@@ -479,10 +479,11 @@
handle->device->cfg.blockSize = 512;
}
- if (handle->device->ctrl.ocr & SD_CARD_HIGH_CAPACITY)
+ if (handle->device->ctrl.ocr & SD_CARD_HIGH_CAPACITY) {
EMMC_TRACE("Sector addressing\n");
- else
+ } else {
EMMC_TRACE("Byte addressing\n");
+ }
EMMC_TRACE("Ext_CSD_storage[162]: 0x%02X Ext_CSD_storage[179]: 0x%02X\n",
emmc_global_buf_ptr->u.Ext_CSD_storage[162],
diff --git a/drivers/brcm/emmc/emmc_pboot_hal_memory_drv.c b/drivers/brcm/emmc/emmc_pboot_hal_memory_drv.c
index 68f93e7..fcd499f 100644
--- a/drivers/brcm/emmc/emmc_pboot_hal_memory_drv.c
+++ b/drivers/brcm/emmc/emmc_pboot_hal_memory_drv.c
@@ -278,8 +278,9 @@
SDIO_base = EMMC_CTRL_REGS_BASE_ADDR;
- if (SDIO_base == SDIO0_EMMCSDXC_SYSADDR)
+ if (SDIO_base == SDIO0_EMMCSDXC_SYSADDR) {
EMMC_TRACE(" ---> for SDIO 0 Controller\n\n");
+ }
memset(p_sdhandle, 0, sizeof(struct sd_handle));
@@ -290,8 +291,9 @@
memset(p_sdhandle->card, 0, sizeof(struct sd_card_info));
if (chal_sd_start((CHAL_HANDLE *) p_sdhandle->device,
- SD_PIO_MODE, SDIO_base, SDIO_base) != SD_OK)
+ SD_PIO_MODE, SDIO_base, SDIO_base) != SD_OK) {
return NULL;
+ }
set_config(p_sdhandle, SD_NORMAL_SPEED, MAX_CMD_RETRY, SD_DMA_OFF,
SD_DMA_BOUNDARY_4K, EMMC_BLOCK_SIZE, EMMC_WFE_RETRY);
@@ -330,14 +332,16 @@
VERBOSE("EMMC READ: dst=0x%lx, src=0x%lx, size=0x%lx\n",
storage_addr, mem_addr, bytes_to_read);
- if (storage_size < bytes_to_read)
+ if (storage_size < bytes_to_read) {
/* Don't have sufficient storage to complete the operation */
return 0;
+ }
/* Range check non high capacity memory */
if ((p_sdhandle->device->ctrl.ocr & SD_CARD_HIGH_CAPACITY) == 0) {
- if (mem_addr > 0x80000000)
+ if (mem_addr > 0x80000000) {
return 0;
+ }
}
/* High capacity card use block address mode */
@@ -384,10 +388,11 @@
/* Update Physical address */
outputBuf += manual_copy_size;
- if (p_sdhandle->device->ctrl.ocr & SD_CARD_HIGH_CAPACITY)
+ if (p_sdhandle->device->ctrl.ocr & SD_CARD_HIGH_CAPACITY) {
blockAddr++;
- else
+ } else {
blockAddr += blockSize;
+ }
} else {
return 0;
}
@@ -395,10 +400,11 @@
while (remSize >= blockSize) {
- if (remSize >= SD_MAX_BLK_TRANSFER_LENGTH)
+ if (remSize >= SD_MAX_BLK_TRANSFER_LENGTH) {
readLen = SD_MAX_BLK_TRANSFER_LENGTH;
- else
+ } else {
readLen = (remSize / blockSize) * blockSize;
+ }
/* Check for overflow */
if ((rdCount + readLen) > storage_size ||
@@ -409,10 +415,11 @@
}
if (!read_block(p_sdhandle, outputBuf, blockAddr, readLen)) {
- if (p_sdhandle->device->ctrl.ocr & SD_CARD_HIGH_CAPACITY)
+ if (p_sdhandle->device->ctrl.ocr & SD_CARD_HIGH_CAPACITY) {
blockAddr += (readLen / blockSize);
- else
+ } else {
blockAddr += readLen;
+ }
remSize -= readLen;
rdCount += readLen;
@@ -463,8 +470,9 @@
/* range check non high capacity memory */
if ((p_sdhandle->device->ctrl.ocr & SD_CARD_HIGH_CAPACITY) == 0) {
- if (mem_addr > 0x80000000)
+ if (mem_addr > 0x80000000) {
return 0;
+ }
}
/* the high capacity card use block address mode */
@@ -491,11 +499,12 @@
blockAddr, p_sdhandle->device->cfg.blockSize)) {
if (remSize <
- (p_sdhandle->device->cfg.blockSize - offset))
+ (p_sdhandle->device->cfg.blockSize - offset)) {
manual_copy_size = remSize;
- else
+ } else {
manual_copy_size =
p_sdhandle->device->cfg.blockSize - offset;
+ }
memcpy((void *)((uintptr_t)
(emmc_global_buf_ptr->u.tempbuf + offset)),
@@ -530,11 +539,12 @@
inputBuf += manual_copy_size;
if (p_sdhandle->device->ctrl.ocr &
- SD_CARD_HIGH_CAPACITY)
+ SD_CARD_HIGH_CAPACITY) {
blockAddr++;
- else
+ } else {
blockAddr +=
p_sdhandle->device->cfg.blockSize;
+ }
} else
return 0;
} else {
diff --git a/drivers/console/multi_console.c b/drivers/console/multi_console.c
index e3fb749..93c38d8 100644
--- a/drivers/console/multi_console.c
+++ b/drivers/console/multi_console.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2023, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -11,7 +11,7 @@
#include <drivers/console.h>
console_t *console_list;
-uint8_t console_state = CONSOLE_FLAG_BOOT;
+static uint8_t console_state = CONSOLE_FLAG_BOOT;
IMPORT_SYM(console_t *, __STACKS_START__, stacks_start)
IMPORT_SYM(console_t *, __STACKS_END__, stacks_end)
diff --git a/drivers/imx/usdhc/imx_usdhc.c b/drivers/imx/usdhc/imx_usdhc.c
index 07f55b7..49dfc07 100644
--- a/drivers/imx/usdhc/imx_usdhc.c
+++ b/drivers/imx/usdhc/imx_usdhc.c
@@ -136,7 +136,8 @@
break;
case MMC_CMD(18):
multiple = 1;
- /* fall thru for read op */
+ /* for read op */
+ /* fallthrough */
case MMC_CMD(17):
case MMC_CMD(8):
mixctl |= MIXCTRL_DTDSEL;
@@ -144,7 +145,8 @@
break;
case MMC_CMD(25):
multiple = 1;
- /* fall thru for data op flag */
+ /* for data op flag */
+ /* fallthrough */
case MMC_CMD(24):
data = 1;
break;
diff --git a/drivers/io/io_block.c b/drivers/io/io_block.c
index 5d45c2f..b5e0e5f 100644
--- a/drivers/io/io_block.c
+++ b/drivers/io/io_block.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2023, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -271,7 +271,7 @@
block_size = cur->dev_spec->block_size;
assert((length <= cur->size) &&
(length > 0U) &&
- (ops->read != 0));
+ (ops->read != NULL));
/*
* We don't know the number of bytes that we are going
@@ -383,8 +383,8 @@
block_size = cur->dev_spec->block_size;
assert((length <= cur->size) &&
(length > 0U) &&
- (ops->read != 0) &&
- (ops->write != 0));
+ (ops->read != NULL) &&
+ (ops->write != NULL));
/*
* We don't know the number of bytes that we are going
diff --git a/drivers/measured_boot/event_log/event_log.c b/drivers/measured_boot/event_log/event_log.c
index d661c35..6f2898d 100644
--- a/drivers/measured_boot/event_log/event_log.c
+++ b/drivers/measured_boot/event_log/event_log.c
@@ -14,8 +14,6 @@
#include <drivers/auth/crypto_mod.h>
#include <drivers/measured_boot/event_log/event_log.h>
-#include <plat/common/platform.h>
-
#if TPM_ALG_ID == TPM_ALG_SHA512
#define CRYPTO_MD_ID CRYPTO_MD_SHA512
#elif TPM_ALG_ID == TPM_ALG_SHA384
@@ -32,9 +30,6 @@
/* Pointer to the first byte past end of the Event Log buffer */
static uintptr_t log_end;
-/* Pointer to event_log_metadata_t */
-static const event_log_metadata_t *plat_metadata_ptr;
-
/* TCG_EfiSpecIdEvent */
static const id_event_headers_t id_event_header = {
.header = {
@@ -173,10 +168,6 @@
void event_log_init(uint8_t *event_log_start, uint8_t *event_log_finish)
{
event_log_buf_init(event_log_start, event_log_finish);
-
- /* Get pointer to platform's event_log_metadata_t structure */
- plat_metadata_ptr = plat_event_log_get_metadata();
- assert(plat_metadata_ptr != NULL);
}
void event_log_write_specid_event(void)
@@ -276,16 +267,19 @@
* @param[in] data_base Address of data
* @param[in] data_size Size of data
* @param[in] data_id Data ID
+ * @param[in] metadata_ptr Event Log metadata
* @return:
* 0 = success
* < 0 = error
*/
int event_log_measure_and_record(uintptr_t data_base, uint32_t data_size,
- uint32_t data_id)
+ uint32_t data_id,
+ const event_log_metadata_t *metadata_ptr)
{
unsigned char hash_data[CRYPTO_MD_MAX_SIZE];
int rc;
- const event_log_metadata_t *metadata_ptr = plat_metadata_ptr;
+
+ assert(metadata_ptr != NULL);
/* Get the metadata associated with this image. */
while ((metadata_ptr->id != EVLOG_INVALID_ID) &&
diff --git a/drivers/nxp/auth/csf_hdr_parser/csf_hdr_parser.c b/drivers/nxp/auth/csf_hdr_parser/csf_hdr_parser.c
index b878082..4f31c6e 100644
--- a/drivers/nxp/auth/csf_hdr_parser/csf_hdr_parser.c
+++ b/drivers/nxp/auth/csf_hdr_parser/csf_hdr_parser.c
@@ -38,7 +38,7 @@
/* Flag to indicate if values are there in rotpk_hash_table */
bool rotpk_not_dpld = true;
-uint8_t rotpk_hash_table[MAX_KEY_ENTRIES][SHA256_BYTES];
+uint8_t rotpk_hash_table[MAX_KEY_ENTRIES][SHA256_BYTES] __aligned(CACHE_WRITEBACK_GRANULE);
uint32_t num_rotpk_hash_entries;
/*
diff --git a/drivers/nxp/crypto/caam/src/jobdesc.c b/drivers/nxp/crypto/caam/src/jobdesc.c
index f559c4b..92fcb74 100644
--- a/drivers/nxp/crypto/caam/src/jobdesc.c
+++ b/drivers/nxp/crypto/caam/src/jobdesc.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2017-2020 NXP
+ * Copyright 2017-2022 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -11,13 +11,13 @@
#include <stdio.h>
#include <stdlib.h>
+#include <assert.h>
#include "caam.h"
#include <common/debug.h>
#include "jobdesc.h"
#include "rsa.h"
#include "sec_hw_specific.h"
-
/* Return Length of desctiptr from first word */
uint32_t desc_length(uint32_t *desc)
{
@@ -41,6 +41,8 @@
{
uint32_t len = desc_length(desc);
+ assert((len + 1) < MAX_DESC_SIZE_WORDS);
+
/* Add Word at Last */
uint32_t *last = desc + len;
*last = word;
@@ -54,6 +56,9 @@
{
uint32_t len = desc_length(desc);
+ assert((len + (uint32_t) (sizeof(phys_addr_t) / sizeof(uint32_t)))
+ < MAX_DESC_SIZE_WORDS);
+
/* Add Word at Last */
phys_addr_t *last = (phys_addr_t *) (desc + len);
diff --git a/drivers/nxp/ddr/nxp-ddr/ddr.c b/drivers/nxp/ddr/nxp-ddr/ddr.c
index c051b3b..faf20e9 100644
--- a/drivers/nxp/ddr/nxp-ddr/ddr.c
+++ b/drivers/nxp/ddr/nxp-ddr/ddr.c
@@ -269,7 +269,7 @@
unsigned int i;
const struct dynamic_odt *pdodt = NULL;
- const static struct dynamic_odt *table[2][5] = {
+ static const struct dynamic_odt *table[2][5] = {
{single_S, single_D, NULL, NULL},
{dual_SS, dual_DD, NULL, NULL},
};
diff --git a/drivers/nxp/ddr/nxp-ddr/regs.c b/drivers/nxp/ddr/nxp-ddr/regs.c
index cedd7ca..26155ab 100644
--- a/drivers/nxp/ddr/nxp-ddr/regs.c
+++ b/drivers/nxp/ddr/nxp-ddr/regs.c
@@ -1302,7 +1302,7 @@
return 0;
}
- if ((bin[i].taamin_ps[j] == 0) ||
+ if (((bin[i].taamin_ps[j] == 0) && j > 0) ||
(bin[i].taamin_ps[j] > taamin_ps && j > 0)) {
j--;
}
diff --git a/drivers/nxp/ddr/phy-gen2/messages.h b/drivers/nxp/ddr/phy-gen2/messages.h
index 7dec7df..a2310f2 100644
--- a/drivers/nxp/ddr/phy-gen2/messages.h
+++ b/drivers/nxp/ddr/phy-gen2/messages.h
@@ -13,7 +13,7 @@
const char *msg;
};
-const static struct phy_msg messages_1d[] = {
+static const struct phy_msg messages_1d[] = {
{0x00000001,
"PMU1:prbsGenCtl:%x\n"
},
@@ -1239,7 +1239,7 @@
},
};
-const static struct phy_msg messages_2d[] = {
+static const struct phy_msg messages_2d[] = {
{0x00000001,
"PMU0: Converting %d into an MR\n"
},
diff --git a/drivers/nxp/ddr/phy-gen2/phy.c b/drivers/nxp/ddr/phy-gen2/phy.c
index 9e52145..2006c04 100644
--- a/drivers/nxp/ddr/phy-gen2/phy.c
+++ b/drivers/nxp/ddr/phy-gen2/phy.c
@@ -241,12 +241,6 @@
rwmax = tmp;
}
- tmp = wrmax;
- wrmax = cdd[56];
- if (tmp > wrmax) {
- wrmax = tmp;
- }
-
break;
case 2U:
@@ -276,15 +270,7 @@
rwmax = tmp;
}
- buf[0] = cdd[56];
- buf[1] = cdd[55];
- buf[2] = cdd[52];
- buf[3] = cdd[51];
- tmp = wrmax;
- wrmax = findmax(buf, 4U);
- if (tmp > wrmax) {
- wrmax = tmp;
- }
+ wrmax = wwmax;
break;
@@ -310,12 +296,7 @@
rwmax = tmp;
}
- tmp = wrmax;
- c = &cdd[41];
- wrmax = findmax(c, 16U);
- if (tmp > wrmax) {
- wrmax = tmp;
- }
+ wrmax = wwmax;
break;
@@ -390,7 +371,12 @@
#ifdef NXP_WARM_BOOT
int save_phy_training_values(uint16_t **phy_ptr, uint32_t address_to_store,
- uint32_t num_of_phy, int train2d)
+ uint32_t num_of_phy, int train2d
+#ifdef NXP_APPLY_MAX_CDD
+ , struct ddr_ctrl_reg_values *ddrctrl_regs
+#endif
+ )
+
{
uint16_t *phy = NULL, value = 0x0;
uint32_t size = 1U, num_of_regs = 1U, phy_store = 0U;
@@ -457,6 +443,15 @@
ret = xspi_write(phy_store, training_2D_values,
size);
}
+
+#ifdef NXP_APPLY_MAX_CDD
+ /* Save DDR control register Timing CFG 0 and 4 */
+ phy_store += size;
+ size = sizeof(ddrctrl_regs);
+ if (ret != 0) {
+ ret = xspi_write(phy_store, ddrctrl_regs, size);
+ }
+#endif
/* Disable clocks in case they were disabled. */
phy_io_write16(phy, t_drtub |
csr_ucclk_hclk_enables_addr, 0x0);
@@ -472,7 +467,11 @@
}
int restore_phy_training_values(uint16_t **phy_ptr, uint32_t address_to_restore,
- uint32_t num_of_phy, int train2d)
+ uint32_t num_of_phy, int train2d
+#ifdef NXP_APPLY_MAX_CDD
+ , struct ddr_ctrl_reg_values *ddrctrl_regs
+#endif
+ )
{
uint16_t *phy = NULL;
uint32_t size = 1U, num_of_regs = 1U, phy_store = 0U;
@@ -504,6 +503,14 @@
/* Reading 1D training values from flash*/
ret = xspi_read(phy_store, (uint32_t *)training_1D_values,
size);
+ if (ret != 0) {
+#ifdef DEBUG_WARM_RESET
+ debug("Unable to Read 1D training values %d\n",
+ ret);
+#endif
+ return -EINVAL;
+ }
+
debug("Restoring 1D Training reg val at:%08x\n", phy_store);
for (i = 0; i < num_of_regs; i++) {
phy_io_write16(phy, training_1D_values[i].addr,
@@ -523,6 +530,15 @@
/* Reading 2D training values from flash */
ret = xspi_read(phy_store,
(uint32_t *)training_2D_values, size);
+
+ if (ret != 0) {
+#ifdef DEBUG_WARM_RESET
+ debug("Unable to Read 2D training values %d\n",
+ ret);
+#endif
+ return -EINVAL;
+ }
+
debug("Restoring 2D Training reg val at:%08x\n",
phy_store);
for (i = 0; i < num_of_regs; i++) {
@@ -537,6 +553,11 @@
#endif
}
}
+#ifdef NXP_APPLY_MAX_CDD
+ phy_store = phy_store + size;
+ size = sizeof(ddrctrl_regs);
+ ret = xspi_read(phy_store, (uint32_t *)ddrctrl_regs, size);
+#endif
/* Disable clocks in case they were disabled. */
phy_io_write16(phy, t_drtub |
csr_ucclk_hclk_enables_addr, 0x0);
@@ -2292,6 +2313,7 @@
if (i < 0 || i > 3) {
printf("Error: invalid chip-select value\n");
+ return;
}
switch (val) {
case DDR_ODT_CS:
@@ -2473,6 +2495,9 @@
__unused const soc_info_t *soc_info;
#ifdef NXP_APPLY_MAX_CDD
unsigned int tcfg0, tcfg4, rank;
+#ifdef NXP_WARM_BOOT
+ struct ddr_ctrl_reg_values ddrctrl_regs;
+#endif
#endif
if (dimm_param == NULL) {
@@ -2577,11 +2602,19 @@
ret = restore_phy_training_values(priv->phy,
PHY_TRAINING_REGS_ON_FLASH,
priv->num_ctlrs,
- input.basic.train2d);
+ input.basic.train2d
+#ifdef NXP_APPLY_MAX_CDD
+ , &ddrctrl_regs
+#endif
+ );
if (ret != 0) {
ERROR("Restoring of training data failed %d\n", ret);
return ret;
}
+#ifdef NXP_APPLY_MAX_CDD
+ regs->timing_cfg[0] = ddrctrl_regs.timing_cfg0;
+ regs->timing_cfg[4] = ddrctrl_regs.timing_cfg4;
+#endif
} else {
#endif
/* Mapping IMG buffer firstly */
@@ -2644,12 +2677,20 @@
#ifdef NXP_WARM_BOOT
if (priv->warm_boot_flag != DDR_WRM_BOOT_NT_SUPPORTED &&
ret == 0) {
+#ifdef NXP_APPLY_MAX_CDD
+ ddrctrl_regs.timing_cfg0 = regs->timing_cfg[0];
+ ddrctrl_regs.timing_cfg4 = regs->timing_cfg[4];
+#endif
debug("save the phy training data\n");
//Save training data TBD
ret = save_phy_training_values(priv->phy,
PHY_TRAINING_REGS_ON_FLASH,
priv->num_ctlrs,
- input.basic.train2d);
+ input.basic.train2d
+#ifdef NXP_APPLY_MAX_CDD
+ , &ddrctrl_regs
+#endif
+ );
if (ret != 0) {
ERROR("Saving training data failed.");
ERROR("Warm boot will fail. Error=%d.\n", ret);
diff --git a/drivers/nxp/ddr/phy-gen2/phy.h b/drivers/nxp/ddr/phy-gen2/phy.h
index 15e80d1..5e80f36 100644
--- a/drivers/nxp/ddr/phy-gen2/phy.h
+++ b/drivers/nxp/ddr/phy-gen2/phy.h
@@ -11,11 +11,18 @@
/* To store sector size to be erase on flash*/
#define PHY_ERASE_SIZE F_SECTOR_ERASE_SZ
+/*Structure to save DDR controller timing register 0 and 4 values*/
+struct ddr_ctrl_reg_values {
+ uint32_t timing_cfg0;
+ uint32_t timing_cfg4;
+};
+
/*Structure to implement address-data map tuples to store PHY training values*/
struct phy_training_values {
uint32_t addr;
uint16_t data;
};
+
/* Saves PHY Training Register values after cold reset
*@param[in] phy_ptr array to store addresses of PHYs
*@param[in] address_to_store address to save PHY training register values
@@ -24,6 +31,8 @@
*to be saved
*@param[in] train2d flag to store whether 2D training registers are to
*be saved or not
+ *@param[in] ddrctrl_regs to save ddr controller registers in case
+ *NXP_APPLY_MAX_CDD is applied
*
*PHY training values will be stored on flash at contigous memory in the order:
*1D training registers, 2D training registers
@@ -31,9 +40,13 @@
*
*if train2d is false saving 2D training registers will be skipped
*/
-int save_phy_training_values(uint16_t **phy_ptr, uint32_t address_to_store,
- uint32_t num_of_phy, int train2d);
+int save_phy_training_values(uint16_t **phy_ptr, uint32_t address_to_store,
+ uint32_t num_of_phy, int train2d
+#ifdef NXP_APPLY_MAX_CDD
+ , struct ddr_ctrl_reg_values *ddrctrl_regs
+#endif
+ );
/*Restores PHY Training Register values after warm reset
*@param[in] phy_ptr array to store addresses of PHYs
*@param[in] address_to_store address to retrieve PHY training register
@@ -42,12 +55,17 @@
*to be restored
*@param[in] train2d flag to store whether 2D training registers are
*to be restored or not
- *
+ *@param[in] ddrctrl_regs to restore ddr controller registers in case
+ *NXP_APPLY_MAX_CDD is applied
*if train2d is false saving 2D training registers will be skipped
*/
int restore_phy_training_values(uint16_t **phy_ptr, uint32_t address_to_restore,
- uint32_t num_of_phy, int train2d);
+ uint32_t num_of_phy, int train2d
+#ifdef NXP_APPLY_MAX_CDD
+ , struct ddr_ctrl_reg_values *ddrctrl_regs
+#endif
+ );
/*
* Address data tuples to store the PHY 1D
diff --git a/drivers/nxp/flexspi/nor/fspi.c b/drivers/nxp/flexspi/nor/fspi.c
index 7c919b8..1e8c5a2 100644
--- a/drivers/nxp/flexspi/nor/fspi.c
+++ b/drivers/nxp/flexspi/nor/fspi.c
@@ -123,6 +123,9 @@
cmd_id1 = FSPI_NOR_CMD_RDSR;
cmd_id2 = FSPI_NOR_CMD_RDSR;
break;
+ default:
+ ERROR("Unsupported command\n");
+ return;
}
x_addr = FSPI_LUTREG_OFFSET + (uint32_t)(0x10 * fspi_op_seq_id);
diff --git a/drivers/nxp/tzc/plat_tzc380.c b/drivers/nxp/tzc/plat_tzc380.c
index 13cf3b9..5b27563 100644
--- a/drivers/nxp/tzc/plat_tzc380.c
+++ b/drivers/nxp/tzc/plat_tzc380.c
@@ -91,20 +91,37 @@
}
/* Continue with list entries for index > 0 */
if (dram_idx == 0) {
- /* TZC Region 1 on DRAM0 for Secure Memory*/
+ /*
+ * Region 1: Secure Region on DRAM 1 for 2MB out of 2MB,
+ * excluding 0 sub-region(=256KB).
+ */
tzc380_reg_list[list_idx].secure = TZC_ATTR_SP_S_RW;
tzc380_reg_list[list_idx].enabled = TZC_ATTR_REGION_ENABLE;
tzc380_reg_list[list_idx].addr = dram_start_addr + dram_size;
- tzc380_reg_list[list_idx].size = secure_dram_sz;
+ tzc380_reg_list[list_idx].size = TZC_REGION_SIZE_2M;
tzc380_reg_list[list_idx].sub_mask = 0x0; /* all enabled */
list_idx++;
- /* TZC Region 2 on DRAM0 for Shared Memory*/
+ /*
+ * Region 2: Secure Region on DRAM 1 for 54MB out of 64MB,
+ * excluding 1 sub-rgion(=8MB) of 8MB.
+ */
tzc380_reg_list[list_idx].secure = TZC_ATTR_SP_S_RW;
tzc380_reg_list[list_idx].enabled = TZC_ATTR_REGION_ENABLE;
+ tzc380_reg_list[list_idx].addr = dram_start_addr + dram_size + shrd_dram_sz;
+ tzc380_reg_list[list_idx].size = TZC_REGION_SIZE_64M;
+ tzc380_reg_list[list_idx].sub_mask = 0x80; /* Disable sub-region 7 */
+ list_idx++;
+
+ /*
+ * Region 3: Secure Region on DRAM 1 for 6MB out of 8MB,
+ * excluding 2 sub-rgion(=1MB) of 2MB.
+ */
+ tzc380_reg_list[list_idx].secure = TZC_ATTR_SP_S_RW;
+ tzc380_reg_list[list_idx].enabled = TZC_ATTR_REGION_ENABLE;
tzc380_reg_list[list_idx].addr = dram_start_addr + dram_size + secure_dram_sz;
- tzc380_reg_list[list_idx].size = shrd_dram_sz;
- tzc380_reg_list[list_idx].sub_mask = 0x0; /* all enabled */
+ tzc380_reg_list[list_idx].size = TZC_REGION_SIZE_8M;
+ tzc380_reg_list[list_idx].sub_mask = 0xC0; /* Disable sub-region 6 & 7 */
list_idx++;
}
diff --git a/drivers/renesas/common/emmc/emmc_cmd.c b/drivers/renesas/common/emmc/emmc_cmd.c
index d255bff..02fc26b 100644
--- a/drivers/renesas/common/emmc/emmc_cmd.c
+++ b/drivers/renesas/common/emmc/emmc_cmd.c
@@ -254,8 +254,7 @@
(SD_INFO2_ALL_ERR | SD_INFO2_CLEAR));
state = ESTATE_ISSUE_CMD;
- /* through */
-
+ /* fallthrough */
case ESTATE_ISSUE_CMD:
/* ARG */
SETR_32(SD_ARG, mmc_drv_obj.cmd_info.arg);
@@ -454,8 +453,8 @@
SETR_32(SD_STOP, 0x00000000U);
mmc_drv_obj.during_dma_transfer = FALSE;
}
- /* through */
+ /* fallthrough */
case ESTATE_ERROR:
if (err_not_care_flag == TRUE) {
mmc_drv_obj.during_cmd_processing = FALSE;
diff --git a/drivers/renesas/common/rom/rom_api.c b/drivers/renesas/common/rom/rom_api.c
index fda2815..4eede17 100644
--- a/drivers/renesas/common/rom/rom_api.c
+++ b/drivers/renesas/common/rom/rom_api.c
@@ -11,7 +11,7 @@
#include "rcar_def.h"
#include "rom_api.h"
-typedef uint32_t(*rom_secure_boot_api_f) (uint32_t *key, uint32_t *cert,
+typedef uint32_t(*rom_secure_boot_api_f) (uint32_t key, uint32_t cert,
rom_read_flash_f pFuncReadFlash);
typedef uint32_t(*rom_get_lcs_api_f) (uint32_t *lcs);
@@ -68,7 +68,7 @@
return index;
}
-uint32_t rcar_rom_secure_boot_api(uint32_t *key, uint32_t *cert,
+uint32_t rcar_rom_secure_boot_api(uint32_t key, uint32_t cert,
rom_read_flash_f read_flash)
{
static const uintptr_t rom_api_table[API_TABLE_MAX] = {
diff --git a/drivers/renesas/common/rom/rom_api.h b/drivers/renesas/common/rom/rom_api.h
index 1d5b03d..4b10080 100644
--- a/drivers/renesas/common/rom/rom_api.h
+++ b/drivers/renesas/common/rom/rom_api.h
@@ -24,7 +24,7 @@
#define LCS_FA (0x7U)
typedef uint32_t(*rom_read_flash_f) (uint64_t src, uint8_t *dst, uint32_t len);
-uint32_t rcar_rom_secure_boot_api(uint32_t *key, uint32_t *cert,
+uint32_t rcar_rom_secure_boot_api(uint32_t key, uint32_t cert,
rom_read_flash_f f);
uint32_t rcar_rom_get_lcs(uint32_t *lcs);
diff --git a/drivers/st/clk/clk-stm32-core.c b/drivers/st/clk/clk-stm32-core.c
index bb03125..9fe8c8c 100644
--- a/drivers/st/clk/clk-stm32-core.c
+++ b/drivers/st/clk/clk-stm32-core.c
@@ -466,10 +466,9 @@
{
const struct clk_stm32 *clk = _clk_get(priv, id);
int parent;
- unsigned long rate = 0UL;
if ((unsigned int)id >= priv->num) {
- return rate;
+ return 0UL;
}
parent = _clk_stm32_get_parent(priv, id);
@@ -484,21 +483,14 @@
prate = _clk_stm32_get_rate(priv, parent);
}
- rate = clk->ops->recalc_rate(priv, id, prate);
-
- return rate;
+ return clk->ops->recalc_rate(priv, id, prate);
}
- switch (parent) {
- case CLK_IS_ROOT:
+ if (parent == CLK_IS_ROOT) {
panic();
-
- default:
- rate = _clk_stm32_get_rate(priv, parent);
- break;
}
- return rate;
+ return _clk_stm32_get_rate(priv, parent);
}
unsigned long _clk_stm32_get_parent_rate(struct stm32_clk_priv *priv, int id)
@@ -519,7 +511,7 @@
bool _stm32_clk_is_flags(struct stm32_clk_priv *priv, int id, uint8_t flag)
{
- if (_stm32_clk_get_flags(priv, id) & flag) {
+ if ((_stm32_clk_get_flags(priv, id) & flag) != 0U) {
return true;
}
@@ -549,7 +541,7 @@
}
if (parent != CLK_IS_ROOT) {
ret = _clk_stm32_enable_core(priv, parent);
- if (ret) {
+ if (ret != 0) {
return ret;
}
}
diff --git a/drivers/st/clk/clk-stm32mp13.c b/drivers/st/clk/clk-stm32mp13.c
index c960928..db427ad 100644
--- a/drivers/st/clk/clk-stm32mp13.c
+++ b/drivers/st/clk/clk-stm32mp13.c
@@ -456,7 +456,7 @@
},\
}
-static const struct parent_cfg parent_mp13[] = {
+static const struct parent_cfg parent_mp13[MUX_MAX] = {
MUX_CFG(MUX_ADC1, ADC1_src, RCC_ADC12CKSELR, 0, 2),
MUX_CFG(MUX_ADC2, ADC2_src, RCC_ADC12CKSELR, 2, 2),
MUX_RDY_CFG(MUX_AXI, AXI_src, RCC_ASSCKSELR, 0, 3),
@@ -841,7 +841,7 @@
.bitrdy = _bitrdy,\
}
-static const struct div_cfg dividers_mp13[] = {
+static const struct div_cfg dividers_mp13[DIV_MAX] = {
DIV_CFG(DIV_PLL1DIVP, RCC_PLL1CFGR2, 0, 7, 0, NULL, DIV_NO_BIT_RDY),
DIV_CFG(DIV_PLL2DIVP, RCC_PLL2CFGR2, 0, 7, 0, NULL, DIV_NO_BIT_RDY),
DIV_CFG(DIV_PLL2DIVQ, RCC_PLL2CFGR2, 8, 7, 0, NULL, DIV_NO_BIT_RDY),
@@ -1119,7 +1119,7 @@
return ret;
}
- if (enable) {
+ if (enable != 0) {
clk_stm32_enable_call_ops(priv, clk_id);
} else {
clk_stm32_disable_call_ops(priv, clk_id);
@@ -1450,7 +1450,7 @@
/* Configure PLLs source */
ret = stm32_clk_configure_mux(priv, pll_conf->vco.src);
- if (ret) {
+ if (ret != 0) {
return ret;
}
@@ -1485,7 +1485,7 @@
{
struct stm32_pll_dt_cfg *pll_conf = clk_stm32_pll_get_pdata(pll_idx);
- if (pll_conf->vco.status) {
+ if (pll_conf->vco.status != 0U) {
return _clk_stm32_pll_init(priv, pll_idx, pll_conf);
}
@@ -1497,22 +1497,22 @@
int err = 0;
err = clk_stm32_pll_init(priv, _PLL1);
- if (err) {
+ if (err != 0) {
return err;
}
err = clk_stm32_pll_init(priv, _PLL2);
- if (err) {
+ if (err != 0) {
return err;
}
err = clk_stm32_pll_init(priv, _PLL3);
- if (err) {
+ if (err != 0) {
return err;
}
err = clk_stm32_pll_init(priv, _PLL4);
- if (err) {
+ if (err != 0) {
return err;
}
@@ -2242,7 +2242,7 @@
size_t i = 0U;
for (i = _PLL1; i < pdata->npll; i++) {
- struct stm32_pll_dt_cfg *pll = pdata->pll + i;
+ struct stm32_pll_dt_cfg *pll = &pdata->pll[i];
char name[RCC_PLL_NAME_SIZE];
int subnode = 0;
int err = 0;
diff --git a/drivers/st/crypto/stm32_pka.c b/drivers/st/crypto/stm32_pka.c
index e03cf0f..2bbb31d 100644
--- a/drivers/st/crypto/stm32_pka.c
+++ b/drivers/st/crypto/stm32_pka.c
@@ -254,13 +254,6 @@
static struct stm32_pka_platdata pka_pdata;
-#pragma weak stm32_pka_get_platdata
-
-int stm32_pka_get_platdata(struct stm32_pka_platdata *pdata)
-{
- return -ENODEV;
-}
-
static int stm32_pka_parse_fdt(void)
{
int node;
@@ -583,10 +576,7 @@
err = stm32_pka_parse_fdt();
if (err != 0) {
- err = stm32_pka_get_platdata(&pka_pdata);
- if (err != 0) {
- return err;
- }
+ return err;
}
clk_enable(pka_pdata.clock_id);
diff --git a/drivers/st/crypto/stm32_saes.c b/drivers/st/crypto/stm32_saes.c
index 02baf21..f4da571 100644
--- a/drivers/st/crypto/stm32_saes.c
+++ b/drivers/st/crypto/stm32_saes.c
@@ -139,15 +139,8 @@
#define SET_CHAINING_MODE(mod, cr) \
mmio_clrsetbits_32((cr), _SAES_CR_CHMOD_MASK, _SAES_CR_CHMOD_##mod << _SAES_CR_CHMOD_SHIFT)
-#define pragma weak stm32_saes_get_platdata
-
static struct stm32_saes_platdata saes_pdata;
-int stm32_saes_get_platdata(struct stm32_saes_platdata *pdata)
-{
- return -ENODEV;
-}
-
static int stm32_saes_parse_fdt(struct stm32_saes_platdata *pdata)
{
int node;
@@ -389,10 +382,7 @@
err = stm32_saes_parse_fdt(&saes_pdata);
if (err != 0) {
- err = stm32_saes_get_platdata(&saes_pdata);
- if (err != 0) {
- return err;
- }
+ return err;
}
clk_enable(saes_pdata.clock_id);
diff --git a/drivers/st/gpio/stm32_gpio.c b/drivers/st/gpio/stm32_gpio.c
index 708989f..a4a64ca 100644
--- a/drivers/st/gpio/stm32_gpio.c
+++ b/drivers/st/gpio/stm32_gpio.c
@@ -234,27 +234,27 @@
clk_enable(clock);
mmio_clrsetbits_32(base + GPIO_MODE_OFFSET,
- (uint32_t)GPIO_MODE_MASK << (pin << 1),
- mode << (pin << 1));
+ (uint32_t)GPIO_MODE_MASK << (pin << 1U),
+ mode << (pin << 1U));
mmio_clrsetbits_32(base + GPIO_TYPE_OFFSET,
(uint32_t)GPIO_TYPE_MASK << pin,
type << pin);
mmio_clrsetbits_32(base + GPIO_SPEED_OFFSET,
- (uint32_t)GPIO_SPEED_MASK << (pin << 1),
- speed << (pin << 1));
+ (uint32_t)GPIO_SPEED_MASK << (pin << 1U),
+ speed << (pin << 1U));
mmio_clrsetbits_32(base + GPIO_PUPD_OFFSET,
- (uint32_t)GPIO_PULL_MASK << (pin << 1),
- pull << (pin << 1));
+ (uint32_t)GPIO_PULL_MASK << (pin << 1U),
+ pull << (pin << 1U));
if (pin < GPIO_ALT_LOWER_LIMIT) {
mmio_clrsetbits_32(base + GPIO_AFRL_OFFSET,
- (uint32_t)GPIO_ALTERNATE_MASK << (pin << 2),
- alternate << (pin << 2));
+ (uint32_t)GPIO_ALTERNATE_MASK << (pin << 2U),
+ alternate << (pin << 2U));
} else {
- size_t shift = (pin - GPIO_ALT_LOWER_LIMIT) << 2;
+ uint32_t shift = (pin - GPIO_ALT_LOWER_LIMIT) << 2U;
mmio_clrsetbits_32(base + GPIO_AFRH_OFFSET,
(uint32_t)GPIO_ALTERNATE_MASK << shift,
diff --git a/drivers/st/io/io_mmc.c b/drivers/st/io/io_mmc.c
deleted file mode 100644
index 2bf88e6..0000000
--- a/drivers/st/io/io_mmc.c
+++ /dev/null
@@ -1,143 +0,0 @@
-/*
- * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <assert.h>
-#include <errno.h>
-#include <string.h>
-
-#include <common/debug.h>
-#include <drivers/io/io_driver.h>
-#include <drivers/io/io_storage.h>
-#include <drivers/mmc.h>
-#include <drivers/st/io_mmc.h>
-#include <drivers/st/stm32_sdmmc2.h>
-
-/* SDMMC device functions */
-static int mmc_dev_open(const uintptr_t init_params, io_dev_info_t **dev_info);
-static int mmc_block_open(io_dev_info_t *dev_info, const uintptr_t spec,
- io_entity_t *entity);
-static int mmc_dev_init(io_dev_info_t *dev_info, const uintptr_t init_params);
-static int mmc_block_seek(io_entity_t *entity, int mode,
- signed long long offset);
-static int mmc_block_read(io_entity_t *entity, uintptr_t buffer, size_t length,
- size_t *length_read);
-static int mmc_block_close(io_entity_t *entity);
-static int mmc_dev_close(io_dev_info_t *dev_info);
-static io_type_t device_type_mmc(void);
-
-static signed long long seek_offset;
-static size_t (*_read_blocks)(int lba, uintptr_t buf, size_t size);
-
-static const io_dev_connector_t mmc_dev_connector = {
- .dev_open = mmc_dev_open
-};
-
-static const io_dev_funcs_t mmc_dev_funcs = {
- .type = device_type_mmc,
- .open = mmc_block_open,
- .seek = mmc_block_seek,
- .size = NULL,
- .read = mmc_block_read,
- .write = NULL,
- .close = mmc_block_close,
- .dev_init = mmc_dev_init,
- .dev_close = mmc_dev_close,
-};
-
-static const io_dev_info_t mmc_dev_info = {
- .funcs = &mmc_dev_funcs,
- .info = 0,
-};
-
-/* Identify the device type as mmc device */
-static io_type_t device_type_mmc(void)
-{
- return IO_TYPE_MMC;
-}
-
-/* Open a connection to the mmc device */
-static int mmc_dev_open(const uintptr_t init_params, io_dev_info_t **dev_info)
-{
- struct io_mmc_dev_spec *device_spec =
- (struct io_mmc_dev_spec *)init_params;
-
- assert(dev_info != NULL);
- *dev_info = (io_dev_info_t *)&mmc_dev_info;
-
- _read_blocks = !device_spec->use_boot_part ?
- mmc_read_blocks : mmc_boot_part_read_blocks;
-
- return 0;
-}
-
-static int mmc_dev_init(io_dev_info_t *dev_info, const uintptr_t init_params)
-{
- return 0;
-}
-
-/* Close a connection to the mmc device */
-static int mmc_dev_close(io_dev_info_t *dev_info)
-{
- return 0;
-}
-
-/* Open a file on the mmc device */
-static int mmc_block_open(io_dev_info_t *dev_info, const uintptr_t spec,
- io_entity_t *entity)
-{
- seek_offset = 0;
- return 0;
-}
-
-/* Seek to a particular file offset on the mmc device */
-static int mmc_block_seek(io_entity_t *entity, int mode,
- signed long long offset)
-{
- seek_offset = offset;
- return 0;
-}
-
-/* Read data from a file on the mmc device */
-static int mmc_block_read(io_entity_t *entity, uintptr_t buffer,
- size_t length, size_t *length_read)
-{
- uint8_t retries;
-
- for (retries = 0U; retries < 3U; retries++) {
- *length_read = _read_blocks(seek_offset / MMC_BLOCK_SIZE,
- buffer, length);
-
- if (*length_read == length) {
- return 0;
- }
- WARN("%s: length_read = %lu (!= %lu), retry %u\n", __func__,
- (unsigned long)*length_read, (unsigned long)length,
- retries + 1U);
- }
-
- return -EIO;
-}
-
-/* Close a file on the mmc device */
-static int mmc_block_close(io_entity_t *entity)
-{
- return 0;
-}
-
-/* Register the mmc driver with the IO abstraction */
-int register_io_dev_mmc(const io_dev_connector_t **dev_con)
-{
- int result;
-
- assert(dev_con != NULL);
-
- result = io_register_device(&mmc_dev_info);
- if (result == 0) {
- *dev_con = &mmc_dev_connector;
- }
-
- return result;
-}
diff --git a/drivers/st/mmc/stm32_sdmmc2.c b/drivers/st/mmc/stm32_sdmmc2.c
index 6bdd782..1ee3580 100644
--- a/drivers/st/mmc/stm32_sdmmc2.c
+++ b/drivers/st/mmc/stm32_sdmmc2.c
@@ -528,12 +528,12 @@
uint32_t data_ctrl = SDMMC_DCTRLR_DTDIR;
uint32_t arg_size;
- assert(size != 0U);
+ assert((size != 0U) && (size <= UINT32_MAX));
if (size > MMC_BLOCK_SIZE) {
arg_size = MMC_BLOCK_SIZE;
} else {
- arg_size = size;
+ arg_size = (uint32_t)size;
}
sdmmc2_params.use_dma = plat_sdmmc2_use_dma(base, buf);
diff --git a/drivers/st/pmic/stm32mp_pmic.c b/drivers/st/pmic/stm32mp_pmic.c
index 5b43760..1e16287 100644
--- a/drivers/st/pmic/stm32mp_pmic.c
+++ b/drivers/st/pmic/stm32mp_pmic.c
@@ -20,6 +20,7 @@
#include <platform_def.h>
#define PMIC_NODE_NOT_FOUND 1
+#define NB_REG 14U
static struct i2c_handle_s i2c_handle;
static uint32_t pmic_i2c_addr;
@@ -454,13 +455,13 @@
};
#define DEFINE_REGU(name) { \
- .node_name = name, \
+ .node_name = (name), \
.ops = &pmic_ops, \
.driver_data = NULL, \
.enable_ramp_delay = 1000, \
}
-static const struct regul_description pmic_regs[] = {
+static const struct regul_description pmic_regs[NB_REG] = {
[STPMIC1_BUCK1] = DEFINE_REGU("buck1"),
[STPMIC1_BUCK2] = DEFINE_REGU("buck2"),
[STPMIC1_BUCK3] = DEFINE_REGU("buck3"),
@@ -477,8 +478,6 @@
[STPMIC1_SW_OUT] = DEFINE_REGU("pwr_sw2"),
};
-#define NB_REG ARRAY_SIZE(pmic_regs)
-
static int register_pmic(void)
{
void *fdt;
@@ -506,7 +505,7 @@
unsigned int i;
int ret;
- for (i = 0; i < NB_REG; i++) {
+ for (i = 0U; i < NB_REG; i++) {
desc = &pmic_regs[i];
if (strcmp(desc->node_name, reg_name) == 0) {
break;
diff --git a/drivers/st/regulator/regulator_core.c b/drivers/st/regulator/regulator_core.c
index 5cc8329..2a5d0f7 100644
--- a/drivers/st/regulator/regulator_core.c
+++ b/drivers/st/regulator/regulator_core.c
@@ -17,14 +17,16 @@
#define MAX_PROPERTY_LEN 64
+CASSERT(PLAT_NB_RDEVS >= 1U, plat_nb_rdevs_must_be_higher);
+
static struct rdev rdev_array[PLAT_NB_RDEVS];
#define for_each_rdev(rdev) \
- for (rdev = rdev_array; rdev < (rdev_array + PLAT_NB_RDEVS); rdev++)
+ for ((rdev) = rdev_array; (rdev) <= &rdev_array[PLAT_NB_RDEVS - 1U]; (rdev)++)
#define for_each_registered_rdev(rdev) \
- for (rdev = rdev_array; \
- (rdev < (rdev_array + PLAT_NB_RDEVS)) && (rdev->desc != NULL); rdev++)
+ for ((rdev) = rdev_array; \
+ ((rdev) <= &rdev_array[PLAT_NB_RDEVS - 1U]) && ((rdev)->desc != NULL); (rdev)++)
static void lock_driver(const struct rdev *rdev)
{
@@ -86,7 +88,7 @@
char prop_name[MAX_PROPERTY_LEN];
len = snprintf(prop_name, MAX_PROPERTY_LEN - 1, "%s-supply", name);
- assert((len >= 0) && (len < MAX_PROPERTY_LEN - 1));
+ assert((len >= 0) && (len < (MAX_PROPERTY_LEN - 1)));
cuint = fdt_getprop(fdt, node, prop_name, NULL);
if (cuint != NULL) {
@@ -156,7 +158,7 @@
assert(rdev != NULL);
- if (rdev->flags & REGUL_ALWAYS_ON) {
+ if ((rdev->flags & REGUL_ALWAYS_ON) != 0U) {
return 0;
}
@@ -525,7 +527,7 @@
}
}
- if (rdev == rdev_array + PLAT_NB_RDEVS) {
+ if (rdev > &rdev_array[PLAT_NB_RDEVS - 1U]) {
WARN("Not enough place for regulators, PLAT_NB_RDEVS should be increased.\n");
return -ENOMEM;
}
diff --git a/drivers/st/usb/stm32mp1_usb.c b/drivers/st/usb/stm32mp1_usb.c
index 9a49690..78890f5 100644
--- a/drivers/st/usb/stm32mp1_usb.c
+++ b/drivers/st/usb/stm32mp1_usb.c
@@ -4,6 +4,7 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
+#include <assert.h>
#include <stdint.h>
#include <arch_helpers.h>
@@ -794,7 +795,7 @@
uint32_t epint;
uint32_t epnum;
uint32_t temp;
- enum usb_status ret;
+ enum usb_status __unused ret;
if (usb_dwc2_get_mode(handle) != USB_OTG_MODE_DEVICE) {
return USB_NOTHING;
@@ -947,9 +948,7 @@
/* Setup EP0 to receive SETUP packets */
ret = usb_dwc2_ep0_out_start(handle);
- if (ret != USBD_OK) {
- return ret;
- }
+ assert(ret == USBD_OK);
mmio_write_32(usb_base_addr + OTG_GINTSTS, OTG_GINTSTS_USBRST);
@@ -959,9 +958,7 @@
/* Handle enumeration done interrupt */
if ((usb_dwc2_read_int(handle) & OTG_GINTSTS_ENUMDNE) != 0U) {
ret = usb_dwc2_activate_setup(handle);
- if (ret != USBD_OK) {
- return ret;
- }
+ assert(ret == USBD_OK);
mmio_clrbits_32(usb_base_addr + OTG_GUSBCFG, OTG_GUSBCFG_TRDT);
diff --git a/fdts/fvp-base-psci-common.dtsi b/fdts/fvp-base-psci-common.dtsi
index 6018f0c..7838fde 100644
--- a/fdts/fvp-base-psci-common.dtsi
+++ b/fdts/fvp-base-psci-common.dtsi
@@ -28,7 +28,7 @@
#size-cells = <2>;
#if (ENABLE_RME == 1)
- chosen { bootargs = "mem=1G console=ttyAMA0 earlycon=pl011,0x1c090000 root=/dev/vda ip=on";};
+ chosen { bootargs = "console=ttyAMA0 earlycon=pl011,0x1c090000 root=/dev/vda ip=on";};
#else
chosen {};
#endif
diff --git a/fdts/stm32mp151.dtsi b/fdts/stm32mp151.dtsi
index a938edc..869b912 100644
--- a/fdts/stm32mp151.dtsi
+++ b/fdts/stm32mp151.dtsi
@@ -127,8 +127,8 @@
compatible = "st,stm32mp15-i2c";
reg = <0x40013000 0x400>;
interrupt-names = "event", "error";
- interrupts = <&exti 22 IRQ_TYPE_LEVEL_HIGH>,
- <&intc GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&exti 22 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc I2C2_K>;
resets = <&rcc I2C2_R>;
#address-cells = <1>;
diff --git a/fdts/stm32mp157c-ed1.dts b/fdts/stm32mp157c-ed1.dts
index d928563..63753bd 100644
--- a/fdts/stm32mp157c-ed1.dts
+++ b/fdts/stm32mp157c-ed1.dts
@@ -169,23 +169,12 @@
vbus_otg: pwr_sw1 {
regulator-name = "vbus_otg";
- };
+ };
- vbus_sw: pwr_sw2 {
+ vbus_sw: pwr_sw2 {
regulator-name = "vbus_sw";
regulator-active-discharge = <1>;
- };
- };
-
- onkey {
- compatible = "st,stpmic1-onkey";
- power-off-time-sec = <10>;
- status = "okay";
- };
-
- watchdog {
- compatible = "st,stpmic1-wdt";
- status = "disabled";
+ };
};
};
};
diff --git a/fdts/tc.dts b/fdts/tc.dts
index 5a8792e..192f407 100644
--- a/fdts/tc.dts
+++ b/fdts/tc.dts
@@ -213,9 +213,9 @@
linux,cma-default;
};
- optee@0xfce00000 {
- reg = <0x00000000 0xfce00000 0 0x00200000>;
- no-map;
+ optee@0xf8e00000 {
+ compatible = "restricted-dma-pool";
+ reg = <0x00000000 0xf8e00000 0 0x00200000>;
};
};
@@ -463,17 +463,18 @@
interrupt-names = "JOB", "MMU", "GPU";
clocks = <&soc_refclk100mhz>;
clock-names = "clk_mali";
+ iommus = <&smmu_700 0x200>;
operating-points = <
/* KHz uV */
50000 820000
>;
};
- smmu: smmu@2ce00000 {
+ smmu_700: smmu_700@3f000000 {
#iommu-cells = <1>;
compatible = "arm,smmu-v3";
- reg = <0x0 0x2ce00000 0x0 0x20000>;
- status = "okay";
+ reg = <0x0 0x3f000000 0x0 0x5000000>;
+ dma-coherent;
};
dp0: display@2cc00000 {
@@ -485,9 +486,7 @@
interrupt-names = "DPU";
clocks = <&scmi_clk 0>;
clock-names = "aclk";
- iommus = <&smmu 0>, <&smmu 1>, <&smmu 2>, <&smmu 3>,
- <&smmu 4>, <&smmu 5>, <&smmu 6>, <&smmu 7>,
- <&smmu 8>, <&smmu 9>;
+ iommus = <&smmu_700 0x100>;
pl0: pipeline@0 {
reg = <0>;
clocks = <&scmi_clk 1>;
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h
index f63e923..9e13c3d 100644
--- a/include/arch/aarch64/arch.h
+++ b/include/arch/aarch64/arch.h
@@ -1282,6 +1282,12 @@
#define GCR_EL1 S3_0_C1_C0_6
/*******************************************************************************
+ * Armv8.5 - Random Number Generator Registers
+ ******************************************************************************/
+#define RNDR S3_3_C2_C4_0
+#define RNDRRS S3_3_C2_C4_1
+
+/*******************************************************************************
* FEAT_HCX - Extended Hypervisor Configuration Register
******************************************************************************/
#define HCRX_EL2 S3_4_C1_C2_2
diff --git a/include/arch/aarch64/arch_features.h b/include/arch/aarch64/arch_features.h
index 932e885..2b801ac 100644
--- a/include/arch/aarch64/arch_features.h
+++ b/include/arch/aarch64/arch_features.h
@@ -10,6 +10,7 @@
#include <stdbool.h>
#include <arch_helpers.h>
+#include <common/feat_detect.h>
static inline bool is_armv7_gentimer_present(void)
{
@@ -97,12 +98,25 @@
ID_AA64MMFR1_EL1_TWED_MASK) == ID_AA64MMFR1_EL1_TWED_SUPPORTED);
}
-static inline bool is_armv8_6_fgt_present(void)
+static unsigned int read_feat_fgt_id_field(void)
{
- return ((read_id_aa64mmfr0_el1() >> ID_AA64MMFR0_EL1_FGT_SHIFT) &
- ID_AA64MMFR0_EL1_FGT_MASK) != 0U;
+ return (read_id_aa64mmfr0_el1() >> ID_AA64MMFR0_EL1_FGT_SHIFT) &
+ ID_AA64MMFR0_EL1_FGT_MASK;
}
+static inline bool is_feat_fgt_supported(void)
+{
+ if (ENABLE_FEAT_FGT == FEAT_STATE_DISABLED) {
+ return false;
+ }
+
+ if (ENABLE_FEAT_FGT == FEAT_STATE_ALWAYS) {
+ return true;
+ }
+
+ return read_feat_fgt_id_field() != 0U;
+}
+
static inline unsigned long int get_armv8_6_ecv_support(void)
{
return ((read_id_aa64mmfr0_el1() >> ID_AA64MMFR0_EL1_ECV_SHIFT) &
@@ -115,10 +129,31 @@
ID_AA64ISAR0_RNDR_MASK);
}
+/*******************************************************************************
+ * Functions to identify the presence of the Activity Monitors Extension
+ ******************************************************************************/
+static unsigned int read_feat_amu_id_field(void)
+{
+ return (read_id_aa64pfr0_el1() >> ID_AA64PFR0_AMU_SHIFT) &
+ ID_AA64PFR0_AMU_MASK;
+}
+
+static inline bool is_feat_amu_supported(void)
+{
+ if (ENABLE_FEAT_AMUv1 == FEAT_STATE_DISABLED) {
+ return false;
+ }
+
+ if (ENABLE_FEAT_AMUv1 == FEAT_STATE_ALWAYS) {
+ return true;
+ }
+
+ return read_feat_amu_id_field() >= ID_AA64PFR0_AMU_V1;
+}
+
static inline bool is_armv8_6_feat_amuv1p1_present(void)
{
- return (((read_id_aa64pfr0_el1() >> ID_AA64PFR0_AMU_SHIFT) &
- ID_AA64PFR0_AMU_MASK) >= ID_AA64PFR0_AMU_V1P1);
+ return read_feat_amu_id_field() >= ID_AA64PFR0_AMU_V1P1;
}
/*
@@ -138,10 +173,23 @@
ID_AA64PFR1_MPAM_FRAC_SHIFT) & ID_AA64PFR1_MPAM_FRAC_MASK));
}
+static inline unsigned int read_feat_hcx_id_field(void)
+{
+ return (read_id_aa64mmfr1_el1() >> ID_AA64MMFR1_EL1_HCX_SHIFT) &
+ ID_AA64MMFR1_EL1_HCX_MASK;
+}
+
-static inline bool is_feat_hcx_present(void)
+static inline bool is_feat_hcx_supported(void)
{
- return (((read_id_aa64mmfr1_el1() >> ID_AA64MMFR1_EL1_HCX_SHIFT) &
- ID_AA64MMFR1_EL1_HCX_MASK) == ID_AA64MMFR1_EL1_HCX_SUPPORTED);
+ if (ENABLE_FEAT_HCX == FEAT_STATE_DISABLED) {
+ return false;
+ }
+
+ if (ENABLE_FEAT_HCX == FEAT_STATE_ALWAYS) {
+ return true;
+ }
+
+ return read_feat_hcx_id_field() != 0U;
}
static inline bool is_feat_rng_trap_present(void)
@@ -226,16 +274,6 @@
ID_AA64DFR0_TRACEFILT_MASK) == ID_AA64DFR0_TRACEFILT_SUPPORTED);
}
-/*******************************************************************************
- * Function to identify the presence of FEAT_AMUv1 (Activity Monitors-
- * Extension v1)
- ******************************************************************************/
-static inline bool is_armv8_4_feat_amuv1_present(void)
-{
- return (((read_id_aa64pfr0_el1() >> ID_AA64PFR0_AMU_SHIFT) &
- ID_AA64PFR0_AMU_MASK) >= ID_AA64PFR0_AMU_V1);
-}
-
/********************************************************************************
* Function to identify the presence of FEAT_NV2 (Enhanced Nested Virtualization
* Support)
diff --git a/include/arch/aarch64/arch_helpers.h b/include/arch/aarch64/arch_helpers.h
index 50a5ad4..86c1dbe 100644
--- a/include/arch/aarch64/arch_helpers.h
+++ b/include/arch/aarch64/arch_helpers.h
@@ -27,6 +27,14 @@
return v; \
}
+#define _DEFINE_SYSREG_READ_FUNC_NV(_name, _reg_name) \
+static inline u_register_t read_ ## _name(void) \
+{ \
+ u_register_t v; \
+ __asm__ ("mrs %0, " #_reg_name : "=r" (v)); \
+ return v; \
+}
+
#define _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) \
static inline void write_ ## _name(u_register_t v) \
{ \
@@ -58,6 +66,14 @@
#define DEFINE_RENAME_SYSREG_WRITE_FUNC(_name, _reg_name) \
_DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name)
+/* Define read function for ID register (w/o volatile qualifier) */
+#define DEFINE_IDREG_READ_FUNC(_name) \
+ _DEFINE_SYSREG_READ_FUNC_NV(_name, _name)
+
+/* Define read function for renamed ID register (w/o volatile qualifier) */
+#define DEFINE_RENAME_IDREG_READ_FUNC(_name, _reg_name) \
+ _DEFINE_SYSREG_READ_FUNC_NV(_name, _reg_name)
+
/**********************************************************************
* Macros to create inline functions for system instructions
*********************************************************************/
@@ -247,14 +263,14 @@
#define write_daifset(val) SYSREG_WRITE_CONST(daifset, val)
DEFINE_SYSREG_RW_FUNCS(par_el1)
-DEFINE_SYSREG_READ_FUNC(id_pfr1_el1)
-DEFINE_SYSREG_READ_FUNC(id_aa64isar0_el1)
-DEFINE_SYSREG_READ_FUNC(id_aa64isar1_el1)
-DEFINE_RENAME_SYSREG_READ_FUNC(id_aa64isar2_el1, ID_AA64ISAR2_EL1)
-DEFINE_SYSREG_READ_FUNC(id_aa64pfr0_el1)
-DEFINE_SYSREG_READ_FUNC(id_aa64pfr1_el1)
-DEFINE_SYSREG_READ_FUNC(id_aa64dfr0_el1)
-DEFINE_SYSREG_READ_FUNC(id_afr0_el1)
+DEFINE_IDREG_READ_FUNC(id_pfr1_el1)
+DEFINE_IDREG_READ_FUNC(id_aa64isar0_el1)
+DEFINE_IDREG_READ_FUNC(id_aa64isar1_el1)
+DEFINE_RENAME_IDREG_READ_FUNC(id_aa64isar2_el1, ID_AA64ISAR2_EL1)
+DEFINE_IDREG_READ_FUNC(id_aa64pfr0_el1)
+DEFINE_IDREG_READ_FUNC(id_aa64pfr1_el1)
+DEFINE_IDREG_READ_FUNC(id_aa64dfr0_el1)
+DEFINE_IDREG_READ_FUNC(id_afr0_el1)
DEFINE_SYSREG_READ_FUNC(CurrentEl)
DEFINE_SYSREG_READ_FUNC(ctr_el0)
DEFINE_SYSREG_RW_FUNCS(daif)
@@ -367,10 +383,10 @@
/*******************************************************************************
* System register accessor prototypes
******************************************************************************/
-DEFINE_SYSREG_READ_FUNC(midr_el1)
+DEFINE_IDREG_READ_FUNC(midr_el1)
DEFINE_SYSREG_READ_FUNC(mpidr_el1)
-DEFINE_SYSREG_READ_FUNC(id_aa64mmfr0_el1)
-DEFINE_SYSREG_READ_FUNC(id_aa64mmfr1_el1)
+DEFINE_IDREG_READ_FUNC(id_aa64mmfr0_el1)
+DEFINE_IDREG_READ_FUNC(id_aa64mmfr1_el1)
DEFINE_SYSREG_RW_FUNCS(scr_el3)
DEFINE_SYSREG_RW_FUNCS(hcr_el2)
@@ -516,7 +532,7 @@
DEFINE_RENAME_SYSREG_WRITE_FUNC(zcr_el3, ZCR_EL3)
DEFINE_RENAME_SYSREG_WRITE_FUNC(zcr_el2, ZCR_EL2)
-DEFINE_RENAME_SYSREG_READ_FUNC(id_aa64smfr0_el1, ID_AA64SMFR0_EL1)
+DEFINE_RENAME_IDREG_READ_FUNC(id_aa64smfr0_el1, ID_AA64SMFR0_EL1)
DEFINE_RENAME_SYSREG_RW_FUNCS(smcr_el3, SMCR_EL3)
DEFINE_RENAME_SYSREG_READ_FUNC(erridr_el1, ERRIDR_EL1)
@@ -530,7 +546,7 @@
DEFINE_RENAME_SYSREG_READ_FUNC(erxmisc1_el1, ERXMISC1_EL1)
/* Armv8.2 Registers */
-DEFINE_RENAME_SYSREG_READ_FUNC(id_aa64mmfr2_el1, ID_AA64MMFR2_EL1)
+DEFINE_RENAME_IDREG_READ_FUNC(id_aa64mmfr2_el1, ID_AA64MMFR2_EL1)
/* Armv8.3 Pointer Authentication Registers */
DEFINE_RENAME_SYSREG_RW_FUNCS(apiakeyhi_el1, APIAKeyHi_EL1)
@@ -546,8 +562,16 @@
DEFINE_RENAME_SYSREG_RW_FUNCS(gcr_el1, GCR_EL1)
/* Armv8.5 FEAT_RNG Registers */
-DEFINE_SYSREG_READ_FUNC(rndr)
-DEFINE_SYSREG_READ_FUNC(rndrrs)
+DEFINE_RENAME_SYSREG_READ_FUNC(rndr, RNDR)
+DEFINE_RENAME_SYSREG_READ_FUNC(rndrrs, RNDRRS)
+
+/* Armv8.6 FEAT_FGT Registers */
+DEFINE_RENAME_SYSREG_RW_FUNCS(hdfgrtr_el2, HDFGRTR_EL2)
+DEFINE_RENAME_SYSREG_RW_FUNCS(hafgrtr_el2, HAFGRTR_EL2)
+DEFINE_RENAME_SYSREG_RW_FUNCS(hdfgwtr_el2, HDFGWTR_EL2)
+DEFINE_RENAME_SYSREG_RW_FUNCS(hfgitr_el2, HFGITR_EL2)
+DEFINE_RENAME_SYSREG_RW_FUNCS(hfgrtr_el2, HFGRTR_EL2)
+DEFINE_RENAME_SYSREG_RW_FUNCS(hfgwtr_el2, HFGWTR_EL2)
/* FEAT_HCX Register */
DEFINE_RENAME_SYSREG_RW_FUNCS(hcrx_el2, HCRX_EL2)
diff --git a/include/bl31/sync_handle.h b/include/bl31/sync_handle.h
new file mode 100644
index 0000000..e211575
--- /dev/null
+++ b/include/bl31/sync_handle.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2022, ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef TRAP_HANDLE_H
+#define TRAP_HANDLE_H
+
+#include <stdbool.h>
+#include <context.h>
+
+#define ISS_SYSREG_OPCODE_MASK 0x3ffc1eUL
+#define ISS_SYSREG_REG_MASK 0x0003e0UL
+#define ISS_SYSREG_REG_SHIFT 5U
+#define ISS_SYSREG_DIRECTION_MASK 0x000001UL
+
+#define ISS_SYSREG_OPCODE_RNDR 0x30c808U
+#define ISS_SYSREG_OPCODE_RNDRRS 0x32c808U
+
+#define TRAP_RET_UNHANDLED -1
+#define TRAP_RET_REPEAT 0
+#define TRAP_RET_CONTINUE 1
+
+#ifndef __ASSEMBLER__
+static inline unsigned int get_sysreg_iss_rt(uint64_t esr)
+{
+ return (esr & ISS_SYSREG_REG_MASK) >> ISS_SYSREG_REG_SHIFT;
+}
+
+static inline bool is_sysreg_iss_write(uint64_t esr)
+{
+ return !(esr & ISS_SYSREG_DIRECTION_MASK);
+}
+
+/**
+ * handle_sysreg_trap() - Handle AArch64 system register traps from lower ELs
+ * @esr_el3: The content of ESR_EL3, containing the trap syndrome information
+ * @ctx: Pointer to the lower EL context, containing saved registers
+ *
+ * Called by the exception handler when a synchronous trap identifies as a
+ * system register trap (EC=0x18). ESR contains the encoding of the op[x] and
+ * CRm/CRn fields, to identify the system register, and the target/source
+ * GPR plus the direction (MRS/MSR). The lower EL's context can be altered
+ * by the function, to inject back the result of the emulation.
+ *
+ * Return: indication how to proceed with the trap:
+ * TRAP_RET_UNHANDLED(-1): trap is unhandled, trigger panic
+ * TRAP_RET_REPEAT(0): trap was handled, return to the trapping instruction
+ * (repeating it)
+ * TRAP_RET_CONTINUE(1): trap was handled, return to the next instruction
+ * (continuing after it)
+ */
+int handle_sysreg_trap(uint64_t esr_el3, cpu_context_t *ctx);
+
+/* Prototypes for system register emulation handlers provided by platforms. */
+int plat_handle_rng_trap(uint64_t esr_el3, cpu_context_t *ctx);
+
+#endif /* __ASSEMBLER__ */
+
+#endif
diff --git a/include/common/feat_detect.h b/include/common/feat_detect.h
index 0f0f105..788dfb3 100644
--- a/include/common/feat_detect.h
+++ b/include/common/feat_detect.h
@@ -7,26 +7,12 @@
#ifndef FEAT_DETECT_H
#define FEAT_DETECT_H
-#include <arch_features.h>
-#include <common/debug.h>
-
/* Function Prototypes */
void detect_arch_features(void);
/* Macro Definitions */
-#define FEAT_STATE_1 1
-#define FEAT_STATE_2 2
-#define feat_detect_panic(a, b) ((a) ? (void)0 : feature_panic(b))
-
-/*******************************************************************************
- * Function : feature_panic
- * Customised panic module with error logging mechanism to list the feature
- * not supported by the PE.
- ******************************************************************************/
-static inline void feature_panic(char *feat_name)
-{
- ERROR("FEAT_%s not supported by the PE\n", feat_name);
- panic();
-}
+#define FEAT_STATE_DISABLED 0
+#define FEAT_STATE_ALWAYS 1
+#define FEAT_STATE_CHECK 2
#endif /* FEAT_DETECT_H */
diff --git a/include/drivers/arm/css/scmi.h b/include/drivers/arm/css/scmi.h
index 9dd08e5..356012b 100644
--- a/include/drivers/arm/css/scmi.h
+++ b/include/drivers/arm/css/scmi.h
@@ -168,7 +168,7 @@
int scmi_ap_core_get_reset_addr(void *p, uint64_t *reset_addr, uint32_t *attr);
/* API to get the platform specific SCMI channel information. */
-scmi_channel_plat_info_t *plat_css_get_scmi_info(int channel_id);
+scmi_channel_plat_info_t *plat_css_get_scmi_info(unsigned int channel_id);
/* API to override default PSCI callbacks for platforms that support SCMI. */
const plat_psci_ops_t *css_scmi_override_pm_ops(plat_psci_ops_t *ops);
diff --git a/include/drivers/console.h b/include/drivers/console.h
index 99bf960..f499571 100644
--- a/include/drivers/console.h
+++ b/include/drivers/console.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2023, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -48,6 +48,8 @@
/* Additional private driver data may follow here. */
} console_t;
+extern console_t *console_list;
+
/* offset macro assertions for console_t */
#include <drivers/console_assertions.h>
diff --git a/include/drivers/measured_boot/event_log/event_log.h b/include/drivers/measured_boot/event_log/event_log.h
index eb0e2b1..794d613 100644
--- a/include/drivers/measured_boot/event_log/event_log.h
+++ b/include/drivers/measured_boot/event_log/event_log.h
@@ -115,13 +115,13 @@
void event_log_write_specid_event(void);
void event_log_write_header(void);
void dump_event_log(uint8_t *log_addr, size_t log_size);
-const event_log_metadata_t *plat_event_log_get_metadata(void);
int event_log_measure(uintptr_t data_base, uint32_t data_size,
unsigned char hash_data[CRYPTO_MD_MAX_SIZE]);
void event_log_record(const uint8_t *hash, uint32_t event_type,
const event_log_metadata_t *metadata_ptr);
int event_log_measure_and_record(uintptr_t data_base, uint32_t data_size,
- uint32_t data_id);
+ uint32_t data_id,
+ const event_log_metadata_t *metadata_ptr);
size_t event_log_get_cur_size(uint8_t *event_log_start);
#endif /* EVENT_LOG_H */
diff --git a/include/drivers/nxp/smmu/nxp_smmu.h b/include/drivers/nxp/smmu/nxp_smmu.h
index d64c33b..bc17703 100644
--- a/include/drivers/nxp/smmu/nxp_smmu.h
+++ b/include/drivers/nxp/smmu/nxp_smmu.h
@@ -10,10 +10,13 @@
#define SMMU_SCR0 (0x0)
#define SMMU_NSCR0 (0x400)
+#define SMMU_SACR (0x10)
#define SCR0_CLIENTPD_MASK 0x00000001
#define SCR0_USFCFG_MASK 0x00000400
+#define SMMU_SACR_CACHE_LOCK_ENABLE_BIT (1ULL << 26U)
+
static inline void bypass_smmu(uintptr_t smmu_base_addr)
{
uint32_t val;
@@ -27,4 +30,13 @@
mmio_write_32((smmu_base_addr + SMMU_NSCR0), val);
}
+static inline void smmu_cache_unlock(uintptr_t smmu_base_addr)
+{
+ uint32_t val;
+
+ val = mmio_read_32((smmu_base_addr + SMMU_SACR));
+ val &= (uint32_t)~SMMU_SACR_CACHE_LOCK_ENABLE_BIT;
+ mmio_write_32((smmu_base_addr + SMMU_SACR), val);
+}
+
#endif
diff --git a/include/drivers/st/io_mmc.h b/include/drivers/st/io_mmc.h
deleted file mode 100644
index 6179e89..0000000
--- a/include/drivers/st/io_mmc.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef IO_MMC_H
-#define IO_MMC_H
-
-#include <drivers/io/io_driver.h>
-
-struct io_mmc_dev_spec {
- bool use_boot_part;
-};
-
-int register_io_dev_mmc(const io_dev_connector_t **dev_con);
-
-#endif /* IO_MMC_H */
diff --git a/include/lib/cpus/aarch32/cortex_a72.h b/include/lib/cpus/aarch32/cortex_a72.h
index 4b1af61..954f736 100644
--- a/include/lib/cpus/aarch32/cortex_a72.h
+++ b/include/lib/cpus/aarch32/cortex_a72.h
@@ -37,16 +37,21 @@
#define CORTEX_A72_CPUACTLR_NO_ALLOC_WBWA (ULL(1) << 49)
#define CORTEX_A72_CPUACTLR_DCC_AS_DCCI (ULL(1) << 44)
#define CORTEX_A72_CPUACTLR_DIS_INSTR_PREFETCH (ULL(1) << 32)
+#define CORTEX_A72_CPUACTLR_DELAY_EXCLUSIVE_SNOOP (ULL(1) << 31)
/*******************************************************************************
* L2 Control register specific definitions.
******************************************************************************/
#define CORTEX_A72_L2CTLR p15, 1, c9, c0, 2
+#define CORTEX_A72_L2CTLR_EL1_ECC_AND_PARITY_ENABLE (ULL(1) << 21)
+#define CORTEX_A72_L2CTLR_EL1_DATA_INLINE_ECC_ENABLE (ULL(1) << 20)
+
#define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT U(0)
#define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT U(6)
#define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES U(0x2)
+#define CORTEX_A72_L2_DATA_RAM_LATENCY_4_CYCLES U(0x3)
#define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES U(0x1)
#define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES U(0x2)
diff --git a/include/lib/cpus/aarch64/cortex_a72.h b/include/lib/cpus/aarch64/cortex_a72.h
index 1777645..bef9337 100644
--- a/include/lib/cpus/aarch64/cortex_a72.h
+++ b/include/lib/cpus/aarch64/cortex_a72.h
@@ -40,6 +40,7 @@
#define CORTEX_A72_CPUACTLR_EL1_NO_ALLOC_WBWA (ULL(1) << 49)
#define CORTEX_A72_CPUACTLR_EL1_DCC_AS_DCCI (ULL(1) << 44)
#define CORTEX_A72_CPUACTLR_EL1_DIS_INSTR_PREFETCH (ULL(1) << 32)
+#define CORTEX_A72_CPUACTLR_EL1_DELAY_EXCLUSIVE_SNOOP (ULL(1) << 31)
/*******************************************************************************
* L2 Auxiliary Control register specific definitions.
@@ -60,6 +61,9 @@
******************************************************************************/
#define CORTEX_A72_L2CTLR_EL1 S3_1_C11_C0_2
+#define CORTEX_A72_L2CTLR_EL1_ECC_AND_PARITY_ENABLE (ULL(1) << 21)
+#define CORTEX_A72_L2CTLR_EL1_DATA_INLINE_ECC_ENABLE (ULL(1) << 20)
+
#define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT U(0)
#define CORTEX_A72_L2CTLR_DATA_RAM_SETUP_SHIFT U(5)
#define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT U(6)
@@ -68,6 +72,7 @@
#define CORTEX_A72_L2_DATA_RAM_LATENCY_MASK U(0x7)
#define CORTEX_A72_L2_TAG_RAM_LATENCY_MASK U(0x7)
#define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES U(0x2)
+#define CORTEX_A72_L2_DATA_RAM_LATENCY_4_CYCLES U(0x3)
#define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES U(0x1)
#define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES U(0x2)
diff --git a/include/lib/cpus/aarch64/cortex_a78.h b/include/lib/cpus/aarch64/cortex_a78.h
index 31da99e..fb325b6 100644
--- a/include/lib/cpus/aarch64/cortex_a78.h
+++ b/include/lib/cpus/aarch64/cortex_a78.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2022, ARM Limited. All rights reserved.
+ * Copyright (c) 2019-2023, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -40,6 +40,8 @@
#define CORTEX_A78_ACTLR2_EL1_BIT_2 (ULL(1) << 2)
#define CORTEX_A78_ACTLR2_EL1_BIT_40 (ULL(1) << 40)
+#define CORTEX_A78_ACTLR3_EL1 S3_0_C15_C1_2
+
/*******************************************************************************
* CPU Activity Monitor Unit register specific definitions.
******************************************************************************/
diff --git a/include/lib/cpus/aarch64/neoverse_v1.h b/include/lib/cpus/aarch64/neoverse_v1.h
index 9c7e967..4c10484 100644
--- a/include/lib/cpus/aarch64/neoverse_v1.h
+++ b/include/lib/cpus/aarch64/neoverse_v1.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2022, ARM Limited. All rights reserved.
+ * Copyright (c) 2019-2023, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -41,4 +41,6 @@
#define NEOVERSE_V1_ACTLR2_EL1_BIT_28 (ULL(1) << 28)
#define NEOVERSE_V1_ACTLR2_EL1_BIT_40 (ULL(1) << 40)
+#define NEOVERSE_V1_ACTLR3_EL1 S3_0_C15_C1_2
+
#endif /* NEOVERSE_V1_H */
diff --git a/include/lib/el3_runtime/aarch64/context.h b/include/lib/el3_runtime/aarch64/context.h
index 6c13166..6986e0e 100644
--- a/include/lib/el3_runtime/aarch64/context.h
+++ b/include/lib/el3_runtime/aarch64/context.h
@@ -523,10 +523,6 @@
void el2_sysregs_context_save_mpam(el2_sysregs_t *regs);
void el2_sysregs_context_restore_mpam(el2_sysregs_t *regs);
#endif /* ENABLE_MPAM_FOR_LOWER_ELS */
-#if ENABLE_FEAT_FGT
-void el2_sysregs_context_save_fgt(el2_sysregs_t *regs);
-void el2_sysregs_context_restore_fgt(el2_sysregs_t *regs);
-#endif /* ENABLE_FEAT_FGT */
#if ENABLE_FEAT_ECV
void el2_sysregs_context_save_ecv(el2_sysregs_t *regs);
void el2_sysregs_context_restore_ecv(el2_sysregs_t *regs);
@@ -551,10 +547,6 @@
void el2_sysregs_context_save_csv2(el2_sysregs_t *regs);
void el2_sysregs_context_restore_csv2(el2_sysregs_t *regs);
#endif /* ENABLE_FEAT_CSV2_2 */
-#if ENABLE_FEAT_HCX
-void el2_sysregs_context_save_hcx(el2_sysregs_t *regs);
-void el2_sysregs_context_restore_hcx(el2_sysregs_t *regs);
-#endif /* ENABLE_FEAT_HCX */
#endif /* CTX_INCLUDE_EL2_REGS */
#if CTX_INCLUDE_FPREGS
diff --git a/include/lib/fconf/fconf.h b/include/lib/fconf/fconf.h
index 131c542..3762021 100644
--- a/include/lib/fconf/fconf.h
+++ b/include/lib/fconf/fconf.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020, ARM Limited. All rights reserved.
+ * Copyright (c) 2019-2022, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -21,7 +21,7 @@
*/
#define FCONF_REGISTER_POPULATOR(config, name, callback) \
__attribute__((used, section(".fconf_populator"))) \
- const struct fconf_populator (name##__populator) = { \
+ static const struct fconf_populator (name##__populator) = { \
.config_type = (#config), \
.info = (#name), \
.populate = (callback) \
diff --git a/include/lib/libc/aarch32/limits_.h b/include/lib/libc/aarch32/limits_.h
index 26cec17..a67ec53 100644
--- a/include/lib/libc/aarch32/limits_.h
+++ b/include/lib/libc/aarch32/limits_.h
@@ -1,11 +1,11 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2023, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#define SCHAR_MAX 0x7F
-#define SCHAR_MIN (-SCHAR_MIN - 1)
+#define SCHAR_MIN (-SCHAR_MAX - 1)
#define CHAR_MAX 0x7F
#define CHAR_MIN (-CHAR_MAX - 1)
#define UCHAR_MAX 0xFFU
diff --git a/include/lib/libc/aarch64/limits_.h b/include/lib/libc/aarch64/limits_.h
index e36cfe7..1bb0681 100644
--- a/include/lib/libc/aarch64/limits_.h
+++ b/include/lib/libc/aarch64/limits_.h
@@ -1,11 +1,11 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2023, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#define SCHAR_MAX 0x7F
-#define SCHAR_MIN (-SCHAR_MIN - 1)
+#define SCHAR_MIN (-SCHAR_MAX - 1)
#define CHAR_MAX 0x7F
#define CHAR_MIN (-CHAR_MAX - 1)
#define UCHAR_MAX 0xFFU
diff --git a/include/lib/psa/measured_boot.h b/include/lib/psa/measured_boot.h
index 47aa0b9..231da2c 100644
--- a/include/lib/psa/measured_boot.h
+++ b/include/lib/psa/measured_boot.h
@@ -74,4 +74,53 @@
size_t measurement_value_size,
bool lock_measurement);
+/**
+ * Retrieves a measurement from the requested slot.
+ *
+ * index Slot number from which measurement is to be
+ * retrieved.
+ * signer_id Pointer to signer_id buffer.
+ * signer_id_size Size of the signer_id buffer in bytes.
+ * signer_id_len On success, number of bytes that make up
+ * signer_id.
+ * version Pointer to version buffer.
+ * version_size Size of the version buffer in bytes.
+ * version_len On success, number of bytes that makeup the
+ * version.
+ * measurement_algo Pointer to measurement_algo.
+ * sw_type Pointer to sw_type buffer.
+ * sw_type_size Size of the sw_type buffer in bytes.
+ * sw_type_len On success, number of bytes that makeup the
+ * sw_type.
+ * measurement_value Pointer to measurement_value buffer.
+ * measurement_value_size Size of the measurement_value buffer in bytes.
+ * measurement_value_len On success, number of bytes that make up the
+ * measurement_value.
+ * is_locked Pointer to lock status of requested measurement
+ * slot.
+ *
+ * PSA_SUCCESS
+ * - Success.
+ * PSA_ERROR_INVALID_ARGUMENT
+ * - The size of at least one of the output buffers is incorrect or the
+ * requested slot index is invalid.
+ * PSA_ERROR_DOES_NOT_EXIST
+ * - The requested slot is empty, does not contain a measurement.
+ */
+psa_status_t rss_measured_boot_read_measurement(uint8_t index,
+ uint8_t *signer_id,
+ size_t signer_id_size,
+ size_t *signer_id_len,
+ uint8_t *version,
+ size_t version_size,
+ size_t *version_len,
+ uint32_t *measurement_algo,
+ uint8_t *sw_type,
+ size_t sw_type_size,
+ size_t *sw_type_len,
+ uint8_t *measurement_value,
+ size_t measurement_value_size,
+ size_t *measurement_value_len,
+ bool *is_locked);
+
#endif /* PSA_MEASURED_BOOT_H */
diff --git a/include/lib/utils_def.h b/include/lib/utils_def.h
index 198b890..63eda63 100644
--- a/include/lib/utils_def.h
+++ b/include/lib/utils_def.h
@@ -68,14 +68,14 @@
__typeof__(x) _x = (x); \
__typeof__(y) _y = (y); \
(void)(&_x == &_y); \
- _x < _y ? _x : _y; \
+ (_x < _y) ? _x : _y; \
})
#define MAX(x, y) __extension__ ({ \
__typeof__(x) _x = (x); \
__typeof__(y) _y = (y); \
(void)(&_x == &_y); \
- _x > _y ? _x : _y; \
+ (_x > _y) ? _x : _y; \
})
#define CLAMP(x, min, max) __extension__ ({ \
@@ -84,7 +84,7 @@
__typeof__(max) _max = (max); \
(void)(&_x == &_min); \
(void)(&_x == &_max); \
- (_x > _max ? _max : (_x < _min ? _min : _x)); \
+ ((_x > _max) ? _max : ((_x < _min) ? _min : _x)); \
})
/*
diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h
index ab0e4ff..36b1bdb 100644
--- a/include/plat/arm/common/arm_def.h
+++ b/include/plat/arm/common/arm_def.h
@@ -20,10 +20,12 @@
*****************************************************************************/
/*
- * Root of trust key hash lengths
+ * Root of trust key lengths
*/
#define ARM_ROTPK_HEADER_LEN 19
#define ARM_ROTPK_HASH_LEN 32
+/* ARM_ROTPK_KEY_LEN includes DER header + raw key material */
+#define ARM_ROTPK_KEY_LEN 294
/* Special value used to verify platform parameters from BL2 to BL31 */
#define ARM_BL31_PLAT_PARAM_VAL ULL(0x0f1e2d3c4b5a6978)
diff --git a/include/plat/arm/common/arm_pas_def.h b/include/plat/arm/common/arm_pas_def.h
index c199302..fba8d2c 100644
--- a/include/plat/arm/common/arm_pas_def.h
+++ b/include/plat/arm/common/arm_pas_def.h
@@ -21,24 +21,30 @@
* ============================================================================
* 0GB | 1GB |L0 GPT|ANY |TBROM (EL3 code) |Fixed mapping
* | | | |TSRAM (EL3 data) |
- * | | | |IO (incl.UARTs & GIC) |
+ * 00000000 | | | |IO (incl.UARTs & GIC) |
* ----------------------------------------------------------------------------
* 1GB | 1GB |L0 GPT|ANY |IO |Fixed mapping
+ * 40000000 | | | | |
* ----------------------------------------------------------------------------
- * 2GB | 1GB |L1 GPT|NS |DRAM (NS Kernel) |Use T.Descrip
+ * 2GB |2GB-64MB |L1 GPT|NS |DRAM (NS Kernel) |Use T.Descrip
+ * 80000000 | | | | |
* ----------------------------------------------------------------------------
- * 3GB |1GB-64MB |L1 GPT|NS |DRAM (NS Kernel) |Use T.Descrip
- * ----------------------------------------------------------------------------
- * 4GB-64MB |64MB-32MB | | | |
- * | -4MB |L1 GPT|SECURE|DRAM TZC |Use T.Descrip
+ * 4GB-64MB |64MB-32MB-4MB|L1 GPT|SECURE|DRAM TZC |Use T.Descrip
+ * FC000000 | | | | |
* ----------------------------------------------------------------------------
* 4GB-32MB | | | | |
* -3MB-1MB |32MB |L1 GPT|REALM |RMM |Use T.Descrip
+ * FDC00000 | | | | |
* ----------------------------------------------------------------------------
* 4GB-3MB | | | | |
* -1MB |3MB |L1 GPT|ROOT |EL3 DRAM data |Use T.Descrip
+ * FFC00000 | | | | |
* ----------------------------------------------------------------------------
* 4GB-1MB |1MB |L1 GPT|ROOT |DRAM (L1 GPTs, SCP TZC) |Fixed mapping
+ * FFF00000 | | | | |
+ * ----------------------------------------------------------------------------
+ * 34GB |2GB |L1 GPT|NS |DRAM (NS Kernel) |Use T.Descrip
+ * 880000000| | | | |
* ============================================================================
*
* - 4KB of L0 GPT reside in TSRAM, on top of the CONFIG section.
@@ -55,7 +61,7 @@
/* Device memory 0 to 2GB */
#define ARM_PAS_1_BASE (U(0))
-#define ARM_PAS_1_SIZE ((ULL(1)<<31)) /* 2GB */
+#define ARM_PAS_1_SIZE ((ULL(1) << 31)) /* 2GB */
/* NS memory 2GB to (end - 64MB) */
#define ARM_PAS_2_BASE (ARM_PAS_1_BASE + ARM_PAS_1_SIZE)
@@ -69,9 +75,14 @@
#define ARM_PAS_3_BASE (ARM_AP_TZC_DRAM1_BASE)
#define ARM_PAS_3_SIZE (ARM_AP_TZC_DRAM1_SIZE)
+/* NS memory 2GB */
+#define ARM_PAS_4_BASE ARM_DRAM2_BASE
+#define ARM_PAS_4_SIZE ((ULL(1) << 31)) /* 2GB */
+
#define ARM_PAS_GPI_ANY MAP_GPT_REGION(ARM_PAS_1_BASE, \
ARM_PAS_1_SIZE, \
GPT_GPI_ANY)
+
#define ARM_PAS_KERNEL GPT_MAP_REGION_GRANULE(ARM_PAS_2_BASE, \
ARM_PAS_2_SIZE, \
GPT_GPI_NS)
@@ -80,6 +91,9 @@
ARM_PAS_3_SIZE, \
GPT_GPI_SECURE)
+#define ARM_PAS_KERNEL_1 GPT_MAP_REGION_GRANULE(ARM_PAS_4_BASE, \
+ ARM_PAS_4_SIZE, \
+ GPT_GPI_NS)
/*
* REALM and Shared area share the same PAS, so consider them a single
* PAS region to configure in GPT.
diff --git a/include/plat/arm/common/plat_arm.h b/include/plat/arm/common/plat_arm.h
index 6c0d91d..494e470 100644
--- a/include/plat/arm/common/plat_arm.h
+++ b/include/plat/arm/common/plat_arm.h
@@ -159,7 +159,7 @@
#define ARM_ROTPK_REGS_ID 1
#define ARM_ROTPK_DEVEL_RSA_ID 2
#define ARM_ROTPK_DEVEL_ECDSA_ID 3
-
+#define ARM_ROTPK_DEVEL_FULL_DEV_RSA_KEY_ID 4
/* IO storage utility functions */
int arm_io_setup(void);
diff --git a/include/plat/common/platform.h b/include/plat/common/platform.h
index 8407bbd..3351036 100644
--- a/include/plat/common/platform.h
+++ b/include/plat/common/platform.h
@@ -421,4 +421,17 @@
void plat_fwu_set_images_source(const struct fwu_metadata *metadata);
uint32_t plat_fwu_get_boot_idx(void);
+/*
+ * Optional function to indicate if cache management operations can be
+ * performed.
+ */
+#if CONDITIONAL_CMO
+uint64_t plat_can_cmo(void);
+#else
+static inline uint64_t plat_can_cmo(void)
+{
+ return 1;
+}
+#endif /* CONDITIONAL_CMO */
+
#endif /* PLATFORM_H */
diff --git a/include/services/rmm_core_manifest.h b/include/services/rmm_core_manifest.h
index 2f25858..7edef46 100644
--- a/include/services/rmm_core_manifest.h
+++ b/include/services/rmm_core_manifest.h
@@ -38,6 +38,7 @@
/* Boot manifest core structure as per v0.1 */
typedef struct rmm_manifest {
uint32_t version; /* Manifest version */
+ uint32_t padding; /* RES0 */
uintptr_t plat_data; /* Manifest platform data */
} rmm_manifest_t;
diff --git a/include/services/trp/trp_helpers.h b/include/services/trp/trp_helpers.h
index 8e786e2..83ec740 100644
--- a/include/services/trp/trp_helpers.h
+++ b/include/services/trp/trp_helpers.h
@@ -39,5 +39,12 @@
__dead2 void trp_boot_abort(uint64_t err);
+/* TRP SMC result registers X0-X4 */
+#define TRP_SMC_RESULT_REGS 5
+
+struct trp_smc_result {
+ unsigned long long x[TRP_SMC_RESULT_REGS];
+};
+
#endif /* __ASSEMBLER __ */
#endif /* TRP_HELPERS_H */
diff --git a/lib/cpus/aarch64/cortex_a710.S b/lib/cpus/aarch64/cortex_a710.S
index fed3f33..cebd6f0 100644
--- a/lib/cpus/aarch64/cortex_a710.S
+++ b/lib/cpus/aarch64/cortex_a710.S
@@ -355,22 +355,22 @@
/* ---------------------------------------------------------------
* Errata Workaround for Cortex-A710 Erratum 2282622.
- * This applies to revision r0p0, r1p0 and r2p0.
- * It is fixed in r2p1.
+ * This applies to revision r0p0, r1p0, r2p0 and r2p1.
+ * It is still open.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0, x1, x17
* ---------------------------------------------------------------
*/
func errata_a710_2282622_wa
- /* Compare x0 against revision r2p0 */
+ /* Compare x0 against revision r2p1 */
mov x17, x30
bl check_errata_2282622
cbz x0, 1f
/* Apply the workaround */
mrs x1, CORTEX_A710_CPUACTLR2_EL1
- orr x1, x1, BIT(0)
+ orr x1, x1, #BIT(0)
msr CORTEX_A710_CPUACTLR2_EL1, x1
1:
@@ -378,8 +378,8 @@
endfunc errata_a710_2282622_wa
func check_errata_2282622
- /* Applies to r0p0, r1p0 and r2p0 */
- mov x1, #0x20
+ /* Applies to r0p0, r1p0, r2p0 and r2p1 */
+ mov x1, #0x21
b cpu_rev_var_ls
endfunc check_errata_2282622
@@ -482,6 +482,30 @@
b cpu_rev_var_ls
endfunc check_errata_2371105
+/* ----------------------------------------------------
+ * Errata Workaround for Cortex-A710 Errata #2768515
+ * This applies to revisions <= r2p1 and is still open.
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x17
+ * ----------------------------------------------------
+ */
+func errata_a710_2768515_wa
+ mov x17, x30
+ bl check_errata_2768515
+ cbz x0, 1f
+
+ /* dsb before isb of power down sequence */
+ dsb sy
+1:
+ ret x17
+endfunc errata_a710_2768515_wa
+
+func check_errata_2768515
+ /* Applies to all revisions <= r2p1 */
+ mov x1, #0x21
+ b cpu_rev_var_ls
+endfunc check_errata_2768515
+
func check_errata_cve_2022_23960
#if WORKAROUND_CVE_2022_23960
mov x0, #ERRATA_APPLIES
@@ -518,6 +542,12 @@
mrs x0, CORTEX_A710_CPUPWRCTLR_EL1
orr x0, x0, #CORTEX_A710_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
msr CORTEX_A710_CPUPWRCTLR_EL1, x0
+#if ERRATA_A710_2768515
+ mov x15, x30
+ bl cpu_get_rev_var
+ bl errata_a710_2768515_wa
+ mov x30, x15
+#endif /* ERRATA_A710_2768515 */
isb
ret
endfunc cortex_a710_core_pwr_dwn
@@ -550,6 +580,7 @@
report_errata ERRATA_A710_2216384, cortex_a710, 2216384
report_errata ERRATA_A710_2291219, cortex_a710, 2291219
report_errata ERRATA_A710_2371105, cortex_a710, 2371105
+ report_errata ERRATA_A710_2768515, cortex_a710, 2768515
report_errata WORKAROUND_CVE_2022_23960, cortex_a710, cve_2022_23960
report_errata ERRATA_DSU_2313941, cortex_a710, dsu_2313941
diff --git a/lib/cpus/aarch64/cortex_a78.S b/lib/cpus/aarch64/cortex_a78.S
index dd3487a..a3932e8 100644
--- a/lib/cpus/aarch64/cortex_a78.S
+++ b/lib/cpus/aarch64/cortex_a78.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2022, ARM Limited. All rights reserved.
+ * Copyright (c) 2019-2023, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -326,6 +326,60 @@
b cpu_rev_var_ls
endfunc check_errata_2395406
+/* ----------------------------------------------------
+ * Errata Workaround for Cortex-A78 Errata 2772019
+ * This applies to revisions <= r1p2 and is still open.
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x17
+ * ----------------------------------------------------
+ */
+func errata_a78_2772019_wa
+ mov x17, x30
+ bl check_errata_2772019
+ cbz x0, 1f
+
+
+ /* dsb before isb of power down sequence */
+ dsb sy
+1:
+ ret x17
+endfunc errata_a78_2772019_wa
+
+func check_errata_2772019
+ /* Applies to all revisions <= r1p2 */
+ mov x1, #0x12
+ b cpu_rev_var_ls
+endfunc check_errata_2772019
+
+/* ----------------------------------------------------
+ * Errata Workaround for Cortex A78 Errata 2779479.
+ * This applies to revisions r0p0, r1p0, r1p1, and r1p2.
+ * It is still open.
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x1, x17
+ * ----------------------------------------------------
+ */
+func errata_a78_2779479_wa
+ /* Check revision. */
+ mov x17, x30
+ bl check_errata_2779479
+ cbz x0, 1f
+
+ /* Apply the workaround */
+ mrs x1, CORTEX_A78_ACTLR3_EL1
+ orr x1, x1, #BIT(47)
+ msr CORTEX_A78_ACTLR3_EL1, x1
+
+1:
+ ret x17
+endfunc errata_a78_2779479_wa
+
+func check_errata_2779479
+ /* Applies to r0p0, r1p0, r1p1, r1p2 */
+ mov x1, #CPU_REV(1, 2)
+ b cpu_rev_var_ls
+endfunc check_errata_2779479
+
func check_errata_cve_2022_23960
#if WORKAROUND_CVE_2022_23960
mov x0, #ERRATA_APPLIES
@@ -389,6 +443,11 @@
bl errata_a78_2395406_wa
#endif
+#if ERRATA_A78_2779479
+ mov x0, x18
+ bl errata_a78_2779479_wa
+#endif
+
#if ENABLE_AMU
/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
mrs x0, actlr_el3
@@ -434,6 +493,12 @@
mrs x0, CORTEX_A78_CPUPWRCTLR_EL1
orr x0, x0, #CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
msr CORTEX_A78_CPUPWRCTLR_EL1, x0
+#if ERRATA_A78_2772019
+ mov x15, x30
+ bl cpu_get_rev_var
+ bl errata_a78_2772019_wa
+ mov x30, x15
+#endif /* ERRATA_A78_2772019 */
isb
ret
endfunc cortex_a78_core_pwr_dwn
@@ -461,6 +526,8 @@
report_errata ERRATA_A78_2242635, cortex_a78, 2242635
report_errata ERRATA_A78_2376745, cortex_a78, 2376745
report_errata ERRATA_A78_2395406, cortex_a78, 2395406
+ report_errata ERRATA_A78_2772019, cortex_a78, 2772019
+ report_errata ERRATA_A78_2779479, cortex_a78, 2779479
report_errata WORKAROUND_CVE_2022_23960, cortex_a78, cve_2022_23960
ldp x8, x30, [sp], #16
diff --git a/lib/cpus/aarch64/cortex_x2.S b/lib/cpus/aarch64/cortex_x2.S
index c810be6..497bd52 100644
--- a/lib/cpus/aarch64/cortex_x2.S
+++ b/lib/cpus/aarch64/cortex_x2.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -267,13 +267,43 @@
b cpu_rev_var_range
endfunc check_errata_2147715
-/* -------------------------------------------------------
- * Errata Workaround for Cortex-X2 Erratum 2371105.
- * This applies to revisions <= r2p0 and is fixed in r2p1.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * -------------------------------------------------------
- */
+ /* ---------------------------------------------------------------
+ * Errata Workaround for Cortex-X2 Erratum 2282622.
+ * This applies to revision r0p0, r1p0, r2p0 and r2p1.
+ * It is still open.
+ * Inputs:
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0, x1, x17
+ * ---------------------------------------------------------------
+ */
+func errata_x2_2282622_wa
+ /* Compare x0 against revision r2p1 */
+ mov x17, x30
+ bl check_errata_2282622
+ cbz x0, 1f
+
+ /* Apply the workaround */
+ mrs x1, CORTEX_X2_CPUACTLR2_EL1
+ orr x1, x1, #BIT(0)
+ msr CORTEX_X2_CPUACTLR2_EL1, x1
+
+1:
+ ret x17
+endfunc errata_x2_2282622_wa
+
+func check_errata_2282622
+ /* Applies to r0p0, r1p0, r2p0 and r2p1 */
+ mov x1, #0x21
+ b cpu_rev_var_ls
+endfunc check_errata_2282622
+
+ /* -------------------------------------------------------
+ * Errata Workaround for Cortex-X2 Erratum 2371105.
+ * This applies to revisions <= r2p0 and is fixed in r2p1.
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x17
+ * -------------------------------------------------------
+ */
func errata_x2_2371105_wa
/* Check workaround compatibility. */
mov x17, x30
@@ -296,6 +326,30 @@
endfunc check_errata_2371105
/* ----------------------------------------------------
+ * Errata Workaround for Cortex-X2 Errata #2768515
+ * This applies to revisions <= r2p1 and is still open.
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x17
+ * ----------------------------------------------------
+ */
+func errata_x2_2768515_wa
+ mov x17, x30
+ bl check_errata_2768515
+ cbz x0, 1f
+
+ /* dsb before isb of power down sequence */
+ dsb sy
+1:
+ ret x17
+endfunc errata_x2_2768515_wa
+
+func check_errata_2768515
+ /* Applies to all revisions <= r2p1 */
+ mov x1, #0x21
+ b cpu_rev_var_ls
+endfunc check_errata_2768515
+
+ /* ----------------------------------------------------
* HW will do the cache maintenance while powering down
* ----------------------------------------------------
*/
@@ -307,6 +361,12 @@
mrs x0, CORTEX_X2_CPUPWRCTLR_EL1
orr x0, x0, #CORTEX_X2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
msr CORTEX_X2_CPUPWRCTLR_EL1, x0
+#if ERRATA_X2_2768515
+ mov x15, x30
+ bl cpu_get_rev_var
+ bl errata_x2_2768515_wa
+ mov x30, x15
+#endif /* ERRATA_X2_2768515 */
isb
ret
endfunc cortex_x2_core_pwr_dwn
@@ -332,7 +392,9 @@
report_errata ERRATA_X2_2083908, cortex_x2, 2083908
report_errata ERRATA_X2_2147715, cortex_x2, 2147715
report_errata ERRATA_X2_2216384, cortex_x2, 2216384
+ report_errata ERRATA_X2_2282622, cortex_x2, 2282622
report_errata ERRATA_X2_2371105, cortex_x2, 2371105
+ report_errata ERRATA_X2_2768515, cortex_x2, 2768515
report_errata WORKAROUND_CVE_2022_23960, cortex_x2, cve_2022_23960
report_errata ERRATA_DSU_2313941, cortex_x2, dsu_2313941
@@ -390,6 +452,11 @@
bl errata_x2_2147715_wa
#endif
+#if ERRATA_X2_2282622
+ mov x0, x18
+ bl errata_x2_2282622_wa
+#endif
+
#if ERRATA_X2_2371105
mov x0, x18
bl errata_x2_2371105_wa
diff --git a/lib/cpus/aarch64/neoverse_n2.S b/lib/cpus/aarch64/neoverse_n2.S
index 5861dec..dbf5941 100644
--- a/lib/cpus/aarch64/neoverse_n2.S
+++ b/lib/cpus/aarch64/neoverse_n2.S
@@ -428,6 +428,30 @@
b cpu_rev_var_ls
endfunc check_errata_2388450
+/* -------------------------------------------------------
+ * Errata Workaround for Neoverse N2 Erratum 2743089.
+ * This applies to revisions <= r0p2 and is fixed in r0p3.
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x17
+ * -------------------------------------------------------
+ */
+func errata_n2_2743089_wa
+ mov x17, x30
+ bl check_errata_2743089
+ cbz x0, 1f
+
+ /* dsb before isb of power down sequence */
+ dsb sy
+1:
+ ret x17
+endfunc errata_n2_2743089_wa
+
+func check_errata_2743089
+ /* Applies to all revisions <= r0p2 */
+ mov x1, #0x02
+ b cpu_rev_var_ls
+endfunc check_errata_2743089
+
func check_errata_cve_2022_23960
#if WORKAROUND_CVE_2022_23960
mov x0, #ERRATA_APPLIES
@@ -576,6 +600,12 @@
mrs x0, NEOVERSE_N2_CPUPWRCTLR_EL1
orr x0, x0, #NEOVERSE_N2_CORE_PWRDN_EN_BIT
msr NEOVERSE_N2_CPUPWRCTLR_EL1, x0
+#if ERRATA_N2_2743089
+ mov x15, x30
+ bl cpu_get_rev_var
+ bl errata_n2_2743089_wa
+ mov x30, x15
+#endif /* ERRATA_N2_2743089 */
isb
ret
endfunc neoverse_n2_core_pwr_dwn
@@ -607,6 +637,7 @@
report_errata ERRATA_N2_2326639, neoverse_n2, 2326639
report_errata ERRATA_N2_2376738, neoverse_n2, 2376738
report_errata ERRATA_N2_2388450, neoverse_n2, 2388450
+ report_errata ERRATA_N2_2743089, neoverse_n2, 2743089
report_errata WORKAROUND_CVE_2022_23960, neoverse_n2, cve_2022_23960
report_errata ERRATA_DSU_2313941, neoverse_n2, dsu_2313941
diff --git a/lib/cpus/aarch64/neoverse_v1.S b/lib/cpus/aarch64/neoverse_v1.S
index 3282fbc..f9a5789 100644
--- a/lib/cpus/aarch64/neoverse_v1.S
+++ b/lib/cpus/aarch64/neoverse_v1.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -462,6 +462,59 @@
b cpu_rev_var_ls
endfunc check_errata_2372203
+ /* ----------------------------------------------------
+ * Errata Workaround for Neoverse V1 Errata #2743093.
+ * This applies to revisions <= r1p2 and is still open.
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x17
+ * ----------------------------------------------------
+ */
+func errata_neoverse_v1_2743093_wa
+ mov x17, x30
+ bl check_errata_2743093
+ cbz x0, 1f
+
+ /* dsb before isb of power down sequence */
+ dsb sy
+1:
+ ret x17
+endfunc errata_neoverse_v1_2743093_wa
+
+func check_errata_2743093
+ /* Applies to all revisions <= r1p2 */
+ mov x1, #0x12
+ b cpu_rev_var_ls
+endfunc check_errata_2743093
+
+ /* ----------------------------------------------------
+ * Errata Workaround for Neoverse V1 Errata #2779461.
+ * This applies to revisions r0p0, r1p0, r1p1, and r1p2.
+ * It is still open.
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x1, x17
+ * ----------------------------------------------------
+ */
+func errata_neoverse_v1_2779461_wa
+ /* Check revision. */
+ mov x17, x30
+ bl check_errata_2779461
+ cbz x0, 1f
+
+ /* Apply the workaround */
+ mrs x1, NEOVERSE_V1_ACTLR3_EL1
+ orr x1, x1, #BIT(47)
+ msr NEOVERSE_V1_ACTLR3_EL1, x1
+
+1:
+ ret x17
+endfunc errata_neoverse_v1_2779461_wa
+
+func check_errata_2779461
+ /* Applies to r0p0, r1p0, r1p1, r1p2 */
+ mov x1, #CPU_REV(1, 2)
+ b cpu_rev_var_ls
+endfunc check_errata_2779461
+
func check_errata_cve_2022_23960
#if WORKAROUND_CVE_2022_23960
mov x0, #ERRATA_APPLIES
@@ -483,6 +536,12 @@
mrs x0, NEOVERSE_V1_CPUPWRCTLR_EL1
orr x0, x0, #NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
msr NEOVERSE_V1_CPUPWRCTLR_EL1, x0
+#if ERRATA_V1_2743093
+ mov x15, x30
+ bl cpu_get_rev_var
+ bl errata_neoverse_v1_2743093_wa
+ mov x30, x15
+#endif /* ERRATA_V1_2743093 */
isb
ret
endfunc neoverse_v1_core_pwr_dwn
@@ -513,6 +572,8 @@
report_errata ERRATA_V1_2216392, neoverse_v1, 2216392
report_errata ERRATA_V1_2294912, neoverse_v1, 2294912
report_errata ERRATA_V1_2372203, neoverse_v1, 2372203
+ report_errata ERRATA_V1_2743093, neoverse_v1, 2743093
+ report_errata ERRATA_V1_2779461, neoverse_v1, 2779461
report_errata WORKAROUND_CVE_2022_23960, neoverse_v1, cve_2022_23960
ldp x8, x30, [sp], #16
@@ -591,6 +652,11 @@
bl errata_neoverse_v1_2372203_wa
#endif
+#if ERRATA_V1_2779461
+ mov x0, x18
+ bl errata_neoverse_v1_2779461_wa
+#endif
+
#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
/*
* The Neoverse-V1 generic vectors are overridden to apply errata
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index 8ef794b..4d50c1b 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2014-2022, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2014-2023, Arm Limited and Contributors. All rights reserved.
# Copyright (c) 2020-2022, NVIDIA Corporation. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
@@ -357,6 +357,15 @@
# to revisions r0p0, r1p0, r1p1, and r1p2 of the A78 cpu. It is still open.
ERRATA_A78_2395406 ?=0
+# Flag to apply erratum 2772019 workaround during powerdown. This erratum
+# applies to revisions r0p0, r1p0, r1p1 and r1p2 of the A78 cpu. It is still
+# open.
+ERRATA_A78_2772019 ?=0
+
+# Flag to apply erratum 2779479 workaround during reset. This erratum applies
+# to revision r0p0, r1p0, r1p1 and r1p2 of the A78 cpu. It is still open.
+ERRATA_A78_2779479 ?=0
+
# Flag to apply erratum 1941500 workaround during reset. This erratum applies
# to revisions r0p0 and r0p1 of the A78 AE cpu. It is still open.
ERRATA_A78_AE_1941500 ?=0
@@ -462,10 +471,6 @@
# applies to all revisions <= r4p1 of the Neoverse N1 cpu and is still open.
ERRATA_N1_2743102 ?=0
-# Flag to apply erratum 2002655 workaround during reset. This erratum applies
-# to revisions r0p0 of the Neoverse-N2 cpu, it is still open.
-ERRATA_N2_2002655 ?=0
-
# Flag to apply erratum 1618635 workaround during reset. This erratum applies
# to revision r0p0 of the Neoverse V1 cpu and was fixed in the revision r1p0.
ERRATA_V1_1618635 ?=0
@@ -516,6 +521,16 @@
# to revisions r0p0, r1p0 and r1p1 of the Neoverse V1 cpu and is still open.
ERRATA_V1_2372203 ?=0
+# Flag to apply erratum 2743093 workaround during powerdown. This erratum
+# applies to revisions r0p0, r1p0, r1p1 and r1p2 of the Neoverse V1 cpu and is
+# still open.
+ERRATA_V1_2743093 ?=0
+
+# Flag to apply erratum 2779461 workaround during powerdown. This erratum
+# applies to revisions r0p0, r1p0, r1p1 and r1p2 of the Neoverse V1 cpu and is
+# still open.
+ERRATA_V1_2779461 ?=0
+
# Flag to apply erratum 1987031 workaround during reset. This erratum applies
# to revisions r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is still open.
ERRATA_A710_1987031 ?=0
@@ -557,7 +572,8 @@
ERRATA_A710_2216384 ?=0
# Flag to apply erratum 2282622 workaround during reset. This erratum applies
-# to revision r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is fixed in r2p1.
+# to revision r0p0, r1p0, r2p0 and r2p1 of the Cortex-A710 cpu and is still
+# open.
ERRATA_A710_2282622 ?=0
# Flag to apply erratum 2291219 workaround during reset. This erratum applies
@@ -572,6 +588,15 @@
# to revision r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is fixed in r2p1.
ERRATA_A710_2371105 ?=0
+# Flag to apply erratum 2768515 workaround during power down. This erratum
+# applies to revision r0p0, r1p0, r2p0 and r2p1 of the Cortex-A710 cpu and is
+# still open.
+ERRATA_A710_2768515 ?=0
+
+# Flag to apply erratum 2002655 workaround during reset. This erratum applies
+# to revisions r0p0 of the Neoverse-N2 cpu, it is still open.
+ERRATA_N2_2002655 ?=0
+
# Flag to apply erratum 2067956 workaround during reset. This erratum applies
# to revision r0p0 of the Neoverse N2 cpu and is still open.
ERRATA_N2_2067956 ?=0
@@ -620,6 +645,10 @@
# to revision r0p0 of the Neoverse N2 cpu, it is fixed in r0p1.
ERRATA_N2_2388450 ?=0
+# Flag to apply erratum 2743089 workaround during during powerdown. This erratum
+# applies to all revisions <= r0p2 of the Neoverse N2 cpu, it is fixed in r0p3.
+ERRATA_N2_2743089 ?=0
+
# Flag to apply erratum 2002765 workaround during reset. This erratum applies
# to revisions r0p0, r1p0, and r2p0 of the Cortex-X2 cpu and is still open.
ERRATA_X2_2002765 ?=0
@@ -651,10 +680,20 @@
# only to revision r2p0 of the Cortex-X2 cpu, it is fixed in r2p1.
ERRATA_X2_2147715 ?=0
+# Flag to apply erratum 2282622 workaround during reset. This erratum applies
+# to revision r0p0, r1p0, r2p0 and r2p1 of the Cortex-X2 cpu and is still
+# open.
+ERRATA_X2_2282622 ?=0
+
# Flag to apply erratum 2371105 workaround during reset. This erratum applies
# to revision r0p0, r1p0 and r2p0 of the Cortex-X2 cpu and is fixed in r2p1.
ERRATA_X2_2371105 ?=0
+# Flag to apply erratum 2768515 workaround during power down. This erratum
+# applies to revision r0p0, r1p0, r2p0 and r2p1 of the Cortex-X2 cpu and is
+# still open.
+ERRATA_X2_2768515 ?=0
+
# Flag to apply erratum 2313909 workaround on powerdown. This erratum applies
# to revisions r0p0 and r1p0 of the Cortex-X3 cpu, it is fixed in r1p1.
ERRATA_X3_2313909 ?=0
@@ -996,6 +1035,14 @@
$(eval $(call assert_boolean,ERRATA_A78_2395406))
$(eval $(call add_define,ERRATA_A78_2395406))
+# Process ERRATA_A78_2772019 flag
+$(eval $(call assert_boolean,ERRATA_A78_2772019))
+$(eval $(call add_define,ERRATA_A78_2772019))
+
+# Process ERRATA_A78_2779479 flag
+$(eval $(call assert_boolean,ERRATA_A78_2779479))
+$(eval $(call add_define,ERRATA_A78_2779479))
+
# Process ERRATA_A78_AE_1941500 flag
$(eval $(call assert_boolean,ERRATA_A78_AE_1941500))
$(eval $(call add_define,ERRATA_A78_AE_1941500))
@@ -1099,10 +1146,6 @@
# Process ERRATA_N1_2743102 flag
$(eval $(call assert_boolean,ERRATA_N1_2743102))
$(eval $(call add_define,ERRATA_N1_2743102))
-#
-# Process ERRATA_N2_2002655 flag
-$(eval $(call assert_boolean,ERRATA_N2_2002655))
-$(eval $(call add_define,ERRATA_N2_2002655))
# Process ERRATA_V1_1618635 flag
$(eval $(call assert_boolean,ERRATA_V1_1618635))
@@ -1152,6 +1195,14 @@
$(eval $(call assert_boolean,ERRATA_V1_2372203))
$(eval $(call add_define,ERRATA_V1_2372203))
+# Process ERRATA_V1_2743093 flag
+$(eval $(call assert_boolean,ERRATA_V1_2743093))
+$(eval $(call add_define,ERRATA_V1_2743093))
+
+# Process ERRATA_V1_2779461 flag
+$(eval $(call assert_boolean,ERRATA_V1_2779461))
+$(eval $(call add_define,ERRATA_V1_2779461))
+
# Process ERRATA_A710_1987031 flag
$(eval $(call assert_boolean,ERRATA_A710_1987031))
$(eval $(call add_define,ERRATA_A710_1987031))
@@ -1208,6 +1259,14 @@
$(eval $(call assert_boolean,ERRATA_A710_2371105))
$(eval $(call add_define,ERRATA_A710_2371105))
+# Process ERRATA_A710_2768515 flag
+$(eval $(call assert_boolean,ERRATA_A710_2768515))
+$(eval $(call add_define,ERRATA_A710_2768515))
+
+# Process ERRATA_N2_2002655 flag
+$(eval $(call assert_boolean,ERRATA_N2_2002655))
+$(eval $(call add_define,ERRATA_N2_2002655))
+
# Process ERRATA_N2_2067956 flag
$(eval $(call assert_boolean,ERRATA_N2_2067956))
$(eval $(call add_define,ERRATA_N2_2067956))
@@ -1256,6 +1315,10 @@
$(eval $(call assert_boolean,ERRATA_N2_2388450))
$(eval $(call add_define,ERRATA_N2_2388450))
+# Process ERRATA_N2_2743089 flag
+$(eval $(call assert_boolean,ERRATA_N2_2743089))
+$(eval $(call add_define,ERRATA_N2_2743089))
+
# Process ERRATA_X2_2002765 flag
$(eval $(call assert_boolean,ERRATA_X2_2002765))
$(eval $(call add_define,ERRATA_X2_2002765))
@@ -1284,10 +1347,18 @@
$(eval $(call assert_boolean,ERRATA_X2_2147715))
$(eval $(call add_define,ERRATA_X2_2147715))
+# Process ERRATA_X2_2282622 flag
+$(eval $(call assert_boolean,ERRATA_X2_2282622))
+$(eval $(call add_define,ERRATA_X2_2282622))
+
# Process ERRATA_X2_2371105 flag
$(eval $(call assert_boolean,ERRATA_X2_2371105))
$(eval $(call add_define,ERRATA_X2_2371105))
+# Process ERRATA_X2_2768515 flag
+$(eval $(call assert_boolean,ERRATA_X2_2768515))
+$(eval $(call add_define,ERRATA_X2_2768515))
+
# Process ERRATA_X3_2313909 flag
$(eval $(call assert_boolean,ERRATA_X3_2313909))
$(eval $(call add_define,ERRATA_X3_2313909))
diff --git a/lib/el3_runtime/aarch64/context.S b/lib/el3_runtime/aarch64/context.S
index 6b88a90..b5d61ff 100644
--- a/lib/el3_runtime/aarch64/context.S
+++ b/lib/el3_runtime/aarch64/context.S
@@ -25,10 +25,6 @@
.global el2_sysregs_context_save_mpam
.global el2_sysregs_context_restore_mpam
#endif /* ENABLE_MPAM_FOR_LOWER_ELS */
-#if ENABLE_FEAT_FGT
- .global el2_sysregs_context_save_fgt
- .global el2_sysregs_context_restore_fgt
-#endif /* ENABLE_FEAT_FGT */
#if ENABLE_FEAT_ECV
.global el2_sysregs_context_save_ecv
.global el2_sysregs_context_restore_ecv
@@ -53,10 +49,6 @@
.global el2_sysregs_context_save_csv2
.global el2_sysregs_context_restore_csv2
#endif /* ENABLE_FEAT_CSV2_2 */
-#if ENABLE_FEAT_HCX
- .global el2_sysregs_context_save_hcx
- .global el2_sysregs_context_restore_hcx
-#endif /* ENABLE_FEAT_HCX */
#endif /* CTX_INCLUDE_EL2_REGS */
.global el1_sysregs_context_save
@@ -285,7 +277,7 @@
mrs x12, MPAMVPMV_EL2
stp x11, x12, [x0, #CTX_MPAMVPM7_EL2]
ret
-endfunc func el2_sysregs_context_save_mpam
+endfunc el2_sysregs_context_save_mpam
func el2_sysregs_context_restore_mpam
ldr x10, [x0, #CTX_MPAM2_EL2]
@@ -314,45 +306,6 @@
endfunc el2_sysregs_context_restore_mpam
#endif /* ENABLE_MPAM_FOR_LOWER_ELS */
-#if ENABLE_FEAT_FGT
-func el2_sysregs_context_save_fgt
- mrs x13, HDFGRTR_EL2
-#if ENABLE_FEAT_AMUv1
- mrs x14, HAFGRTR_EL2
- stp x13, x14, [x0, #CTX_HDFGRTR_EL2]
-#else
- str x13, [x0, #CTX_HDFGRTR_EL2]
-#endif /* ENABLE_FEAT_AMUv1 */
- mrs x15, HDFGWTR_EL2
- mrs x16, HFGITR_EL2
- stp x15, x16, [x0, #CTX_HDFGWTR_EL2]
-
- mrs x9, HFGRTR_EL2
- mrs x10, HFGWTR_EL2
- stp x9, x10, [x0, #CTX_HFGRTR_EL2]
- ret
-endfunc el2_sysregs_context_save_fgt
-
-func el2_sysregs_context_restore_fgt
- #if ENABLE_FEAT_AMUv1
- ldp x13, x14, [x0, #CTX_HDFGRTR_EL2]
- msr HAFGRTR_EL2, x14
-#else
- ldr x13, [x0, #CTX_HDFGRTR_EL2]
-#endif /* ENABLE_FEAT_AMUv1 */
- msr HDFGRTR_EL2, x13
-
- ldp x15, x16, [x0, #CTX_HDFGWTR_EL2]
- msr HDFGWTR_EL2, x15
- msr HFGITR_EL2, x16
-
- ldp x9, x10, [x0, #CTX_HFGRTR_EL2]
- msr HFGRTR_EL2, x9
- msr HFGWTR_EL2, x10
- ret
-endfunc el2_sysregs_context_restore_fgt
-#endif /* ENABLE_FEAT_FGT */
-
#if ENABLE_FEAT_ECV
func el2_sysregs_context_save_ecv
mrs x11, CNTPOFF_EL2
@@ -475,19 +428,6 @@
endfunc el2_sysregs_context_restore_csv2
#endif /* ENABLE_FEAT_CSV2_2 */
-#if ENABLE_FEAT_HCX
-func el2_sysregs_context_save_hcx
- mrs x14, hcrx_el2
- str x14, [x0, #CTX_HCRX_EL2]
- ret
-endfunc el2_sysregs_context_save_hcx
-
-func el2_sysregs_context_restore_hcx
- ldr x14, [x0, #CTX_HCRX_EL2]
- msr hcrx_el2, x14
- ret
-endfunc el2_sysregs_context_restore_hcx
-#endif /* ENABLE_FEAT_HCX */
#endif /* CTX_INCLUDE_EL2_REGS */
/* ------------------------------------------------------------------
@@ -788,6 +728,15 @@
#endif /* CTX_INCLUDE_FPREGS */
/*
+ * Set SCR_EL3.EA bit to enable SErrors at EL3
+ */
+ .macro enable_serror_at_el3
+ mrs x8, scr_el3
+ orr x8, x8, #SCR_EA_BIT
+ msr scr_el3, x8
+ .endm
+
+ /*
* Set the PSTATE bits not set when the exception was taken as
* described in the AArch64.TakeException() pseudocode function
* in ARM DDI 0487F.c page J1-7635 to a default value.
@@ -917,6 +866,7 @@
*/
func prepare_el3_entry
save_gp_pmcr_pauth_regs
+ enable_serror_at_el3
/*
* Set the PSTATE bits not described in the Aarch64.TakeException
* pseudocode to their default values.
@@ -1064,16 +1014,6 @@
msr spsel, #MODE_SP_ELX
str x17, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
- /* ----------------------------------------------------------
- * Restore SPSR_EL3, ELR_EL3 and SCR_EL3 prior to ERET
- * ----------------------------------------------------------
- */
- ldr x18, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3]
- ldp x16, x17, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
- msr scr_el3, x18
- msr spsr_el3, x16
- msr elr_el3, x17
-
#if IMAGE_BL31
/* ----------------------------------------------------------
* Restore CPTR_EL3.
@@ -1103,17 +1043,6 @@
1:
#endif /* IMAGE_BL31 && DYNAMIC_WORKAROUND_CVE_2018_3639 */
- restore_ptw_el1_sys_regs
-
- /* ----------------------------------------------------------
- * Restore general purpose (including x30), PMCR_EL0 and
- * ARMv8.3-PAuth registers.
- * Exit EL3 via ERET to a lower exception level.
- * ----------------------------------------------------------
- */
- bl restore_gp_pmcr_pauth_regs
- ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
-
#if IMAGE_BL31 && RAS_EXTENSION
/* ----------------------------------------------------------
* Issue Error Synchronization Barrier to synchronize SErrors
@@ -1127,6 +1056,27 @@
dsb sy
#endif /* IMAGE_BL31 && RAS_EXTENSION */
+ /* ----------------------------------------------------------
+ * Restore SPSR_EL3, ELR_EL3 and SCR_EL3 prior to ERET
+ * ----------------------------------------------------------
+ */
+ ldr x18, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3]
+ ldp x16, x17, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
+ msr scr_el3, x18
+ msr spsr_el3, x16
+ msr elr_el3, x17
+
+ restore_ptw_el1_sys_regs
+
+ /* ----------------------------------------------------------
+ * Restore general purpose (including x30), PMCR_EL0 and
+ * ARMv8.3-PAuth registers.
+ * Exit EL3 via ERET to a lower exception level.
+ * ----------------------------------------------------------
+ */
+ bl restore_gp_pmcr_pauth_regs
+ ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
+
#ifdef IMAGE_BL31
str xzr, [sp, #CTX_EL3STATE_OFFSET + CTX_IS_IN_EL3]
#endif /* IMAGE_BL31 */
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index 866ac41..3bcefdb 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -320,9 +320,9 @@
* If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting
* SCR_EL3.HXEn.
*/
-#if ENABLE_FEAT_HCX
- scr_el3 |= SCR_HXEn_BIT;
-#endif
+ if (is_feat_hcx_supported()) {
+ scr_el3 |= SCR_HXEn_BIT;
+ }
/*
* If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS
@@ -359,7 +359,7 @@
&& (GET_M32(ep->spsr) == MODE32_hyp))) {
scr_el3 |= SCR_HCE_BIT;
- if (is_armv8_6_fgt_present()) {
+ if (is_feat_fgt_supported()) {
scr_el3 |= SCR_FGTEN_BIT;
}
@@ -792,6 +792,35 @@
}
#if CTX_INCLUDE_EL2_REGS
+
+static void el2_sysregs_context_save_fgt(el2_sysregs_t *ctx)
+{
+ if (is_feat_fgt_supported()) {
+ write_ctx_reg(ctx, CTX_HDFGRTR_EL2, read_hdfgrtr_el2());
+ if (is_feat_amu_supported()) {
+ write_ctx_reg(ctx, CTX_HAFGRTR_EL2, read_hafgrtr_el2());
+ }
+ write_ctx_reg(ctx, CTX_HDFGWTR_EL2, read_hdfgwtr_el2());
+ write_ctx_reg(ctx, CTX_HFGITR_EL2, read_hfgitr_el2());
+ write_ctx_reg(ctx, CTX_HFGRTR_EL2, read_hfgrtr_el2());
+ write_ctx_reg(ctx, CTX_HFGWTR_EL2, read_hfgwtr_el2());
+ }
+}
+
+static void el2_sysregs_context_restore_fgt(el2_sysregs_t *ctx)
+{
+ if (is_feat_fgt_supported()) {
+ write_hdfgrtr_el2(read_ctx_reg(ctx, CTX_HDFGRTR_EL2));
+ if (is_feat_amu_supported()) {
+ write_hafgrtr_el2(read_ctx_reg(ctx, CTX_HAFGRTR_EL2));
+ }
+ write_hdfgwtr_el2(read_ctx_reg(ctx, CTX_HDFGWTR_EL2));
+ write_hfgitr_el2(read_ctx_reg(ctx, CTX_HFGITR_EL2));
+ write_hfgrtr_el2(read_ctx_reg(ctx, CTX_HFGRTR_EL2));
+ write_hfgwtr_el2(read_ctx_reg(ctx, CTX_HFGWTR_EL2));
+ }
+}
+
/*******************************************************************************
* Save EL2 sysreg context
******************************************************************************/
@@ -823,9 +852,9 @@
#if ENABLE_MPAM_FOR_LOWER_ELS
el2_sysregs_context_save_mpam(el2_sysregs_ctx);
#endif
-#if ENABLE_FEAT_FGT
+
el2_sysregs_context_save_fgt(el2_sysregs_ctx);
-#endif
+
#if ENABLE_FEAT_ECV
el2_sysregs_context_save_ecv(el2_sysregs_ctx);
#endif
@@ -844,9 +873,9 @@
#if ENABLE_FEAT_CSV2_2
el2_sysregs_context_save_csv2(el2_sysregs_ctx);
#endif
-#if ENABLE_FEAT_HCX
- el2_sysregs_context_save_hcx(el2_sysregs_ctx);
-#endif
+ if (is_feat_hcx_supported()) {
+ write_ctx_reg(el2_sysregs_ctx, CTX_HCRX_EL2, read_hcrx_el2());
+ }
}
}
@@ -881,9 +910,9 @@
#if ENABLE_MPAM_FOR_LOWER_ELS
el2_sysregs_context_restore_mpam(el2_sysregs_ctx);
#endif
-#if ENABLE_FEAT_FGT
+
el2_sysregs_context_restore_fgt(el2_sysregs_ctx);
-#endif
+
#if ENABLE_FEAT_ECV
el2_sysregs_context_restore_ecv(el2_sysregs_ctx);
#endif
@@ -902,9 +931,9 @@
#if ENABLE_FEAT_CSV2_2
el2_sysregs_context_restore_csv2(el2_sysregs_ctx);
#endif
-#if ENABLE_FEAT_HCX
- el2_sysregs_context_restore_hcx(el2_sysregs_ctx);
-#endif
+ if (is_feat_hcx_supported()) {
+ write_hcrx_el2(read_ctx_reg(el2_sysregs_ctx, CTX_HCRX_EL2));
+ }
}
}
#endif /* CTX_INCLUDE_EL2_REGS */
diff --git a/lib/gpt_rme/gpt_rme.c b/lib/gpt_rme/gpt_rme.c
index a6e17a3..f5353cb 100644
--- a/lib/gpt_rme/gpt_rme.c
+++ b/lib/gpt_rme/gpt_rme.c
@@ -762,7 +762,7 @@
* Return
* Negative Linux error code in the event of a failure, 0 for success.
*/
-int gpt_init_l0_tables(unsigned int pps, uintptr_t l0_mem_base,
+int gpt_init_l0_tables(gpccr_pps_e pps, uintptr_t l0_mem_base,
size_t l0_mem_size)
{
int ret;
diff --git a/lib/libc/putchar.c b/lib/libc/putchar.c
index 3472b24..340bdd8 100644
--- a/lib/libc/putchar.c
+++ b/lib/libc/putchar.c
@@ -1,14 +1,13 @@
/*
- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2023, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <stdio.h>
-int __putchar(int c)
+#pragma weak putchar
+int putchar(int c)
{
return c;
}
-
-int putchar(int c) __attribute__((weak,alias("__putchar")));
diff --git a/lib/libc/snprintf.c b/lib/libc/snprintf.c
index 6a2f0ba..0e3256c 100644
--- a/lib/libc/snprintf.c
+++ b/lib/libc/snprintf.c
@@ -209,6 +209,7 @@
break;
case 'X':
capitalise = true;
+ /* fallthrough */
case 'x':
unum = get_unum_va_args(args, l_count);
unsigned_num_print(&s, n, &chars_printed,
diff --git a/lib/psa/measured_boot.c b/lib/psa/measured_boot.c
index 61747f2..10c43f1 100644
--- a/lib/psa/measured_boot.c
+++ b/lib/psa/measured_boot.c
@@ -111,6 +111,61 @@
NULL, 0);
}
+psa_status_t rss_measured_boot_read_measurement(uint8_t index,
+ uint8_t *signer_id,
+ size_t signer_id_size,
+ size_t *signer_id_len,
+ uint8_t *version,
+ size_t version_size,
+ size_t *version_len,
+ uint32_t *measurement_algo,
+ uint8_t *sw_type,
+ size_t sw_type_size,
+ size_t *sw_type_len,
+ uint8_t *measurement_value,
+ size_t measurement_value_size,
+ size_t *measurement_value_len,
+ bool *is_locked)
+{
+ psa_status_t status;
+ struct measured_boot_read_iovec_in_t read_iov_in = {
+ .index = index,
+ .sw_type_size = sw_type_size,
+ .version_size = version_size,
+ };
+
+ struct measured_boot_read_iovec_out_t read_iov_out;
+
+ psa_invec in_vec[] = {
+ {.base = &read_iov_in,
+ .len = sizeof(struct measured_boot_read_iovec_in_t)},
+ };
+
+ psa_outvec out_vec[] = {
+ {.base = &read_iov_out,
+ .len = sizeof(struct measured_boot_read_iovec_out_t)},
+ {.base = signer_id, .len = signer_id_size},
+ {.base = measurement_value, .len = measurement_value_size}
+ };
+
+ status = psa_call(RSS_MEASURED_BOOT_HANDLE, RSS_MEASURED_BOOT_READ,
+ in_vec, IOVEC_LEN(in_vec),
+ out_vec, IOVEC_LEN(out_vec));
+
+ if (status == PSA_SUCCESS) {
+ *is_locked = read_iov_out.is_locked;
+ *measurement_algo = read_iov_out.measurement_algo;
+ *sw_type_len = read_iov_out.sw_type_len;
+ *version_len = read_iov_out.version_len;
+ memcpy(sw_type, read_iov_out.sw_type, read_iov_out.sw_type_len);
+ memcpy(version, read_iov_out.version, read_iov_out.version_len);
+ *signer_id_len = out_vec[1].len;
+ *measurement_value_len = out_vec[2].len;
+ }
+
+ return status;
+}
+
#else /* !PLAT_RSS_NOT_SUPPORTED */
psa_status_t
@@ -133,4 +188,24 @@
return PSA_SUCCESS;
}
+
+psa_status_t rss_measured_boot_read_measurement(uint8_t index,
+ uint8_t *signer_id,
+ size_t signer_id_size,
+ size_t *signer_id_len,
+ uint8_t *version,
+ size_t version_size,
+ size_t *version_len,
+ uint32_t *measurement_algo,
+ uint8_t *sw_type,
+ size_t sw_type_size,
+ size_t *sw_type_len,
+ uint8_t *measurement_value,
+ size_t measurement_value_size,
+ size_t *measurement_value_len,
+ bool *is_locked)
+{
+ return PSA_SUCCESS;
+}
+
#endif /* !PLAT_RSS_NOT_SUPPORTED */
diff --git a/lib/psa/measured_boot_private.h b/lib/psa/measured_boot_private.h
index 649c3f6..80d2c19 100644
--- a/lib/psa/measured_boot_private.h
+++ b/lib/psa/measured_boot_private.h
@@ -11,8 +11,24 @@
#include <stdint.h>
/* Measured boot message types that distinguish its services */
+#define RSS_MEASURED_BOOT_READ 1001U
#define RSS_MEASURED_BOOT_EXTEND 1002U
+struct measured_boot_read_iovec_in_t {
+ uint8_t index;
+ uint8_t sw_type_size;
+ uint8_t version_size;
+};
+
+struct measured_boot_read_iovec_out_t {
+ uint8_t is_locked;
+ uint32_t measurement_algo;
+ uint8_t sw_type[SW_TYPE_MAX_SIZE];
+ uint8_t sw_type_len;
+ uint8_t version[VERSION_MAX_SIZE];
+ uint8_t version_len;
+};
+
struct measured_boot_extend_iovec_t {
uint8_t index;
uint8_t lock_measurement;
diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk
index 683d7ac..a66123a 100644
--- a/make_helpers/defaults.mk
+++ b/make_helpers/defaults.mk
@@ -400,9 +400,10 @@
# Enable Link Time Optimization
ENABLE_LTO := 0
-# Build flag to include EL2 registers in cpu context save and restore during
-# S-EL2 firmware entry/exit. This flag is to be used with SPD=spmd option.
-# Default is 0.
+# This option will include EL2 registers in cpu context save and restore during
+# EL2 firmware entry/exit. Internal flag not meant for direct setting.
+# Use SPD=spmd and SPMD_SPM_AT_SEL2=1 or ENABLE_RME=1 to enable
+# CTX_INCLUDE_EL2_REGS.
CTX_INCLUDE_EL2_REGS := 0
# Enable Memory tag extension which is supported for architecture greater
diff --git a/plat/arm/board/common/board_arm_trusted_boot.c b/plat/arm/board/common/board_arm_trusted_boot.c
index 714c444..24d88ee 100644
--- a/plat/arm/board/common/board_arm_trusted_boot.c
+++ b/plat/arm/board/common/board_arm_trusted_boot.c
@@ -47,7 +47,8 @@
#pragma weak plat_get_nv_ctr
#pragma weak plat_set_nv_ctr
-extern unsigned char arm_rotpk_header[], arm_rotpk_hash_end[];
+extern unsigned char arm_rotpk_header[], arm_rotpk_key[], arm_rotpk_hash_end[],
+ arm_rotpk_key_end[];
#if (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_REGS_ID) || ARM_CRYPTOCELL_INTEG
static unsigned char rotpk_hash_der[ARM_ROTPK_HEADER_LEN + ARM_ROTPK_HASH_LEN];
@@ -93,16 +94,20 @@
#endif
#if (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_RSA_ID) || \
- (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_ECDSA_ID)
-/*
- * Return development ROTPK hash generated from ROT_KEY.
- */
+ (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_ECDSA_ID) || \
+ (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_FULL_DEV_RSA_KEY_ID)
int arm_get_rotpk_info_dev(void **key_ptr, unsigned int *key_len,
unsigned int *flags)
{
- *key_ptr = arm_rotpk_header;
- *key_len = arm_rotpk_hash_end - arm_rotpk_header;
- *flags = ROTPK_IS_HASH;
+ if (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_FULL_DEV_RSA_KEY_ID) {
+ *key_ptr = arm_rotpk_key;
+ *key_len = arm_rotpk_key_end - arm_rotpk_key;
+ *flags = 0;
+ } else {
+ *key_ptr = arm_rotpk_header;
+ *key_len = arm_rotpk_hash_end - arm_rotpk_header;
+ *flags = ROTPK_IS_HASH;
+ }
return 0;
}
#endif
@@ -130,7 +135,7 @@
#endif
/*
- * Wrapper function for most Arm platforms to get ROTPK hash.
+ * Wrapper function for most Arm platforms to get ROTPK info.
*/
static int get_rotpk_info(void **key_ptr, unsigned int *key_len,
unsigned int *flags)
@@ -140,7 +145,8 @@
#else
#if (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_RSA_ID) || \
- (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_ECDSA_ID)
+ (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_ECDSA_ID) || \
+ (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_FULL_DEV_RSA_KEY_ID)
return arm_get_rotpk_info_dev(key_ptr, key_len, flags);
#elif (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_REGS_ID)
return arm_get_rotpk_info_regs(key_ptr, key_len, flags);
diff --git a/plat/arm/board/common/board_common.mk b/plat/arm/board/common/board_common.mk
index 1d0eb13..d73c2e3 100644
--- a/plat/arm/board/common/board_common.mk
+++ b/plat/arm/board/common/board_common.mk
@@ -12,6 +12,7 @@
BL2_SOURCES += drivers/cfi/v2m/v2m_flash.c
ifneq (${TRUSTED_BOARD_BOOT},0)
+ARM_ROTPK_S = plat/arm/board/common/rotpk/arm_dev_rotpk.S
ifneq (${ARM_CRYPTOCELL_INTEG}, 1)
# ROTPK hash location
ifeq (${ARM_ROTPK_LOCATION}, regs)
@@ -32,6 +33,12 @@
$(BUILD_PLAT)/bl2/arm_dev_rotpk.o : $(ARM_ROTPK_HASH)
$(warning Development keys support for FVP is deprecated. Use `regs` \
option instead)
+else ifeq (${ARM_ROTPK_LOCATION}, devel_full_dev_rsa_key)
+ CRYPTO_ALG=rsa
+ ARM_ROTPK_LOCATION_ID = ARM_ROTPK_DEVEL_FULL_DEV_RSA_KEY_ID
+ ARM_ROTPK_S = plat/arm/board/common/rotpk/arm_full_dev_rsa_rotpk.S
+$(warning Development keys support for FVP is deprecated. Use `regs` \
+option instead)
else
$(error "Unsupported ARM_ROTPK_LOCATION value")
endif
@@ -67,9 +74,9 @@
NTFW_NVCTR_VAL ?= 0
endif
BL1_SOURCES += plat/arm/board/common/board_arm_trusted_boot.c \
- plat/arm/board/common/rotpk/arm_dev_rotpk.S
+ ${ARM_ROTPK_S}
BL2_SOURCES += plat/arm/board/common/board_arm_trusted_boot.c \
- plat/arm/board/common/rotpk/arm_dev_rotpk.S
+ ${ARM_ROTPK_S}
# Allows platform code to provide implementation variants depending on the
# selected chain of trust.
diff --git a/plat/arm/board/common/rotpk/arm_dev_rotpk.S b/plat/arm/board/common/rotpk/arm_dev_rotpk.S
index 06e2a06..a7fadf6 100644
--- a/plat/arm/board/common/rotpk/arm_dev_rotpk.S
+++ b/plat/arm/board/common/rotpk/arm_dev_rotpk.S
@@ -14,7 +14,6 @@
#endif
.global arm_rotpk_header
- .global arm_rotpk_header_end
.section .rodata.arm_rotpk_hash, "a"
arm_rotpk_header:
diff --git a/plat/arm/board/common/rotpk/arm_full_dev_rsa_rotpk.S b/plat/arm/board/common/rotpk/arm_full_dev_rsa_rotpk.S
new file mode 100644
index 0000000..4bb04dc
--- /dev/null
+++ b/plat/arm/board/common/rotpk/arm_full_dev_rsa_rotpk.S
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2022, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* corstone1000 platform provides custom values for the macros defined in
+ * arm_def.h , so only platform_def.h needs to be included
+ */
+#if !defined(TARGET_PLATFORM_FVP) && !defined(TARGET_PLATFORM_FPGA)
+#include "plat/arm/common/arm_def.h"
+#else
+#include <platform_def.h>
+#endif
+
+ .global arm_rotpk_key
+ .global arm_rotpk_key_end
+
+ .section .rodata.arm_rotpk_key, "a"
+
+arm_rotpk_key:
+ .byte 0x30, 0x82, 0x01, 0x22, 0x30, 0x0D, 0x06, 0x09, 0x2A, 0x86, 0x48, 0x86, 0xF7, 0x0D, 0x01, 0x01, 0x01
+ .byte 0x05, 0x00, 0x03, 0x82, 0x01, 0x0F, 0x00, 0x30, 0x82, 0x01, 0x0A, 0x02, 0x82, 0x01, 0x01
+ .byte 0x00, 0xCB, 0x2C, 0x60, 0xD5, 0x8D, 0x63, 0xD4, 0x07, 0x79, 0x7E, 0xC7, 0x16, 0x96, 0xBD, 0x4D, 0x24, 0x4E, 0xAC, 0x86, 0xE6, 0xB7, 0x71, 0xE3, 0xC5, 0x54, 0x0B, 0xE7, 0x14, 0x1C, 0xBD, 0x29, 0x1A, 0xC1, 0x3F, 0x7A, 0xB6, 0x02, 0xAA, 0xAB, 0x36, 0xC4, 0xD9, 0x36, 0x69, 0x6C, 0xE2, 0x65, 0xC3, 0x9B, 0xB1, 0xBF, 0x3D, 0xA8, 0x56, 0x26, 0xCB, 0xFD, 0x04, 0x01, 0xBA, 0xAC, 0x3E, 0x54, 0x32, 0xCA, 0x79, 0x5E, 0xBB, 0xB2, 0x05, 0xEA, 0x06, 0x58, 0xF2, 0x74, 0xBA, 0xE1, 0xF4, 0x87, 0xC0, 0x19, 0x0A, 0x1F, 0x66, 0x07, 0x77, 0x84, 0x83, 0xA1, 0x1C, 0xEF, 0xFF, 0x28, 0x59, 0xE7, 0xC3, 0x68, 0x7D, 0x26, 0x20, 0x43, 0xEB, 0x56, 0x63, 0xF3, 0x39, 0x31, 0xD8, 0x2B, 0x51, 0xA9, 0xBC, 0x4F, 0xD0, 0xF6, 0xDE, 0x95, 0xDC, 0x5F, 0x5B, 0xC1, 0xED, 0x90, 0x6F, 0xEC, 0x28, 0x91, 0x7E, 0x17, 0xED, 0x78, 0x90, 0xF4, 0x60, 0xA7, 0xC4, 0xC7, 0x4F, 0x50, 0xED, 0x5D, 0x13, 0x3A, 0x21, 0x2B, 0x70, 0xC5, 0x61, 0x7B, 0x08, 0x21, 0x65, 0x3A, 0xCD, 0x82, 0x56, 0x8C, 0x7A, 0x47, 0xAC, 0x89, 0xE8, 0xA5, 0x48, 0x48
+ .byte 0x31, 0xD9, 0x1D, 0x46, 0xE5, 0x85, 0x86, 0x98, 0xA0, 0xE5, 0xC0, 0xA6, 0x6A, 0xBD, 0x07, 0xE4, 0x92, 0x57, 0x61, 0x07, 0x8F, 0x7D, 0x5A, 0x4D, 0xCA, 0xAE, 0x36, 0xB9, 0x56, 0x04, 0x10, 0xF2, 0x6C, 0xBE, 0xF6, 0x3B, 0x6C, 0x80, 0x3E, 0xBE , 0x0E, 0xA3, 0x4D , 0xC7 , 0xD4, 0x7E , 0xA7 , 0x49, 0xD4, 0xF2, 0xD2, 0xBC, 0xCF, 0x30, 0xA8, 0xE7, 0x74, 0x8F, 0x64, 0xDF, 0xBC, 0x5C, 0x47, 0x68, 0xCC, 0x40, 0x4C, 0xF8, 0x83, 0xCC, 0xCB, 0x40, 0x35, 0x04, 0x60, 0xCA, 0xB3, 0xA4, 0x17, 0x9F, 0x03, 0xCA, 0x1D, 0x5A, 0xFA, 0xD1, 0xAF, 0x21, 0x57, 0x10, 0xD3, 0x02, 0x03, 0x01, 0x00, 0x01
+
+arm_rotpk_key_end:
+
+.if ARM_ROTPK_KEY_LEN != arm_rotpk_key_end - arm_rotpk_key
+.error "Invalid ROTPK length."
+.endif
+
diff --git a/plat/arm/board/fvp/fvp_bl2_measured_boot.c b/plat/arm/board/fvp/fvp_bl2_measured_boot.c
index e938e24..29b6619 100644
--- a/plat/arm/board/fvp/fvp_bl2_measured_boot.c
+++ b/plat/arm/board/fvp/fvp_bl2_measured_boot.c
@@ -125,7 +125,8 @@
/* Calculate image hash and record data in Event Log */
int err = event_log_measure_and_record((uintptr_t)base, (uint32_t)size,
- critical_data_id);
+ critical_data_id,
+ fvp_event_log_metadata);
if (err != 0) {
ERROR("%s%s critical data (%i)\n",
"Failed to ", "record", err);
diff --git a/plat/arm/board/fvp/fvp_common.c b/plat/arm/board/fvp/fvp_common.c
index f8463f1..f5d9940 100644
--- a/plat/arm/board/fvp/fvp_common.c
+++ b/plat/arm/board/fvp/fvp_common.c
@@ -536,6 +536,7 @@
assert(manifest != NULL);
manifest->version = RMMD_MANIFEST_VERSION;
+ manifest->padding = 0U; /* RES0 */
manifest->plat_data = (uintptr_t)NULL;
return 0;
diff --git a/plat/arm/board/fvp/fvp_common_measured_boot.c b/plat/arm/board/fvp/fvp_common_measured_boot.c
index 93aa055..b5b8f10 100644
--- a/plat/arm/board/fvp/fvp_common_measured_boot.c
+++ b/plat/arm/board/fvp/fvp_common_measured_boot.c
@@ -16,11 +16,6 @@
extern event_log_metadata_t fvp_event_log_metadata[];
extern struct rss_mboot_metadata fvp_rss_mboot_metadata[];
-const event_log_metadata_t *plat_event_log_get_metadata(void)
-{
- return fvp_event_log_metadata;
-}
-
struct rss_mboot_metadata *plat_rss_mboot_get_metadata(void)
{
return fvp_rss_mboot_metadata;
@@ -34,7 +29,8 @@
/* Calculate image hash and record data in Event Log */
err = event_log_measure_and_record(image_data->image_base,
image_data->image_size,
- image_id);
+ image_id,
+ fvp_event_log_metadata);
if (err != 0) {
ERROR("%s%s image id %u (%i)\n",
"Failed to ", "record in event log", image_id, err);
diff --git a/plat/arm/board/fvp/fvp_sync_traps.c b/plat/arm/board/fvp/fvp_sync_traps.c
new file mode 100644
index 0000000..91240f7
--- /dev/null
+++ b/plat/arm/board/fvp/fvp_sync_traps.c
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2022, ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file just contains demonstration code, to "handle" RNG traps.
+ */
+
+#include <stdbool.h>
+
+#include <arch.h>
+#include <arch_helpers.h>
+#include <bl31/sync_handle.h>
+#include <context.h>
+
+/*
+ * SCR_EL3.SCR_TRNDR_BIT also affects execution in EL3, so allow to disable
+ * the trap temporarily.
+ */
+static void enable_rng_trap(bool enable)
+{
+ uint64_t scr_el3 = read_scr_el3();
+
+ if (enable) {
+ scr_el3 |= SCR_TRNDR_BIT;
+ } else {
+ scr_el3 &= ~SCR_TRNDR_BIT;
+ }
+
+ write_scr_el3(scr_el3);
+ isb();
+}
+
+/*
+ * This emulation code here is not very meaningful: enabling the RNG
+ * trap typically happens for a reason, so just calling the actual
+ * hardware instructions might not be useful or even possible.
+ */
+int plat_handle_rng_trap(uint64_t esr_el3, cpu_context_t *ctx)
+{
+ /* extract the target register number from the exception syndrome */
+ unsigned int rt = get_sysreg_iss_rt(esr_el3);
+
+ /* ignore XZR accesses and writes to the register */
+ if (rt == 31 || is_sysreg_iss_write(esr_el3)) {
+ return TRAP_RET_CONTINUE;
+ }
+
+ enable_rng_trap(false);
+ if ((esr_el3 & ISS_SYSREG_OPCODE_MASK) == ISS_SYSREG_OPCODE_RNDR) {
+ ctx->gpregs_ctx.ctx_regs[rt] = read_rndr();
+ } else {
+ ctx->gpregs_ctx.ctx_regs[rt] = read_rndrrs();
+ }
+ enable_rng_trap(true);
+
+ /*
+ * We successfully handled the trap, continue with the next
+ * instruction.
+ */
+ return TRAP_RET_CONTINUE;
+}
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index 51ba035..efbf68f 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -198,6 +198,10 @@
plat/arm/board/fvp/fvp_realm_attest_key.c
endif
+ifeq (${ENABLE_FEAT_RNG_TRAP},1)
+BL31_SOURCES += plat/arm/board/fvp/fvp_sync_traps.c
+endif
+
ifeq (${BL2_AT_EL3},1)
BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \
plat/arm/board/fvp/fvp_bl2_el3_setup.c \
@@ -459,6 +463,10 @@
# enable trace filter control registers access to NS by default
ENABLE_TRF_FOR_NS := 1
+# Linux relies on EL3 enablement if those features are present
+ENABLE_FEAT_FGT := 2
+ENABLE_FEAT_HCX := 2
+
ifeq (${SPMC_AT_EL3}, 1)
PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_el3_spmc.c
endif
diff --git a/plat/arm/board/juno/juno_topology.c b/plat/arm/board/juno/juno_topology.c
index 075f512..768741e 100644
--- a/plat/arm/board/juno/juno_topology.c
+++ b/plat/arm/board/juno/juno_topology.c
@@ -20,7 +20,7 @@
.ring_doorbell = &mhu_ring_doorbell,
};
-scmi_channel_plat_info_t *plat_css_get_scmi_info(int channel_id)
+scmi_channel_plat_info_t *plat_css_get_scmi_info(unsigned int channel_id)
{
return &juno_scmi_plat_info;
}
diff --git a/plat/arm/board/morello/morello_bl31_setup.c b/plat/arm/board/morello/morello_bl31_setup.c
index a044212..e04587d 100644
--- a/plat/arm/board/morello/morello_bl31_setup.c
+++ b/plat/arm/board/morello/morello_bl31_setup.c
@@ -19,7 +19,7 @@
.ring_doorbell = &mhu_ring_doorbell
};
-scmi_channel_plat_info_t *plat_css_get_scmi_info(int channel_id)
+scmi_channel_plat_info_t *plat_css_get_scmi_info(unsigned int channel_id)
{
return &morello_scmi_plat_info;
}
diff --git a/plat/arm/board/n1sdp/n1sdp_bl31_setup.c b/plat/arm/board/n1sdp/n1sdp_bl31_setup.c
index 5e897fe..ad6c1f8 100644
--- a/plat/arm/board/n1sdp/n1sdp_bl31_setup.c
+++ b/plat/arm/board/n1sdp/n1sdp_bl31_setup.c
@@ -62,7 +62,7 @@
0
};
-scmi_channel_plat_info_t *plat_css_get_scmi_info(int channel_id)
+scmi_channel_plat_info_t *plat_css_get_scmi_info(unsigned int channel_id)
{
return &n1sdp_scmi_plat_info;
}
diff --git a/plat/arm/board/rdn1edge/rdn1edge_plat.c b/plat/arm/board/rdn1edge/rdn1edge_plat.c
index 1dbbf26..045c316 100644
--- a/plat/arm/board/rdn1edge/rdn1edge_plat.c
+++ b/plat/arm/board/rdn1edge/rdn1edge_plat.c
@@ -65,7 +65,8 @@
#if defined(IMAGE_BL31)
void bl31_platform_setup(void)
{
- int i, ret;
+ unsigned int i;
+ int ret;
if (plat_arm_sgi_get_multi_chip_mode() == 0 && CSS_SGI_CHIP_COUNT > 1) {
ERROR("Chip Count is set to %d but multi-chip mode not enabled\n",
diff --git a/plat/arm/board/rdn2/include/platform_def.h b/plat/arm/board/rdn2/include/platform_def.h
index 3474016..8e63de5 100644
--- a/plat/arm/board/rdn2/include/platform_def.h
+++ b/plat/arm/board/rdn2/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020-2023, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -92,6 +92,8 @@
#if (CSS_SGI_PLATFORM_VARIANT == 1)
#define PLAT_ARM_GICR_BASE UL(0x30100000)
+#elif (CSS_SGI_PLATFORM_VARIANT == 3)
+#define PLAT_ARM_GICR_BASE UL(0x30300000)
#else
#define PLAT_ARM_GICR_BASE UL(0x301C0000)
#endif
diff --git a/plat/arm/board/rdn2/platform.mk b/plat/arm/board/rdn2/platform.mk
index 7492fe5..b30e3fc 100644
--- a/plat/arm/board/rdn2/platform.mk
+++ b/plat/arm/board/rdn2/platform.mk
@@ -1,13 +1,13 @@
-# Copyright (c) 2020-2022, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2020-2023, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
-RD_N2_VARIANTS := 0 1 2
+RD_N2_VARIANTS := 0 1 2 3
ifneq ($(CSS_SGI_PLATFORM_VARIANT),\
$(filter $(CSS_SGI_PLATFORM_VARIANT),$(RD_N2_VARIANTS)))
- $(error "CSS_SGI_PLATFORM_VARIANT for RD-N2 should be 0, 1 or 2, currently set \
- to ${CSS_SGI_PLATFORM_VARIANT}.")
+ $(error "CSS_SGI_PLATFORM_VARIANT for RD-N2 should be 0, 1, 2 or 3, currently \
+ set to ${CSS_SGI_PLATFORM_VARIANT}.")
endif
$(eval $(call CREATE_SEQ,SEQ,4))
diff --git a/plat/arm/board/rdn2/rdn2_topology.c b/plat/arm/board/rdn2/rdn2_topology.c
index 89300f8..24acc4d 100644
--- a/plat/arm/board/rdn2/rdn2_topology.c
+++ b/plat/arm/board/rdn2/rdn2_topology.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020-2023, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -16,19 +16,22 @@
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
-#if (CSS_SGI_PLATFORM_VARIANT != 2 || (CSS_SGI_PLATFORM_VARIANT == 2 && CSS_SGI_CHIP_COUNT > 1))
+#if (PLAT_ARM_CLUSTER_COUNT > 4 || \
+ (CSS_SGI_PLATFORM_VARIANT == 2 && CSS_SGI_CHIP_COUNT > 1))
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
#endif
-#if (CSS_SGI_PLATFORM_VARIANT == 0 || (CSS_SGI_PLATFORM_VARIANT == 2 && CSS_SGI_CHIP_COUNT > 2))
+#if (PLAT_ARM_CLUSTER_COUNT > 8 || \
+ (CSS_SGI_PLATFORM_VARIANT == 2 && CSS_SGI_CHIP_COUNT > 2))
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
#endif
-#if (CSS_SGI_PLATFORM_VARIANT == 0 || (CSS_SGI_PLATFORM_VARIANT == 2 && CSS_SGI_CHIP_COUNT > 3))
+#if (PLAT_ARM_CLUSTER_COUNT > 8 || \
+ (CSS_SGI_PLATFORM_VARIANT == 2 && CSS_SGI_CHIP_COUNT > 3))
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
@@ -83,7 +86,7 @@
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x5)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x6)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x7)),
-#if (CSS_SGI_PLATFORM_VARIANT == 0)
+#if (PLAT_ARM_CLUSTER_COUNT > 8)
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x8)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x9)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xA)),
diff --git a/plat/arm/board/tc/include/platform_def.h b/plat/arm/board/tc/include/platform_def.h
index bc4f254..a3b7839 100644
--- a/plat/arm/board/tc/include/platform_def.h
+++ b/plat/arm/board/tc/include/platform_def.h
@@ -25,13 +25,28 @@
* The top 16MB of ARM_DRAM1 is configured as secure access only using the TZC,
* its base is ARM_AP_TZC_DRAM1_BASE.
*
- * Reserve 32MB below ARM_AP_TZC_DRAM1_BASE for:
+ * Reserve 96 MB below ARM_AP_TZC_DRAM1_BASE for:
* - BL32_BASE when SPD_spmd is enabled
- * - Region to load Trusted OS
+ * - Region to load secure partitions
+ *
+ *
+ * 0xF900_0000 ------------------ TC_TZC_DRAM1_BASE
+ * | |
+ * | SPMC |
+ * | SP |
+ * | (96MB) |
+ * 0xFF00_0000 ------------------ ARM_AP_TZC_DRAM1_BASE
+ * | AP |
+ * | EL3 Monitor |
+ * | SCP |
+ * | (16MB) |
+ * 0xFFFF_FFFF ------------------
+ *
+ *
*/
#define TC_TZC_DRAM1_BASE (ARM_AP_TZC_DRAM1_BASE - \
TC_TZC_DRAM1_SIZE)
-#define TC_TZC_DRAM1_SIZE UL(0x02000000) /* 32 MB */
+#define TC_TZC_DRAM1_SIZE 96 * SZ_1M /* 96 MB */
#define TC_TZC_DRAM1_END (TC_TZC_DRAM1_BASE + \
TC_TZC_DRAM1_SIZE - 1)
@@ -68,7 +83,9 @@
* max size of BL32 image.
*/
#if defined(SPD_spmd)
-#define PLAT_ARM_SPMC_BASE TC_TZC_DRAM1_BASE
+#define TC_EL2SPMC_LOAD_ADDR (TC_TZC_DRAM1_BASE + 0x04000000)
+
+#define PLAT_ARM_SPMC_BASE TC_EL2SPMC_LOAD_ADDR
#define PLAT_ARM_SPMC_SIZE UL(0x200000) /* 2 MB */
#endif
@@ -101,7 +118,7 @@
* PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size
* plus a little space for growth.
*/
-#define PLAT_ARM_MAX_BL1_RW_SIZE 0xD000
+#define PLAT_ARM_MAX_BL1_RW_SIZE 0x12000
/*
* PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page
@@ -129,7 +146,7 @@
* BL2 and BL1-RW. Current size is considering that TRUSTED_BOARD_BOOT and
* MEASURED_BOOT is enabled.
*/
-#define PLAT_ARM_MAX_BL31_SIZE 0x47000
+#define PLAT_ARM_MAX_BL31_SIZE 0x60000
/*
* Size of cacheable stacks
@@ -152,7 +169,7 @@
# if SPM_MM
# define PLATFORM_STACK_SIZE 0x500
# else
-# define PLATFORM_STACK_SIZE 0x400
+# define PLATFORM_STACK_SIZE 0xa00
# endif
#elif defined(IMAGE_BL32)
# define PLATFORM_STACK_SIZE 0x440
@@ -276,8 +293,8 @@
(TZC_REGION_ACCESS_RDWR(TZC_NSAID_DEFAULT))
/*
- * The first region below, TC_TZC_DRAM1_BASE (0xfd000000) to
- * ARM_SCP_TZC_DRAM1_END (0xffffffff) will mark the last 48 MB of DRAM as
+ * The first region below, TC_TZC_DRAM1_BASE (0xf9000000) to
+ * ARM_SCP_TZC_DRAM1_END (0xffffffff) will mark the last 112 MB of DRAM as
* secure. The second and third regions gives non secure access to rest of DRAM.
*/
#define TC_TZC_REGIONS_DEF \
diff --git a/plat/arm/board/tc/include/tc_plat.h b/plat/arm/board/tc/include/tc_plat.h
index 28c0308..f7ce2fe 100644
--- a/plat/arm/board/tc/include/tc_plat.h
+++ b/plat/arm/board/tc/include/tc_plat.h
@@ -9,4 +9,8 @@
void tc_bl31_common_platform_setup(void);
+#ifdef PLATFORM_TEST
+void run_platform_tests(void);
+#endif
+
#endif /* TC_PLAT_H */
diff --git a/plat/arm/board/tc/plat_def_fip_uuid.h b/plat/arm/board/tc/plat_def_fip_uuid.h
new file mode 100644
index 0000000..631f7c9
--- /dev/null
+++ b/plat/arm/board/tc/plat_def_fip_uuid.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2022, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef __PLAT_DEF_FIP_UUID__
+#define __PLAT_DEF_FIP_UUID__
+
+#include "uuid.h"
+
+#define UUID_RSS_FIRMWARE_BL1_2 \
+ {{0x0a, 0xa5, 0xb1, 0xbe}, {0xe7, 0x84}, {0x41, 0xc5}, 0x81, 0xb8, {0x4a, 0x41, 0xcb, 0x4a, 0xd2, 0xdf}}
+
+#define UUID_RSS_FIRMWARE_BL2 \
+ {{0xa3, 0xb3, 0xb3, 0x0d}, {0xeb, 0xc9}, {0x40, 0x48}, 0xb4, 0x80, {0x15, 0x53, 0x61, 0xc1, 0x70, 0x48}}
+
+#define UUID_RSS_FIRMWARE_SCP_BL1 \
+ {{0xbf, 0xd5, 0x09, 0x8d}, {0xa7, 0x07}, {0x4f, 0x15}, 0x89, 0x1c, {0x37, 0x22, 0x10, 0xcb, 0x51, 0xe2}}
+
+#define UUID_RSS_FIRMWARE_AP_BL1 \
+ {{0x12, 0x4c, 0x50, 0xe0}, {0xf2, 0xda}, {0x45, 0xe9}, 0x85, 0xc8, {0xda, 0xd9, 0x60, 0x9b, 0x7a, 0x11}}
+
+#define UUID_RSS_FIRMWARE_NS \
+ {{0x8d, 0x95, 0x9f, 0x72}, {0xb8, 0xb1}, {0x42, 0x11}, 0x9a, 0xe6, {0x4b, 0x80, 0x97, 0x47, 0x5a, 0xd9}}
+
+#define UUID_RSS_FIRMWARE_S \
+ {{0x22, 0xea, 0x33, 0x85}, {0xf8, 0x6e}, {0x47, 0x93}, 0x96, 0x8a, {0x2f, 0xe3, 0xdd, 0x50, 0x33, 0xcc}}
+
+#define UUID_RSS_SIC_TABLES_NS \
+ {{0xd9, 0x10, 0x00, 0x72}, {0x6a, 0x28}, {0x4b, 0xec}, 0xb0, 0xd6, {0x8c, 0xed, 0xc4, 0x15, 0x7c, 0xe0}}
+
+#define UUID_RSS_SIC_TABLES_S \
+ {{0xc7, 0x38, 0xd0, 0xde}, {0x8c, 0x26}, {0x48, 0x51}, 0x93, 0x36, {0xf3, 0xdb, 0xe2, 0x96, 0x65, 0x18}}
+
+#endif /* __PLAT_DEF_FIP_UUID__ */
diff --git a/plat/arm/board/tc/plat_def_uuid_config.c b/plat/arm/board/tc/plat_def_uuid_config.c
new file mode 100644
index 0000000..903310b
--- /dev/null
+++ b/plat/arm/board/tc/plat_def_uuid_config.c
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2022, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <stddef.h>
+
+#include <firmware_image_package.h>
+
+#include "tbbr_config.h"
+
+toc_entry_t plat_def_toc_entries[] = {
+ {
+ .name = "RSS Firmware BL1_2 image",
+ .uuid = UUID_RSS_FIRMWARE_BL1_2,
+ .cmdline_name = "rss-bl1_2"
+ },
+ {
+ .name = "RSS Firmware BL2 image",
+ .uuid = UUID_RSS_FIRMWARE_BL2,
+ .cmdline_name = "rss-bl2"
+ },
+ {
+ .name = "RSS Firmware SCP BL1 image",
+ .uuid = UUID_RSS_FIRMWARE_SCP_BL1,
+ .cmdline_name = "rss-scp-bl1"
+ },
+ {
+ .name = "RSS Firmware AP BL1 image",
+ .uuid = UUID_RSS_FIRMWARE_AP_BL1,
+ .cmdline_name = "rss-ap-bl1"
+ },
+ {
+ .name = "RSS Firmware non-secure image",
+ .uuid = UUID_RSS_FIRMWARE_NS,
+ .cmdline_name = "rss-ns"
+ },
+ {
+ .name = "RSS Firmware secure image",
+ .uuid = UUID_RSS_FIRMWARE_S,
+ .cmdline_name = "rss-s"
+ },
+ {
+ .name = "RSS Firmware non-secure SIC tables",
+ .uuid = UUID_RSS_SIC_TABLES_NS,
+ .cmdline_name = "rss-sic-tables-ns"
+ },
+ {
+ .name = "RSS Firmware secure SIC tables",
+ .uuid = UUID_RSS_SIC_TABLES_S,
+ .cmdline_name = "rss-sic-tables-s"
+ },
+
+ {
+ .name = NULL,
+ .uuid = { {0} },
+ .cmdline_name = NULL,
+ }
+};
diff --git a/plat/arm/board/tc/plat_fiptool.mk b/plat/arm/board/tc/plat_fiptool.mk
new file mode 100644
index 0000000..0e13556
--- /dev/null
+++ b/plat/arm/board/tc/plat_fiptool.mk
@@ -0,0 +1,33 @@
+#
+# Copyright (c) 2021, NXP. All rights reserved.
+# Copyright (c) 2022, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# Name of the platform defined source file name,
+# which contains platform defined UUID entries populated
+# in the plat_def_toc_entries[].
+PLAT_DEF_UUID_CONFIG_FILE_NAME := plat_def_uuid_config
+
+PLAT_DEF_UUID_CONFIG_FILE_PATH := ../../plat/arm/board/tc
+
+PLAT_DEF_UUID := yes
+PLAT_DEF_UUID_OID_CONFIG_PATH := ../../plat/arm/board/tc
+
+
+INCLUDE_PATHS += -I${PLAT_DEF_UUID_OID_CONFIG_PATH} \
+ -I./
+# Clean the stale object file.
+$(shell rm ${PLAT_DEF_UUID_CONFIG_FILE_PATH}/${PLAT_DEF_UUID_CONFIG_FILE_NAME}.o)
+
+ifeq (${PLAT_DEF_OID},yes)
+HOSTCCFLAGS += -DPLAT_DEF_OID
+endif
+
+ifeq (${PLAT_DEF_UUID},yes)
+HOSTCCFLAGS += -DPLAT_DEF_FIP_UUID
+PLAT_OBJECTS += ${PLAT_DEF_UUID_CONFIG_FILE_PATH}/${PLAT_DEF_UUID_CONFIG_FILE_NAME}.o
+endif
+
+OBJECTS += ${PLAT_OBJECTS}
diff --git a/plat/arm/board/tc/plat_tc_mbedtls_config.h b/plat/arm/board/tc/plat_tc_mbedtls_config.h
new file mode 100644
index 0000000..d776b63
--- /dev/null
+++ b/plat/arm/board/tc/plat_tc_mbedtls_config.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2022, Arm Ltd. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLAT_TC_MBEDTLS_CONFIG_H
+#define PLAT_TC_MBEDTLS_CONFIG_H
+
+#include <mbedtls_config.h>
+#include <export/lib/utils_def_exp.h>
+
+#ifndef TF_MBEDTLS_HEAP_SIZE
+#error TF_MBEDTLS_HEAP_SIZE is not defined
+#else
+#define PLATFORM_TEST_MIN_MBEDTLS_HEAP_SIZE (8 * 1024)
+/* Only change heap size if it is less then the minimum required. */
+#if TF_MBEDTLS_HEAP_SIZE < PLATFORM_TEST_MIN_MBEDTLS_HEAP_SIZE
+#undef TF_MBEDTLS_HEAP_SIZE
+#define TF_MBEDTLS_HEAP_SIZE PLATFORM_TEST_MIN_MBEDTLS_HEAP_SIZE
+#endif
+#endif
+
+#define MBEDTLS_PSA_CRYPTO_C
+#define MBEDTLS_HMAC_DRBG_C
+#define MBEDTLS_ENTROPY_C
+#define MBEDTLS_NO_DEFAULT_ENTROPY_SOURCES
+#define MBEDTLS_NO_PLATFORM_ENTROPY
+#define MBEDTLS_TEST_NULL_ENTROPY
+#define MBEDTLS_ECP_C
+#define MBEDTLS_ECP_DP_SECP384R1_ENABLED
+
+#endif /* PLAT_TC_MBEDTLS_CONFIG_H */
diff --git a/plat/arm/board/tc/platform.mk b/plat/arm/board/tc/platform.mk
index 37ba229..2182477 100644
--- a/plat/arm/board/tc/platform.mk
+++ b/plat/arm/board/tc/platform.mk
@@ -53,6 +53,9 @@
# enable trace filter control registers access to NS by default
ENABLE_TRF_FOR_NS := 1
+# Enable RSS-required FIP UUIDs
+$(shell cp plat/arm/board/tc/plat_fiptool.mk ${PLAT_DIR})
+
# Include GICv3 driver files
include drivers/arm/gic/v3/gicv3.mk
@@ -193,6 +196,11 @@
endif
+# Add this include as first, before arm_common.mk. This is necessary because
+# arm_common.mk builds Mbed TLS, and platform_test.mk can change the list of
+# Mbed TLS files that are to be compiled (LIBMBEDTLS_SRCS).
+include plat/arm/board/tc/platform_test.mk
+
include plat/arm/common/arm_common.mk
include plat/arm/css/common/css_common.mk
include plat/arm/soc/common/soc_css.mk
diff --git a/plat/arm/board/tc/platform_test.mk b/plat/arm/board/tc/platform_test.mk
new file mode 100644
index 0000000..c2ee69e
--- /dev/null
+++ b/plat/arm/board/tc/platform_test.mk
@@ -0,0 +1,80 @@
+# Copyright (c) 2022, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+ifeq (${PLATFORM_TEST},1)
+
+ # The variables need to be set to compile the platform test:
+ ifeq (${TF_M_TESTS_PATH},)
+ # Example: ../rss/tf-m-tests
+ $(error Error: TF_M_TESTS_PATH not set)
+ endif
+ ifeq (${TF_M_EXTRAS_PATH},)
+ # Example: ../rss/tf-m-extras
+ $(error Error: TF_M_EXTRAS_PATH not set)
+ endif
+ ifeq (${MEASUREMENT_VALUE_SIZE},)
+ MEASUREMENT_VALUE_SIZE := 32
+ endif
+ ifeq (${MEASURED_BOOT_HASH_ALG},)
+ MEASURED_BOOT_HASH_ALG := "PSA_ALG_SHA_256"
+ endif
+
+ DELEGATED_ATTEST_TESTS_PATH = $(TF_M_EXTRAS_PATH)/partitions/delegated_attestation/test
+ MEASURED_BOOT_TESTS_PATH = $(TF_M_EXTRAS_PATH)/partitions/measured_boot/test
+
+ MBEDTLS_CONFIG_FILE = "<plat_tc_mbedtls_config.h>"
+
+ LIBMBEDTLS_SRCS += $(addprefix ${MBEDTLS_DIR}/library/, \
+ entropy.c \
+ entropy_poll.c \
+ hmac_drbg.c \
+ psa_crypto.c \
+ psa_crypto_client.c \
+ psa_crypto_driver_wrappers.c \
+ psa_crypto_hash.c \
+ psa_crypto_rsa.c \
+ psa_crypto_ecp.c \
+ psa_crypto_slot_management.c \
+ )
+
+ BL31_SOURCES += ${RSS_COMMS_SOURCES} \
+ plat/arm/common/arm_dyn_cfg.c \
+ ${TC_BASE}/rss_ap_tests.c \
+ ${TC_BASE}/rss_ap_testsuites.c \
+ ${TC_BASE}/rss_ap_test_stubs.c \
+ $(TF_M_TESTS_PATH)/test/framework/test_framework.c \
+ $(MEASURED_BOOT_TESTS_PATH)/measured_boot_common.c \
+ $(MEASURED_BOOT_TESTS_PATH)/measured_boot_tests_common.c \
+ $(DELEGATED_ATTEST_TESTS_PATH)/delegated_attest_test.c \
+ drivers/auth/mbedtls/mbedtls_common.c \
+ lib/psa/measured_boot.c \
+ lib/psa/delegated_attestation.c
+
+ PLAT_INCLUDES += -I$(TF_M_EXTRAS_PATH)/partitions/measured_boot/interface/include \
+ -I$(TF_M_EXTRAS_PATH)/partitions/delegated_attestation/interface/include \
+ -I$(TF_M_TESTS_PATH)/test/framework \
+ -I$(TF_M_TESTS_PATH)/log \
+ -I$(TF_M_TESTS_PATH)/test/secure_fw/suites/extra \
+ -I$(MEASURED_BOOT_TESTS_PATH)/non_secure \
+ -I$(DELEGATED_ATTEST_TESTS_PATH) \
+ -I$(DELEGATED_ATTEST_TESTS_PATH)/non_secure \
+ -Iplat/arm/board/tc \
+ -Iinclude/drivers/auth/mbedtls \
+ -Iinclude/drivers/arm
+
+ # Some of the PSA functions are declared in multiple header files, that
+ # triggers this warning.
+ TF_CFLAGS += -Wno-error=redundant-decls
+
+ # TODO: Created patch for warning in tf-m-tests
+ TF_CFLAGS += -Wno-error=return-type
+
+ # Define macros that are used by the code coming from the tf-m-extras repo.
+ $(eval $(call add_define,MEASUREMENT_VALUE_SIZE))
+ $(eval $(call add_define,MEASURED_BOOT_HASH_ALG))
+ $(eval $(call add_define,DELEG_ATTEST_DUMP_TOKEN_AND_KEY))
+
+ $(eval $(call add_define,PLATFORM_TEST))
+endif
diff --git a/plat/arm/board/tc/region_defs.h b/plat/arm/board/tc/region_defs.h
new file mode 100644
index 0000000..d3dfd13
--- /dev/null
+++ b/plat/arm/board/tc/region_defs.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2022, Arm Ltd. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef REGION_DEFS_H
+#define REGION_DEFS_H
+
+#define PSA_INITIAL_ATTEST_TOKEN_MAX_SIZE 0x800
+
+#endif /* REGION_DEFS_H */
diff --git a/plat/arm/board/tc/rss_ap_test_stubs.c b/plat/arm/board/tc/rss_ap_test_stubs.c
new file mode 100644
index 0000000..aa97476
--- /dev/null
+++ b/plat/arm/board/tc/rss_ap_test_stubs.c
@@ -0,0 +1,121 @@
+/*
+ * Copyright (c) 2022, Arm Ltd. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdarg.h>
+#include <stdbool.h>
+#include <stdio.h>
+
+#include <delegated_attestation.h>
+#include <measured_boot.h>
+#include <psa/error.h>
+
+
+psa_status_t
+tfm_measured_boot_extend_measurement(uint8_t index,
+ const uint8_t *signer_id,
+ size_t signer_id_size,
+ const uint8_t *version,
+ size_t version_size,
+ uint32_t measurement_algo,
+ const uint8_t *sw_type,
+ size_t sw_type_size,
+ const uint8_t *measurement_value,
+ size_t measurement_value_size,
+ bool lock_measurement)
+{
+ return rss_measured_boot_extend_measurement(index,
+ signer_id,
+ signer_id_size,
+ version,
+ version_size,
+ measurement_algo,
+ sw_type,
+ sw_type_size,
+ measurement_value,
+ measurement_value_size,
+ lock_measurement);
+}
+
+psa_status_t
+tfm_measured_boot_read_measurement(uint8_t index,
+ uint8_t *signer_id,
+ size_t signer_id_size,
+ size_t *signer_id_len,
+ uint8_t *version,
+ size_t version_size,
+ size_t *version_len,
+ uint32_t *measurement_algo,
+ uint8_t *sw_type,
+ size_t sw_type_size,
+ size_t *sw_type_len,
+ uint8_t *measurement_value,
+ size_t measurement_value_size,
+ size_t *measurement_value_len,
+ bool *is_locked)
+{
+ return rss_measured_boot_read_measurement(index,
+ signer_id,
+ signer_id_size,
+ signer_id_len,
+ version,
+ version_size,
+ version_len,
+ measurement_algo,
+ sw_type,
+ sw_type_size,
+ sw_type_len,
+ measurement_value,
+ measurement_value_size,
+ measurement_value_len,
+ is_locked);
+}
+
+psa_status_t
+tfm_delegated_attest_get_token(const uint8_t *dak_pub_hash,
+ size_t dak_pub_hash_size,
+ uint8_t *token_buf,
+ size_t token_buf_size,
+ size_t *token_size)
+{
+ return rss_delegated_attest_get_token(dak_pub_hash,
+ dak_pub_hash_size,
+ token_buf,
+ token_buf_size,
+ token_size);
+}
+
+psa_status_t
+tfm_delegated_attest_get_delegated_key(uint8_t ecc_curve,
+ uint32_t key_bits,
+ uint8_t *key_buf,
+ size_t key_buf_size,
+ size_t *key_size,
+ uint32_t hash_algo)
+{
+ return rss_delegated_attest_get_delegated_key(ecc_curve,
+ key_bits,
+ key_buf,
+ key_buf_size,
+ key_size,
+ hash_algo);
+}
+
+int tfm_log_printf(const char *fmt, ...)
+{
+ int count;
+ va_list ap;
+
+ va_start(ap, fmt);
+ count = vprintf(fmt, ap);
+ va_end(ap);
+
+ return count;
+}
+
+void printf_set_color(int color_id)
+{
+ (void)color_id;
+}
diff --git a/plat/arm/board/tc/rss_ap_tests.c b/plat/arm/board/tc/rss_ap_tests.c
new file mode 100644
index 0000000..b62043e
--- /dev/null
+++ b/plat/arm/board/tc/rss_ap_tests.c
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2022, Arm Ltd. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <stdio.h>
+
+#include <mbedtls_common.h>
+#include <plat/common/platform.h>
+#include <psa/crypto.h>
+#include <rss_comms.h>
+
+#include "rss_ap_testsuites.h"
+
+static struct test_suite_t test_suites[] = {
+ {.freg = register_testsuite_delegated_attest},
+ {.freg = register_testsuite_measured_boot},
+};
+
+static void run_tests(void)
+{
+ enum test_suite_err_t ret;
+ psa_status_t status;
+ size_t i;
+
+ rss_comms_init(PLAT_RSS_AP_SND_MHU_BASE, PLAT_RSS_AP_RCV_MHU_BASE);
+ mbedtls_init();
+ status = psa_crypto_init();
+ if (status != PSA_SUCCESS) {
+ printf("\n\npsa_crypto_init failed (status = %d)\n", status);
+ assert(false);
+ plat_error_handler(-1);
+ }
+
+ for (i = 0; i < ARRAY_SIZE(test_suites); ++i) {
+ struct test_suite_t *suite = &(test_suites[i]);
+
+ suite->freg(suite);
+ ret = run_testsuite(suite);
+ if (ret != TEST_SUITE_ERR_NO_ERROR) {
+ printf("\n\nError during executing testsuite '%s'.\n", suite->name);
+ assert(false);
+ plat_error_handler(-1);
+ }
+ }
+ printf("\nAll tests are run.\n");
+}
+
+void run_platform_tests(void)
+{
+ size_t i;
+
+ run_tests();
+
+ printf("\n\n");
+
+ /* Print a summary of all the tests that had been run. */
+ printf("SUMMARY:\n");
+ for (i = 0; i < ARRAY_SIZE(test_suites); ++i) {
+
+ struct test_suite_t *suite = &(test_suites[i]);
+
+ switch (suite->val) {
+ case TEST_PASSED:
+ printf(" %s PASSED.\n", suite->name);
+ break;
+ case TEST_FAILED:
+ printf(" %s FAILED.\n", suite->name);
+ break;
+ case TEST_SKIPPED:
+ printf(" %s SKIPPED.\n", suite->name);
+ break;
+ default:
+ assert(false);
+ break;
+ }
+ }
+
+ printf("\n\n");
+}
diff --git a/plat/arm/board/tc/rss_ap_testsuites.c b/plat/arm/board/tc/rss_ap_testsuites.c
new file mode 100644
index 0000000..aa47d4c
--- /dev/null
+++ b/plat/arm/board/tc/rss_ap_testsuites.c
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2022, Arm Ltd. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * `delegated_attest_ns_interface_testsuite.c` and
+ * `measured_boot_ns_interface_testsuite.c` are not added to the build directly.
+ * but are included in this file, and this file is added to the build. This is
+ * necessary because both files define the function `extra_tests_init`, so a
+ * linker error occurs when both are linked to BL31. This file defines a macro
+ * that renames the colliding function names to something unique.
+ * `plat/arm/board/tc/rss_ap_tests.c` can call the test init functions with
+ * their new name.
+ */
+
+#define register_testsuite_extra_ns_interface \
+ register_testsuite_delegated_attest
+#include <delegated_attest_ns_interface_testsuite.c>
+
+#undef register_testsuite_extra_ns_interface
+#define register_testsuite_extra_ns_interface \
+ register_testsuite_measured_boot
+#include <measured_boot_ns_interface_testsuite.c>
\ No newline at end of file
diff --git a/plat/arm/board/tc/rss_ap_testsuites.h b/plat/arm/board/tc/rss_ap_testsuites.h
new file mode 100644
index 0000000..58502ab
--- /dev/null
+++ b/plat/arm/board/tc/rss_ap_testsuites.h
@@ -0,0 +1,16 @@
+
+/*
+ * Copyright (c) 2022, Arm Ltd. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef RSS_AP_TESTSUITES_H
+#define RSS_AP_TESTSUITES_H
+
+#include <test_framework.h>
+
+void register_testsuite_measured_boot(struct test_suite_t *p_test_suite);
+void register_testsuite_delegated_attest(struct test_suite_t *p_test_suite);
+
+#endif /* RSS_AP_TESTSUITES_H */
diff --git a/plat/arm/board/tc/tc_bl31_setup.c b/plat/arm/board/tc/tc_bl31_setup.c
index 0523ef8..c79558d 100644
--- a/plat/arm/board/tc/tc_bl31_setup.c
+++ b/plat/arm/board/tc/tc_bl31_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020-2022, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -33,7 +33,7 @@
tc_bl31_common_platform_setup();
}
-scmi_channel_plat_info_t *plat_css_get_scmi_info(int channel_id)
+scmi_channel_plat_info_t *plat_css_get_scmi_info(unsigned int channel_id)
{
return &tc_scmi_plat_info[channel_id];
@@ -52,6 +52,12 @@
void tc_bl31_common_platform_setup(void)
{
arm_bl31_platform_setup();
+#ifdef PLATFORM_TEST
+ run_platform_tests();
+
+ /* Suspend booting */
+ plat_error_handler(-1);
+#endif
}
const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops)
diff --git a/plat/arm/common/arm_bl2_setup.c b/plat/arm/common/arm_bl2_setup.c
index 08c014d..02e419a 100644
--- a/plat/arm/common/arm_bl2_setup.c
+++ b/plat/arm/common/arm_bl2_setup.c
@@ -143,11 +143,12 @@
ARM_PAS_SECURE,
ARM_PAS_REALM,
ARM_PAS_EL3_DRAM,
- ARM_PAS_GPTS
+ ARM_PAS_GPTS,
+ ARM_PAS_KERNEL_1
};
/* Initialize entire protected space to GPT_GPI_ANY. */
- if (gpt_init_l0_tables(GPCCR_PPS_4GB, ARM_L0_GPT_ADDR_BASE,
+ if (gpt_init_l0_tables(GPCCR_PPS_64GB, ARM_L0_GPT_ADDR_BASE,
ARM_L0_GPT_SIZE) < 0) {
ERROR("gpt_init_l0_tables() failed!\n");
panic();
diff --git a/plat/arm/common/trp/arm_trp_setup.c b/plat/arm/common/trp/arm_trp_setup.c
index 59b4c06..aeacd10 100644
--- a/plat/arm/common/trp/arm_trp_setup.c
+++ b/plat/arm/common/trp/arm_trp_setup.c
@@ -28,6 +28,9 @@
static int arm_trp_process_manifest(rmm_manifest_t *manifest)
{
+ /* padding field on the manifest must be RES0 */
+ assert(manifest->padding == 0U);
+
/* Verify the Boot Manifest Version. Only the Major is considered */
if (RMMD_MANIFEST_VERSION_MAJOR !=
RMMD_GET_MANIFEST_VERSION_MAJOR(manifest->version)) {
diff --git a/plat/arm/css/common/css_pm.c b/plat/arm/css/common/css_pm.c
index 9b2639c..3222226 100644
--- a/plat/arm/css/common/css_pm.c
+++ b/plat/arm/css/common/css_pm.c
@@ -130,9 +130,6 @@
/* Prevent interrupts from spuriously waking up this cpu */
plat_arm_gic_cpuif_disable();
- /* Turn redistributor off */
- plat_arm_gic_redistif_off();
-
/* Cluster is to be turned off, so disable coherency */
if (CSS_CLUSTER_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF) {
plat_arm_interconnect_exit_coherency();
diff --git a/plat/arm/css/sgi/include/sgi_variant.h b/plat/arm/css/sgi/include/sgi_variant.h
index 223ac3e..8f9529a 100644
--- a/plat/arm/css/sgi/include/sgi_variant.h
+++ b/plat/arm/css/sgi/include/sgi_variant.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2023, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -22,6 +22,7 @@
/* SID Version values for RD-N2 variants */
#define RD_N2_CFG1_SID_VER_PART_NUM 0x07B6
+#define RD_N2_CFG3_SID_VER_PART_NUM 0x07F1
/* SID Version values for RD-V2 */
#define RD_V2_SID_VER_PART_NUM 0x07F2
diff --git a/plat/arm/css/sgi/sgi_bl31_setup.c b/plat/arm/css/sgi/sgi_bl31_setup.c
index 27cf183..df2ce38 100644
--- a/plat/arm/css/sgi/sgi_bl31_setup.c
+++ b/plat/arm/css/sgi/sgi_bl31_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -74,13 +74,14 @@
#endif
};
-scmi_channel_plat_info_t *plat_css_get_scmi_info(int channel_id)
+scmi_channel_plat_info_t *plat_css_get_scmi_info(unsigned int channel_id)
{
if (sgi_plat_info.platform_id == RD_N1E1_EDGE_SID_VER_PART_NUM ||
sgi_plat_info.platform_id == RD_V1_SID_VER_PART_NUM ||
sgi_plat_info.platform_id == RD_N2_SID_VER_PART_NUM ||
sgi_plat_info.platform_id == RD_V2_SID_VER_PART_NUM ||
- sgi_plat_info.platform_id == RD_N2_CFG1_SID_VER_PART_NUM) {
+ sgi_plat_info.platform_id == RD_N2_CFG1_SID_VER_PART_NUM ||
+ sgi_plat_info.platform_id == RD_N2_CFG3_SID_VER_PART_NUM) {
if (channel_id >= ARRAY_SIZE(plat_rd_scmi_info))
panic();
return &plat_rd_scmi_info[channel_id];
diff --git a/plat/common/aarch64/crash_console_helpers.S b/plat/common/aarch64/crash_console_helpers.S
index e2950f5..75b4208 100644
--- a/plat/common/aarch64/crash_console_helpers.S
+++ b/plat/common/aarch64/crash_console_helpers.S
@@ -68,12 +68,12 @@
mov x4, x30 /* x3 and x4 are not clobbered by spin_lock() */
mov x3, #0 /* return value */
+ adrp x0, crash_console_spinlock
+ add x0, x0, :lo12:crash_console_spinlock
+
mrs x1, sctlr_el3
tst x1, #SCTLR_C_BIT
beq skip_spinlock /* can't synchronize when cache disabled */
-
- adrp x0, crash_console_spinlock
- add x0, x0, :lo12:crash_console_spinlock
bl spin_lock
skip_spinlock:
diff --git a/plat/imx/common/imx_sip_handler.c b/plat/imx/common/imx_sip_handler.c
index d4b3425..ec8631a 100644
--- a/plat/imx/common/imx_sip_handler.c
+++ b/plat/imx/common/imx_sip_handler.c
@@ -20,7 +20,7 @@
#if defined(PLAT_imx8qm) || defined(PLAT_imx8qx)
#ifdef PLAT_imx8qm
-const static int ap_cluster_index[PLATFORM_CLUSTER_COUNT] = {
+static const int ap_cluster_index[PLATFORM_CLUSTER_COUNT] = {
SC_R_A53, SC_R_A72,
};
#endif
diff --git a/plat/imx/imx8m/imx8m_measured_boot.c b/plat/imx/imx8m/imx8m_measured_boot.c
index ec61606..e9ea2d8 100644
--- a/plat/imx/imx8m/imx8m_measured_boot.c
+++ b/plat/imx/imx8m/imx8m_measured_boot.c
@@ -24,17 +24,13 @@
{ EVLOG_INVALID_ID, NULL, (unsigned int)(-1) } /* Terminator */
};
-const event_log_metadata_t *plat_event_log_get_metadata(void)
-{
- return imx8m_event_log_metadata;
-}
-
int plat_mboot_measure_image(unsigned int image_id, image_info_t *image_data)
{
/* Calculate image hash and record data in Event Log */
int err = event_log_measure_and_record(image_data->image_base,
image_data->image_size,
- image_id);
+ image_id,
+ imx8m_event_log_metadata);
if (err != 0) {
ERROR("%s%s image id %u (%i)\n",
"Failed to ", "record", image_id, err);
diff --git a/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c b/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c
index 59c3779..4706c20 100644
--- a/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c
+++ b/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c
@@ -124,6 +124,7 @@
void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
+ static console_t console;
int i;
/* enable CSU NS access permission */
for (i = 0; i < 64; i++) {
@@ -132,12 +133,10 @@
imx_aipstz_init(aipstz);
-#if DEBUG_CONSOLE
- static console_t console;
-
console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ,
IMX_CONSOLE_BAUDRATE, &console);
-#endif
+ /* This console is only used for boot stage */
+ console_set_scope(&console, CONSOLE_FLAG_BOOT);
imx8m_caam_init();
@@ -176,23 +175,22 @@
void bl31_plat_arch_setup(void)
{
- mmap_add_region(BL31_BASE, BL31_BASE, (BL31_LIMIT - BL31_BASE),
- MT_MEMORY | MT_RW | MT_SECURE);
- mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, (BL_CODE_END - BL_CODE_BASE),
- MT_MEMORY | MT_RO | MT_SECURE);
-
- /* Map TEE memory */
- mmap_add_region(BL32_BASE, BL32_BASE, BL32_SIZE, MT_MEMORY | MT_RW);
-
- mmap_add(imx_mmap);
-
+ const mmap_region_t bl_regions[] = {
+ MAP_REGION_FLAT(BL31_START, BL31_SIZE,
+ MT_MEMORY | MT_RW | MT_SECURE),
+ MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE,
+ MT_MEMORY | MT_RO | MT_SECURE),
#if USE_COHERENT_MEM
- mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE,
- BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
- MT_DEVICE | MT_RW | MT_SECURE);
+ MAP_REGION_FLAT(BL_COHERENT_RAM_BASE,
+ BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
+ MT_DEVICE | MT_RW | MT_SECURE),
#endif
- /* setup xlat table */
- init_xlat_tables();
+ /* Map TEE memory */
+ MAP_REGION_FLAT(BL32_BASE, BL32_SIZE, MT_MEMORY | MT_RW),
+ {0},
+ };
+
+ setup_page_tables(bl_regions, imx_mmap);
/* enable the MMU */
enable_mmu_el3(0);
}
@@ -227,11 +225,6 @@
return COUNTER_FREQUENCY;
}
-void bl31_plat_runtime_setup(void)
-{
- return;
-}
-
#ifdef SPD_trusty
void plat_trusty_set_boot_args(aapcs64_params_t *args)
{
diff --git a/plat/imx/imx8m/imx8mq/imx8mq_psci.c b/plat/imx/imx8m/imx8mq/imx8mq_psci.c
index 662017d..01582af 100644
--- a/plat/imx/imx8m/imx8mq/imx8mq_psci.c
+++ b/plat/imx/imx8m/imx8mq/imx8mq_psci.c
@@ -41,7 +41,7 @@
void imx_domain_suspend(const psci_power_state_t *target_state)
{
- uint64_t base_addr = BL31_BASE;
+ uint64_t base_addr = BL31_START;
uint64_t mpidr = read_mpidr_el1();
unsigned int core_id = MPIDR_AFFLVL0_VAL(mpidr);
diff --git a/plat/imx/imx8m/imx8mq/include/platform_def.h b/plat/imx/imx8m/imx8mq/include/platform_def.h
index 1dd22d9..bb57074 100644
--- a/plat/imx/imx8m/imx8mq/include/platform_def.h
+++ b/plat/imx/imx8m/imx8mq/include/platform_def.h
@@ -4,6 +4,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
+#include <plat/common/common_def.h>
+
#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
#define PLATFORM_LINKER_ARCH aarch64
@@ -31,7 +33,8 @@
#define PLAT_STOP_OFF_STATE U(3)
#define BL31_BASE U(0x910000)
-#define BL31_LIMIT U(0x920000)
+#define BL31_SIZE SZ_64K
+#define BL31_LIMIT (BL31_BASE + BL31_SIZE)
/* non-secure uboot base */
#define PLAT_NS_IMAGE_OFFSET U(0x40200000)
@@ -54,7 +57,6 @@
#define HAB_RVT_BASE U(0x00000880) /* HAB_RVT for i.MX8MQ */
-#define IMX_BOOT_UART_BASE U(0x30860000)
#define IMX_BOOT_UART_CLK_IN_HZ 25000000 /* Select 25Mhz oscillator */
#define PLAT_CRASH_UART_BASE IMX_BOOT_UART_BASE
#define PLAT_CRASH_UART_CLK_IN_HZ 25000000
@@ -128,5 +130,4 @@
#define COUNTER_FREQUENCY 8333333 /* 25MHz / 3 */
-#define DEBUG_CONSOLE 0
#define IMX_WDOG_B_RESET
diff --git a/plat/imx/imx8m/imx8mq/platform.mk b/plat/imx/imx8m/imx8mq/platform.mk
index 7b6df92..901a974 100644
--- a/plat/imx/imx8m/imx8mq/platform.mk
+++ b/plat/imx/imx8m/imx8mq/platform.mk
@@ -38,6 +38,7 @@
${XLAT_TABLES_LIB_SRCS} \
${IMX_GIC_SOURCES}
+ENABLE_PIE := 1
USE_COHERENT_MEM := 1
RESET_TO_BL31 := 1
A53_DISABLE_NON_TEMPORAL_HINT := 0
@@ -52,6 +53,9 @@
BL32_SIZE ?= 0x2000000
$(eval $(call add_define,BL32_SIZE))
+IMX_BOOT_UART_BASE ?= 0x30860000
+$(eval $(call add_define,IMX_BOOT_UART_BASE))
+
ifeq (${SPD},trusty)
BL31_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC=1
endif
diff --git a/plat/imx/imx8qm/imx8qm_bl31_setup.c b/plat/imx/imx8qm/imx8qm_bl31_setup.c
index 68eb534..bd7896a 100644
--- a/plat/imx/imx8qm/imx8qm_bl31_setup.c
+++ b/plat/imx/imx8qm/imx8qm_bl31_setup.c
@@ -62,7 +62,7 @@
#error "Provide proper UART number in IMX_DEBUG_UART"
#endif
-const static int imx8qm_cci_map[] = {
+static const int imx8qm_cci_map[] = {
CLUSTER0_CCI_SLVAE_IFACE,
CLUSTER1_CCI_SLVAE_IFACE
};
diff --git a/plat/imx/imx8qm/imx8qm_psci.c b/plat/imx/imx8qm/imx8qm_psci.c
index bdba37c..dcc502f 100644
--- a/plat/imx/imx8qm/imx8qm_psci.c
+++ b/plat/imx/imx8qm/imx8qm_psci.c
@@ -26,7 +26,7 @@
#define SYSTEM_PWR_STATE(state) \
((state)->pwr_domain_state[PLAT_MAX_PWR_LVL])
-const static int ap_core_index[PLATFORM_CORE_COUNT] = {
+static const int ap_core_index[PLATFORM_CORE_COUNT] = {
SC_R_A53_0, SC_R_A53_1, SC_R_A53_2,
SC_R_A53_3, SC_R_A72_0, SC_R_A72_1,
};
diff --git a/plat/imx/imx8qx/imx8qx_psci.c b/plat/imx/imx8qx/imx8qx_psci.c
index aab3a2d..5f05566 100644
--- a/plat/imx/imx8qx/imx8qx_psci.c
+++ b/plat/imx/imx8qx/imx8qx_psci.c
@@ -18,7 +18,7 @@
#include "../../common/sci/imx8_mu.h"
-const static int ap_core_index[PLATFORM_CORE_COUNT] = {
+static const int ap_core_index[PLATFORM_CORE_COUNT] = {
SC_R_A35_0, SC_R_A35_1, SC_R_A35_2, SC_R_A35_3
};
diff --git a/plat/intel/soc/agilex/bl31_plat_setup.c b/plat/intel/soc/agilex/bl31_plat_setup.c
index b1b9514..26ed7ef 100644
--- a/plat/intel/soc/agilex/bl31_plat_setup.c
+++ b/plat/intel/soc/agilex/bl31_plat_setup.c
@@ -17,6 +17,7 @@
#include "ccu/ncore_ccu.h"
#include "socfpga_mailbox.h"
#include "socfpga_private.h"
+#include "socfpga_sip_svc.h"
static entry_point_info_t bl32_image_ep_info;
static entry_point_info_t bl33_image_ep_info;
@@ -35,6 +36,25 @@
return NULL;
}
+void setup_smmu_secure_context(void)
+{
+ /*
+ * Program SCR0 register (0xFA000000)
+ * to set SMCFCFG bit[21] to 0x1 which raise stream match conflict fault
+ * to set CLIENTPD bit[0] to 0x0 which enables SMMU for secure context
+ */
+ mmio_write_32(0xFA000000, 0x00200000);
+
+ /*
+ * Program SCR1 register (0xFA000004)
+ * to set NSNUMSMRGO bit[14:8] to 0x4 which stream mapping register
+ * for non-secure context and the rest will be secure context
+ * to set NSNUMCBO bit[5:0] to 0x4 which allocate context bank
+ * for non-secure context and the rest will be secure context
+ */
+ mmio_write_32(0xFA000004, 0x00000404);
+}
+
void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
@@ -109,6 +129,7 @@
gicv2_distif_init();
gicv2_pcpu_distif_init();
gicv2_cpuif_enable();
+ setup_smmu_secure_context();
/* Signal secondary CPUs to jump to BL31 (BL2 = U-boot SPL) */
mmio_write_64(PLAT_CPU_RELEASE_ADDR,
diff --git a/plat/intel/soc/common/drivers/ccu/ncore_ccu.c b/plat/intel/soc/common/drivers/ccu/ncore_ccu.c
index d9a238e..99d48d2 100644
--- a/plat/intel/soc/common/drivers/ccu/ncore_ccu.c
+++ b/plat/intel/soc/common/drivers/ccu/ncore_ccu.c
@@ -40,7 +40,7 @@
dir_sf_en = DIRECTORY_UNIT(dir, NCORE_DIRUSFER);
/* Initialize All Entries */
- mmio_write_32(dir_sf_mtn, SNOOP_FILTER_ID(dir));
+ mmio_write_32(dir_sf_mtn, SNOOP_FILTER_ID(sf));
/* Poll Active Bit */
ret = poll_active_bit(dir);
@@ -49,8 +49,9 @@
return -ETIMEDOUT;
}
- /* Snoope Filter Enable */
- mmio_setbits_32(dir_sf_en, BIT(sf));
+ /* Disable snoop filter, a bit per snoop filter */
+ mmio_clrbits_32(dir_sf_en, BIT(sf));
+
}
}
diff --git a/plat/intel/soc/common/include/socfpga_fcs.h b/plat/intel/soc/common/include/socfpga_fcs.h
index 893551d..8a8f348 100644
--- a/plat/intel/soc/common/include/socfpga_fcs.h
+++ b/plat/intel/soc/common/include/socfpga_fcs.h
@@ -84,6 +84,14 @@
#define FCS_ECDSA_HASH_SIGN_CMD_MAX_WORD_SIZE 17U
#define FCS_ECDSA_HASH_SIG_VERIFY_CMD_MAX_WORD_SIZE 52U
#define FCS_ECDH_REQUEST_CMD_MAX_WORD_SIZE 29U
+
+#define FCS_CRYPTO_ECB_BUFFER_SIZE 12U
+#define FCS_CRYPTO_CBC_CTR_BUFFER_SIZE 28U
+#define FCS_CRYPTO_BLOCK_MODE_MASK 0x07
+#define FCS_CRYPTO_ECB_MODE 0x00
+#define FCS_CRYPTO_CBC_MODE 0x01
+#define FCS_CRYPTO_CTR_MODE 0x02
+
/* FCS Payload Structure */
typedef struct fcs_rng_payload_t {
uint32_t session_id;
@@ -235,6 +243,11 @@
uint32_t src_addr, uint32_t src_size,
uint64_t dst_addr, uint32_t *dst_size,
uint8_t is_finalised, uint32_t *mbox_error);
+int intel_fcs_get_digest_smmu_update_finalize(uint32_t session_id, uint32_t context_id,
+ uint32_t src_addr, uint32_t src_size,
+ uint64_t dst_addr, uint32_t *dst_size,
+ uint8_t is_finalised, uint32_t *mbox_error,
+ uint32_t *send_id);
int intel_fcs_mac_verify_init(uint32_t session_id, uint32_t context_id,
uint32_t key_id, uint32_t param_size,
@@ -244,6 +257,11 @@
uint64_t dst_addr, uint32_t *dst_size,
uint32_t data_size, uint8_t is_finalised,
uint32_t *mbox_error);
+int intel_fcs_mac_verify_smmu_update_finalize(uint32_t session_id, uint32_t context_id,
+ uint32_t src_addr, uint32_t src_size,
+ uint64_t dst_addr, uint32_t *dst_size,
+ uint32_t data_size, uint8_t is_finalised,
+ uint32_t *mbox_error, uint32_t *send_id);
int intel_fcs_ecdsa_hash_sign_init(uint32_t session_id, uint32_t context_id,
uint32_t key_id, uint32_t param_size,
@@ -270,6 +288,11 @@
uint32_t src_size, uint64_t dst_addr,
uint32_t *dst_size, uint8_t is_finalised,
uint32_t *mbox_error);
+int intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(uint32_t session_id,
+ uint32_t context_id, uint32_t src_addr,
+ uint32_t src_size, uint64_t dst_addr,
+ uint32_t *dst_size, uint8_t is_finalised,
+ uint32_t *mbox_error, uint32_t *send_id);
int intel_fcs_ecdsa_sha2_data_sig_verify_init(uint32_t session_id,
uint32_t context_id, uint32_t key_id,
@@ -280,6 +303,12 @@
uint32_t src_size, uint64_t dst_addr,
uint32_t *dst_size, uint32_t data_size,
uint8_t is_finalised, uint32_t *mbox_error);
+int intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize(uint32_t session_id,
+ uint32_t context_id, uint32_t src_addr,
+ uint32_t src_size, uint64_t dst_addr,
+ uint32_t *dst_size, uint32_t data_size,
+ uint8_t is_finalised, uint32_t *mbox_error,
+ uint32_t *send_id);
int intel_fcs_ecdsa_get_pubkey_init(uint32_t session_id, uint32_t context_id,
uint32_t key_id, uint32_t param_size,
diff --git a/plat/intel/soc/common/include/socfpga_mailbox.h b/plat/intel/soc/common/include/socfpga_mailbox.h
index 1f4b2a4..3abf39d 100644
--- a/plat/intel/soc/common/include/socfpga_mailbox.h
+++ b/plat/intel/soc/common/include/socfpga_mailbox.h
@@ -129,6 +129,10 @@
#define MBOX_BUSY -5
#define MBOX_TIMEOUT -2047
+/* Key Status */
+#define MBOX_RET_SDOS_DECRYPTION_ERROR_102 -258
+#define MBOX_RET_SDOS_DECRYPTION_ERROR_103 -259
+
/* Reconfig Status Response */
#define RECONFIG_STATUS_STATE 0
#define RECONFIG_STATUS_PIN_STATUS 2
@@ -139,6 +143,7 @@
#define SOFTFUNC_STATUS_CONF_DONE (1 << 0)
#define MBOX_CFGSTAT_STATE_IDLE 0x00000000
#define MBOX_CFGSTAT_STATE_CONFIG 0x10000000
+#define MBOX_CFGSTAT_VAB_BS_PREAUTH 0x20000000
#define MBOX_CFGSTAT_STATE_FAILACK 0x08000000
#define MBOX_CFGSTAT_STATE_ERROR_INVALID 0xf0000001
#define MBOX_CFGSTAT_STATE_ERROR_CORRUPT 0xf0000002
diff --git a/plat/intel/soc/common/include/socfpga_sip_svc.h b/plat/intel/soc/common/include/socfpga_sip_svc.h
index 0803eb5..21169f7 100644
--- a/plat/intel/soc/common/include/socfpga_sip_svc.h
+++ b/plat/intel/soc/common/include/socfpga_sip_svc.h
@@ -86,49 +86,57 @@
#define INTEL_SIP_SMC_GET_USERCODE 0xC200003D
/* FPGA Crypto Services */
-#define INTEL_SIP_SMC_FCS_RANDOM_NUMBER 0xC200005A
-#define INTEL_SIP_SMC_FCS_RANDOM_NUMBER_EXT 0x4200008F
-#define INTEL_SIP_SMC_FCS_CRYPTION 0x4200005B
-#define INTEL_SIP_SMC_FCS_CRYPTION_EXT 0xC2000090
-#define INTEL_SIP_SMC_FCS_SERVICE_REQUEST 0x4200005C
-#define INTEL_SIP_SMC_FCS_SEND_CERTIFICATE 0x4200005D
-#define INTEL_SIP_SMC_FCS_GET_PROVISION_DATA 0x4200005E
-#define INTEL_SIP_SMC_FCS_CNTR_SET_PREAUTH 0xC200005F
-#define INTEL_SIP_SMC_FCS_PSGSIGMA_TEARDOWN 0xC2000064
-#define INTEL_SIP_SMC_FCS_CHIP_ID 0xC2000065
-#define INTEL_SIP_SMC_FCS_ATTESTATION_SUBKEY 0xC2000066
-#define INTEL_SIP_SMC_FCS_ATTESTATION_MEASUREMENTS 0xC2000067
-#define INTEL_SIP_SMC_FCS_GET_ATTESTATION_CERT 0xC2000068
-#define INTEL_SIP_SMC_FCS_CREATE_CERT_ON_RELOAD 0xC2000069
-#define INTEL_SIP_SMC_FCS_OPEN_CS_SESSION 0xC200006E
-#define INTEL_SIP_SMC_FCS_CLOSE_CS_SESSION 0xC200006F
-#define INTEL_SIP_SMC_FCS_IMPORT_CS_KEY 0x42000070
-#define INTEL_SIP_SMC_FCS_EXPORT_CS_KEY 0xC2000071
-#define INTEL_SIP_SMC_FCS_REMOVE_CS_KEY 0xC2000072
-#define INTEL_SIP_SMC_FCS_GET_CS_KEY_INFO 0xC2000073
-#define INTEL_SIP_SMC_FCS_AES_CRYPT_INIT 0xC2000074
-#define INTEL_SIP_SMC_FCS_AES_CRYPT_UPDATE 0x42000075
-#define INTEL_SIP_SMC_FCS_AES_CRYPT_FINALIZE 0x42000076
-#define INTEL_SIP_SMC_FCS_GET_DIGEST_INIT 0xC2000077
-#define INTEL_SIP_SMC_FCS_GET_DIGEST_UPDATE 0xC2000078
-#define INTEL_SIP_SMC_FCS_GET_DIGEST_FINALIZE 0xC2000079
-#define INTEL_SIP_SMC_FCS_MAC_VERIFY_INIT 0xC200007A
-#define INTEL_SIP_SMC_FCS_MAC_VERIFY_UPDATE 0xC200007B
-#define INTEL_SIP_SMC_FCS_MAC_VERIFY_FINALIZE 0xC200007C
-#define INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_INIT 0xC200007D
-#define INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_FINALIZE 0xC200007F
-#define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_INIT 0xC2000080
-#define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE 0xC2000081
-#define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE 0xC2000082
-#define INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_INIT 0xC2000083
-#define INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE 0xC2000085
-#define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT 0xC2000086
-#define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_UPDATE 0xC2000087
-#define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE 0xC2000088
-#define INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_INIT 0xC2000089
-#define INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_FINALIZE 0xC200008B
-#define INTEL_SIP_SMC_FCS_ECDH_REQUEST_INIT 0xC200008C
-#define INTEL_SIP_SMC_FCS_ECDH_REQUEST_FINALIZE 0xC200008E
+#define INTEL_SIP_SMC_FCS_RANDOM_NUMBER 0xC200005A
+#define INTEL_SIP_SMC_FCS_RANDOM_NUMBER_EXT 0x4200008F
+#define INTEL_SIP_SMC_FCS_CRYPTION 0x4200005B
+#define INTEL_SIP_SMC_FCS_CRYPTION_EXT 0xC2000090
+#define INTEL_SIP_SMC_FCS_SERVICE_REQUEST 0x4200005C
+#define INTEL_SIP_SMC_FCS_SEND_CERTIFICATE 0x4200005D
+#define INTEL_SIP_SMC_FCS_GET_PROVISION_DATA 0x4200005E
+#define INTEL_SIP_SMC_FCS_CNTR_SET_PREAUTH 0xC200005F
+#define INTEL_SIP_SMC_FCS_PSGSIGMA_TEARDOWN 0xC2000064
+#define INTEL_SIP_SMC_FCS_CHIP_ID 0xC2000065
+#define INTEL_SIP_SMC_FCS_ATTESTATION_SUBKEY 0xC2000066
+#define INTEL_SIP_SMC_FCS_ATTESTATION_MEASUREMENTS 0xC2000067
+#define INTEL_SIP_SMC_FCS_GET_ATTESTATION_CERT 0xC2000068
+#define INTEL_SIP_SMC_FCS_CREATE_CERT_ON_RELOAD 0xC2000069
+#define INTEL_SIP_SMC_FCS_OPEN_CS_SESSION 0xC200006E
+#define INTEL_SIP_SMC_FCS_CLOSE_CS_SESSION 0xC200006F
+#define INTEL_SIP_SMC_FCS_IMPORT_CS_KEY 0x42000070
+#define INTEL_SIP_SMC_FCS_EXPORT_CS_KEY 0xC2000071
+#define INTEL_SIP_SMC_FCS_REMOVE_CS_KEY 0xC2000072
+#define INTEL_SIP_SMC_FCS_GET_CS_KEY_INFO 0xC2000073
+#define INTEL_SIP_SMC_FCS_AES_CRYPT_INIT 0xC2000074
+#define INTEL_SIP_SMC_FCS_AES_CRYPT_UPDATE 0x42000075
+#define INTEL_SIP_SMC_FCS_AES_CRYPT_FINALIZE 0x42000076
+#define INTEL_SIP_SMC_FCS_GET_DIGEST_INIT 0xC2000077
+#define INTEL_SIP_SMC_FCS_GET_DIGEST_UPDATE 0xC2000078
+#define INTEL_SIP_SMC_FCS_GET_DIGEST_FINALIZE 0xC2000079
+#define INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_UPDATE 0x42000091
+#define INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_FINALIZE 0x42000092
+#define INTEL_SIP_SMC_FCS_MAC_VERIFY_INIT 0xC200007A
+#define INTEL_SIP_SMC_FCS_MAC_VERIFY_UPDATE 0xC200007B
+#define INTEL_SIP_SMC_FCS_MAC_VERIFY_FINALIZE 0xC200007C
+#define INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_UPDATE 0x42000093
+#define INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_FINALIZE 0x42000094
+#define INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_INIT 0xC200007D
+#define INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_FINALIZE 0xC200007F
+#define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_INIT 0xC2000080
+#define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE 0xC2000081
+#define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE 0xC2000082
+#define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_UPDATE 0x42000095
+#define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_FINALIZE 0x42000096
+#define INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_INIT 0xC2000083
+#define INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE 0xC2000085
+#define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT 0xC2000086
+#define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_UPDATE 0xC2000087
+#define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE 0xC2000088
+#define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_UPDATE 0x42000097
+#define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_FINALIZE 0x42000098
+#define INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_INIT 0xC2000089
+#define INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_FINALIZE 0xC200008B
+#define INTEL_SIP_SMC_FCS_ECDH_REQUEST_INIT 0xC200008C
+#define INTEL_SIP_SMC_FCS_ECDH_REQUEST_FINALIZE 0xC200008E
#define INTEL_SIP_SMC_FCS_SHA_MODE_MASK 0xF
#define INTEL_SIP_SMC_FCS_DIGEST_SIZE_MASK 0xF
@@ -166,8 +174,14 @@
#define SIP_SVC_VERSION 0x8200ff03
/* SiP Service Calls version numbers */
-#define SIP_SVC_VERSION_MAJOR 1
-#define SIP_SVC_VERSION_MINOR 0
+/*
+ * Increase if there is any backward compatibility impact
+ */
+#define SIP_SVC_VERSION_MAJOR 2
+/*
+ * Increase if there is new SMC function ID being added
+ */
+#define SIP_SVC_VERSION_MINOR 1
/* Structure Definitions */
diff --git a/plat/intel/soc/common/include/socfpga_system_manager.h b/plat/intel/soc/common/include/socfpga_system_manager.h
index 7f67313..69ee6d3 100644
--- a/plat/intel/soc/common/include/socfpga_system_manager.h
+++ b/plat/intel/soc/common/include/socfpga_system_manager.h
@@ -42,6 +42,8 @@
#define IDLE_DATA_SOC2FPGA BIT(0)
#define IDLE_DATA_MASK (IDLE_DATA_LWSOC2FPGA | IDLE_DATA_SOC2FPGA)
+#define SYSMGR_QSPI_REFCLK_MASK GENMASK(27, 0)
+
#define SYSMGR_ECC_OCRAM_MASK BIT(1)
#define SYSMGR_ECC_DDR0_MASK BIT(16)
#define SYSMGR_ECC_DDR1_MASK BIT(17)
diff --git a/plat/intel/soc/common/sip/socfpga_sip_fcs.c b/plat/intel/soc/common/sip/socfpga_sip_fcs.c
index facee0f..3b0b370 100644
--- a/plat/intel/soc/common/sip/socfpga_sip_fcs.c
+++ b/plat/intel/soc/common/sip/socfpga_sip_fcs.c
@@ -411,7 +411,10 @@
(uint32_t *) &payload, payload_size,
CMD_CASUAL, resp_data, &resp_len);
- if (status < 0) {
+ if (status == MBOX_RET_SDOS_DECRYPTION_ERROR_102 ||
+ status == MBOX_RET_SDOS_DECRYPTION_ERROR_103) {
+ *mbox_error = -status;
+ } else if (status < 0) {
*mbox_error = -status;
return INTEL_SIP_SMC_STATUS_ERROR;
}
@@ -946,6 +949,104 @@
return INTEL_SIP_SMC_STATUS_OK;
}
+int intel_fcs_get_digest_smmu_update_finalize(uint32_t session_id,
+ uint32_t context_id, uint32_t src_addr,
+ uint32_t src_size, uint64_t dst_addr,
+ uint32_t *dst_size, uint8_t is_finalised,
+ uint32_t *mbox_error, uint32_t *send_id)
+{
+ int status;
+ uint32_t i;
+ uint32_t flag;
+ uint32_t crypto_header;
+ uint32_t resp_len;
+ uint32_t payload[FCS_GET_DIGEST_CMD_MAX_WORD_SIZE] = {0U};
+
+ /* Source data must be 8 bytes aligned */
+ if (dst_size == NULL || mbox_error == NULL ||
+ !is_8_bytes_aligned(src_size)) {
+ return INTEL_SIP_SMC_STATUS_REJECTED;
+ }
+
+ if (fcs_sha_get_digest_param.session_id != session_id ||
+ fcs_sha_get_digest_param.context_id != context_id) {
+ return INTEL_SIP_SMC_STATUS_REJECTED;
+ }
+
+ if (!is_address_in_ddr_range(src_addr, src_size) ||
+ !is_address_in_ddr_range(dst_addr, *dst_size)) {
+ return INTEL_SIP_SMC_STATUS_REJECTED;
+ }
+
+ resp_len = *dst_size / MBOX_WORD_BYTE;
+
+ /* Prepare crypto header */
+ flag = 0;
+
+ if (fcs_sha_get_digest_param.is_updated) {
+ fcs_sha_get_digest_param.crypto_param_size = 0;
+ } else {
+ flag |= FCS_CS_FIELD_FLAG_INIT;
+ }
+
+ if (is_finalised != 0U) {
+ flag |= FCS_CS_FIELD_FLAG_FINALIZE;
+ } else {
+ flag |= FCS_CS_FIELD_FLAG_UPDATE;
+ fcs_sha_get_digest_param.is_updated = 1;
+ }
+
+ crypto_header = ((flag << FCS_CS_FIELD_FLAG_OFFSET) |
+ (fcs_sha_get_digest_param.crypto_param_size &
+ FCS_CS_FIELD_SIZE_MASK));
+
+ /* Prepare command payload */
+ i = 0;
+ payload[i] = fcs_sha_get_digest_param.session_id;
+ i++;
+ payload[i] = fcs_sha_get_digest_param.context_id;
+ i++;
+ payload[i] = crypto_header;
+ i++;
+
+ if ((crypto_header >> FCS_CS_FIELD_FLAG_OFFSET) &
+ FCS_CS_FIELD_FLAG_INIT) {
+ payload[i] = fcs_sha_get_digest_param.key_id;
+ i++;
+ /* Crypto parameters */
+ payload[i] = fcs_sha_get_digest_param.crypto_param
+ & INTEL_SIP_SMC_FCS_SHA_MODE_MASK;
+ payload[i] |= ((fcs_sha_get_digest_param.crypto_param
+ >> INTEL_SIP_SMC_FCS_DIGEST_SIZE_OFFSET)
+ & INTEL_SIP_SMC_FCS_DIGEST_SIZE_MASK)
+ << FCS_SHA_HMAC_CRYPTO_PARAM_SIZE_OFFSET;
+ i++;
+ }
+ /* Data source address and size */
+ payload[i] = src_addr;
+ i++;
+ payload[i] = src_size;
+ i++;
+
+ status = mailbox_send_cmd_async(send_id, MBOX_FCS_GET_DIGEST_REQ,
+ payload, i, CMD_INDIRECT);
+
+ if (is_finalised != 0U) {
+ memset((void *)&fcs_sha_get_digest_param, 0,
+ sizeof(fcs_crypto_service_data));
+ }
+
+ if (status < 0) {
+ *mbox_error = -status;
+ return INTEL_SIP_SMC_STATUS_ERROR;
+ }
+
+ *dst_size = resp_len * MBOX_WORD_BYTE;
+ flush_dcache_range(dst_addr, *dst_size);
+
+ return INTEL_SIP_SMC_STATUS_OK;
+}
+
int intel_fcs_mac_verify_init(uint32_t session_id, uint32_t context_id,
uint32_t key_id, uint32_t param_size,
uint64_t param_data, uint32_t *mbox_error)
@@ -1071,6 +1172,127 @@
return INTEL_SIP_SMC_STATUS_OK;
}
+int intel_fcs_mac_verify_smmu_update_finalize(uint32_t session_id,
+ uint32_t context_id, uint32_t src_addr,
+ uint32_t src_size, uint64_t dst_addr,
+ uint32_t *dst_size, uint32_t data_size,
+ uint8_t is_finalised, uint32_t *mbox_error,
+ uint32_t *send_id)
+{
+ int status;
+ uint32_t i;
+ uint32_t flag;
+ uint32_t crypto_header;
+ uint32_t resp_len;
+ uint32_t payload[FCS_MAC_VERIFY_CMD_MAX_WORD_SIZE] = {0U};
+ uintptr_t mac_offset;
+
+ /*
+ * Source data must be 4 bytes aligned
+ * User data must be 8 bytes aligned
+ */
+ if (dst_size == NULL || mbox_error == NULL ||
+ !is_size_4_bytes_aligned(src_size) ||
+ !is_8_bytes_aligned(data_size)) {
+ return INTEL_SIP_SMC_STATUS_REJECTED;
+ }
+
+ if (data_size > src_size) {
+ return INTEL_SIP_SMC_STATUS_REJECTED;
+ }
+
+ if (fcs_sha_mac_verify_param.session_id != session_id ||
+ fcs_sha_mac_verify_param.context_id != context_id) {
+ return INTEL_SIP_SMC_STATUS_REJECTED;
+ }
+
+ if (!is_address_in_ddr_range(src_addr, src_size) ||
+ !is_address_in_ddr_range(dst_addr, *dst_size)) {
+ return INTEL_SIP_SMC_STATUS_REJECTED;
+ }
+
+ resp_len = *dst_size / MBOX_WORD_BYTE;
+
+ /* Prepare crypto header */
+ flag = 0;
+
+ if (fcs_sha_mac_verify_param.is_updated) {
+ fcs_sha_mac_verify_param.crypto_param_size = 0;
+ } else {
+ flag |= FCS_CS_FIELD_FLAG_INIT;
+ }
+
+ if (is_finalised) {
+ flag |= FCS_CS_FIELD_FLAG_FINALIZE;
+ } else {
+ flag |= FCS_CS_FIELD_FLAG_UPDATE;
+ fcs_sha_mac_verify_param.is_updated = 1;
+ }
+
+ crypto_header = ((flag << FCS_CS_FIELD_FLAG_OFFSET) |
+ (fcs_sha_mac_verify_param.crypto_param_size &
+ FCS_CS_FIELD_SIZE_MASK));
+
+ /* Prepare command payload */
+ i = 0;
+ payload[i] = fcs_sha_mac_verify_param.session_id;
+ i++;
+ payload[i] = fcs_sha_mac_verify_param.context_id;
+ i++;
+ payload[i] = crypto_header;
+ i++;
+
+ if ((crypto_header >> FCS_CS_FIELD_FLAG_OFFSET) &
+ FCS_CS_FIELD_FLAG_INIT) {
+ payload[i] = fcs_sha_mac_verify_param.key_id;
+ i++;
+ /* Crypto parameters */
+ payload[i] = ((fcs_sha_mac_verify_param.crypto_param
+ >> INTEL_SIP_SMC_FCS_DIGEST_SIZE_OFFSET)
+ & INTEL_SIP_SMC_FCS_DIGEST_SIZE_MASK)
+ << FCS_SHA_HMAC_CRYPTO_PARAM_SIZE_OFFSET;
+ i++;
+ }
+ /* Data source address and size */
+ payload[i] = src_addr;
+ i++;
+ payload[i] = data_size;
+ i++;
+
+ if ((crypto_header >> FCS_CS_FIELD_FLAG_OFFSET) &
+ FCS_CS_FIELD_FLAG_FINALIZE) {
+ /* Copy mac data to command
+ * Using dst_addr (physical address) to store mac_offset
+ * mac_offset = MAC data
+ */
+ mac_offset = dst_addr;
+ memcpy((uint8_t *) &payload[i], (uint8_t *) mac_offset,
+ src_size - data_size);
+
+ memset((void *)&dst_addr, 0, sizeof(dst_size));
+
+ i += (src_size - data_size) / MBOX_WORD_BYTE;
+ }
+
+ status = mailbox_send_cmd_async(send_id, MBOX_FCS_MAC_VERIFY_REQ,
+ payload, i, CMD_INDIRECT);
+
+ if (is_finalised) {
+ memset((void *)&fcs_sha_mac_verify_param, 0,
+ sizeof(fcs_crypto_service_data));
+ }
+
+ if (status < 0) {
+ *mbox_error = -status;
+ return INTEL_SIP_SMC_STATUS_ERROR;
+ }
+
+ *dst_size = resp_len * MBOX_WORD_BYTE;
+ flush_dcache_range(dst_addr, *dst_size);
+
+ return INTEL_SIP_SMC_STATUS_OK;
+}
+
int intel_fcs_ecdsa_hash_sign_init(uint32_t session_id, uint32_t context_id,
uint32_t key_id, uint32_t param_size,
uint64_t param_data, uint32_t *mbox_error)
@@ -1348,6 +1570,99 @@
return INTEL_SIP_SMC_STATUS_OK;
}
+int intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(uint32_t session_id,
+ uint32_t context_id, uint32_t src_addr,
+ uint32_t src_size, uint64_t dst_addr,
+ uint32_t *dst_size, uint8_t is_finalised,
+ uint32_t *mbox_error, uint32_t *send_id)
+{
+ int status;
+ int i;
+ uint32_t flag;
+ uint32_t crypto_header;
+ uint32_t payload[FCS_ECDSA_SHA2_DATA_SIGN_CMD_MAX_WORD_SIZE] = {0U};
+ uint32_t resp_len;
+
+ /* Source data must be 8 bytes aligned */
+ if ((dst_size == NULL) || (mbox_error == NULL ||
+ !is_8_bytes_aligned(src_size))) {
+ return INTEL_SIP_SMC_STATUS_REJECTED;
+ }
+
+ if (fcs_sha2_data_sign_param.session_id != session_id ||
+ fcs_sha2_data_sign_param.context_id != context_id) {
+ return INTEL_SIP_SMC_STATUS_REJECTED;
+ }
+
+ if (!is_address_in_ddr_range(src_addr, src_size) ||
+ !is_address_in_ddr_range(dst_addr, *dst_size)) {
+ return INTEL_SIP_SMC_STATUS_REJECTED;
+ }
+
+ resp_len = *dst_size / MBOX_WORD_BYTE;
+
+ /* Prepare crypto header */
+ flag = 0;
+ if (fcs_sha2_data_sign_param.is_updated) {
+ fcs_sha2_data_sign_param.crypto_param_size = 0;
+ } else {
+ flag |= FCS_CS_FIELD_FLAG_INIT;
+ }
+
+ if (is_finalised != 0U) {
+ flag |= FCS_CS_FIELD_FLAG_FINALIZE;
+ } else {
+ flag |= FCS_CS_FIELD_FLAG_UPDATE;
+ fcs_sha2_data_sign_param.is_updated = 1;
+ }
+ crypto_header = (flag << FCS_CS_FIELD_FLAG_OFFSET) |
+ fcs_sha2_data_sign_param.crypto_param_size;
+
+ /* Prepare command payload */
+ i = 0;
+ payload[i] = fcs_sha2_data_sign_param.session_id;
+ i++;
+ payload[i] = fcs_sha2_data_sign_param.context_id;
+ i++;
+ payload[i] = crypto_header;
+ i++;
+
+ if ((crypto_header >> FCS_CS_FIELD_FLAG_OFFSET) &
+ FCS_CS_FIELD_FLAG_INIT) {
+ payload[i] = fcs_sha2_data_sign_param.key_id;
+ /* Crypto parameters */
+ i++;
+ payload[i] = fcs_sha2_data_sign_param.crypto_param
+ & INTEL_SIP_SMC_FCS_ECC_ALGO_MASK;
+ i++;
+ }
+
+ /* Data source address and size */
+ payload[i] = src_addr;
+ i++;
+ payload[i] = src_size;
+ i++;
+
+ status = mailbox_send_cmd_async(send_id,
+ MBOX_FCS_ECDSA_SHA2_DATA_SIGN_REQ,
+ payload, i, CMD_INDIRECT);
+
+ if (is_finalised != 0U) {
+ memset((void *)&fcs_sha2_data_sign_param, 0,
+ sizeof(fcs_crypto_service_data));
+ }
+
+ if (status < 0) {
+ *mbox_error = -status;
+ return INTEL_SIP_SMC_STATUS_ERROR;
+ }
+
+ *dst_size = resp_len * MBOX_WORD_BYTE;
+ flush_dcache_range(dst_addr, *dst_size);
+
+ return INTEL_SIP_SMC_STATUS_OK;
+}
+
int intel_fcs_ecdsa_sha2_data_sig_verify_init(uint32_t session_id,
uint32_t context_id, uint32_t key_id,
uint32_t param_size, uint64_t param_data,
@@ -1469,6 +1784,121 @@
return INTEL_SIP_SMC_STATUS_OK;
}
+int intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize(uint32_t session_id,
+ uint32_t context_id, uint32_t src_addr,
+ uint32_t src_size, uint64_t dst_addr,
+ uint32_t *dst_size, uint32_t data_size,
+ uint8_t is_finalised, uint32_t *mbox_error,
+ uint32_t *send_id)
+{
+ int status;
+ uint32_t i;
+ uint32_t flag;
+ uint32_t crypto_header;
+ uint32_t payload[FCS_ECDSA_SHA2_DATA_SIG_VERIFY_CMD_MAX_WORD_SIZE] = {0U};
+ uint32_t resp_len;
+ uintptr_t sig_pubkey_offset;
+
+ /*
+ * Source data must be 4 bytes aligned
+ * Source addrress must be 8 bytes aligned
+ * User data must be 8 bytes aligned
+ */
+ if ((dst_size == NULL) || (mbox_error == NULL) ||
+ !is_size_4_bytes_aligned(src_size) ||
+ !is_8_bytes_aligned(src_addr) ||
+ !is_8_bytes_aligned(data_size)) {
+ return INTEL_SIP_SMC_STATUS_REJECTED;
+ }
+
+ if (fcs_sha2_data_sig_verify_param.session_id != session_id ||
+ fcs_sha2_data_sig_verify_param.context_id != context_id) {
+ return INTEL_SIP_SMC_STATUS_REJECTED;
+ }
+
+ if (!is_address_in_ddr_range(src_addr, src_size) ||
+ !is_address_in_ddr_range(dst_addr, *dst_size)) {
+ return INTEL_SIP_SMC_STATUS_REJECTED;
+ }
+
+ resp_len = *dst_size / MBOX_WORD_BYTE;
+
+ /* Prepare crypto header */
+ flag = 0;
+ if (fcs_sha2_data_sig_verify_param.is_updated)
+ fcs_sha2_data_sig_verify_param.crypto_param_size = 0;
+ else
+ flag |= FCS_CS_FIELD_FLAG_INIT;
+
+ if (is_finalised != 0U)
+ flag |= FCS_CS_FIELD_FLAG_FINALIZE;
+ else {
+ flag |= FCS_CS_FIELD_FLAG_UPDATE;
+ fcs_sha2_data_sig_verify_param.is_updated = 1;
+ }
+ crypto_header = (flag << FCS_CS_FIELD_FLAG_OFFSET) |
+ fcs_sha2_data_sig_verify_param.crypto_param_size;
+
+ /* Prepare command payload */
+ i = 0;
+ payload[i] = fcs_sha2_data_sig_verify_param.session_id;
+ i++;
+ payload[i] = fcs_sha2_data_sig_verify_param.context_id;
+ i++;
+ payload[i] = crypto_header;
+ i++;
+
+ if ((crypto_header >> FCS_CS_FIELD_FLAG_OFFSET) &
+ FCS_CS_FIELD_FLAG_INIT) {
+ payload[i] = fcs_sha2_data_sig_verify_param.key_id;
+ i++;
+ /* Crypto parameters */
+ payload[i] = fcs_sha2_data_sig_verify_param.crypto_param
+ & INTEL_SIP_SMC_FCS_ECC_ALGO_MASK;
+ i++;
+ }
+
+ /* Data source address and size */
+ payload[i] = src_addr;
+ i++;
+ payload[i] = data_size;
+ i++;
+
+ if ((crypto_header >> FCS_CS_FIELD_FLAG_OFFSET) &
+ FCS_CS_FIELD_FLAG_FINALIZE) {
+ /* Copy mac data to command
+ * Using dst_addr (physical address) to store sig_pubkey_offset
+ * sig_pubkey_offset is Signature + Public Key Data
+ */
+ sig_pubkey_offset = dst_addr;
+ memcpy((uint8_t *) &payload[i], (uint8_t *) sig_pubkey_offset,
+ src_size - data_size);
+
+ memset((void *)&dst_addr, 0, sizeof(dst_size));
+
+ i += (src_size - data_size) / MBOX_WORD_BYTE;
+ }
+
+ status = mailbox_send_cmd_async(send_id,
+ MBOX_FCS_ECDSA_SHA2_DATA_SIGN_VERIFY,
+ payload, i, CMD_INDIRECT);
+
+ if (is_finalised != 0U) {
+ memset((void *) &fcs_sha2_data_sig_verify_param, 0,
+ sizeof(fcs_crypto_service_data));
+ }
+
+ if (status < 0) {
+ *mbox_error = -status;
+ return INTEL_SIP_SMC_STATUS_ERROR;
+ }
+
+ *dst_size = resp_len * MBOX_WORD_BYTE;
+ flush_dcache_range(dst_addr, *dst_size);
+
+ return INTEL_SIP_SMC_STATUS_OK;
+}
+
int intel_fcs_ecdsa_get_pubkey_init(uint32_t session_id, uint32_t context_id,
uint32_t key_id, uint32_t param_size,
uint64_t param_data, uint32_t *mbox_error)
@@ -1620,6 +2050,29 @@
uint32_t key_id, uint64_t param_addr,
uint32_t param_size, uint32_t *mbox_error)
{
+ /* ptr to get param_addr value */
+ uint64_t *param_addr_ptr;
+
+ param_addr_ptr = (uint64_t *) param_addr;
+
+ /*
+ * Since crypto param size vary between mode.
+ * Check ECB here and limit to size 12 bytes
+ */
+ if (((*param_addr_ptr & FCS_CRYPTO_BLOCK_MODE_MASK) == FCS_CRYPTO_ECB_MODE) &&
+ (param_size > FCS_CRYPTO_ECB_BUFFER_SIZE)) {
+ return INTEL_SIP_SMC_STATUS_REJECTED;
+ }
+ /*
+ * Since crypto param size vary between mode.
+ * Check CBC/CTR here and limit to size 28 bytes
+ */
+ if ((((*param_addr_ptr & FCS_CRYPTO_BLOCK_MODE_MASK) == FCS_CRYPTO_CBC_MODE) ||
+ ((*param_addr_ptr & FCS_CRYPTO_BLOCK_MODE_MASK) == FCS_CRYPTO_CTR_MODE)) &&
+ (param_size > FCS_CRYPTO_CBC_CTR_BUFFER_SIZE)) {
+ return INTEL_SIP_SMC_STATUS_REJECTED;
+ }
+
if (mbox_error == NULL) {
return INTEL_SIP_SMC_STATUS_REJECTED;
}
diff --git a/plat/intel/soc/common/soc/socfpga_mailbox.c b/plat/intel/soc/common/soc/socfpga_mailbox.c
index d14ac9a..7010d81 100644
--- a/plat/intel/soc/common/soc/socfpga_mailbox.c
+++ b/plat/intel/soc/common/soc/socfpga_mailbox.c
@@ -10,6 +10,7 @@
#include "socfpga_mailbox.h"
#include "socfpga_sip_svc.h"
+#include "socfpga_system_manager.h"
static mailbox_payload_t mailbox_resp_payload;
static mailbox_container_t mailbox_resp_ctr = {0, 0, &mailbox_resp_payload};
@@ -464,8 +465,26 @@
void mailbox_set_qspi_direct(void)
{
+ uint32_t response[1], qspi_clk, reg;
+ unsigned int resp_len = ARRAY_SIZE(response);
+
mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_DIRECT, NULL, 0U,
- CMD_CASUAL, NULL, NULL);
+ CMD_CASUAL, response, &resp_len);
+
+ qspi_clk = response[0];
+ INFO("QSPI ref clock: %u\n", qspi_clk);
+
+ /*
+ * Store QSPI ref clock frequency in BOOT_SCRATCH_COLD_0 register for
+ * later boot loader (i.e. u-boot) use.
+ * The frequency is stored in kHz and occupies BOOT_SCRATCH_COLD_0
+ * register bits[27:0].
+ */
+ qspi_clk /= 1000;
+ reg = mmio_read_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_0));
+ reg &= ~SYSMGR_QSPI_REFCLK_MASK;
+ reg |= qspi_clk & SYSMGR_QSPI_REFCLK_MASK;
+ mmio_write_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_0), reg);
}
void mailbox_set_qspi_close(void)
@@ -590,6 +609,11 @@
}
res = response[RECONFIG_STATUS_STATE];
+
+ if (res == MBOX_CFGSTAT_VAB_BS_PREAUTH) {
+ return MBOX_CFGSTAT_STATE_CONFIG;
+ }
+
if ((res != 0U) && (res != MBOX_CFGSTAT_STATE_CONFIG)) {
return res;
}
diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c
index b57ab92..79f743f 100644
--- a/plat/intel/soc/common/socfpga_sip_svc.c
+++ b/plat/intel/soc/common/socfpga_sip_svc.c
@@ -344,6 +344,28 @@
case(0xF8011120): /* INTSTAT */
case(0xF8011124): /* DIAGINTTEST */
case(0xF801112C): /* DERRADDRA */
+ case(0xFA000000): /* SMMU SCR0 */
+ case(0xFA000004): /* SMMU SCR1 */
+ case(0xFA000400): /* SMMU NSCR0 */
+ case(0xFA004000): /* SMMU SSD0_REG */
+ case(0xFA000820): /* SMMU SMR8 */
+ case(0xFA000c20): /* SMMU SCR8 */
+ case(0xFA028000): /* SMMU CB8_SCTRL */
+ case(0xFA001020): /* SMMU CBAR8 */
+ case(0xFA028030): /* SMMU TCR_LPAE */
+ case(0xFA028020): /* SMMU CB8_TTBR0_LOW */
+ case(0xFA028024): /* SMMU CB8_PRRR_HIGH */
+ case(0xFA028038): /* SMMU CB8_PRRR_MIR0 */
+ case(0xFA02803C): /* SMMU CB8_PRRR_MIR1 */
+ case(0xFA028010): /* SMMU_CB8)TCR2 */
+ case(0xFFD080A4): /* SDM SMMU STREAM ID REG */
+ case(0xFA001820): /* SMMU_CBA2R8 */
+ case(0xFA000074): /* SMMU_STLBGSTATUS */
+ case(0xFA0287F4): /* SMMU_CB8_TLBSTATUS */
+ case(0xFA000060): /* SMMU_STLBIALL */
+ case(0xFA000070): /* SMMU_STLBGSYNC */
+ case(0xFA028618): /* CB8_TLBALL */
+ case(0xFA0287F0): /* CB8_TLBSYNC */
case(0xFFD12028): /* SDMMCGRP_CTRL */
case(0xFFD12044): /* EMAC0 */
case(0xFFD12048): /* EMAC1 */
@@ -589,7 +611,10 @@
*ret_size = resp_len * MBOX_WORD_BYTE;
flush_dcache_range(addr, *ret_size);
- if (status != MBOX_RET_OK) {
+ if (status == MBOX_RET_SDOS_DECRYPTION_ERROR_102 ||
+ status == MBOX_RET_SDOS_DECRYPTION_ERROR_103) {
+ *mbox_error = -status;
+ } else if (status != MBOX_RET_OK) {
*mbox_error = -status;
return INTEL_SIP_SMC_STATUS_ERROR;
}
@@ -927,6 +952,22 @@
&mbox_error);
SMC_RET4(handle, status, mbox_error, x5, x6);
+ case INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_UPDATE:
+ x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
+ x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
+ status = intel_fcs_get_digest_smmu_update_finalize(x1, x2, x3,
+ x4, x5, (uint32_t *) &x6, false,
+ &mbox_error, &send_id);
+ SMC_RET4(handle, status, mbox_error, x5, x6);
+
+ case INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_FINALIZE:
+ x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
+ x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
+ status = intel_fcs_get_digest_smmu_update_finalize(x1, x2, x3,
+ x4, x5, (uint32_t *) &x6, true,
+ &mbox_error, &send_id);
+ SMC_RET4(handle, status, mbox_error, x5, x6);
+
case INTEL_SIP_SMC_FCS_MAC_VERIFY_INIT:
x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
status = intel_fcs_mac_verify_init(x1, x2, x3,
@@ -951,6 +992,24 @@
true, &mbox_error);
SMC_RET4(handle, status, mbox_error, x5, x6);
+ case INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_UPDATE:
+ x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
+ x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
+ x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
+ status = intel_fcs_mac_verify_smmu_update_finalize(x1, x2, x3,
+ x4, x5, (uint32_t *) &x6, x7,
+ false, &mbox_error, &send_id);
+ SMC_RET4(handle, status, mbox_error, x5, x6);
+
+ case INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_FINALIZE:
+ x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
+ x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
+ x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
+ status = intel_fcs_mac_verify_smmu_update_finalize(x1, x2, x3,
+ x4, x5, (uint32_t *) &x6, x7,
+ true, &mbox_error, &send_id);
+ SMC_RET4(handle, status, mbox_error, x5, x6);
+
case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_INIT:
x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
status = intel_fcs_ecdsa_sha2_data_sign_init(x1, x2, x3,
@@ -973,6 +1032,22 @@
&mbox_error);
SMC_RET4(handle, status, mbox_error, x5, x6);
+ case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_UPDATE:
+ x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
+ x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
+ status = intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(x1,
+ x2, x3, x4, x5, (uint32_t *) &x6, false,
+ &mbox_error, &send_id);
+ SMC_RET4(handle, status, mbox_error, x5, x6);
+
+ case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_FINALIZE:
+ x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
+ x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
+ status = intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(x1,
+ x2, x3, x4, x5, (uint32_t *) &x6, true,
+ &mbox_error, &send_id);
+ SMC_RET4(handle, status, mbox_error, x5, x6);
+
case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_INIT:
x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
status = intel_fcs_ecdsa_hash_sign_init(x1, x2, x3,
@@ -1014,6 +1089,24 @@
x7, false, &mbox_error);
SMC_RET4(handle, status, mbox_error, x5, x6);
+ case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_UPDATE:
+ x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
+ x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
+ x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
+ status = intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize(
+ x1, x2, x3, x4, x5, (uint32_t *) &x6,
+ x7, false, &mbox_error, &send_id);
+ SMC_RET4(handle, status, mbox_error, x5, x6);
+
+ case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_FINALIZE:
+ x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
+ x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
+ x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
+ status = intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize(
+ x1, x2, x3, x4, x5, (uint32_t *) &x6,
+ x7, true, &mbox_error, &send_id);
+ SMC_RET4(handle, status, mbox_error, x5, x6);
+
case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE:
x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
diff --git a/plat/mediatek/build_helpers/options.mk b/plat/mediatek/build_helpers/options.mk
index 0279648..128b14f 100644
--- a/plat/mediatek/build_helpers/options.mk
+++ b/plat/mediatek/build_helpers/options.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2022, MediaTek Inc. All rights reserved.
+# Copyright (c) 2022-2023, MediaTek Inc. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -23,3 +23,4 @@
$(eval $(call add_defined_option,CONFIG_MTK_CPU_SUSPEND_EN))
$(eval $(call add_defined_option,CONFIG_MTK_PM_ARCH))
$(eval $(call add_defined_option,CONFIG_MTK_CPU_PM_ARCH))
+$(eval $(call add_defined_option,CONFIG_MTK_SUPPORT_SYSTEM_SUSPEND))
diff --git a/plat/mediatek/common/lpm/mt_lp_api.c b/plat/mediatek/common/lpm/mt_lp_api.c
new file mode 100644
index 0000000..2a1da6a
--- /dev/null
+++ b/plat/mediatek/common/lpm/mt_lp_api.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <lpm/mt_lp_api.h>
+
+int mt_audio_update(int type)
+{
+ int ret, val;
+
+ switch (type) {
+ case AUDIO_AFE_ENTER:
+ case AUDIO_AFE_LEAVE:
+ val = (type == AUDIO_AFE_ENTER) ? 1 : 0;
+ ret = mt_lp_rm_do_update(-1, PLAT_RC_IS_FMAUDIO, &val);
+ break;
+ case AUDIO_DSP_ENTER:
+ case AUDIO_DSP_LEAVE:
+ val = (type == AUDIO_DSP_ENTER) ? 1 : 0;
+ ret = mt_lp_rm_do_update(-1, PLAT_RC_IS_ADSP, &val);
+ break;
+ default:
+ ret = -1;
+ break;
+ }
+
+ return ret;
+}
+
+int mtk_usb_update(int type)
+{
+ int ret, val;
+
+ switch (type) {
+ case LPM_USB_ENTER:
+ case LPM_USB_LEAVE:
+ val = (type == LPM_USB_ENTER) ? 1 : 0;
+ ret = mt_lp_rm_do_update(-1, PLAT_RC_IS_USB_INFRA, &val);
+ break;
+ default:
+ ret = -1;
+ break;
+ }
+
+ return ret;
+}
diff --git a/plat/mediatek/common/lpm/mt_lp_rm.c b/plat/mediatek/common/lpm/mt_lp_rm.c
index 0bafc66..9f07968 100644
--- a/plat/mediatek/common/lpm/mt_lp_rm.c
+++ b/plat/mediatek/common/lpm/mt_lp_rm.c
@@ -1,11 +1,11 @@
/*
- * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2020-2023, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
-#include <mt_lp_rm.h>
#include <stddef.h>
+#include <lpm/mt_lp_rm.h>
struct platform_mt_resource_manager {
unsigned int count;
@@ -36,12 +36,11 @@
return MT_RM_STATUS_OK;
}
-int mt_lp_rm_reset_constraint(int idx, unsigned int cpuid, int stateid)
+int mt_lp_rm_reset_constraint(unsigned int idx, unsigned int cpuid, int stateid)
{
struct mt_resource_constraint const *rc = NULL;
- if ((plat_mt_rm.plat_rm == NULL) || (idx < 0) ||
- (idx >= plat_mt_rm.count)) {
+ if ((plat_mt_rm.plat_rm == NULL) || (idx >= plat_mt_rm.count)) {
return MT_RM_STATUS_BAD;
}
@@ -54,39 +53,92 @@
return rc->reset(cpuid, stateid);
}
-int mt_lp_rm_find_and_run_constraint(int idx, unsigned int cpuid,
- int stateid, void *priv)
+int mt_lp_rm_get_status(unsigned int type, void *priv)
+{
+ int res = 0;
+ struct mt_resource_constraint *const *con;
+ struct mt_resource_manager *rm = plat_mt_rm.plat_rm;
+
+ if ((rm == NULL) || (type >= PLAT_RC_MAX)) {
+ return -1;
+ }
+
+ for (con = rm->consts; *con != NULL; con++) {
+ if ((*con)->get_status == NULL) {
+ continue;
+ }
+ res = (*con)->get_status(type, priv);
+ if (res == MT_RM_STATUS_STOP) {
+ break;
+ }
+ }
+
+ return res;
+}
+
+int mt_lp_rm_do_constraint(unsigned int constraint_id, unsigned int cpuid, int stateid)
+{
+ int res = MT_RM_STATUS_BAD;
+ struct mt_resource_constraint const *rc;
+ struct mt_resource_manager *rm = plat_mt_rm.plat_rm;
+
+ if ((rm == NULL) || (constraint_id >= plat_mt_rm.count)) {
+ return res;
+ }
+
+ rc = rm->consts[constraint_id];
+ if ((rc != NULL) && (rc->run != NULL)) {
+ res = rc->run(cpuid, stateid);
+ }
+
+ return res;
+}
+
+int mt_lp_rm_find_constraint(unsigned int idx, unsigned int cpuid,
+ int stateid, void *priv)
{
- int i, res = MT_RM_STATUS_BAD;
+ unsigned int i;
+ int res = MT_RM_STATUS_BAD;
struct mt_resource_constraint *const *rc;
struct mt_resource_manager *rm = plat_mt_rm.plat_rm;
- if ((rm == NULL) || (idx < 0) || (idx >= plat_mt_rm.count)) {
+ if ((rm == NULL) || (idx >= plat_mt_rm.count)) {
return res;
}
/* If subsys clk/mtcmos is on, add block-resource-off flag */
if (rm->update != NULL) {
- res = rm->update(rm->consts, stateid, priv);
+ res = rm->update(rm->consts, plat_mt_rm.count, stateid, priv);
if (res != 0) {
- return res;
+ return MT_RM_STATUS_BAD;
}
}
+ res = MT_RM_STATUS_BAD;
for (i = idx, rc = (rm->consts + idx); *rc != NULL; i++, rc++) {
if (((*rc)->is_valid != NULL) &&
((*rc)->is_valid(cpuid, stateid))) {
- if (((*rc)->run != NULL) &&
- ((*rc)->run(cpuid, stateid) == 0)) {
- res = i;
- break;
- }
+ res = i;
+ break;
}
}
return res;
}
+int mt_lp_rm_find_and_run_constraint(unsigned int idx, unsigned int cpuid,
+ int stateid, void *priv)
+{
+ int res = MT_RM_STATUS_BAD;
+
+ res = mt_lp_rm_find_constraint(idx, cpuid, stateid, priv);
+ if (res != MT_RM_STATUS_BAD) {
+ mt_lp_rm_do_constraint(res, cpuid, stateid);
+ }
+
+ return res;
+}
+
int mt_lp_rm_do_update(int stateid, int type, void const *p)
{
int res = MT_RM_STATUS_BAD;
diff --git a/plat/mediatek/common/lpm/mt_lp_rm.h b/plat/mediatek/common/lpm/mt_lp_rm.h
deleted file mode 100644
index e93dac3..0000000
--- a/plat/mediatek/common/lpm/mt_lp_rm.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef MT_LP_RM_H
-#define MT_LP_RM_H
-
-#include <stdbool.h>
-
-#define MT_RM_STATUS_OK 0
-#define MT_RM_STATUS_BAD -1
-
-enum PLAT_MT_LPM_RC_TYPE {
- PLAT_RC_UPDATE_CONDITION,
- PLAT_RC_UPDATE_REMAIN_IRQS
-};
-
-struct mt_resource_constraint {
- int level;
- int (*init)(void);
- bool (*is_valid)(unsigned int cpu, int stateid);
- int (*update)(int stateid, int type, const void *p);
- int (*run)(unsigned int cpu, int stateid);
- int (*reset)(unsigned int cpu, int stateid);
- unsigned int (*allow)(int stateid);
-};
-
-struct mt_resource_manager {
- int (*update)(struct mt_resource_constraint **con,
- int stateid, void *priv);
- struct mt_resource_constraint **consts;
-};
-
-extern int mt_lp_rm_register(struct mt_resource_manager *rm);
-extern int mt_lp_rm_find_and_run_constraint(int idx, unsigned int cpuid,
- int stateid, void *priv);
-extern int mt_lp_rm_reset_constraint(int constraint_id, unsigned int cpuid,
- int stateid);
-extern int mt_lp_rm_do_update(int stateid, int type, void const *p);
-#endif /* MT_LP_RM_H */
diff --git a/plat/mediatek/common/lpm/mt_lp_rq.c b/plat/mediatek/common/lpm/mt_lp_rq.c
new file mode 100644
index 0000000..7b83fed
--- /dev/null
+++ b/plat/mediatek/common/lpm/mt_lp_rq.c
@@ -0,0 +1,204 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <common/debug.h>
+#include <drivers/console.h>
+#include <lib/spinlock.h>
+#include <lpm/mt_lp_rqm.h>
+
+struct mt_lp_res_req_m {
+ unsigned int uname[MT_LP_RQ_USER_MAX];
+ unsigned int user_num;
+ unsigned int user_valid;
+ unsigned int resource_num;
+ unsigned int generic_resource_req;
+ unsigned int flag;
+ struct mt_resource_req_manager *plat_rqm;
+};
+
+static struct mt_lp_res_req_m plat_mt_rqm;
+static spinlock_t mt_lp_rq_lock;
+
+static int mt_lp_resource_request(struct mt_lp_resource_user *this, unsigned int resource)
+{
+ int i;
+ struct mt_lp_res_req *const *rs;
+
+ if ((this == NULL) || (resource == 0) || (resource > MT_LP_RQ_ALL)) {
+ ERROR("invalid request(%x)\n", resource);
+ return MT_LP_RQ_STA_BAD;
+ }
+
+ spin_lock(&mt_lp_rq_lock);
+
+ rs = (plat_mt_rqm.plat_rqm)->res;
+ for (i = 0; i < plat_mt_rqm.resource_num; i++) {
+ if ((resource & rs[i]->res_id) != 0) {
+ rs[i]->res_usage |= this->umask;
+ }
+ }
+
+ plat_mt_rqm.flag = MT_LP_RQ_FLAG_NEED_UPDATE;
+ spin_unlock(&mt_lp_rq_lock);
+
+ return MT_LP_RQ_STA_OK;
+}
+
+static int mt_lp_resource_release(struct mt_lp_resource_user *this)
+{
+ int i;
+ struct mt_lp_res_req *const *rs;
+
+ if (this == NULL) {
+ return MT_LP_RQ_STA_BAD;
+ }
+
+ spin_lock(&mt_lp_rq_lock);
+
+ rs = (plat_mt_rqm.plat_rqm)->res;
+ for (i = 0; i < plat_mt_rqm.resource_num; i++) {
+ rs[i]->res_usage &= ~(this->umask);
+ }
+
+ plat_mt_rqm.flag = MT_LP_RQ_FLAG_NEED_UPDATE;
+ spin_unlock(&mt_lp_rq_lock);
+
+ return MT_LP_RQ_STA_OK;
+}
+
+int mt_lp_resource_request_manager_register(struct mt_resource_req_manager *rqm)
+{
+ unsigned int count;
+ struct mt_lp_res_req *const *rs;
+
+ if ((rqm == NULL) || (rqm->res == NULL) || (plat_mt_rqm.plat_rqm != NULL)) {
+ return MT_LP_RQ_STA_BAD;
+ }
+
+ rs = rqm->res;
+ count = 0;
+ while (*rs != NULL) {
+ count++;
+ rs++;
+ }
+
+ plat_mt_rqm.plat_rqm = rqm;
+ plat_mt_rqm.resource_num = count;
+
+ return MT_LP_RQ_STA_OK;
+}
+
+int mt_lp_resource_user_register(char *user, struct mt_lp_resource_user *ru)
+{
+ int i, len;
+ unsigned int uname;
+
+ if ((plat_mt_rqm.plat_rqm == NULL) || (plat_mt_rqm.user_num >= MT_LP_RQ_USER_MAX) ||
+ (user == NULL)) {
+ ru->uid = MT_LP_RQ_USER_INVALID;
+ ru->umask = 0;
+ ru->request = NULL;
+ ru->release = NULL;
+ ERROR("rqm register user invalid\n");
+ return MT_LP_RQ_STA_BAD;
+ }
+
+ len = strnlen(user, MT_LP_RQ_USER_NAME_LEN);
+
+ uname = 0;
+ for (i = 0; i < len; i++) {
+ uname |= (user[i] << (MT_LP_RQ_USER_CHAR_U * i));
+ }
+
+ spin_lock(&mt_lp_rq_lock);
+ i = plat_mt_rqm.user_num;
+ plat_mt_rqm.user_num += 1;
+ plat_mt_rqm.uname[i] = uname;
+ plat_mt_rqm.user_valid |= BIT(i);
+ spin_unlock(&mt_lp_rq_lock);
+
+ ru->umask = BIT(i);
+ ru->uid = i;
+ ru->request = mt_lp_resource_request;
+ ru->release = mt_lp_resource_release;
+ INFO("%s register by %s, uid = %d\n", __func__, user, ru->uid);
+
+ return MT_LP_RQ_STA_OK;
+}
+
+int mt_lp_rq_get_status(int type, void *p)
+{
+ int i;
+ unsigned int update_sta;
+ struct mt_lp_res_req *const *rs;
+ struct resource_req_status *rq_sta = (struct resource_req_status *)p;
+
+ if (plat_mt_rqm.flag != 0) {
+ spin_lock(&mt_lp_rq_lock);
+
+ update_sta = 0;
+ rs = (plat_mt_rqm.plat_rqm)->res;
+ for (i = 0; i < plat_mt_rqm.resource_num; i++) {
+ update_sta |= ((rs[i]->res_usage & plat_mt_rqm.user_valid) != 0) ?
+ rs[i]->res_rq : 0;
+ }
+
+ plat_mt_rqm.generic_resource_req = update_sta;
+ plat_mt_rqm.flag = MT_LP_RQ_FLAG_DONE;
+ spin_unlock(&mt_lp_rq_lock);
+ }
+
+ switch (type) {
+ case PLAT_RQ_REQ_USAGE:
+ rs = (plat_mt_rqm.plat_rqm)->res;
+ rq_sta->val = (rq_sta->id < plat_mt_rqm.resource_num) ?
+ rs[rq_sta->id]->res_usage : plat_mt_rqm.generic_resource_req;
+ break;
+ case PLAT_RQ_USER_NUM:
+ rq_sta->val = plat_mt_rqm.user_num;
+ break;
+ case PLAT_RQ_USER_VALID:
+ rq_sta->val = plat_mt_rqm.user_valid;
+ break;
+ case PLAT_RQ_PER_USER_NAME:
+ rq_sta->val = (rq_sta->id < plat_mt_rqm.user_num) ?
+ plat_mt_rqm.uname[rq_sta->id] : 0;
+ break;
+ case PLAT_RQ_REQ_NUM:
+ rq_sta->val = plat_mt_rqm.resource_num;
+ break;
+ default:
+ break;
+ }
+
+ return MT_LP_RQ_STA_OK;
+}
+
+int mt_lp_rq_update_status(int type, void *p)
+{
+ unsigned int user_mask;
+ struct resource_req_status *rq_sta = (struct resource_req_status *)p;
+
+ switch (type) {
+ case PLAT_RQ_USER_VALID:
+ if (rq_sta->id < plat_mt_rqm.user_num) {
+ user_mask = BIT(rq_sta->id);
+ spin_lock(&mt_lp_rq_lock);
+ plat_mt_rqm.user_valid = (rq_sta->val == 0) ?
+ (plat_mt_rqm.user_valid & ~(user_mask)) :
+ (plat_mt_rqm.user_valid | user_mask);
+ plat_mt_rqm.flag = MT_LP_RQ_FLAG_NEED_UPDATE;
+ spin_unlock(&mt_lp_rq_lock);
+ }
+ break;
+ default:
+ break;
+ }
+
+ return MT_LP_RQ_STA_OK;
+}
diff --git a/plat/mediatek/common/lpm/rules.mk b/plat/mediatek/common/lpm/rules.mk
index 87a212a..eb68e03 100644
--- a/plat/mediatek/common/lpm/rules.mk
+++ b/plat/mediatek/common/lpm/rules.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2022, MediaTek Inc. All rights reserved.
+# Copyright (c) 2023, MediaTek Inc. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -7,7 +7,10 @@
LOCAL_DIR := $(call GET_LOCAL_DIR)
MODULE := lpm
-LOCAL_SRCS-y := $(LOCAL_DIR)/mt_lp_rm.c
+
+LOCAL_SRCS-y := $(LOCAL_DIR)/mt_lp_api.c
+LOCAL_SRCS-y += $(LOCAL_DIR)/mt_lp_rm.c
+LOCAL_SRCS-y += $(LOCAL_DIR)/mt_lp_rq.c
PLAT_INCLUDES += -I${LOCAL_DIR}
diff --git a/plat/mediatek/common/mtk_smc_handlers.c b/plat/mediatek/common/mtk_smc_handlers.c
index 51a960f..92b3873 100644
--- a/plat/mediatek/common/mtk_smc_handlers.c
+++ b/plat/mediatek/common/mtk_smc_handlers.c
@@ -51,6 +51,7 @@
x3 = x3 & MASK_32_BIT; \
x4 = x4 & MASK_32_BIT; \
} \
+ /* fallthrough */ \
case _smc_id##_AARCH64: \
{ \
if (_smc_id##_descriptor_index < 0) { \
diff --git a/plat/mediatek/drivers/cpu_pm/cpcv3_2/mt_cpu_pm.c b/plat/mediatek/drivers/cpu_pm/cpcv3_2/mt_cpu_pm.c
index 313ad47..6281cc0 100644
--- a/plat/mediatek/drivers/cpu_pm/cpcv3_2/mt_cpu_pm.c
+++ b/plat/mediatek/drivers/cpu_pm/cpcv3_2/mt_cpu_pm.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2022-2023, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -11,10 +11,10 @@
#include <lib/mtk_init/mtk_init.h>
#include <lib/pm/mtk_pm.h>
+#include <lpm/mt_lp_rm.h>
#include "mt_cpu_pm.h"
#include "mt_cpu_pm_cpc.h"
#include "mt_cpu_pm_mbox.h"
-#include <mt_lp_rm.h>
#include "mt_smp.h"
#include <mtk_mmap_pool.h>
#include <platform_def.h>
diff --git a/plat/mediatek/drivers/iommu/mtk_iommu_smc.c b/plat/mediatek/drivers/iommu/mtk_iommu_smc.c
index 9762d0b..e998725 100644
--- a/plat/mediatek/drivers/iommu/mtk_iommu_smc.c
+++ b/plat/mediatek/drivers/iommu/mtk_iommu_smc.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2022-2023, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -75,25 +75,32 @@
return MTK_SIP_E_SUCCESS;
}
-static int mtk_infra_master_config_sec(uint32_t dev_id, uint32_t enable)
+static int mtk_infra_master_config_sec(uint32_t dev_id_msk, uint32_t enable)
{
const struct mtk_ifr_mst_config *ifr_cfg;
- uint32_t reg_addr;
+ uint32_t dev_id, reg_addr, reg_mask;
mtk_infra_iommu_enable_protect();
- if (dev_id >= MMU_DEV_NUM) {
- return MTK_SIP_E_NOT_SUPPORTED;
+ if (dev_id_msk >= BIT(MMU_DEV_NUM)) {
+ return MTK_SIP_E_INVALID_PARAM;
}
- ifr_cfg = &g_ifr_mst_cfg[dev_id];
- reg_addr = g_ifr_mst_cfg_base[(ifr_cfg->cfg_addr_idx)] +
- g_ifr_mst_cfg_offs[(ifr_cfg->cfg_addr_idx)];
+ for (dev_id = 0U; dev_id < MMU_DEV_NUM; dev_id++) {
+ if ((dev_id_msk & BIT(dev_id)) == 0U) {
+ continue;
+ }
- if (enable > 0U) {
- mmio_setbits_32(reg_addr, IFR_CFG_MMU_EN_MSK(ifr_cfg->r_mmu_en_bit));
- } else {
- mmio_clrbits_32(reg_addr, IFR_CFG_MMU_EN_MSK(ifr_cfg->r_mmu_en_bit));
+ ifr_cfg = &g_ifr_mst_cfg[dev_id];
+ reg_addr = g_ifr_mst_cfg_base[(ifr_cfg->cfg_addr_idx)] +
+ g_ifr_mst_cfg_offs[(ifr_cfg->cfg_addr_idx)];
+ reg_mask = IFR_CFG_MMU_EN_MSK(ifr_cfg->r_mmu_en_bit);
+
+ if (enable > 0U) {
+ mmio_setbits_32(reg_addr, reg_mask);
+ } else {
+ mmio_clrbits_32(reg_addr, reg_mask);
+ }
}
return MTK_SIP_E_SUCCESS;
diff --git a/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_api.c b/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_api.c
new file mode 100644
index 0000000..257caa3
--- /dev/null
+++ b/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_api.c
@@ -0,0 +1,171 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <lpm/mt_lpm_smc.h>
+#include <mt_spm.h>
+#include "mt_spm_rc_api.h"
+#include "mt_spm_rc_internal.h"
+
+int spm_rc_condition_modifier(unsigned int id, unsigned int act,
+ const void *val,
+ enum mt_spm_rm_rc_type dest_rc_id,
+ struct mt_spm_cond_tables * const tlb)
+{
+ unsigned int rc_id, cond_id, cond;
+ int res = 0;
+
+ spin_lock(&spm_lock);
+ rc_id = SPM_RC_UPDATE_COND_RC_ID_GET(id);
+ cond_id = SPM_RC_UPDATE_COND_ID_GET(id);
+
+ do {
+ if ((dest_rc_id != rc_id) || (val == NULL) || (tlb == NULL)) {
+ res = -1;
+ break;
+ }
+
+ cond = *((unsigned int *)val);
+
+ if (cond_id < PLAT_SPM_COND_MAX) {
+ if ((act & MT_LPM_SMC_ACT_SET) > 0U) {
+ SPM_RC_BITS_SET(tlb->table_cg[cond_id], cond);
+ } else if ((act & MT_LPM_SMC_ACT_CLR) > 0U) {
+ SPM_RC_BITS_CLR(tlb->table_cg[cond_id], cond);
+ } else {
+ res = -1;
+ }
+ } else if ((cond_id - PLAT_SPM_COND_MAX) < PLAT_SPM_COND_PLL_MAX) {
+ unsigned int pll_idx = cond_id - PLAT_SPM_COND_MAX;
+
+ cond = !!cond;
+ if ((act & MT_LPM_SMC_ACT_SET) > 0U) {
+ SPM_RC_BITS_SET(tlb->table_pll, (cond << pll_idx));
+ } else if ((act & MT_LPM_SMC_ACT_CLR) > 0U) {
+ SPM_RC_BITS_CLR(tlb->table_pll, (cond << pll_idx));
+ } else {
+ res = -1;
+ }
+ } else {
+ res = -1;
+ }
+ } while (0);
+
+ spin_unlock(&spm_lock);
+
+ return res;
+}
+
+int spm_rc_constraint_status_get(unsigned int id, unsigned int type,
+ unsigned int act,
+ enum mt_spm_rm_rc_type dest_rc_id,
+ struct constraint_status * const src,
+ struct constraint_status * const dest)
+{
+ if (((id != MT_RM_CONSTRAINT_ID_ALL) && (id != dest_rc_id)) || (dest == NULL) ||
+ (src == NULL)) {
+ return -1;
+ }
+ spin_lock(&spm_lock);
+
+ switch (type) {
+ case CONSTRAINT_GET_ENTER_CNT:
+ if (id == MT_RM_CONSTRAINT_ID_ALL) {
+ dest->enter_cnt += src->enter_cnt;
+ } else {
+ dest->enter_cnt = src->enter_cnt;
+ }
+ break;
+ case CONSTRAINT_GET_VALID:
+ dest->is_valid = src->is_valid;
+ break;
+ case CONSTRAINT_COND_BLOCK:
+ dest->is_cond_block = src->is_cond_block;
+ dest->all_pll_dump = src->all_pll_dump;
+ break;
+ case CONSTRAINT_GET_COND_BLOCK_DETAIL:
+ dest->cond_res = src->cond_res;
+ break;
+ case CONSTRAINT_GET_RESIDNECY:
+ dest->residency = src->residency;
+ if (act & MT_LPM_SMC_ACT_CLR) {
+ src->residency = 0;
+ }
+ break;
+ default:
+ break;
+ }
+
+ spin_unlock(&spm_lock);
+ return 0;
+}
+
+int spm_rc_constraint_status_set(unsigned int id, unsigned int type,
+ unsigned int act,
+ enum mt_spm_rm_rc_type dest_rc_id,
+ struct constraint_status * const src,
+ struct constraint_status * const dest)
+{
+ if (((id != MT_RM_CONSTRAINT_ID_ALL) && (id != dest_rc_id)) || (dest == NULL)) {
+ return -1;
+ }
+
+ spin_lock(&spm_lock);
+
+ switch (type) {
+ case CONSTRAINT_UPDATE_VALID:
+ if (src != NULL) {
+ if ((act & MT_LPM_SMC_ACT_SET) > 0U) {
+ SPM_RC_BITS_SET(dest->is_valid, src->is_valid);
+ } else if ((act & MT_LPM_SMC_ACT_CLR) > 0U) {
+ SPM_RC_BITS_CLR(dest->is_valid, src->is_valid);
+ }
+ }
+ break;
+ case CONSTRAINT_RESIDNECY:
+ if (act & MT_LPM_SMC_ACT_CLR) {
+ dest->residency = 0;
+ }
+ break;
+ default:
+ break;
+ }
+
+ spin_unlock(&spm_lock);
+
+ return 0;
+}
+
+int spm_rc_constraint_valid_set(enum mt_spm_rm_rc_type id,
+ enum mt_spm_rm_rc_type dest_rc_id,
+ unsigned int valid,
+ struct constraint_status * const dest)
+{
+ if (((id != MT_RM_CONSTRAINT_ID_ALL) && (id != dest_rc_id)) || (dest == NULL)) {
+ return -1;
+ }
+
+ spin_lock(&spm_lock);
+ SPM_RC_BITS_SET(dest->is_valid, valid);
+ spin_unlock(&spm_lock);
+
+ return 0;
+}
+
+int spm_rc_constraint_valid_clr(enum mt_spm_rm_rc_type id,
+ enum mt_spm_rm_rc_type dest_rc_id,
+ unsigned int valid,
+ struct constraint_status * const dest)
+{
+ if (((id != MT_RM_CONSTRAINT_ID_ALL) && (id != dest_rc_id)) || (dest == NULL)) {
+ return -1;
+ }
+
+ spin_lock(&spm_lock);
+ SPM_RC_BITS_CLR(dest->is_valid, valid);
+ spin_unlock(&spm_lock);
+
+ return 0;
+}
diff --git a/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_api.h b/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_api.h
new file mode 100644
index 0000000..0736ca3
--- /dev/null
+++ b/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_api.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_RC_API_H
+#define MT_SPM_RC_API_H
+
+#include <mt_spm.h>
+#include <mt_spm_cond.h>
+#include <mt_spm_constraint.h>
+#include <mt_spm_internal.h>
+
+#define SPM_RC_BITS_SET(dest, src) ({ (dest) |= (src); })
+#define SPM_RC_BITS_CLR(dest, src) ({ (dest) &= (~src); })
+
+int spm_rc_condition_modifier(unsigned int id, unsigned int act,
+ const void *val,
+ enum mt_spm_rm_rc_type dest_rc_id,
+ struct mt_spm_cond_tables * const tlb);
+
+int spm_rc_constraint_status_get(unsigned int id, unsigned int type,
+ unsigned int act,
+ enum mt_spm_rm_rc_type dest_rc_id,
+ struct constraint_status * const src,
+ struct constraint_status * const dest);
+
+int spm_rc_constraint_status_set(unsigned int id, unsigned int type,
+ unsigned int act,
+ enum mt_spm_rm_rc_type dest_rc_id,
+ struct constraint_status * const src,
+ struct constraint_status * const dest);
+
+int spm_rc_constraint_valid_set(enum mt_spm_rm_rc_type id,
+ enum mt_spm_rm_rc_type dest_rc_id,
+ unsigned int valid,
+ struct constraint_status * const dest);
+
+int spm_rc_constraint_valid_clr(enum mt_spm_rm_rc_type id,
+ enum mt_spm_rm_rc_type dest_rc_id,
+ unsigned int valid,
+ struct constraint_status * const dest);
+
+#endif
diff --git a/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_bus26m.c b/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_bus26m.c
new file mode 100644
index 0000000..0b792ab
--- /dev/null
+++ b/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_bus26m.c
@@ -0,0 +1,397 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#ifndef MTK_PLAT_CIRQ_UNSUPPORT
+#include <mtk_cirq.h>
+#endif
+#include <drivers/spm/mt_spm_resource_req.h>
+#include <lib/pm/mtk_pm.h>
+#include <lpm/mt_lp_rm.h>
+#include <mt_spm.h>
+#include <mt_spm_cond.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_constraint.h>
+#include <mt_spm_idle.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_notifier.h>
+#include "mt_spm_rc_api.h"
+#include "mt_spm_rc_internal.h"
+#include <mt_spm_reg.h>
+#include <mt_spm_suspend.h>
+
+#define CONSTRAINT_BUS26M_ALLOW (MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF | \
+ MT_RM_CONSTRAINT_ALLOW_DRAM_S0 | \
+ MT_RM_CONSTRAINT_ALLOW_DRAM_S1 | \
+ MT_RM_CONSTRAINT_ALLOW_VCORE_LP | \
+ MT_RM_CONSTRAINT_ALLOW_LVTS_STATE | \
+ MT_RM_CONSTRAINT_ALLOW_BUS26M_OFF)
+
+#define CONSTRAINT_BUS26M_PCM_FLAG (SPM_FLAG_DISABLE_INFRA_PDN | \
+ SPM_FLAG_DISABLE_VCORE_DVS | \
+ SPM_FLAG_DISABLE_VCORE_DFS | \
+ SPM_FLAG_SRAM_SLEEP_CTRL | \
+ SPM_FLAG_ENABLE_LVTS_WORKAROUND | \
+ SPM_FLAG_KEEP_CSYSPWRACK_HIGH | \
+ SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP)
+
+#define CONSTRAINT_BUS26M_PCM_FLAG1 (SPM_FLAG1_DISABLE_PWRAP_CLK_SWITCH)
+
+/* If sspm sram won't enter sleep voltage then vcore couldn't enter low power mode */
+#if defined(MTK_PLAT_SPM_SRAM_SLP_UNSUPPORT) && SPM_SRAM_SLEEP_RC_RES_RESTRICT
+#define CONSTRAINT_BUS26M_RESOURCE_REQ (MT_SPM_26M)
+#else
+#define CONSTRAINT_BUS26M_RESOURCE_REQ (0)
+#endif
+
+static unsigned int bus26m_ext_opand;
+static unsigned int bus26m_ext_opand2;
+
+static struct mt_irqremain *refer2remain_irq;
+
+static struct mt_spm_cond_tables cond_bus26m = {
+ .table_cg = {
+ 0xFF5DD002, /* MTCMOS1 */
+ 0x0000003C, /* MTCMOS2 */
+ 0x27AF8000, /* INFRA0 */
+ 0x22010876, /* INFRA1 */
+ 0x86000650, /* INFRA2 */
+ 0x30008020, /* INFRA3 */
+ 0x80000000, /* INFRA4 */
+ 0x01002A3B, /* PERI0 */
+ 0x00090000, /* VPPSYS0_0 */
+ 0x38FF3E69, /* VPPSYS0_1 */
+ 0xF0081450, /* VPPSYS1_0 */
+ 0x00003000, /* VPPSYS1_1 */
+ 0x00000000, /* VDOSYS0_0 */
+ 0x00000000, /* VDOSYS0_1 */
+ 0x000001FF, /* VDOSYS1_0 */
+ 0x000001E0, /* VDOSYS1_1 */
+ 0x00FB0007, /* VDOSYS1_2 */
+ },
+ .table_pll = (PLL_BIT_UNIVPLL |
+ PLL_BIT_MFGPLL |
+ PLL_BIT_MSDCPLL |
+ PLL_BIT_TVDPLL1 |
+ PLL_BIT_TVDPLL2 |
+ PLL_BIT_MMPLL |
+ PLL_BIT_ETHPLL |
+ PLL_BIT_IMGPLL |
+ PLL_BIT_APLL1 |
+ PLL_BIT_APLL2 |
+ PLL_BIT_APLL3 |
+ PLL_BIT_APLL4 |
+ PLL_BIT_APLL5),
+};
+
+static struct mt_spm_cond_tables cond_bus26m_res = {
+ .table_cg = { 0U },
+ .table_pll = 0U,
+};
+
+static struct constraint_status status = {
+ .id = MT_RM_CONSTRAINT_ID_BUS26M,
+ .is_valid = (MT_SPM_RC_VALID_SW |
+ MT_SPM_RC_VALID_COND_CHECK |
+ MT_SPM_RC_VALID_COND_LATCH |
+ MT_SPM_RC_VALID_TRACE_TIME),
+ .is_cond_block = 0U,
+ .enter_cnt = 0U,
+ .all_pll_dump = 0U,
+ .cond_res = &cond_bus26m_res,
+ .residency = 0ULL,
+};
+
+#ifdef MTK_PLAT_CIRQ_UNSUPPORT
+#define do_irqs_delivery()
+#else
+static void mt_spm_irq_remain_dump(struct mt_irqremain *irqs,
+ unsigned int irq_index,
+ struct wake_status *wakeup)
+{
+ if ((irqs == NULL) || (wakeup == NULL)) {
+ return;
+ }
+
+ INFO("[SPM] r12=0x%08x(0x%08x), flag=0x%08x 0x%08x 0x%08x, irq:%u(0x%08x) set pending\n",
+ wakeup->tr.comm.r12,
+ wakeup->md32pcm_wakeup_sta,
+ wakeup->tr.comm.debug_flag,
+ wakeup->tr.comm.b_sw_flag0,
+ wakeup->tr.comm.b_sw_flag1,
+ irqs->wakeupsrc[irq_index],
+ irqs->irqs[irq_index]);
+}
+
+static void do_irqs_delivery(void)
+{
+ unsigned int idx;
+ struct wake_status *wakeup = NULL;
+ struct mt_irqremain *irqs = refer2remain_irq;
+
+ if (irqs == NULL) {
+ return;
+ }
+
+ if (spm_conservation_get_result(&wakeup) == 0) {
+ if (wakeup != NULL) {
+ for (idx = 0; idx < irqs->count; idx++) {
+ if (((wakeup->tr.comm.r12 & irqs->wakeupsrc[idx]) != 0U) ||
+ ((wakeup->tr.comm.raw_sta & irqs->wakeupsrc[idx]) != 0U)) {
+ if ((irqs->wakeupsrc_cat[idx] &
+ MT_IRQ_REMAIN_CAT_LOG) != 0U) {
+ mt_spm_irq_remain_dump(irqs, idx, wakeup);
+ }
+ mt_irq_set_pending(irqs->irqs[idx]);
+ }
+ }
+ }
+ }
+}
+#endif
+
+int spm_bus26m_conduct(int state_id, struct spm_lp_scen *spm_lp, unsigned int *resource_req)
+{
+ unsigned int res_req = CONSTRAINT_BUS26M_RESOURCE_REQ;
+
+ if ((spm_lp == NULL) || (resource_req == NULL)) {
+ return -1;
+ }
+
+ spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_BUS26M_PCM_FLAG;
+ spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_BUS26M_PCM_FLAG1;
+
+ *resource_req |= res_req;
+ return 0;
+}
+
+bool spm_is_valid_rc_bus26m(unsigned int cpu, int state_id)
+{
+ return (!(status.is_cond_block && (status.is_valid & MT_SPM_RC_VALID_COND_CHECK) > 0) &&
+ IS_MT_RM_RC_READY(status.is_valid) &&
+ (IS_PLAT_SUSPEND_ID(state_id) || (state_id == MT_PLAT_PWR_STATE_SYSTEM_BUS)));
+}
+
+static int update_rc_condition(const void *val)
+{
+ const struct mt_spm_cond_tables *tlb = (const struct mt_spm_cond_tables *)val;
+ const struct mt_spm_cond_tables *tlb_check =
+ (const struct mt_spm_cond_tables *)&cond_bus26m;
+
+ if (tlb == NULL) {
+ return MT_RM_STATUS_BAD;
+ }
+
+ status.is_cond_block = mt_spm_cond_check(tlb, tlb_check,
+ (status.is_valid & MT_SPM_RC_VALID_COND_LATCH) ?
+ &cond_bus26m_res : NULL);
+ status.all_pll_dump = mt_spm_dump_all_pll(tlb, tlb_check,
+ (status.is_valid & MT_SPM_RC_VALID_COND_LATCH) ?
+ &cond_bus26m_res : NULL);
+ return MT_RM_STATUS_OK;
+}
+
+static void update_rc_remain_irqs(const void *val)
+{
+ refer2remain_irq = (struct mt_irqremain *)val;
+}
+
+static void update_rc_fmaudio_adsp(int type, const void *val)
+{
+ int *flag = (int *)val;
+ unsigned int ext_op = (type == PLAT_RC_IS_ADSP) ?
+ (MT_SPM_EX_OP_SET_IS_ADSP | MT_SPM_EX_OP_SET_SUSPEND_MODE) :
+ MT_SPM_EX_OP_SET_SUSPEND_MODE;
+
+ if (flag == NULL) {
+ return;
+ }
+
+ if (*flag != 0) {
+ SPM_RC_BITS_SET(bus26m_ext_opand, ext_op);
+ } else {
+ SPM_RC_BITS_CLR(bus26m_ext_opand, ext_op);
+ }
+}
+
+static void update_rc_usb_peri(const void *val)
+{
+ int *flag = (int *)val;
+
+ if (flag == NULL) {
+ return;
+ }
+
+ if (*flag != 0) {
+ SPM_RC_BITS_SET(bus26m_ext_opand2, MT_SPM_EX_OP_PERI_ON);
+ } else {
+ SPM_RC_BITS_CLR(bus26m_ext_opand2, MT_SPM_EX_OP_PERI_ON);
+ }
+}
+
+static void update_rc_usb_infra(const void *val)
+{
+ int *flag = (int *)val;
+
+ if (flag == NULL) {
+ return;
+ }
+
+ if (*flag != 0) {
+ SPM_RC_BITS_SET(bus26m_ext_opand2, MT_SPM_EX_OP_INFRA_ON);
+ } else {
+ SPM_RC_BITS_CLR(bus26m_ext_opand2, MT_SPM_EX_OP_INFRA_ON);
+ }
+}
+
+static void update_rc_status(const void *val)
+{
+ const struct rc_common_state *st;
+
+ st = (const struct rc_common_state *)val;
+
+ if (st == NULL) {
+ return;
+ }
+
+ if (st->type == CONSTRAINT_UPDATE_COND_CHECK) {
+ struct mt_spm_cond_tables * const tlb = &cond_bus26m;
+
+ spm_rc_condition_modifier(st->id, st->act, st->value,
+ MT_RM_CONSTRAINT_ID_BUS26M, tlb);
+ } else if ((st->type == CONSTRAINT_UPDATE_VALID) ||
+ (st->type == CONSTRAINT_RESIDNECY)) {
+ spm_rc_constraint_status_set(st->id, st->type, st->act,
+ MT_RM_CONSTRAINT_ID_BUS26M,
+ (struct constraint_status * const)st->value,
+ (struct constraint_status * const)&status);
+ } else {
+ INFO("[%s:%d] - Unknown type: 0x%x\n", __func__, __LINE__, st->type);
+ }
+}
+
+int spm_update_rc_bus26m(int state_id, int type, const void *val)
+{
+ int res = MT_RM_STATUS_OK;
+
+ switch (type) {
+ case PLAT_RC_UPDATE_CONDITION:
+ res = update_rc_condition(val);
+ break;
+ case PLAT_RC_UPDATE_REMAIN_IRQS:
+ update_rc_remain_irqs(val);
+ break;
+ case PLAT_RC_IS_FMAUDIO:
+ case PLAT_RC_IS_ADSP:
+ update_rc_fmaudio_adsp(type, val);
+ break;
+ case PLAT_RC_IS_USB_PERI:
+ update_rc_usb_peri(val);
+ break;
+ case PLAT_RC_IS_USB_INFRA:
+ update_rc_usb_infra(val);
+ break;
+ case PLAT_RC_STATUS:
+ update_rc_status(val);
+ break;
+ default:
+ INFO("[%s:%d] - Do nothing for type: %d\n", __func__, __LINE__, type);
+ break;
+ }
+ return res;
+}
+
+unsigned int spm_allow_rc_bus26m(int state_id)
+{
+ return CONSTRAINT_BUS26M_ALLOW;
+}
+
+int spm_run_rc_bus26m(unsigned int cpu, int state_id)
+{
+ unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
+
+#ifndef MTK_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+ mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER, CONSTRAINT_BUS26M_ALLOW |
+ (IS_PLAT_SUSPEND_ID(state_id) ?
+ MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND : 0));
+#endif
+ if (status.is_valid & MT_SPM_RC_VALID_TRACE_TIME) {
+ ext_op |= MT_SPM_EX_OP_TRACE_TIMESTAMP_EN;
+ }
+
+ if (IS_PLAT_SUSPEND_ID(state_id)) {
+ mt_spm_suspend_enter(state_id,
+ (MT_SPM_EX_OP_CLR_26M_RECORD |
+ MT_SPM_EX_OP_SET_WDT |
+ MT_SPM_EX_OP_HW_S1_DETECT |
+ bus26m_ext_opand |
+ bus26m_ext_opand2),
+ CONSTRAINT_BUS26M_RESOURCE_REQ);
+ } else {
+ mt_spm_idle_generic_enter(state_id, ext_op, spm_bus26m_conduct);
+ }
+ return MT_RM_STATUS_OK;
+}
+
+int spm_reset_rc_bus26m(unsigned int cpu, int state_id)
+{
+ unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
+
+#ifndef MTK_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+ mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, 0);
+#endif
+ if (status.is_valid & MT_SPM_RC_VALID_TRACE_TIME) {
+ ext_op |= MT_SPM_EX_OP_TRACE_TIMESTAMP_EN;
+ }
+
+ if (IS_PLAT_SUSPEND_ID(state_id)) {
+ mt_spm_suspend_resume(state_id,
+ (bus26m_ext_opand | bus26m_ext_opand2 |
+ MT_SPM_EX_OP_SET_WDT | ext_op),
+ NULL);
+ bus26m_ext_opand = 0;
+ } else {
+ struct wake_status *waken = NULL;
+
+ if (spm_unlikely(status.is_valid & MT_SPM_RC_VALID_TRACE_EVENT)) {
+ ext_op |= MT_SPM_EX_OP_TRACE_LP;
+ }
+
+ mt_spm_idle_generic_resume(state_id, ext_op, &waken, NULL);
+ status.enter_cnt++;
+
+ if (spm_unlikely(status.is_valid & MT_SPM_RC_VALID_RESIDNECY)) {
+ status.residency += (waken != NULL) ? waken->tr.comm.timer_out : 0;
+ }
+ }
+
+ do_irqs_delivery();
+
+ return MT_RM_STATUS_OK;
+}
+
+int spm_get_status_rc_bus26m(unsigned int type, void *priv)
+{
+ int ret = MT_RM_STATUS_OK;
+
+ if (type == PLAT_RC_STATUS) {
+ int res = 0;
+ struct rc_common_state *st = (struct rc_common_state *)priv;
+
+ if (st == NULL) {
+ return MT_RM_STATUS_BAD;
+ }
+
+ res = spm_rc_constraint_status_get(st->id, st->type,
+ st->act, MT_RM_CONSTRAINT_ID_BUS26M,
+ (struct constraint_status * const)&status,
+ (struct constraint_status * const)st->value);
+ if ((res == 0) && (st->id != MT_RM_CONSTRAINT_ID_ALL)) {
+ ret = MT_RM_STATUS_STOP;
+ }
+ }
+ return ret;
+}
diff --git a/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_cpu_buck_ldo.c b/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_cpu_buck_ldo.c
new file mode 100644
index 0000000..1bcd509
--- /dev/null
+++ b/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_cpu_buck_ldo.c
@@ -0,0 +1,191 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <drivers/spm/mt_spm_resource_req.h>
+#include <lib/pm/mtk_pm.h>
+#include <lpm/mt_lpm_smc.h>
+#include <mt_spm.h>
+#include <mt_spm_cond.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_constraint.h>
+#include <mt_spm_idle.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_notifier.h>
+#include "mt_spm_rc_api.h"
+#include "mt_spm_rc_internal.h"
+#include <mt_spm_reg.h>
+#include <mt_spm_suspend.h>
+
+#define CONSTRAINT_CPU_BUCK_PCM_FLAG (SPM_FLAG_DISABLE_INFRA_PDN | \
+ SPM_FLAG_DISABLE_VCORE_DVS | \
+ SPM_FLAG_DISABLE_VCORE_DFS | \
+ SPM_FLAG_SRAM_SLEEP_CTRL | \
+ SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP | \
+ SPM_FLAG_KEEP_CSYSPWRACK_HIGH)
+
+#define CONSTRAINT_CPU_BUCK_PCM_FLAG1 (0)
+
+#define CONSTRAINT_CPU_BUCK_RESOURCE_REQ (MT_SPM_DRAM_S1 | \
+ MT_SPM_DRAM_S0 | \
+ MT_SPM_SYSPLL | \
+ MT_SPM_INFRA | \
+ MT_SPM_26M | \
+ MT_SPM_XO_FPM)
+
+static unsigned int cpubuckldo_status = (MT_SPM_RC_VALID_SW | MT_SPM_RC_VALID_TRACE_TIME);
+static unsigned int cpubuckldo_enter_cnt;
+
+int spm_cpu_bcuk_ldo_conduct(int state_id,
+ struct spm_lp_scen *spm_lp,
+ unsigned int *resource_req)
+{
+ unsigned int res_req = CONSTRAINT_CPU_BUCK_RESOURCE_REQ;
+
+ if ((spm_lp == NULL) || (resource_req == NULL)) {
+ return -1;
+ }
+
+ spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_CPU_BUCK_PCM_FLAG;
+ spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_CPU_BUCK_PCM_FLAG1;
+
+ *resource_req |= res_req;
+ return 0;
+}
+
+bool spm_is_valid_rc_cpu_buck_ldo(unsigned int cpu, int state_id)
+{
+ return IS_MT_RM_RC_READY(cpubuckldo_status);
+}
+
+static void update_rc_status(const void *val)
+{
+ const struct rc_common_state *st = (const struct rc_common_state *)val;
+
+ if (st == NULL) {
+ return;
+ }
+
+ if ((st->type == CONSTRAINT_UPDATE_VALID) && st->value) {
+ if ((st->id == MT_RM_CONSTRAINT_ID_ALL) ||
+ (st->id == MT_RM_CONSTRAINT_ID_CPU_BUCK_LDO)) {
+ struct constraint_status *con = (struct constraint_status *)st->value;
+
+ if ((st->act & MT_LPM_SMC_ACT_CLR) > 0U) {
+ SPM_RC_BITS_CLR(cpubuckldo_status, con->is_valid);
+ } else {
+ SPM_RC_BITS_SET(cpubuckldo_status, con->is_valid);
+ }
+ }
+ }
+}
+
+int spm_update_rc_cpu_buck_ldo(int state_id, int type, const void *val)
+{
+ if (type == PLAT_RC_STATUS) {
+ update_rc_status(val);
+ }
+ return MT_RM_STATUS_OK;
+}
+
+unsigned int spm_allow_rc_cpu_buck_ldo(int state_id)
+{
+ return MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF;
+}
+
+int spm_run_rc_cpu_buck_ldo(unsigned int cpu, int state_id)
+{
+ (void)cpu;
+ unsigned int ext_op = 0U;
+
+#ifndef MTK_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+ mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER,
+ (IS_PLAT_SUSPEND_ID(state_id) ?
+ MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND : (0U)));
+#endif
+ if (cpubuckldo_status & MT_SPM_RC_VALID_TRACE_TIME) {
+ ext_op |= MT_SPM_EX_OP_TRACE_TIMESTAMP_EN;
+ }
+
+ if (IS_PLAT_SUSPEND_ID(state_id)) {
+ mt_spm_suspend_enter(state_id,
+ (MT_SPM_EX_OP_CLR_26M_RECORD |
+ MT_SPM_EX_OP_SET_SUSPEND_MODE |
+ MT_SPM_EX_OP_SET_WDT),
+ CONSTRAINT_CPU_BUCK_RESOURCE_REQ);
+ } else {
+ mt_spm_idle_generic_enter(state_id, ext_op, spm_cpu_bcuk_ldo_conduct);
+ }
+
+ cpubuckldo_enter_cnt++;
+
+ return 0;
+}
+
+int spm_reset_rc_cpu_buck_ldo(unsigned int cpu, int state_id)
+{
+ (void)cpu;
+ unsigned int ext_op = 0U;
+
+#ifndef MTK_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+ mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, 0U);
+#endif
+ if (cpubuckldo_status & MT_SPM_RC_VALID_TRACE_TIME) {
+ ext_op |= MT_SPM_EX_OP_TRACE_TIMESTAMP_EN;
+ }
+
+ if (IS_PLAT_SUSPEND_ID(state_id)) {
+ mt_spm_suspend_resume(state_id, MT_SPM_EX_OP_SET_WDT, NULL);
+ } else {
+ mt_spm_idle_generic_resume(state_id, ext_op, NULL, NULL);
+ }
+
+ return 0;
+}
+
+int spm_get_status_rc_cpu_buck_ldo(unsigned int type, void *priv)
+{
+ int ret = MT_RM_STATUS_OK;
+
+ if (type != PLAT_RC_STATUS) {
+ return ret;
+ }
+
+ struct rc_common_state *st = (struct rc_common_state *)priv;
+
+ if (st == NULL) {
+ return MT_RM_STATUS_BAD;
+ }
+
+ if ((st->id == MT_RM_CONSTRAINT_ID_ALL) ||
+ (st->id == MT_RM_CONSTRAINT_ID_CPU_BUCK_LDO)) {
+ struct constraint_status *dest;
+
+ dest = (struct constraint_status *)st->value;
+ do {
+ if (dest == NULL) {
+ break;
+ }
+ if (st->type == CONSTRAINT_GET_VALID) {
+ dest->is_valid = cpubuckldo_status;
+ } else if (st->type == CONSTRAINT_COND_BLOCK) {
+ dest->is_cond_block = 0;
+ } else if (st->type == CONSTRAINT_GET_ENTER_CNT) {
+ if (st->id == MT_RM_CONSTRAINT_ID_ALL) {
+ dest->enter_cnt += cpubuckldo_enter_cnt;
+ } else {
+ dest->enter_cnt = cpubuckldo_enter_cnt;
+ }
+ } else {
+ break;
+ }
+ if (st->id != MT_RM_CONSTRAINT_ID_ALL) {
+ ret = MT_RM_STATUS_STOP;
+ }
+ } while (0);
+ }
+ return ret;
+}
diff --git a/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_dram.c b/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_dram.c
new file mode 100644
index 0000000..d1a2435
--- /dev/null
+++ b/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_dram.c
@@ -0,0 +1,317 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <drivers/spm/mt_spm_resource_req.h>
+#include <lib/pm/mtk_pm.h>
+#include <lpm/mt_lp_api.h>
+#include <lpm/mt_lp_rm.h>
+#include <mt_spm.h>
+#include <mt_spm_cond.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_constraint.h>
+#include <mt_spm_idle.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_notifier.h>
+#include "mt_spm_rc_api.h"
+#include "mt_spm_rc_internal.h"
+#include <mt_spm_reg.h>
+#include <mt_spm_suspend.h>
+
+#define CONSTRAINT_DRAM_ALLOW (MT_RM_CONSTRAINT_ALLOW_DRAM_S0 | \
+ MT_RM_CONSTRAINT_ALLOW_DRAM_S1 | \
+ MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF)
+
+#define CONSTRAINT_DRAM_PCM_FLAG (SPM_FLAG_DISABLE_INFRA_PDN | \
+ SPM_FLAG_DISABLE_VCORE_DVS | \
+ SPM_FLAG_DISABLE_VCORE_DFS | \
+ SPM_FLAG_SRAM_SLEEP_CTRL | \
+ SPM_FLAG_KEEP_CSYSPWRACK_HIGH | \
+ SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP)
+
+#define CONSTRAINT_DRAM_PCM_FLAG1 (0)
+
+#define CONSTRAINT_DRAM_RESOURCE_REQ (MT_SPM_SYSPLL | MT_SPM_INFRA | MT_SPM_26M)
+
+static struct mt_spm_cond_tables cond_dram = {
+ .table_cg = {
+ 0xFF5DD002, /* MTCMOS1 */
+ 0x0000003C, /* MTCMOS2 */
+ 0x27AF8000, /* INFRA0 */
+ 0x20010876, /* INFRA1 */
+ 0x86000640, /* INFRA2 */
+ 0x00000000, /* INFRA3 */
+ 0x80000000, /* INFRA4 */
+ 0x01002A00, /* PERI0 */
+ 0x00080000, /* VPPSYS0_0 */
+ 0x38803000, /* VPPSYS0_1 */
+ 0x00081450, /* VPPSYS1_0 */
+ 0x00003000, /* VPPSYS1_1 */
+ 0x00000000, /* VDOSYS0_0 */
+ 0x00000000, /* VDOSYS0_1 */
+ 0x000001F8, /* VDOSYS1_0 */
+ 0x000001E0, /* VDOSYS1_1 */
+ 0x00FB0007, /* VDOSYS1_2 */
+ },
+ .table_pll = 0U,
+};
+
+static struct mt_spm_cond_tables cond_dram_res = {
+ .table_cg = { 0U },
+ .table_pll = 0U,
+};
+
+static struct constraint_status status = {
+ .id = MT_RM_CONSTRAINT_ID_DRAM,
+ .is_valid = (MT_SPM_RC_VALID_SW |
+ MT_SPM_RC_VALID_COND_CHECK |
+ MT_SPM_RC_VALID_COND_LATCH |
+ MT_SPM_RC_VALID_XSOC_BBLPM |
+ MT_SPM_RC_VALID_TRACE_TIME),
+ .is_cond_block = 0U,
+ .enter_cnt = 0U,
+ .cond_res = &cond_dram_res,
+ .residency = 0ULL,
+};
+
+static unsigned short ext_status_dram;
+
+int spm_dram_conduct(int state_id, struct spm_lp_scen *spm_lp, unsigned int *resource_req)
+{
+ unsigned int res_req = CONSTRAINT_DRAM_RESOURCE_REQ;
+
+ if ((spm_lp == NULL) || (resource_req == NULL)) {
+ return -1;
+ }
+
+ spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_DRAM_PCM_FLAG;
+ spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_DRAM_PCM_FLAG1;
+
+ *resource_req |= res_req;
+ return 0;
+}
+
+bool spm_is_valid_rc_dram(unsigned int cpu, int state_id)
+{
+ return (!(status.is_cond_block && (status.is_valid & MT_SPM_RC_VALID_COND_CHECK)) &&
+ IS_MT_RM_RC_READY(status.is_valid) &&
+ (IS_PLAT_SUSPEND_ID(state_id) ||
+ (state_id == MT_PLAT_PWR_STATE_SYSTEM_MEM) ||
+ (state_id == MT_PLAT_PWR_STATE_SYSTEM_PLL) ||
+ (state_id == MT_PLAT_PWR_STATE_SYSTEM_BUS)));
+}
+
+static int update_rc_condition(const void *val)
+{
+ const struct mt_spm_cond_tables *tlb = (const struct mt_spm_cond_tables *)val;
+ const struct mt_spm_cond_tables *tlb_check = (const struct mt_spm_cond_tables *)&cond_dram;
+
+ if (tlb == NULL) {
+ return MT_RM_STATUS_BAD;
+ }
+
+ status.is_cond_block = mt_spm_cond_check(tlb, tlb_check,
+ (status.is_valid & MT_SPM_RC_VALID_COND_LATCH) ?
+ &cond_dram_res : NULL);
+ return MT_RM_STATUS_OK;
+}
+
+static void update_rc_clkbuf_status(const void *val)
+{
+ unsigned int is_flight = (val) ? !!(*((unsigned int *)val) == FLIGHT_MODE_ON) : 0;
+
+ if (is_flight != 0U) {
+ spm_rc_constraint_valid_set(MT_RM_CONSTRAINT_ID_DRAM,
+ MT_RM_CONSTRAINT_ID_DRAM,
+ MT_SPM_RC_VALID_FLIGHTMODE,
+ (struct constraint_status * const)&status);
+ } else {
+ spm_rc_constraint_valid_clr(MT_RM_CONSTRAINT_ID_DRAM,
+ MT_RM_CONSTRAINT_ID_DRAM,
+ MT_SPM_RC_VALID_FLIGHTMODE,
+ (struct constraint_status * const)&status);
+ }
+}
+
+static void update_rc_ufs_status(const void *val)
+{
+ unsigned int is_ufs_h8 = (val) ? !!(*((unsigned int *)val) == UFS_REF_CLK_OFF) : 0;
+
+ if (is_ufs_h8 != 0U) {
+ spm_rc_constraint_valid_set(MT_RM_CONSTRAINT_ID_DRAM,
+ MT_RM_CONSTRAINT_ID_DRAM,
+ MT_SPM_RC_VALID_UFS_H8,
+ (struct constraint_status * const)&status);
+ } else {
+ spm_rc_constraint_valid_clr(MT_RM_CONSTRAINT_ID_DRAM,
+ MT_RM_CONSTRAINT_ID_DRAM,
+ MT_SPM_RC_VALID_UFS_H8,
+ (struct constraint_status * const)&status);
+ }
+}
+
+static void update_rc_status(const void *val)
+{
+ const struct rc_common_state *st;
+
+ st = (const struct rc_common_state *)val;
+
+ if (st == NULL) {
+ return;
+ }
+
+ if (st->type == CONSTRAINT_UPDATE_COND_CHECK) {
+ struct mt_spm_cond_tables * const tlb = &cond_dram;
+
+ spm_rc_condition_modifier(st->id, st->act, st->value,
+ MT_RM_CONSTRAINT_ID_DRAM, tlb);
+ } else if ((st->type == CONSTRAINT_UPDATE_VALID) ||
+ (st->type == CONSTRAINT_RESIDNECY)) {
+ spm_rc_constraint_status_set(st->id, st->type, st->act,
+ MT_RM_CONSTRAINT_ID_DRAM,
+ (struct constraint_status * const)st->value,
+ (struct constraint_status * const)&status);
+ } else {
+ INFO("[%s:%d] - Unknown type: 0x%x\n", __func__, __LINE__, st->type);
+ }
+}
+
+int spm_update_rc_dram(int state_id, int type, const void *val)
+{
+ int res = MT_RM_STATUS_OK;
+
+ switch (type) {
+ case PLAT_RC_UPDATE_CONDITION:
+ res = update_rc_condition(val);
+ break;
+ case PLAT_RC_CLKBUF_STATUS:
+ update_rc_clkbuf_status(val);
+ break;
+ case PLAT_RC_UFS_STATUS:
+ update_rc_ufs_status(val);
+ break;
+ case PLAT_RC_STATUS:
+ update_rc_status(val);
+ break;
+ default:
+ INFO("[%s:%d] - Do nothing for type: %d\n", __func__, __LINE__, type);
+ break;
+ }
+
+ return res;
+}
+
+unsigned int spm_allow_rc_dram(int state_id)
+{
+ return CONSTRAINT_DRAM_ALLOW;
+}
+
+int spm_run_rc_dram(unsigned int cpu, int state_id)
+{
+ unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
+ unsigned int allows = CONSTRAINT_DRAM_ALLOW;
+
+ ext_status_dram = status.is_valid;
+
+ if (IS_MT_SPM_RC_BBLPM_MODE(ext_status_dram)) {
+#ifdef MT_SPM_USING_SRCLKEN_RC
+ ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM;
+#else
+ allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM;
+#endif
+ }
+
+#ifndef MTK_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+ mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER, allows | (IS_PLAT_SUSPEND_ID(state_id) ?
+ (MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND) : (0U)));
+#else
+ (void)allows;
+#endif
+
+ if (ext_status_dram & MT_SPM_RC_VALID_TRACE_TIME) {
+ ext_op |= MT_SPM_EX_OP_TRACE_TIMESTAMP_EN;
+ }
+
+ if (IS_PLAT_SUSPEND_ID(state_id)) {
+ mt_spm_suspend_enter(state_id,
+ (MT_SPM_EX_OP_CLR_26M_RECORD |
+ MT_SPM_EX_OP_SET_WDT |
+ MT_SPM_EX_OP_SET_SUSPEND_MODE |
+ MT_SPM_EX_OP_HW_S1_DETECT),
+ CONSTRAINT_DRAM_RESOURCE_REQ);
+ } else {
+ mt_spm_idle_generic_enter(state_id, ext_op, spm_dram_conduct);
+ }
+
+ return 0;
+}
+
+int spm_reset_rc_dram(unsigned int cpu, int state_id)
+{
+ unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
+ unsigned int allows = CONSTRAINT_DRAM_ALLOW;
+
+ if (IS_MT_SPM_RC_BBLPM_MODE(ext_status_dram)) {
+#ifdef MT_SPM_USING_SRCLKEN_RC
+ ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM;
+#else
+ allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM;
+#endif
+ }
+
+#ifndef MTK_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+ mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, allows);
+#else
+ (void)allows;
+#endif
+
+ if (ext_status_dram & MT_SPM_RC_VALID_TRACE_TIME) {
+ ext_op |= MT_SPM_EX_OP_TRACE_TIMESTAMP_EN;
+ }
+
+ if (IS_PLAT_SUSPEND_ID(state_id)) {
+ mt_spm_suspend_resume(state_id,
+ (MT_SPM_EX_OP_SET_WDT | MT_SPM_EX_OP_HW_S1_DETECT),
+ NULL);
+ } else {
+ struct wake_status *waken = NULL;
+
+ if (spm_unlikely(status.is_valid & MT_SPM_RC_VALID_TRACE_EVENT)) {
+ ext_op |= MT_SPM_EX_OP_TRACE_LP;
+ }
+ mt_spm_idle_generic_resume(state_id, ext_op, &waken, NULL);
+ status.enter_cnt++;
+
+ if (spm_unlikely(status.is_valid & MT_SPM_RC_VALID_RESIDNECY)) {
+ status.residency += (waken != NULL) ? waken->tr.comm.timer_out : 0;
+ }
+ }
+
+ return 0;
+}
+
+int spm_get_status_rc_dram(unsigned int type, void *priv)
+{
+ int ret = MT_RM_STATUS_OK;
+
+ if (type == PLAT_RC_STATUS) {
+ int res = 0;
+ struct rc_common_state *st = (struct rc_common_state *)priv;
+
+ if (st == NULL) {
+ return MT_RM_STATUS_BAD;
+ }
+
+ res = spm_rc_constraint_status_get(st->id, st->type,
+ st->act, MT_RM_CONSTRAINT_ID_DRAM,
+ (struct constraint_status * const)&status,
+ (struct constraint_status * const)st->value);
+ if ((res == 0) && (st->id != MT_RM_CONSTRAINT_ID_ALL)) {
+ ret = MT_RM_STATUS_STOP;
+ }
+ }
+ return ret;
+}
diff --git a/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_internal.h b/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_internal.h
new file mode 100644
index 0000000..7763152
--- /dev/null
+++ b/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_internal.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_RC_INTERNAL_H
+#define MT_SPM_RC_INTERNAL_H
+
+#ifdef MTK_PLAT_SPM_SRAM_SLP_UNSUPPORT
+#define SPM_FLAG_SRAM_SLEEP_CTRL (SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP)
+#define SPM_SRAM_SLEEP_RC_RES_RESTRICT (0)
+#else
+#define SPM_FLAG_SRAM_SLEEP_CTRL (0)
+#define SPM_SRAM_SLEEP_RC_RES_RESTRICT (0)
+#endif
+
+#define SPM_RC_UPDATE_COND_ID_MASK (0xffff)
+#define SPM_RC_UPDATE_COND_RC_ID_MASK (0xffff)
+#define SPM_RC_UPDATE_COND_RC_ID_SHIFT (16)
+
+#define SPM_RC_UPDATE_COND_RC_ID_GET(val) \
+ ((val >> SPM_RC_UPDATE_COND_RC_ID_SHIFT) & SPM_RC_UPDATE_COND_RC_ID_MASK)
+
+#define SPM_RC_UPDATE_COND_ID_GET(val) (val & SPM_RC_UPDATE_COND_ID_MASK)
+
+/* cpu buck/ldo constraint function */
+bool spm_is_valid_rc_cpu_buck_ldo(unsigned int cpu, int state_id);
+int spm_update_rc_cpu_buck_ldo(int state_id, int type, const void *val);
+unsigned int spm_allow_rc_cpu_buck_ldo(int state_id);
+int spm_run_rc_cpu_buck_ldo(unsigned int cpu, int state_id);
+int spm_reset_rc_cpu_buck_ldo(unsigned int cpu, int state_id);
+int spm_get_status_rc_cpu_buck_ldo(unsigned int type, void *priv);
+
+/* spm resource dram constraint function */
+bool spm_is_valid_rc_dram(unsigned int cpu, int state_id);
+int spm_update_rc_dram(int state_id, int type, const void *val);
+unsigned int spm_allow_rc_dram(int state_id);
+int spm_run_rc_dram(unsigned int cpu, int state_id);
+int spm_reset_rc_dram(unsigned int cpu, int state_id);
+int spm_get_status_rc_dram(unsigned int type, void *priv);
+
+/* spm resource syspll constraint function */
+bool spm_is_valid_rc_syspll(unsigned int cpu, int state_id);
+int spm_update_rc_syspll(int state_id, int type, const void *val);
+unsigned int spm_allow_rc_syspll(int state_id);
+int spm_run_rc_syspll(unsigned int cpu, int state_id);
+int spm_reset_rc_syspll(unsigned int cpu, int state_id);
+int spm_get_status_rc_syspll(unsigned int type, void *priv);
+
+/* spm resource bus26m constraint function */
+bool spm_is_valid_rc_bus26m(unsigned int cpu, int state_id);
+int spm_update_rc_bus26m(int state_id, int type, const void *val);
+unsigned int spm_allow_rc_bus26m(int state_id);
+int spm_run_rc_bus26m(unsigned int cpu, int state_id);
+int spm_reset_rc_bus26m(unsigned int cpu, int state_id);
+int spm_get_status_rc_bus26m(unsigned int type, void *priv);
+
+#endif
diff --git a/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_syspll.c b/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_syspll.c
new file mode 100644
index 0000000..700f500
--- /dev/null
+++ b/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_syspll.c
@@ -0,0 +1,364 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <common/debug.h>
+#include <drivers/spm/mt_spm_resource_req.h>
+#include <lib/pm/mtk_pm.h>
+#include <lpm/mt_lp_api.h>
+#include <lpm/mt_lp_rm.h>
+#include <mt_spm.h>
+#include <mt_spm_cond.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_constraint.h>
+#include <mt_spm_idle.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_notifier.h>
+#include "mt_spm_rc_api.h"
+#include "mt_spm_rc_internal.h"
+#include <mt_spm_reg.h>
+#include <mt_spm_suspend.h>
+
+#define CONSTRAINT_SYSPLL_ALLOW (MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF | \
+ MT_RM_CONSTRAINT_ALLOW_DRAM_S0 | \
+ MT_RM_CONSTRAINT_ALLOW_DRAM_S1 | \
+ MT_RM_CONSTRAINT_ALLOW_VCORE_LP)
+
+#define CONSTRAINT_SYSPLL_PCM_FLAG (SPM_FLAG_DISABLE_INFRA_PDN | \
+ SPM_FLAG_DISABLE_VCORE_DVS | \
+ SPM_FLAG_DISABLE_VCORE_DFS | \
+ SPM_FLAG_SRAM_SLEEP_CTRL | \
+ SPM_FLAG_KEEP_CSYSPWRACK_HIGH | \
+ SPM_FLAG_ENABLE_6315_CTRL | \
+ SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP | \
+ SPM_FLAG_USE_SRCCLKENO2)
+
+#define CONSTRAINT_SYSPLL_PCM_FLAG1 (0)
+
+/* If sspm sram won't enter sleep voltage then vcore couldn't enter low power mode */
+#if defined(MTK_PLAT_SPM_SRAM_SLP_UNSUPPORT) && SPM_SRAM_SLEEP_RC_RES_RESTRICT
+#define CONSTRAINT_SYSPLL_RESOURCE_REQ (MT_SPM_26M)
+#else
+#define CONSTRAINT_SYSPLL_RESOURCE_REQ (MT_SPM_26M)
+#endif
+
+static unsigned int syspll_ext_opand2;
+static unsigned short ext_status_syspll;
+
+static struct mt_spm_cond_tables cond_syspll = {
+ .table_cg = {
+ 0xFF5DD002, /* MTCMOS1 */
+ 0x0000003C, /* MTCMOS2 */
+ 0x27AF8000, /* INFRA0 */
+ 0x20010876, /* INFRA1 */
+ 0x86000640, /* INFRA2 */
+ 0x30008020, /* INFRA3 */
+ 0x80000000, /* INFRA4 */
+ 0x01002A0B, /* PERI0 */
+ 0x00090000, /* VPPSYS0_0 */
+ 0x38FF3E69, /* VPPSYS0_1 */
+ 0xF0081450, /* VPPSYS1_0 */
+ 0x00003000, /* VPPSYS1_1 */
+ 0x00000000, /* VDOSYS0_0 */
+ 0x00000000, /* VDOSYS0_1 */
+ 0x000001FF, /* VDOSYS1_0 */
+ 0x008001E0, /* VDOSYS1_1 */
+ 0x00FB0007, /* VDOSYS1_2 */
+ },
+ .table_pll = 0U,
+};
+
+static struct mt_spm_cond_tables cond_syspll_res = {
+ .table_cg = { 0U },
+ .table_pll = 0U,
+};
+
+static struct constraint_status status = {
+ .id = MT_RM_CONSTRAINT_ID_SYSPLL,
+ .is_valid = (MT_SPM_RC_VALID_SW |
+ MT_SPM_RC_VALID_COND_CHECK |
+ MT_SPM_RC_VALID_COND_LATCH |
+ MT_SPM_RC_VALID_XSOC_BBLPM |
+ MT_SPM_RC_VALID_TRACE_TIME),
+ .is_cond_block = 0U,
+ .enter_cnt = 0U,
+ .cond_res = &cond_syspll_res,
+ .residency = 0ULL,
+};
+
+int spm_syspll_conduct(int state_id, struct spm_lp_scen *spm_lp, unsigned int *resource_req)
+{
+ unsigned int res_req = CONSTRAINT_SYSPLL_RESOURCE_REQ;
+
+ if ((spm_lp == NULL) || (resource_req == NULL)) {
+ return -1;
+ }
+
+ spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_SYSPLL_PCM_FLAG;
+ spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_SYSPLL_PCM_FLAG1;
+
+ *resource_req |= res_req;
+ return 0;
+}
+
+bool spm_is_valid_rc_syspll(unsigned int cpu, int state_id)
+{
+ return (!(status.is_cond_block && (status.is_valid & MT_SPM_RC_VALID_COND_CHECK) > 0) &&
+ IS_MT_RM_RC_READY(status.is_valid) &&
+ (IS_PLAT_SUSPEND_ID(state_id) ||
+ (state_id == MT_PLAT_PWR_STATE_SYSTEM_PLL) ||
+ (state_id == MT_PLAT_PWR_STATE_SYSTEM_BUS)));
+}
+
+static int update_rc_condition(const void *val)
+{
+ int res = MT_RM_STATUS_OK;
+
+ const struct mt_spm_cond_tables * const tlb =
+ (const struct mt_spm_cond_tables * const)val;
+ const struct mt_spm_cond_tables *tlb_check =
+ (const struct mt_spm_cond_tables *)&cond_syspll;
+
+ if (tlb == NULL) {
+ return MT_RM_STATUS_BAD;
+ }
+
+ status.is_cond_block = mt_spm_cond_check(tlb, tlb_check,
+ (status.is_valid & MT_SPM_RC_VALID_COND_LATCH) ?
+ &cond_syspll_res : NULL);
+ return res;
+}
+
+static void update_rc_clkbuf_status(const void *val)
+{
+ unsigned int is_flight = (val) ? !!(*((unsigned int *)val) == FLIGHT_MODE_ON) : 0;
+
+ if (is_flight != 0U) {
+ spm_rc_constraint_valid_set(MT_RM_CONSTRAINT_ID_SYSPLL,
+ MT_RM_CONSTRAINT_ID_SYSPLL,
+ MT_SPM_RC_VALID_FLIGHTMODE,
+ (struct constraint_status * const)&status);
+ } else {
+ spm_rc_constraint_valid_clr(MT_RM_CONSTRAINT_ID_SYSPLL,
+ MT_RM_CONSTRAINT_ID_SYSPLL,
+ MT_SPM_RC_VALID_FLIGHTMODE,
+ (struct constraint_status * const)&status);
+ }
+}
+
+static void update_rc_ufs_status(const void *val)
+{
+ unsigned int is_ufs_h8 = (val) ? !!(*((unsigned int *)val) == UFS_REF_CLK_OFF) : 0;
+
+ if (is_ufs_h8 != 0U) {
+ spm_rc_constraint_valid_set(MT_RM_CONSTRAINT_ID_SYSPLL,
+ MT_RM_CONSTRAINT_ID_SYSPLL,
+ MT_SPM_RC_VALID_UFS_H8,
+ (struct constraint_status * const)&status);
+ } else {
+ spm_rc_constraint_valid_clr(MT_RM_CONSTRAINT_ID_SYSPLL,
+ MT_RM_CONSTRAINT_ID_SYSPLL,
+ MT_SPM_RC_VALID_UFS_H8,
+ (struct constraint_status * const)&status);
+ }
+}
+
+static void update_rc_usb_peri(const void *val)
+{
+ int *flag = (int *)val;
+
+ if (flag == NULL) {
+ return;
+ }
+
+ if (*flag != 0) {
+ SPM_RC_BITS_SET(syspll_ext_opand2, MT_SPM_EX_OP_PERI_ON);
+ } else {
+ SPM_RC_BITS_CLR(syspll_ext_opand2, MT_SPM_EX_OP_PERI_ON);
+ }
+}
+
+static void update_rc_usb_infra(const void *val)
+{
+ int *flag = (int *)val;
+
+ if (flag == NULL) {
+ return;
+ }
+
+ if (*flag != 0) {
+ SPM_RC_BITS_SET(syspll_ext_opand2, MT_SPM_EX_OP_INFRA_ON);
+ } else {
+ SPM_RC_BITS_CLR(syspll_ext_opand2, MT_SPM_EX_OP_INFRA_ON);
+ }
+}
+
+static void update_rc_status(const void *val)
+{
+ const struct rc_common_state *st;
+
+ st = (const struct rc_common_state *)val;
+
+ if (st == NULL) {
+ return;
+ }
+
+ if (st->type == CONSTRAINT_UPDATE_COND_CHECK) {
+ struct mt_spm_cond_tables * const tlb = &cond_syspll;
+
+ spm_rc_condition_modifier(st->id, st->act, st->value,
+ MT_RM_CONSTRAINT_ID_SYSPLL, tlb);
+ } else if ((st->type == CONSTRAINT_UPDATE_VALID) ||
+ (st->type == CONSTRAINT_RESIDNECY)) {
+ spm_rc_constraint_status_set(st->id, st->type, st->act,
+ MT_RM_CONSTRAINT_ID_SYSPLL,
+ (struct constraint_status * const)st->value,
+ (struct constraint_status * const)&status);
+ } else {
+ INFO("[%s:%d] - Unknown type: 0x%x\n", __func__, __LINE__, st->type);
+ }
+}
+
+int spm_update_rc_syspll(int state_id, int type, const void *val)
+{
+ int res = MT_RM_STATUS_OK;
+
+ switch (type) {
+ case PLAT_RC_UPDATE_CONDITION:
+ res = update_rc_condition(val);
+ break;
+ case PLAT_RC_CLKBUF_STATUS:
+ update_rc_clkbuf_status(val);
+ break;
+ case PLAT_RC_UFS_STATUS:
+ update_rc_ufs_status(val);
+ break;
+ case PLAT_RC_IS_USB_PERI:
+ update_rc_usb_peri(val);
+ break;
+ case PLAT_RC_IS_USB_INFRA:
+ update_rc_usb_infra(val);
+ break;
+ case PLAT_RC_STATUS:
+ update_rc_status(val);
+ break;
+ default:
+ INFO("[%s:%d] - Do nothing for type: %d\n", __func__, __LINE__, type);
+ break;
+ }
+ return res;
+}
+
+unsigned int spm_allow_rc_syspll(int state_id)
+{
+ return CONSTRAINT_SYSPLL_ALLOW;
+}
+
+int spm_run_rc_syspll(unsigned int cpu, int state_id)
+{
+ unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
+ unsigned int allows = CONSTRAINT_SYSPLL_ALLOW;
+
+ ext_status_syspll = status.is_valid;
+
+ if (IS_MT_SPM_RC_BBLPM_MODE(ext_status_syspll)) {
+#ifdef MT_SPM_USING_SRCLKEN_RC
+ ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM;
+#else
+ allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM;
+#endif
+ }
+
+#ifndef MTK_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+ mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER, allows | (IS_PLAT_SUSPEND_ID(state_id) ?
+ MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND : 0));
+#else
+ (void)allows;
+#endif
+ if (ext_status_syspll & MT_SPM_RC_VALID_TRACE_TIME) {
+ ext_op |= MT_SPM_EX_OP_TRACE_TIMESTAMP_EN;
+ }
+
+ if (IS_PLAT_SUSPEND_ID(state_id)) {
+ mt_spm_suspend_enter(state_id,
+ (syspll_ext_opand2 | MT_SPM_EX_OP_CLR_26M_RECORD |
+ MT_SPM_EX_OP_SET_WDT | MT_SPM_EX_OP_HW_S1_DETECT |
+ MT_SPM_EX_OP_SET_SUSPEND_MODE),
+ CONSTRAINT_SYSPLL_RESOURCE_REQ);
+ } else {
+ mt_spm_idle_generic_enter(state_id, ext_op, spm_syspll_conduct);
+ }
+
+ return 0;
+}
+
+int spm_reset_rc_syspll(unsigned int cpu, int state_id)
+{
+ unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
+ unsigned int allows = CONSTRAINT_SYSPLL_ALLOW;
+
+ if (IS_MT_SPM_RC_BBLPM_MODE(ext_status_syspll)) {
+#ifdef MT_SPM_USING_SRCLKEN_RC
+ ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM;
+#else
+ allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM;
+#endif
+ }
+
+#ifndef MTK_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+ mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, allows);
+#else
+ (void)allows;
+#endif
+ if (ext_status_syspll & MT_SPM_RC_VALID_TRACE_TIME) {
+ ext_op |= MT_SPM_EX_OP_TRACE_TIMESTAMP_EN;
+ }
+
+ if (IS_PLAT_SUSPEND_ID(state_id)) {
+ mt_spm_suspend_resume(state_id,
+ (syspll_ext_opand2 | MT_SPM_EX_OP_SET_SUSPEND_MODE |
+ MT_SPM_EX_OP_SET_WDT | MT_SPM_EX_OP_HW_S1_DETECT),
+ NULL);
+ } else {
+ struct wake_status *waken = NULL;
+
+ if (spm_unlikely(status.is_valid & MT_SPM_RC_VALID_TRACE_EVENT)) {
+ ext_op |= MT_SPM_EX_OP_TRACE_LP;
+ }
+
+ mt_spm_idle_generic_resume(state_id, ext_op, &waken, NULL);
+ status.enter_cnt++;
+
+ if (spm_unlikely(status.is_valid & MT_SPM_RC_VALID_RESIDNECY)) {
+ status.residency += (waken != NULL) ? waken->tr.comm.timer_out : 0;
+ }
+ }
+
+ return 0;
+}
+
+int spm_get_status_rc_syspll(unsigned int type, void *priv)
+{
+ int ret = MT_RM_STATUS_OK;
+
+ if (type == PLAT_RC_STATUS) {
+ int res = 0;
+ struct rc_common_state *st = (struct rc_common_state *)priv;
+
+ if (st == NULL) {
+ return MT_RM_STATUS_BAD;
+ }
+
+ res = spm_rc_constraint_status_get(st->id, st->type, st->act,
+ MT_RM_CONSTRAINT_ID_SYSPLL,
+ (struct constraint_status * const)&status,
+ (struct constraint_status * const)st->value);
+ if ((res == 0) && (st->id != MT_RM_CONSTRAINT_ID_ALL)) {
+ ret = MT_RM_STATUS_STOP;
+ }
+ }
+ return ret;
+}
diff --git a/plat/mediatek/drivers/spm/mt8188/mt_spm.c b/plat/mediatek/drivers/spm/mt8188/mt_spm.c
new file mode 100644
index 0000000..6c4e681
--- /dev/null
+++ b/plat/mediatek/drivers/spm/mt8188/mt_spm.c
@@ -0,0 +1,170 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <stddef.h>
+#include <stdio.h>
+#include <string.h>
+
+#include <arch.h>
+#include <common/debug.h>
+#include <drivers/console.h>
+#include <lib/mmio.h>
+#include <lib/utils_def.h>
+
+#include "constraints/mt_spm_rc_internal.h"
+#include <drivers/spm/mt_spm_resource_req.h>
+#include <lib/mtk_init/mtk_init.h>
+#include <lib/pm/mtk_pm.h>
+#include <lpm/mt_lp_rm.h>
+#include <lpm/mt_lp_rqm.h>
+#include <lpm/mt_lpm_smc.h>
+#include "mt_spm.h"
+#include "mt_spm_cond.h"
+#include "mt_spm_conservation.h"
+#include "mt_spm_constraint.h"
+#include "mt_spm_idle.h"
+#include "mt_spm_internal.h"
+#include "mt_spm_pmic_wrap.h"
+#include "mt_spm_reg.h"
+#include "mt_spm_suspend.h"
+#include <mtk_mmap_pool.h>
+#include <platform_def.h>
+#include "sleep_def.h"
+
+/*
+ * System Power Manager (SPM) is a hardware module which provides CPU idle
+ * and system suspend features.
+ */
+
+spinlock_t spm_lock;
+
+#ifdef MTK_PLAT_SPM_UNSUPPORT
+struct mt_resource_manager plat_mt8188_rm = {
+};
+#else
+struct mt_lp_res_req rq_xo_fpm = {
+ .res_id = MT_LP_RQ_XO_FPM,
+ .res_rq = MT_SPM_XO_FPM,
+ .res_usage = 0,
+};
+
+struct mt_lp_res_req rq_26m = {
+ .res_id = MT_LP_RQ_26M,
+ .res_rq = MT_SPM_26M,
+ .res_usage = 0,
+};
+
+struct mt_lp_res_req rq_infra = {
+ .res_id = MT_LP_RQ_INFRA,
+ .res_rq = MT_SPM_INFRA,
+ .res_usage = 0,
+};
+
+struct mt_lp_res_req rq_syspll = {
+ .res_id = MT_LP_RQ_SYSPLL,
+ .res_rq = MT_SPM_SYSPLL,
+ .res_usage = 0,
+};
+
+struct mt_lp_res_req rq_dram_s0 = {
+ .res_id = MT_LP_RQ_DRAM,
+ .res_rq = MT_SPM_DRAM_S0,
+ .res_usage = 0,
+};
+
+struct mt_lp_res_req rq_dram_s1 = {
+ .res_id = MT_LP_RQ_DRAM,
+ .res_rq = MT_SPM_DRAM_S1,
+ .res_usage = 0,
+};
+
+struct mt_lp_res_req *spm_resources[] = {
+ &rq_xo_fpm,
+ &rq_26m,
+ &rq_infra,
+ &rq_syspll,
+ &rq_dram_s0,
+ &rq_dram_s1,
+ NULL,
+};
+
+struct mt_resource_req_manager plat_mt8188_rq = {
+ .res = spm_resources,
+};
+
+struct mt_resource_constraint plat_constraint_bus26m = {
+ .is_valid = spm_is_valid_rc_bus26m,
+ .update = spm_update_rc_bus26m,
+ .allow = spm_allow_rc_bus26m,
+ .run = spm_run_rc_bus26m,
+ .reset = spm_reset_rc_bus26m,
+ .get_status = spm_get_status_rc_bus26m,
+};
+
+struct mt_resource_constraint plat_constraint_syspll = {
+ .is_valid = spm_is_valid_rc_syspll,
+ .update = spm_update_rc_syspll,
+ .allow = spm_allow_rc_syspll,
+ .run = spm_run_rc_syspll,
+ .reset = spm_reset_rc_syspll,
+ .get_status = spm_get_status_rc_syspll,
+};
+
+struct mt_resource_constraint plat_constraint_dram = {
+ .is_valid = spm_is_valid_rc_dram,
+ .update = spm_update_rc_dram,
+ .allow = spm_allow_rc_dram,
+ .run = spm_run_rc_dram,
+ .reset = spm_reset_rc_dram,
+ .get_status = spm_get_status_rc_dram,
+};
+
+struct mt_resource_constraint plat_constraint_cpu = {
+ .is_valid = spm_is_valid_rc_cpu_buck_ldo,
+ .update = spm_update_rc_cpu_buck_ldo,
+ .allow = spm_allow_rc_cpu_buck_ldo,
+ .run = spm_run_rc_cpu_buck_ldo,
+ .reset = spm_reset_rc_cpu_buck_ldo,
+ .get_status = spm_get_status_rc_cpu_buck_ldo,
+};
+
+struct mt_resource_constraint *plat_constraints[] = {
+ &plat_constraint_bus26m,
+ &plat_constraint_syspll,
+ &plat_constraint_dram,
+ &plat_constraint_cpu,
+ NULL,
+};
+
+struct mt_resource_manager plat_mt8188_rm = {
+ .update = mt_spm_cond_update,
+ .consts = plat_constraints,
+};
+#endif
+
+/* Determine for SPM software resource user */
+static struct mt_lp_resource_user spm_res_user;
+
+struct mt_lp_resource_user *get_spm_res_user(void)
+{
+ return &spm_res_user;
+}
+
+int spm_boot_init(void)
+{
+ mt_spm_pmic_wrap_set_phase(PMIC_WRAP_PHASE_ALLINONE);
+ mt_lp_rm_register(&plat_mt8188_rm);
+
+ /* SPM service won't run when SPM not ready */
+#ifndef MTK_PLAT_SPM_UNSUPPORT
+ mt_lp_resource_request_manager_register(&plat_mt8188_rq);
+ mt_lp_resource_user_register("SPM", &spm_res_user);
+#endif
+
+ return 0;
+}
+MTK_ARCH_INIT(spm_boot_init);
diff --git a/plat/mediatek/drivers/spm/mt8188/mt_spm.h b/plat/mediatek/drivers/spm/mt8188/mt_spm.h
new file mode 100644
index 0000000..0688b71
--- /dev/null
+++ b/plat/mediatek/drivers/spm/mt8188/mt_spm.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_H
+#define MT_SPM_H
+
+#include <stdint.h>
+#include <stdio.h>
+#include <lib/spinlock.h>
+#include <lib/pm/mtk_pm.h>
+#include <lpm/mt_lp_rq.h>
+
+/*
+ * ARM v8.2, the cache will turn off automatically when cpu
+ * power down. Therefore, there is no doubt to use the spin_lock here.
+ */
+extern spinlock_t spm_lock;
+
+#ifdef __GNUC__
+#define spm_likely(x) __builtin_expect(!!(x), 1)
+#define spm_unlikely(x) __builtin_expect(!!(x), 0)
+#else
+#define spm_likely(x) (x)
+#define spm_unlikely(x) (x)
+#endif
+
+#define MT_SPM_USING_SRCLKEN_RC
+/* spm extern operand definition */
+#define MT_SPM_EX_OP_CLR_26M_RECORD BIT(0)
+#define MT_SPM_EX_OP_SET_WDT BIT(1)
+#define MT_SPM_EX_OP_NON_GENERIC_RESOURCE_REQ BIT(2)
+#define MT_SPM_EX_OP_SET_SUSPEND_MODE BIT(3)
+#define MT_SPM_EX_OP_SET_IS_ADSP BIT(4)
+#define MT_SPM_EX_OP_SRCLKEN_RC_BBLPM BIT(5)
+#define MT_SPM_EX_OP_HW_S1_DETECT BIT(6)
+#define MT_SPM_EX_OP_TRACE_LP BIT(7)
+#define MT_SPM_EX_OP_TRACE_SUSPEND BIT(8)
+#define MT_SPM_EX_OP_TRACE_TIMESTAMP_EN BIT(9)
+#define MT_SPM_EX_OP_TIME_CHECK BIT(10)
+#define MT_SPM_EX_OP_TIME_OBS BIT(11)
+#define MT_SPM_EX_OP_PERI_ON BIT(12)
+#define MT_SPM_EX_OP_INFRA_ON BIT(13)
+
+typedef enum {
+ WR_NONE = 0,
+ WR_UART_BUSY = 1,
+ WR_ABORT = 2,
+ WR_PCM_TIMER = 3,
+ WR_WAKE_SRC = 4,
+ WR_DVFSRC = 5,
+ WR_TWAM = 6,
+ WR_PMSR = 7,
+ WR_SPM_ACK_CHK = 8,
+ WR_UNKNOWN = 9,
+} wake_reason_t;
+
+struct mt_lp_resource_user *get_spm_res_user(void);
+int spm_boot_init(void);
+
+#endif /* MT_SPM_H */
diff --git a/plat/mediatek/drivers/spm/mt8188/mt_spm_cond.c b/plat/mediatek/drivers/spm/mt8188/mt_spm_cond.c
new file mode 100644
index 0000000..fe6e598
--- /dev/null
+++ b/plat/mediatek/drivers/spm/mt8188/mt_spm_cond.c
@@ -0,0 +1,253 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdbool.h>
+#include <lib/mmio.h>
+#include <lib/pm/mtk_pm.h>
+#include <mt_spm_cond.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_constraint.h>
+#include <platform_def.h>
+
+#define TOPCKGEB_BASE (IO_PHYS)
+
+#define MT_LP_TZ_INFRA_REG(ofs) (INFRACFG_AO_BASE + ofs)
+
+#define MT_LP_TZ_SPM_REG(ofs) (SPM_BASE + ofs)
+#define MT_LP_TZ_TOPCK_REG(ofs) (TOPCKGEB_BASE + ofs)
+#define MT_LP_TZ_APMIXEDSYS(ofs) (APMIXEDSYS + ofs)
+
+#define MT_LP_TZ_VPPSYS0_REG(ofs) (VPPSYS0_BASE + ofs)
+#define MT_LP_TZ_VPPSYS1_REG(ofs) (VPPSYS1_BASE + ofs)
+#define MT_LP_TZ_VDOSYS0_REG(ofs) (VDOSYS0_BASE + ofs)
+#define MT_LP_TZ_VDOSYS1_REG(ofs) (VDOSYS1_BASE + ofs)
+
+#define MT_LP_TZ_PERI_AO_REG(ofs) (PERICFG_AO_BASE + ofs)
+
+#undef SPM_PWR_STATUS
+#define SPM_PWR_STATUS MT_LP_TZ_SPM_REG(0x016C)
+#define SPM_PWR_STATUS_2ND MT_LP_TZ_SPM_REG(0x0170)
+#define SPM_CPU_PWR_STATUS MT_LP_TZ_SPM_REG(0x0174)
+#define INFRA_SW_CG0 MT_LP_TZ_INFRA_REG(0x0090)
+#define INFRA_SW_CG1 MT_LP_TZ_INFRA_REG(0x0094)
+#define INFRA_SW_CG2 MT_LP_TZ_INFRA_REG(0x00AC)
+#define INFRA_SW_CG3 MT_LP_TZ_INFRA_REG(0x00C8)
+#define INFRA_SW_CG4 MT_LP_TZ_INFRA_REG(0x00E8)
+#define TOP_SW_I2C_CG MT_LP_TZ_TOPCK_REG(0x00A4)
+#define PERI_SW_CG0 MT_LP_TZ_PERI_AO_REG(0x0018)
+#define VPPSYS0_SW_CG0 MT_LP_TZ_VPPSYS0_REG(0x0020)
+#define VPPSYS0_SW_CG1 MT_LP_TZ_VPPSYS0_REG(0x002C)
+#define VPPSYS0_SW_CG2 MT_LP_TZ_VPPSYS0_REG(0x0038)
+#define VPPSYS1_SW_CG0 MT_LP_TZ_VPPSYS1_REG(0x0100)
+#define VPPSYS1_SW_CG1 MT_LP_TZ_VPPSYS1_REG(0x0110)
+#define VDOSYS0_SW_CG0 MT_LP_TZ_VDOSYS0_REG(0x0100)
+#define VDOSYS0_SW_CG1 MT_LP_TZ_VDOSYS0_REG(0x0110)
+#define VDOSYS1_SW_CG0 MT_LP_TZ_VDOSYS1_REG(0x0100)
+#define VDOSYS1_SW_CG1 MT_LP_TZ_VDOSYS1_REG(0x0120)
+#define VDOSYS1_SW_CG2 MT_LP_TZ_VDOSYS1_REG(0x0130)
+
+#define CLK_CFG(id) MT_LP_TZ_TOPCK_REG(0x2c + id * 0xc)
+
+enum {
+ /* CLK_CFG_0 1000_002c */
+ CLKMUX_VPP = 0,
+ NF_CLKMUX,
+};
+
+#define CLK_CHECK BIT(31)
+
+static bool check_clkmux_pdn(unsigned int clkmux_id)
+{
+ unsigned int reg, val, idx;
+ bool ret = false;
+
+ if ((clkmux_id & CLK_CHECK) != 0U) {
+ clkmux_id = (clkmux_id & ~CLK_CHECK);
+ reg = clkmux_id / 4U;
+ val = mmio_read_32(CLK_CFG(reg));
+ idx = clkmux_id % 4U;
+ ret = (((val >> (idx * 8U)) & 0x80) != 0U);
+ }
+
+ return ret;
+}
+
+static struct mt_spm_cond_tables spm_cond_t;
+
+/* local definitions */
+struct idle_cond_info {
+ /* check SPM_PWR_STATUS for bit definition */
+ unsigned int subsys_mask;
+ /* cg address */
+ uintptr_t addr;
+ /* bitflip value from *addr ? */
+ bool bBitflip;
+ /* check clkmux if bit 31 = 1, id is bit[30:0] */
+ unsigned int clkmux_id;
+};
+
+#define IDLE_CG(mask, addr, bitflip, clkmux) {mask, (uintptr_t)addr, bitflip, clkmux}
+
+static struct idle_cond_info idle_cg_info[PLAT_SPM_COND_MAX] = {
+ IDLE_CG(0xffffffff, SPM_PWR_STATUS, false, 0),
+ IDLE_CG(0xffffffff, SPM_CPU_PWR_STATUS, false, 0),
+ IDLE_CG(0xffffffff, INFRA_SW_CG0, true, 0),
+ IDLE_CG(0xffffffff, INFRA_SW_CG1, true, 0),
+ IDLE_CG(0xffffffff, INFRA_SW_CG2, true, 0),
+ IDLE_CG(0xffffffff, INFRA_SW_CG3, true, 0),
+ IDLE_CG(0xffffffff, INFRA_SW_CG4, true, 0),
+ IDLE_CG(0xffffffff, PERI_SW_CG0, true, 0),
+ IDLE_CG(0x00000800, VPPSYS0_SW_CG0, true, (CLK_CHECK | CLKMUX_VPP)),
+ IDLE_CG(0x00000800, VPPSYS0_SW_CG1, true, (CLK_CHECK | CLKMUX_VPP)),
+ IDLE_CG(0x00001000, VPPSYS1_SW_CG0, true, (CLK_CHECK | CLKMUX_VPP)),
+ IDLE_CG(0x00001000, VPPSYS1_SW_CG1, true, (CLK_CHECK | CLKMUX_VPP)),
+ IDLE_CG(0x00002000, VDOSYS0_SW_CG0, true, (CLK_CHECK | CLKMUX_VPP)),
+ IDLE_CG(0x00002000, VDOSYS0_SW_CG1, true, (CLK_CHECK | CLKMUX_VPP)),
+ IDLE_CG(0x00004000, VDOSYS1_SW_CG0, true, (CLK_CHECK | CLKMUX_VPP)),
+ IDLE_CG(0x00004000, VDOSYS1_SW_CG1, true, (CLK_CHECK | CLKMUX_VPP)),
+ IDLE_CG(0x00004000, VDOSYS1_SW_CG2, true, (CLK_CHECK | CLKMUX_VPP)),
+};
+
+/* check pll idle condition */
+#define PLL_MFGPLL MT_LP_TZ_APMIXEDSYS(0x340)
+#define PLL_MMPLL MT_LP_TZ_APMIXEDSYS(0x544)
+#define PLL_UNIVPLL MT_LP_TZ_APMIXEDSYS(0x504)
+#define PLL_MSDCPLL MT_LP_TZ_APMIXEDSYS(0x514)
+#define PLL_TVDPLL1 MT_LP_TZ_APMIXEDSYS(0x524)
+#define PLL_TVDPLL2 MT_LP_TZ_APMIXEDSYS(0x534)
+#define PLL_ETHPLL MT_LP_TZ_APMIXEDSYS(0x44c)
+#define PLL_IMGPLL MT_LP_TZ_APMIXEDSYS(0x554)
+#define PLL_APLL1 MT_LP_TZ_APMIXEDSYS(0x304)
+#define PLL_APLL2 MT_LP_TZ_APMIXEDSYS(0x318)
+#define PLL_APLL3 MT_LP_TZ_APMIXEDSYS(0x32c)
+#define PLL_APLL4 MT_LP_TZ_APMIXEDSYS(0x404)
+#define PLL_APLL5 MT_LP_TZ_APMIXEDSYS(0x418)
+
+unsigned int mt_spm_cond_check(const struct mt_spm_cond_tables *src,
+ const struct mt_spm_cond_tables *dest,
+ struct mt_spm_cond_tables *res)
+{
+ unsigned int b_res = 0U;
+ unsigned int i;
+
+ if ((src == NULL) || (dest == NULL)) {
+ return SPM_COND_CHECK_FAIL;
+ }
+
+ for (i = 0; i < PLAT_SPM_COND_MAX; i++) {
+ if (res != NULL) {
+ res->table_cg[i] = (src->table_cg[i] & dest->table_cg[i]);
+
+ if ((res->table_cg[i]) != 0U) {
+ b_res |= BIT(i);
+ }
+ } else if ((src->table_cg[i] & dest->table_cg[i]) != 0U) {
+ b_res |= BIT(i);
+ break;
+ }
+ }
+
+ if (res != NULL) {
+ res->table_pll = (src->table_pll & dest->table_pll);
+
+ if ((res->table_pll) != 0U) {
+ b_res |= (res->table_pll << SPM_COND_BLOCKED_PLL_IDX) |
+ SPM_COND_CHECK_BLOCKED_PLL;
+ }
+ } else if ((src->table_pll & dest->table_pll) != 0U) {
+ b_res |= SPM_COND_CHECK_BLOCKED_PLL;
+ }
+
+ return b_res;
+}
+
+unsigned int mt_spm_dump_all_pll(const struct mt_spm_cond_tables *src,
+ const struct mt_spm_cond_tables *dest,
+ struct mt_spm_cond_tables *res)
+{
+ unsigned int b_res = 0U;
+
+ if (res != NULL) {
+ res->table_all_pll = src->table_all_pll;
+ if ((res->table_all_pll) != 0U) {
+ b_res |= (res->table_all_pll << SPM_COND_BLOCKED_PLL_IDX) |
+ SPM_COND_CHECK_BLOCKED_PLL;
+ }
+ } else if ((src->table_pll & dest->table_pll) != 0U) {
+ b_res |= SPM_COND_CHECK_BLOCKED_PLL;
+ }
+
+ return b_res;
+}
+
+#define IS_MT_SPM_PWR_OFF(mask) \
+ (!(mmio_read_32(SPM_PWR_STATUS) & mask) && \
+ !(mmio_read_32(SPM_PWR_STATUS_2ND) & mask))
+
+int mt_spm_cond_update(struct mt_resource_constraint **con, unsigned int num,
+ int stateid, void *priv)
+{
+ static const struct {
+ uintptr_t en_reg;
+ uint32_t pll_b;
+ } plls[] = {
+ { PLL_MFGPLL, PLL_BIT_MFGPLL },
+ { PLL_MMPLL, PLL_BIT_MMPLL },
+ { PLL_UNIVPLL, PLL_BIT_UNIVPLL },
+ { PLL_MSDCPLL, PLL_BIT_MSDCPLL },
+ { PLL_TVDPLL1, PLL_BIT_TVDPLL1 },
+ { PLL_TVDPLL2, PLL_BIT_TVDPLL2 },
+ { PLL_ETHPLL, PLL_BIT_ETHPLL },
+ { PLL_IMGPLL, PLL_BIT_IMGPLL },
+ { PLL_APLL1, PLL_BIT_APLL1 },
+ { PLL_APLL2, PLL_BIT_APLL2 },
+ { PLL_APLL3, PLL_BIT_APLL3 },
+ { PLL_APLL4, PLL_BIT_APLL4 },
+ { PLL_APLL5, PLL_BIT_APLL5 },
+ };
+
+ int res;
+ unsigned int i;
+ struct mt_resource_constraint *const *_con;
+
+ /* read all cg state */
+ for (i = 0U; i < PLAT_SPM_COND_MAX; i++) {
+ spm_cond_t.table_cg[i] = 0U;
+
+ /* check mtcmos, if off set idle_value and clk to 0 disable */
+ if (IS_MT_SPM_PWR_OFF(idle_cg_info[i].subsys_mask)) {
+ continue;
+ }
+ /* check clkmux */
+ if (check_clkmux_pdn(idle_cg_info[i].clkmux_id)) {
+ continue;
+ }
+ spm_cond_t.table_cg[i] = idle_cg_info[i].bBitflip ?
+ ~mmio_read_32(idle_cg_info[i].addr) :
+ mmio_read_32(idle_cg_info[i].addr);
+ }
+
+ spm_cond_t.table_pll = 0U;
+ for (i = 0U; i < ARRAY_SIZE(plls); i++) {
+ if ((mmio_read_32(plls[i].en_reg) & BIT(9)) != 0U) {
+ spm_cond_t.table_pll |= plls[i].pll_b;
+ }
+ }
+
+ spm_cond_t.priv = priv;
+ for (i = 0U, _con = con; (*_con != NULL) && (i < num); _con++, i++) {
+ if ((*_con)->update == NULL) {
+ continue;
+ }
+ res = (*_con)->update(stateid, PLAT_RC_UPDATE_CONDITION,
+ (void const *)&spm_cond_t);
+ if (res != MT_RM_STATUS_OK) {
+ break;
+ }
+ }
+
+ return 0;
+}
diff --git a/plat/mediatek/drivers/spm/mt8188/mt_spm_cond.h b/plat/mediatek/drivers/spm/mt8188/mt_spm_cond.h
new file mode 100644
index 0000000..793d5e8
--- /dev/null
+++ b/plat/mediatek/drivers/spm/mt8188/mt_spm_cond.h
@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_COND_H
+#define MT_SPM_COND_H
+
+#include <lpm/mt_lp_rm.h>
+
+enum plat_spm_cond {
+ PLAT_SPM_COND_MTCMOS1 = 0,
+ PLAT_SPM_COND_MTCMOS2,
+ PLAT_SPM_COND_CG_INFRA_0,
+ PLAT_SPM_COND_CG_INFRA_1,
+ PLAT_SPM_COND_CG_INFRA_2,
+ PLAT_SPM_COND_CG_INFRA_3,
+ PLAT_SPM_COND_CG_INFRA_4,
+ PLAT_SPM_COND_CG_PERI_0,
+ PLAT_SPM_COND_CG_VPPSYS0_0,
+ PLAT_SPM_COND_CG_VPPSYS0_1,
+ PLAT_SPM_COND_CG_VPPSYS1_0,
+ PLAT_SPM_COND_CG_VPPSYS1_1,
+ PLAT_SPM_COND_CG_VDOSYS0_0,
+ PLAT_SPM_COND_CG_VDOSYS0_1,
+ PLAT_SPM_COND_CG_VDOSYS1_0,
+ PLAT_SPM_COND_CG_VDOSYS1_1,
+ PLAT_SPM_COND_CG_VDOSYS1_2,
+ PLAT_SPM_COND_MAX,
+};
+
+/* For PLL id >= PLAT_SPM_COND_PLL_MAX is not checked in idle condition */
+enum plat_spm_cond_pll {
+ PLAT_SPM_COND_PLL_UNIVPLL = 0,
+ PLAT_SPM_COND_PLL_MFGPLL,
+ PLAT_SPM_COND_PLL_MSDCPLL,
+ PLAT_SPM_COND_PLL_TVDPLL1,
+ PLAT_SPM_COND_PLL_TVDPLL2,
+ PLAT_SPM_COND_PLL_MMPLL,
+ PLAT_SPM_COND_PLL_ETHPLL,
+ PLAT_SPM_COND_PLL_IMGPLL,
+ PLAT_SPM_COND_PLL_APLL1,
+ PLAT_SPM_COND_PLL_APLL2,
+ PLAT_SPM_COND_PLL_APLL3,
+ PLAT_SPM_COND_PLL_APLL4,
+ PLAT_SPM_COND_PLL_APLL5,
+ PLAT_SPM_COND_PLL_MAX,
+};
+
+#define PLL_BIT_MFGPLL BIT(PLAT_SPM_COND_PLL_MFGPLL)
+#define PLL_BIT_MMPLL BIT(PLAT_SPM_COND_PLL_MMPLL)
+#define PLL_BIT_UNIVPLL BIT(PLAT_SPM_COND_PLL_UNIVPLL)
+#define PLL_BIT_MSDCPLL BIT(PLAT_SPM_COND_PLL_MSDCPLL)
+#define PLL_BIT_TVDPLL1 BIT(PLAT_SPM_COND_PLL_TVDPLL1)
+#define PLL_BIT_TVDPLL2 BIT(PLAT_SPM_COND_PLL_TVDPLL2)
+#define PLL_BIT_ETHPLL BIT(PLAT_SPM_COND_PLL_ETHPLL)
+#define PLL_BIT_IMGPLL BIT(PLAT_SPM_COND_PLL_IMGPLL)
+#define PLL_BIT_APLL1 BIT(PLAT_SPM_COND_PLL_APLL1)
+#define PLL_BIT_APLL2 BIT(PLAT_SPM_COND_PLL_APLL2)
+#define PLL_BIT_APLL3 BIT(PLAT_SPM_COND_PLL_APLL3)
+#define PLL_BIT_APLL4 BIT(PLAT_SPM_COND_PLL_APLL4)
+#define PLL_BIT_APLL5 BIT(PLAT_SPM_COND_PLL_APLL5)
+
+/*
+ * Definition about SPM_COND_CHECK_BLOCKED
+ * bit[00:16]: cg blocking index
+ * bit[17:29]: pll blocking index
+ * bit[30]: pll blocking information
+ * bit[31]: idle condition check fail
+ */
+#define SPM_COND_BLOCKED_CG_IDX (0)
+#define SPM_COND_BLOCKED_PLL_IDX (17)
+#define SPM_COND_CHECK_BLOCKED_PLL BIT(30)
+#define SPM_COND_CHECK_FAIL BIT(31)
+
+struct mt_spm_cond_tables {
+ unsigned int table_cg[PLAT_SPM_COND_MAX];
+ unsigned int table_pll;
+ unsigned int table_all_pll;
+ void *priv;
+};
+
+unsigned int mt_spm_cond_check(const struct mt_spm_cond_tables *src,
+ const struct mt_spm_cond_tables *dest,
+ struct mt_spm_cond_tables *res);
+unsigned int mt_spm_dump_all_pll(const struct mt_spm_cond_tables *src,
+ const struct mt_spm_cond_tables *dest,
+ struct mt_spm_cond_tables *res);
+int mt_spm_cond_update(struct mt_resource_constraint **con, unsigned int num,
+ int stateid, void *priv);
+
+#endif
diff --git a/plat/mediatek/drivers/spm/mt8188/mt_spm_conservation.c b/plat/mediatek/drivers/spm/mt8188/mt_spm_conservation.c
new file mode 100644
index 0000000..bcb2df6
--- /dev/null
+++ b/plat/mediatek/drivers/spm/mt8188/mt_spm_conservation.c
@@ -0,0 +1,130 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <stddef.h>
+#include <stdio.h>
+#include <string.h>
+
+#include <common/debug.h>
+#include <lib/mmio.h>
+#include <plat/common/platform.h>
+#include <lib/pm/mtk_pm.h>
+#include <lpm/mt_lp_rqm.h>
+#include "mt_spm.h"
+#include "mt_spm_conservation.h"
+#include "mt_spm_reg.h"
+#include <platform_def.h>
+
+#define INFRA_EMI_DCM_CFG0 U(0x10002028)
+
+static struct wake_status spm_wakesta; /* record last wakesta */
+static wake_reason_t spm_wake_reason = WR_NONE;
+static unsigned int emi_bak;
+
+static int go_to_spm_before_wfi(int state_id, unsigned int ext_opand,
+ struct spm_lp_scen *spm_lp,
+ unsigned int resource_req)
+{
+ int ret = 0;
+ struct pwr_ctrl *pwrctrl;
+ unsigned int cpu = plat_my_core_pos();
+
+ pwrctrl = spm_lp->pwrctrl;
+
+ /* EMI workaround */
+ emi_bak = mmio_read_32(INFRA_EMI_DCM_CFG0) & BIT(22);
+ mmio_setbits_32(INFRA_EMI_DCM_CFG0, BIT(22));
+
+ __spm_set_cpu_status(cpu);
+ __spm_set_power_control(pwrctrl);
+ __spm_set_wakeup_event(pwrctrl);
+
+ __spm_set_pcm_flags(pwrctrl);
+
+ __spm_src_req_update(pwrctrl, resource_req);
+
+ if ((ext_opand & MT_SPM_EX_OP_CLR_26M_RECORD) != 0U) {
+ __spm_clean_before_wfi();
+ }
+
+ if ((ext_opand & MT_SPM_EX_OP_SET_WDT) != 0U) {
+ __spm_set_pcm_wdt(1);
+ }
+
+ if ((ext_opand & MT_SPM_EX_OP_HW_S1_DETECT) != 0U) {
+ spm_hw_s1_state_monitor_resume();
+ }
+
+ __spm_send_cpu_wakeup_event();
+
+ return ret;
+}
+
+static void go_to_spm_after_wfi(int state_id, unsigned int ext_opand,
+ struct spm_lp_scen *spm_lp,
+ struct wake_status **status)
+{
+ unsigned int ext_status = 0U;
+
+ if ((ext_opand & MT_SPM_EX_OP_SET_WDT) != 0U) {
+ __spm_set_pcm_wdt(0);
+ }
+
+ if ((ext_opand & MT_SPM_EX_OP_HW_S1_DETECT) != 0U) {
+ spm_hw_s1_state_monitor_pause(&ext_status);
+ }
+
+ __spm_ext_int_wakeup_req_clr();
+
+ __spm_get_wakeup_status(&spm_wakesta, ext_status);
+
+ if (status != NULL) {
+ *status = &spm_wakesta;
+ }
+
+ __spm_clean_after_wakeup();
+ spm_wake_reason = __spm_output_wake_reason(&spm_wakesta);
+
+ /* EMI workaround */
+ if (emi_bak == 0U) {
+ mmio_clrbits_32(INFRA_EMI_DCM_CFG0, BIT(22));
+ }
+}
+
+int spm_conservation(int state_id, unsigned int ext_opand,
+ struct spm_lp_scen *spm_lp,
+ unsigned int resource_req)
+{
+ unsigned int rc_state = resource_req;
+
+ if (spm_lp == NULL) {
+ return -1;
+ }
+
+ spin_lock(&spm_lock);
+ go_to_spm_before_wfi(state_id, ext_opand, spm_lp, rc_state);
+ spin_unlock(&spm_lock);
+
+ return 0;
+}
+
+void spm_conservation_finish(int state_id, unsigned int ext_opand, struct spm_lp_scen *spm_lp,
+ struct wake_status **status)
+{
+ spin_lock(&spm_lock);
+ go_to_spm_after_wfi(state_id, ext_opand, spm_lp, status);
+ spin_unlock(&spm_lock);
+}
+
+int spm_conservation_get_result(struct wake_status **res)
+{
+ if (res == NULL) {
+ return -1;
+ }
+ *res = &spm_wakesta;
+ return 0;
+}
diff --git a/plat/mediatek/drivers/spm/mt8188/mt_spm_conservation.h b/plat/mediatek/drivers/spm/mt8188/mt_spm_conservation.h
new file mode 100644
index 0000000..4be8567
--- /dev/null
+++ b/plat/mediatek/drivers/spm/mt8188/mt_spm_conservation.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_CONSERVATION_H
+#define MT_SPM_CONSERVATION_H
+
+#include "mt_spm_internal.h"
+
+int spm_conservation(int state_id, unsigned int ext_opand,
+ struct spm_lp_scen *spm_lp,
+ unsigned int resource_req);
+void spm_conservation_finish(int state_id, unsigned int ext_opand,
+ struct spm_lp_scen *spm_lp,
+ struct wake_status **status);
+int spm_conservation_get_result(struct wake_status **res);
+
+#endif /* MT_SPM_CONSERVATION_H */
diff --git a/plat/mediatek/drivers/spm/mt8188/mt_spm_constraint.h b/plat/mediatek/drivers/spm/mt8188/mt_spm_constraint.h
new file mode 100644
index 0000000..43bb76b
--- /dev/null
+++ b/plat/mediatek/drivers/spm/mt8188/mt_spm_constraint.h
@@ -0,0 +1,89 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_CONSTRAINT_H
+#define MT_SPM_CONSTRAINT_H
+
+#include <lpm/mt_lp_rm.h>
+
+#define MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF BIT(0)
+#define MT_RM_CONSTRAINT_ALLOW_DRAM_S0 BIT(1)
+#define MT_RM_CONSTRAINT_ALLOW_DRAM_S1 BIT(2)
+#define MT_RM_CONSTRAINT_ALLOW_VCORE_LP BIT(3)
+#define MT_RM_CONSTRAINT_ALLOW_INFRA_PDN BIT(4)
+#define MT_RM_CONSTRAINT_ALLOW_BUS26M_OFF BIT(5)
+#define MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND BIT(6)
+#define MT_RM_CONSTRAINT_ALLOW_BBLPM BIT(7)
+#define MT_RM_CONSTRAINT_ALLOW_XO_UFS BIT(8)
+#define MT_RM_CONSTRAINT_ALLOW_GPS_STATE BIT(9)
+#define MT_RM_CONSTRAINT_ALLOW_LVTS_STATE BIT(10)
+
+enum mt_spm_rm_rc_type {
+ MT_RM_CONSTRAINT_ID_BUS26M,
+ MT_RM_CONSTRAINT_ID_SYSPLL,
+ MT_RM_CONSTRAINT_ID_DRAM,
+ MT_RM_CONSTRAINT_ID_CPU_BUCK_LDO,
+ MT_RM_CONSTRAINT_ID_ALL,
+};
+
+#define MT_SPM_RC_INVALID (0x0)
+#define MT_SPM_RC_VALID_SW BIT(0)
+#define MT_SPM_RC_VALID_FW BIT(1)
+#define MT_SPM_RC_VALID_RESIDNECY BIT(2)
+#define MT_SPM_RC_VALID_COND_CHECK BIT(3)
+#define MT_SPM_RC_VALID_COND_LATCH BIT(4)
+#define MT_SPM_RC_VALID_UFS_H8 BIT(5)
+#define MT_SPM_RC_VALID_FLIGHTMODE BIT(6)
+#define MT_SPM_RC_VALID_XSOC_BBLPM BIT(7)
+#define MT_SPM_RC_VALID_TRACE_EVENT BIT(8)
+#define MT_SPM_RC_VALID_TRACE_TIME BIT(9)
+
+/* MT_RM_CONSTRAINT_SW_VALID | MT_RM_CONSTRAINT_FW_VALID */
+#define MT_SPM_RC_VALID (MT_SPM_RC_VALID_SW)
+
+#define IS_MT_RM_RC_READY(status) ((status & MT_SPM_RC_VALID) == MT_SPM_RC_VALID)
+
+struct constraint_status {
+ uint16_t id;
+ uint16_t is_valid;
+ uint32_t is_cond_block;
+ uint32_t enter_cnt;
+ uint32_t all_pll_dump;
+ uint64_t residency;
+ struct mt_spm_cond_tables *cond_res;
+};
+
+enum constraint_status_update_type {
+ CONSTRAINT_UPDATE_VALID,
+ CONSTRAINT_UPDATE_COND_CHECK,
+ CONSTRAINT_RESIDNECY,
+};
+
+enum constraint_status_get_type {
+ CONSTRAINT_GET_VALID = 0xD0000000,
+ CONSTRAINT_GET_ENTER_CNT,
+ CONSTRAINT_GET_RESIDENCY,
+ CONSTRAINT_GET_COND_EN,
+ CONSTRAINT_COND_BLOCK,
+ CONSTRAINT_GET_COND_BLOCK_LATCH,
+ CONSTRAINT_GET_COND_BLOCK_DETAIL,
+ CONSTRAINT_GET_RESIDNECY,
+};
+
+struct rc_common_state {
+ unsigned int id;
+ unsigned int act;
+ unsigned int type;
+ void *value;
+};
+
+#define MT_SPM_RC_BBLPM_MODE (MT_SPM_RC_VALID_UFS_H8 | \
+ MT_SPM_RC_VALID_FLIGHTMODE | \
+ MT_SPM_RC_VALID_XSOC_BBLPM)
+
+#define IS_MT_SPM_RC_BBLPM_MODE(st) ((st & (MT_SPM_RC_BBLPM_MODE)) == MT_SPM_RC_BBLPM_MODE)
+
+#endif /* MT_SPM_CONSTRAINT_H */
diff --git a/plat/mediatek/drivers/spm/mt8188/mt_spm_idle.c b/plat/mediatek/drivers/spm/mt8188/mt_spm_idle.c
new file mode 100644
index 0000000..b4dc3f9
--- /dev/null
+++ b/plat/mediatek/drivers/spm/mt8188/mt_spm_idle.c
@@ -0,0 +1,369 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stddef.h>
+#include <stdio.h>
+#include <string.h>
+#include <common/debug.h>
+#include <lib/mmio.h>
+#include <drivers/spm/mt_spm_resource_req.h>
+#include <lib/pm/mtk_pm.h>
+#include <lpm/mt_lp_api.h>
+
+#include <mt_spm.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_idle.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_reg.h>
+
+#define SPM_BYPASS_SYSPWREQ_GENERIC (1)
+
+#define __WAKE_SRC_FOR_IDLE_COMMON__ ( \
+ (R12_PCM_TIMER) | \
+ (R12_KP_IRQ_B) | \
+ (R12_APWDT_EVENT_B) | \
+ (R12_APXGPT1_EVENT_B) | \
+ (R12_MSDC_WAKEUP_B) | \
+ (R12_EINT_EVENT_B) | \
+ (R12_SBD_INTR_WAKEUP_B) | \
+ (R12_SSPM2SPM_WAKEUP_B) | \
+ (R12_SCP2SPM_WAKEUP_B) | \
+ (R12_ADSP2SPM_WAKEUP_B) | \
+ (R12_USBX_CDSC_B) | \
+ (R12_USBX_POWERDWN_B) | \
+ (R12_SYS_TIMER_EVENT_B) | \
+ (R12_EINT_EVENT_SECURE_B) | \
+ (R12_ECE_INT_HDMI_B) | \
+ (R12_AFE_IRQ_MCU_B) | \
+ (R12_SYS_CIRQ_IRQ_B) | \
+ (R12_PCIE_WAKEUPEVENT_B) | \
+ (R12_SPM_CPU_WAKEUPEVENT_B) | \
+ (R12_APUSYS_WAKE_HOST_B))
+
+#if defined(CFG_MICROTRUST_TEE_SUPPORT)
+#define WAKE_SRC_FOR_IDLE (__WAKE_SRC_FOR_IDLE_COMMON__)
+#else
+#define WAKE_SRC_FOR_IDLE (__WAKE_SRC_FOR_IDLE_COMMON__ | R12_SEJ_EVENT_B)
+#endif
+
+static struct pwr_ctrl idle_spm_pwr = {
+ .wake_src = WAKE_SRC_FOR_IDLE,
+
+ /* SPM_AP_STANDBY_CON */
+ /* [0] */
+ .reg_wfi_op = 0,
+ /* [1] */
+ .reg_wfi_type = 0,
+ /* [2] */
+ .reg_mp0_cputop_idle_mask = 0,
+ /* [3] */
+ .reg_mp1_cputop_idle_mask = 0,
+ /* [4] */
+ .reg_mcusys_idle_mask = 0,
+ /* [25] */
+ .reg_md_apsrc_1_sel = 0,
+ /* [26] */
+ .reg_md_apsrc_0_sel = 0,
+ /* [29] */
+ .reg_conn_apsrc_sel = 0,
+
+ /* SPM_SRC_REQ */
+ /* [0] */
+ .reg_spm_apsrc_req = 0,
+ /* [1] */
+ .reg_spm_f26m_req = 0,
+ /* [3] */
+ .reg_spm_infra_req = 0,
+ /* [4] */
+ .reg_spm_vrf18_req = 0,
+ /* [7] */
+ .reg_spm_ddr_en_req = 0,
+ /* [8] */
+ .reg_spm_dvfs_req = 0,
+ /* [9] */
+ .reg_spm_sw_mailbox_req = 0,
+ /* [10] */
+ .reg_spm_sspm_mailbox_req = 0,
+ /* [11] */
+ .reg_spm_adsp_mailbox_req = 0,
+ /* [12] */
+ .reg_spm_scp_mailbox_req = 0,
+
+ /* SPM_SRC_MASK */
+ /* [0] */
+ .reg_sspm_srcclkena_0_mask_b = 1,
+ /* [1] */
+ .reg_sspm_infra_req_0_mask_b = 1,
+ /* [2] */
+ .reg_sspm_apsrc_req_0_mask_b = 1,
+ /* [3] */
+ .reg_sspm_vrf18_req_0_mask_b = 1,
+ /* [4] */
+ .reg_sspm_ddr_en_0_mask_b = 1,
+ /* [5] */
+ .reg_scp_srcclkena_mask_b = 1,
+ /* [6] */
+ .reg_scp_infra_req_mask_b = 1,
+ /* [7] */
+ .reg_scp_apsrc_req_mask_b = 1,
+ /* [8] */
+ .reg_scp_vrf18_req_mask_b = 1,
+ /* [9] */
+ .reg_scp_ddr_en_mask_b = 1,
+ /* [10] */
+ .reg_audio_dsp_srcclkena_mask_b = 1,
+ /* [11] */
+ .reg_audio_dsp_infra_req_mask_b = 1,
+ /* [12] */
+ .reg_audio_dsp_apsrc_req_mask_b = 1,
+ /* [13] */
+ .reg_audio_dsp_vrf18_req_mask_b = 1,
+ /* [14] */
+ .reg_audio_dsp_ddr_en_mask_b = 1,
+ /* [15] */
+ .reg_apu_srcclkena_mask_b = 1,
+ /* [16] */
+ .reg_apu_infra_req_mask_b = 1,
+ /* [17] */
+ .reg_apu_apsrc_req_mask_b = 1,
+ /* [18] */
+ .reg_apu_vrf18_req_mask_b = 1,
+ /* [19] */
+ .reg_apu_ddr_en_mask_b = 1,
+ /* [20] */
+ .reg_cpueb_srcclkena_mask_b = 1,
+ /* [21] */
+ .reg_cpueb_infra_req_mask_b = 1,
+ /* [22] */
+ .reg_cpueb_apsrc_req_mask_b = 1,
+ /* [23] */
+ .reg_cpueb_vrf18_req_mask_b = 1,
+ /* [24] */
+ .reg_cpueb_ddr_en_mask_b = 1,
+ /* [25] */
+ .reg_bak_psri_srcclkena_mask_b = 0,
+ /* [26] */
+ .reg_bak_psri_infra_req_mask_b = 0,
+ /* [27] */
+ .reg_bak_psri_apsrc_req_mask_b = 0,
+ /* [28] */
+ .reg_bak_psri_vrf18_req_mask_b = 0,
+ /* [29] */
+ .reg_bak_psri_ddr_en_mask_b = 0,
+ /* [30] */
+ .reg_cam_ddren_req_mask_b = 1,
+ /* [31] */
+ .reg_img_ddren_req_mask_b = 1,
+
+ /* SPM_SRC2_MASK */
+ /* [0] */
+ .reg_msdc0_srcclkena_mask_b = 1,
+ /* [1] */
+ .reg_msdc0_infra_req_mask_b = 1,
+ /* [2] */
+ .reg_msdc0_apsrc_req_mask_b = 1,
+ /* [3] */
+ .reg_msdc0_vrf18_req_mask_b = 1,
+ /* [4] */
+ .reg_msdc0_ddr_en_mask_b = 1,
+ /* [5] */
+ .reg_msdc1_srcclkena_mask_b = 1,
+ /* [6] */
+ .reg_msdc1_infra_req_mask_b = 1,
+ /* [7] */
+ .reg_msdc1_apsrc_req_mask_b = 1,
+ /* [8] */
+ .reg_msdc1_vrf18_req_mask_b = 1,
+ /* [9] */
+ .reg_msdc1_ddr_en_mask_b = 1,
+ /* [10] */
+ .reg_msdc2_srcclkena_mask_b = 1,
+ /* [11] */
+ .reg_msdc2_infra_req_mask_b = 1,
+ /* [12] */
+ .reg_msdc2_apsrc_req_mask_b = 1,
+ /* [13] */
+ .reg_msdc2_vrf18_req_mask_b = 1,
+ /* [14] */
+ .reg_msdc2_ddr_en_mask_b = 1,
+ /* [15] */
+ .reg_ufs_srcclkena_mask_b = 1,
+ /* [16] */
+ .reg_ufs_infra_req_mask_b = 1,
+ /* [17] */
+ .reg_ufs_apsrc_req_mask_b = 1,
+ /* [18] */
+ .reg_ufs_vrf18_req_mask_b = 1,
+ /* [19] */
+ .reg_ufs_ddr_en_mask_b = 1,
+ /* [20] */
+ .reg_usb_srcclkena_mask_b = 1,
+ /* [21] */
+ .reg_usb_infra_req_mask_b = 1,
+ /* [22] */
+ .reg_usb_apsrc_req_mask_b = 1,
+ /* [23] */
+ .reg_usb_vrf18_req_mask_b = 1,
+ /* [24] */
+ .reg_usb_ddr_en_mask_b = 1,
+ /* [25] */
+ .reg_pextp_p0_srcclkena_mask_b = 1,
+ /* [26] */
+ .reg_pextp_p0_infra_req_mask_b = 1,
+ /* [27] */
+ .reg_pextp_p0_apsrc_req_mask_b = 1,
+ /* [28] */
+ .reg_pextp_p0_vrf18_req_mask_b = 1,
+ /* [29] */
+ .reg_pextp_p0_ddr_en_mask_b = 1,
+
+ /* SPM_SRC3_MASK */
+ /* [0] */
+ .reg_pextp_p1_srcclkena_mask_b = 1,
+ /* [1] */
+ .reg_pextp_p1_infra_req_mask_b = 1,
+ /* [2] */
+ .reg_pextp_p1_apsrc_req_mask_b = 1,
+ /* [3] */
+ .reg_pextp_p1_vrf18_req_mask_b = 1,
+ /* [4] */
+ .reg_pextp_p1_ddr_en_mask_b = 1,
+ /* [5] */
+ .reg_gce0_infra_req_mask_b = 1,
+ /* [6] */
+ .reg_gce0_apsrc_req_mask_b = 1,
+ /* [7] */
+ .reg_gce0_vrf18_req_mask_b = 1,
+ /* [8] */
+ .reg_gce0_ddr_en_mask_b = 1,
+ /* [9] */
+ .reg_gce1_infra_req_mask_b = 1,
+ /* [10] */
+ .reg_gce1_apsrc_req_mask_b = 1,
+ /* [11] */
+ .reg_gce1_vrf18_req_mask_b = 1,
+ /* [12] */
+ .reg_gce1_ddr_en_mask_b = 1,
+ /* [13] */
+ .reg_spm_srcclkena_reserved_mask_b = 1,
+ /* [14] */
+ .reg_spm_infra_req_reserved_mask_b = 1,
+ /* [15] */
+ .reg_spm_apsrc_req_reserved_mask_b = 1,
+ /* [16] */
+ .reg_spm_vrf18_req_reserved_mask_b = 1,
+ /* [17] */
+ .reg_spm_ddr_en_reserved_mask_b = 1,
+ /* [18] */
+ .reg_disp0_apsrc_req_mask_b = 1,
+ /* [19] */
+ .reg_disp0_ddr_en_mask_b = 1,
+ /* [20] */
+ .reg_disp1_apsrc_req_mask_b = 1,
+ /* [21] */
+ .reg_disp1_ddr_en_mask_b = 1,
+ /* [22] */
+ .reg_disp2_apsrc_req_mask_b = 1,
+ /* [23] */
+ .reg_disp2_ddr_en_mask_b = 1,
+ /* [24] */
+ .reg_disp3_apsrc_req_mask_b = 1,
+ /* [25] */
+ .reg_disp3_ddr_en_mask_b = 1,
+ /* [26] */
+ .reg_infrasys_apsrc_req_mask_b = 0,
+ /* [27] */
+ .reg_infrasys_ddr_en_mask_b = 1,
+
+ /* [28] */
+ .reg_cg_check_srcclkena_mask_b = 1,
+ /* [29] */
+ .reg_cg_check_apsrc_req_mask_b = 1,
+ /* [30] */
+ .reg_cg_check_vrf18_req_mask_b = 1,
+ /* [31] */
+ .reg_cg_check_ddr_en_mask_b = 1,
+
+ /* SPM_SRC4_MASK */
+ /* [8:0] */
+ .reg_mcusys_merge_apsrc_req_mask_b = 0,
+ /* [17:9] */
+ .reg_mcusys_merge_ddr_en_mask_b = 0,
+ /* [19:18] */
+ .reg_dramc_md32_infra_req_mask_b = 3,
+ /* [21:20] */
+ .reg_dramc_md32_vrf18_req_mask_b = 3,
+ /* [23:22] */
+ .reg_dramc_md32_ddr_en_mask_b = 0,
+ /* [24] */
+ .reg_dvfsrc_event_trigger_mask_b = 1,
+
+ /* SPM_WAKEUP_EVENT_MASK2 */
+ /* [3:0] */
+ .reg_sc_sw2spm_wakeup_mask_b = 0,
+ /* [4] */
+ .reg_sc_adsp2spm_wakeup_mask_b = 0,
+ /* [8:5] */
+ .reg_sc_sspm2spm_wakeup_mask_b = 0,
+ /* [9] */
+ .reg_sc_scp2spm_wakeup_mask_b = 0,
+ /* [10] */
+ .reg_csyspwrup_ack_mask = 0,
+ /* [11] */
+ .reg_csyspwrup_req_mask = 1,
+
+ /* SPM_WAKEUP_EVENT_MASK */
+ /* [31:0] */
+ .reg_wakeup_event_mask = 0xC1282203,
+
+ /* SPM_WAKEUP_EVENT_EXT_MASK */
+ /* [31:0] */
+ .reg_ext_wakeup_event_mask = 0xFFFFFFFF,
+};
+
+struct spm_lp_scen idle_spm_lp = {
+ .pwrctrl = &idle_spm_pwr,
+};
+
+int mt_spm_idle_generic_enter(int state_id, unsigned int ext_opand, spm_idle_conduct fn)
+{
+ int ret = 0;
+ unsigned int src_req = 0U;
+
+ if (fn != NULL) {
+ fn(state_id, &idle_spm_lp, &src_req);
+ }
+
+ ret = spm_conservation(state_id, ext_opand, &idle_spm_lp, src_req);
+
+ if (ret == 0) {
+ struct mt_lp_publish_event event = {
+ .id = MT_LPM_PUBEVENTS_SYS_POWER_OFF,
+ .val.u32 = 0U,
+ };
+
+ MT_LP_PUBLISH_EVENT(&event);
+ }
+ return ret;
+}
+
+void mt_spm_idle_generic_resume(int state_id, unsigned int ext_opand,
+ struct wake_status **status,
+ spm_idle_conduct_restore fn)
+{
+ struct mt_lp_publish_event event = {
+ .id = MT_LPM_PUBEVENTS_SYS_POWER_ON,
+ .val.u32 = 0U,
+ };
+
+ ext_opand |= (MT_SPM_EX_OP_TIME_CHECK | MT_SPM_EX_OP_TIME_OBS);
+ spm_conservation_finish(state_id, ext_opand, &idle_spm_lp, status);
+
+ if (spm_unlikely(fn)) {
+ fn(state_id, &idle_spm_lp, *status);
+ }
+ MT_LP_PUBLISH_EVENT(&event);
+}
diff --git a/plat/mediatek/drivers/spm/mt8188/mt_spm_idle.h b/plat/mediatek/drivers/spm/mt8188/mt_spm_idle.h
new file mode 100644
index 0000000..4d78a28
--- /dev/null
+++ b/plat/mediatek/drivers/spm/mt8188/mt_spm_idle.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_IDLE_H
+#define MT_SPM_IDLE_H
+
+#include "mt_spm_internal.h"
+
+typedef int (*spm_idle_conduct)(int state_id,
+ struct spm_lp_scen *spm_lp,
+ unsigned int *resource_req);
+typedef int (*spm_idle_conduct_restore)(int state_id,
+ struct spm_lp_scen *spm_lp,
+ struct wake_status *status);
+
+int mt_spm_idle_generic_enter(int state_id, unsigned int ext_opand, spm_idle_conduct fn);
+void mt_spm_idle_generic_resume(int state_id, unsigned int ext_opand,
+ struct wake_status **status,
+ spm_idle_conduct_restore fn);
+
+#endif
diff --git a/plat/mediatek/drivers/spm/mt8188/mt_spm_internal.c b/plat/mediatek/drivers/spm/mt8188/mt_spm_internal.c
new file mode 100644
index 0000000..b38a6d0
--- /dev/null
+++ b/plat/mediatek/drivers/spm/mt8188/mt_spm_internal.c
@@ -0,0 +1,422 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <stddef.h>
+#include <stdio.h>
+#include <string.h>
+
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <lib/mmio.h>
+
+#include <drivers/spm/mt_spm_resource_req.h>
+#include "mt_spm.h"
+#include "mt_spm_internal.h"
+#include "mt_spm_pmic_wrap.h"
+#include "mt_spm_reg.h"
+#include <platform_def.h>
+
+#define SPM_INIT_DONE_US (20) /* Simulation result */
+
+wake_reason_t __spm_output_wake_reason(const struct wake_status *wakesta)
+{
+ wake_reason_t wr = WR_UNKNOWN;
+
+ if (wakesta == NULL) {
+ return wr;
+ }
+
+ if (wakesta->is_abort != 0U) {
+ VERBOSE("SPM EARLY WAKE r12 = 0x%x, debug_flag = 0x%x 0x%x\n",
+ wakesta->tr.comm.r12,
+ wakesta->tr.comm.debug_flag, wakesta->tr.comm.debug_flag1);
+ VERBOSE("SPM EARLY WAKE sw_flag = 0x%x 0x%x b_sw_flag = 0x%x 0x%x\n",
+ wakesta->sw_flag0, wakesta->sw_flag1,
+ wakesta->tr.comm.b_sw_flag0, wakesta->tr.comm.b_sw_flag1);
+ }
+
+ if ((wakesta->tr.comm.r12 & R12_PCM_TIMER) != 0U) {
+
+ if ((wakesta->wake_misc & WAKE_MISC_PCM_TIMER_EVENT) != 0U) {
+ wr = WR_PCM_TIMER;
+ }
+ }
+
+ return wr;
+}
+
+void __spm_set_cpu_status(unsigned int cpu)
+{
+ if (cpu >= 8) {
+ ERROR("%s: error cpu number %d\n", __func__, cpu);
+ return;
+ }
+ mmio_write_32(ROOT_CPUTOP_ADDR, BIT(cpu));
+ mmio_write_32(ROOT_CORE_ADDR, SPM_CPU0_PWR_CON + (cpu * 0x4) + 0x20000000);
+ /* Notify MCUPM to wake the target CPU up */
+ mmio_write_32(MCUPM_MBOX_WAKEUP_CPU, cpu);
+}
+
+void __spm_src_req_update(const struct pwr_ctrl *pwrctrl, unsigned int resource_usage)
+{
+
+ uint8_t reg_spm_apsrc_req = (resource_usage & MT_SPM_DRAM_S0) ?
+ 1 : pwrctrl->reg_spm_apsrc_req;
+ uint8_t reg_spm_ddr_en_req = (resource_usage & MT_SPM_DRAM_S1) ?
+ 1 : pwrctrl->reg_spm_ddr_en_req;
+ uint8_t reg_spm_vrf18_req = (resource_usage & MT_SPM_SYSPLL) ?
+ 1 : pwrctrl->reg_spm_vrf18_req;
+ uint8_t reg_spm_infra_req = (resource_usage & MT_SPM_INFRA) ?
+ 1 : pwrctrl->reg_spm_infra_req;
+ uint8_t reg_spm_f26m_req = (resource_usage & (MT_SPM_26M | MT_SPM_XO_FPM)) ?
+ 1 : pwrctrl->reg_spm_f26m_req;
+
+ /* SPM_SRC_REQ */
+ mmio_write_32(SPM_SRC_REQ,
+ ((reg_spm_apsrc_req & 0x1) << 0) |
+ ((reg_spm_f26m_req & 0x1) << 1) |
+ ((reg_spm_infra_req & 0x1) << 3) |
+ ((reg_spm_vrf18_req & 0x1) << 4) |
+ ((reg_spm_ddr_en_req & 0x1) << 7) |
+ ((pwrctrl->reg_spm_dvfs_req & 0x1) << 8) |
+ ((pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 9) |
+ ((pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 10) |
+ ((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 11) |
+ ((pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 12));
+}
+
+void __spm_set_power_control(const struct pwr_ctrl *pwrctrl)
+{
+ /* SPM_AP_STANDBY_CON */
+ mmio_write_32(SPM_AP_STANDBY_CON,
+ ((pwrctrl->reg_wfi_op & 0x1) << 0) |
+ ((pwrctrl->reg_wfi_type & 0x1) << 1) |
+ ((pwrctrl->reg_mp0_cputop_idle_mask & 0x1) << 2) |
+ ((pwrctrl->reg_mp1_cputop_idle_mask & 0x1) << 3) |
+ ((pwrctrl->reg_mcusys_idle_mask & 0x1) << 4) |
+ ((pwrctrl->reg_md_apsrc_1_sel & 0x1) << 25) |
+ ((pwrctrl->reg_md_apsrc_0_sel & 0x1) << 26) |
+ ((pwrctrl->reg_conn_apsrc_sel & 0x1) << 29));
+
+ /* SPM_SRC_REQ */
+ mmio_write_32(SPM_SRC_REQ,
+ ((pwrctrl->reg_spm_apsrc_req & 0x1) << 0) |
+ ((pwrctrl->reg_spm_f26m_req & 0x1) << 1) |
+ ((pwrctrl->reg_spm_infra_req & 0x1) << 3) |
+ ((pwrctrl->reg_spm_vrf18_req & 0x1) << 4) |
+ ((pwrctrl->reg_spm_ddr_en_req & 0x1) << 7) |
+ ((pwrctrl->reg_spm_dvfs_req & 0x1) << 8) |
+ ((pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 9) |
+ ((pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 10) |
+ ((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 11) |
+ ((pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 12));
+
+ /* SPM_SRC_MASK */
+ mmio_write_32(SPM_SRC_MASK,
+ ((pwrctrl->reg_sspm_srcclkena_0_mask_b & 0x1) << 0) |
+ ((pwrctrl->reg_sspm_infra_req_0_mask_b & 0x1) << 1) |
+ ((pwrctrl->reg_sspm_apsrc_req_0_mask_b & 0x1) << 2) |
+ ((pwrctrl->reg_sspm_vrf18_req_0_mask_b & 0x1) << 3) |
+ ((pwrctrl->reg_sspm_ddr_en_0_mask_b & 0x1) << 4) |
+ ((pwrctrl->reg_scp_srcclkena_mask_b & 0x1) << 5) |
+ ((pwrctrl->reg_scp_infra_req_mask_b & 0x1) << 6) |
+ ((pwrctrl->reg_scp_apsrc_req_mask_b & 0x1) << 7) |
+ ((pwrctrl->reg_scp_vrf18_req_mask_b & 0x1) << 8) |
+ ((pwrctrl->reg_scp_ddr_en_mask_b & 0x1) << 9) |
+ ((pwrctrl->reg_audio_dsp_srcclkena_mask_b & 0x1) << 10) |
+ ((pwrctrl->reg_audio_dsp_infra_req_mask_b & 0x1) << 11) |
+ ((pwrctrl->reg_audio_dsp_apsrc_req_mask_b & 0x1) << 12) |
+ ((pwrctrl->reg_audio_dsp_vrf18_req_mask_b & 0x1) << 13) |
+ ((pwrctrl->reg_audio_dsp_ddr_en_mask_b & 0x1) << 14) |
+ ((pwrctrl->reg_apu_srcclkena_mask_b & 0x1) << 15) |
+ ((pwrctrl->reg_apu_infra_req_mask_b & 0x1) << 16) |
+ ((pwrctrl->reg_apu_apsrc_req_mask_b & 0x1) << 17) |
+ ((pwrctrl->reg_apu_vrf18_req_mask_b & 0x1) << 18) |
+ ((pwrctrl->reg_apu_ddr_en_mask_b & 0x1) << 19) |
+ ((pwrctrl->reg_cpueb_srcclkena_mask_b & 0x1) << 20) |
+ ((pwrctrl->reg_cpueb_infra_req_mask_b & 0x1) << 21) |
+ ((pwrctrl->reg_cpueb_apsrc_req_mask_b & 0x1) << 22) |
+ ((pwrctrl->reg_cpueb_vrf18_req_mask_b & 0x1) << 23) |
+ ((pwrctrl->reg_cpueb_ddr_en_mask_b & 0x1) << 24) |
+ ((pwrctrl->reg_bak_psri_srcclkena_mask_b & 0x1) << 25) |
+ ((pwrctrl->reg_bak_psri_infra_req_mask_b & 0x1) << 26) |
+ ((pwrctrl->reg_bak_psri_apsrc_req_mask_b & 0x1) << 27) |
+ ((pwrctrl->reg_bak_psri_vrf18_req_mask_b & 0x1) << 28) |
+ ((pwrctrl->reg_bak_psri_ddr_en_mask_b & 0x1) << 29) |
+ ((pwrctrl->reg_cam_ddren_req_mask_b & 0x1) << 30) |
+ ((pwrctrl->reg_img_ddren_req_mask_b & 0x1) << 31));
+
+ /* SPM_SRC2_MASK */
+ mmio_write_32(SPM_SRC2_MASK,
+ ((pwrctrl->reg_msdc0_srcclkena_mask_b & 0x1) << 0) |
+ ((pwrctrl->reg_msdc0_infra_req_mask_b & 0x1) << 1) |
+ ((pwrctrl->reg_msdc0_apsrc_req_mask_b & 0x1) << 2) |
+ ((pwrctrl->reg_msdc0_vrf18_req_mask_b & 0x1) << 3) |
+ ((pwrctrl->reg_msdc0_ddr_en_mask_b & 0x1) << 4) |
+ ((pwrctrl->reg_msdc1_srcclkena_mask_b & 0x1) << 5) |
+ ((pwrctrl->reg_msdc1_infra_req_mask_b & 0x1) << 6) |
+ ((pwrctrl->reg_msdc1_apsrc_req_mask_b & 0x1) << 7) |
+ ((pwrctrl->reg_msdc1_vrf18_req_mask_b & 0x1) << 8) |
+ ((pwrctrl->reg_msdc1_ddr_en_mask_b & 0x1) << 9) |
+ ((pwrctrl->reg_msdc2_srcclkena_mask_b & 0x1) << 10) |
+ ((pwrctrl->reg_msdc2_infra_req_mask_b & 0x1) << 11) |
+ ((pwrctrl->reg_msdc2_apsrc_req_mask_b & 0x1) << 12) |
+ ((pwrctrl->reg_msdc2_vrf18_req_mask_b & 0x1) << 13) |
+ ((pwrctrl->reg_msdc2_ddr_en_mask_b & 0x1) << 14) |
+ ((pwrctrl->reg_ufs_srcclkena_mask_b & 0x1) << 15) |
+ ((pwrctrl->reg_ufs_infra_req_mask_b & 0x1) << 16) |
+ ((pwrctrl->reg_ufs_apsrc_req_mask_b & 0x1) << 17) |
+ ((pwrctrl->reg_ufs_vrf18_req_mask_b & 0x1) << 18) |
+ ((pwrctrl->reg_ufs_ddr_en_mask_b & 0x1) << 19) |
+ ((pwrctrl->reg_usb_srcclkena_mask_b & 0x1) << 20) |
+ ((pwrctrl->reg_usb_infra_req_mask_b & 0x1) << 21) |
+ ((pwrctrl->reg_usb_apsrc_req_mask_b & 0x1) << 22) |
+ ((pwrctrl->reg_usb_vrf18_req_mask_b & 0x1) << 23) |
+ ((pwrctrl->reg_usb_ddr_en_mask_b & 0x1) << 24) |
+ ((pwrctrl->reg_pextp_p0_srcclkena_mask_b & 0x1) << 25) |
+ ((pwrctrl->reg_pextp_p0_infra_req_mask_b & 0x1) << 26) |
+ ((pwrctrl->reg_pextp_p0_apsrc_req_mask_b & 0x1) << 27) |
+ ((pwrctrl->reg_pextp_p0_vrf18_req_mask_b & 0x1) << 28) |
+ ((pwrctrl->reg_pextp_p0_ddr_en_mask_b & 0x1) << 29));
+
+ /* SPM_SRC3_MASK */
+ mmio_write_32(SPM_SRC3_MASK,
+ ((pwrctrl->reg_pextp_p1_srcclkena_mask_b & 0x1) << 0) |
+ ((pwrctrl->reg_pextp_p1_infra_req_mask_b & 0x1) << 1) |
+ ((pwrctrl->reg_pextp_p1_apsrc_req_mask_b & 0x1) << 2) |
+ ((pwrctrl->reg_pextp_p1_vrf18_req_mask_b & 0x1) << 3) |
+ ((pwrctrl->reg_pextp_p1_ddr_en_mask_b & 0x1) << 4) |
+ ((pwrctrl->reg_gce0_infra_req_mask_b & 0x1) << 5) |
+ ((pwrctrl->reg_gce0_apsrc_req_mask_b & 0x1) << 6) |
+ ((pwrctrl->reg_gce0_vrf18_req_mask_b & 0x1) << 7) |
+ ((pwrctrl->reg_gce0_ddr_en_mask_b & 0x1) << 8) |
+ ((pwrctrl->reg_gce1_infra_req_mask_b & 0x1) << 9) |
+ ((pwrctrl->reg_gce1_apsrc_req_mask_b & 0x1) << 10) |
+ ((pwrctrl->reg_gce1_vrf18_req_mask_b & 0x1) << 11) |
+ ((pwrctrl->reg_gce1_ddr_en_mask_b & 0x1) << 12) |
+ ((pwrctrl->reg_spm_srcclkena_reserved_mask_b & 0x1) << 13) |
+ ((pwrctrl->reg_spm_infra_req_reserved_mask_b & 0x1) << 14) |
+ ((pwrctrl->reg_spm_apsrc_req_reserved_mask_b & 0x1) << 15) |
+ ((pwrctrl->reg_spm_vrf18_req_reserved_mask_b & 0x1) << 16) |
+ ((pwrctrl->reg_spm_ddr_en_reserved_mask_b & 0x1) << 17) |
+ ((pwrctrl->reg_disp0_ddr_en_mask_b & 0x1) << 18) |
+ ((pwrctrl->reg_disp0_ddr_en_mask_b & 0x1) << 19) |
+ ((pwrctrl->reg_disp1_apsrc_req_mask_b & 0x1) << 20) |
+ ((pwrctrl->reg_disp1_ddr_en_mask_b & 0x1) << 21) |
+ ((pwrctrl->reg_disp2_apsrc_req_mask_b & 0x1) << 22) |
+ ((pwrctrl->reg_disp2_ddr_en_mask_b & 0x1) << 23) |
+ ((pwrctrl->reg_disp3_apsrc_req_mask_b & 0x1) << 24) |
+ ((pwrctrl->reg_disp3_ddr_en_mask_b & 0x1) << 25) |
+ ((pwrctrl->reg_infrasys_apsrc_req_mask_b & 0x1) << 26) |
+ ((pwrctrl->reg_infrasys_ddr_en_mask_b & 0x1) << 27));
+
+ /* SPM_SRC4_MASK */
+ mmio_write_32(SPM_SRC4_MASK,
+ ((pwrctrl->reg_mcusys_merge_apsrc_req_mask_b & 0x1ff) << 0) |
+ ((pwrctrl->reg_mcusys_merge_ddr_en_mask_b & 0x1ff) << 9) |
+ ((pwrctrl->reg_dramc_md32_infra_req_mask_b & 0x3) << 18) |
+ ((pwrctrl->reg_dramc_md32_vrf18_req_mask_b & 0x3) << 20) |
+ ((pwrctrl->reg_dramc_md32_ddr_en_mask_b & 0x3) << 22) |
+ ((pwrctrl->reg_dvfsrc_event_trigger_mask_b & 0x1) << 24));
+
+ /* SPM_WAKEUP_EVENT_MASK */
+ mmio_write_32(SPM_WAKEUP_EVENT_MASK,
+ ((pwrctrl->reg_wakeup_event_mask & 0xffffffff) << 0));
+
+ /* SPM_WAKEUP_EVENT_EXT_MASK */
+ mmio_write_32(SPM_WAKEUP_EVENT_EXT_MASK,
+ ((pwrctrl->reg_ext_wakeup_event_mask & 0xffffffff) << 0));
+}
+
+void __spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl)
+{
+ unsigned int val, mask;
+
+ /* toggle event counter clear */
+ mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY | SPM_EVENT_COUNTER_CLR_LSB);
+ /* toggle for reset SYS TIMER start point */
+ mmio_setbits_32(SYS_TIMER_CON, SYS_TIMER_START_EN_LSB);
+
+ if (pwrctrl->timer_val_cust == 0U) {
+ val = (pwrctrl->timer_val != 0U) ? pwrctrl->timer_val : PCM_TIMER_MAX;
+ } else {
+ val = pwrctrl->timer_val_cust;
+ }
+
+ mmio_write_32(PCM_TIMER_VAL, val);
+ mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY | RG_PCM_TIMER_EN_LSB);
+
+ /* unmask AP wakeup source */
+ if (pwrctrl->wake_src_cust == 0U) {
+ mask = pwrctrl->wake_src;
+ } else {
+ mask = pwrctrl->wake_src_cust;
+ }
+
+ mmio_write_32(SPM_WAKEUP_EVENT_MASK, ~mask);
+
+ /* unmask SPM ISR (keep TWAM setting) */
+ mmio_setbits_32(SPM_IRQ_MASK, ISRM_RET_IRQ_AUX);
+
+ /* toggle event counter clear */
+ mmio_clrsetbits_32(PCM_CON1, SPM_EVENT_COUNTER_CLR_LSB, SPM_REGWR_CFG_KEY);
+ /* toggle for reset SYS TIMER start point */
+ mmio_clrbits_32(SYS_TIMER_CON, SYS_TIMER_START_EN_LSB);
+}
+
+void __spm_set_pcm_flags(struct pwr_ctrl *pwrctrl)
+{
+ /* set PCM flags and data */
+ if (pwrctrl->pcm_flags_cust_clr != 0U) {
+ pwrctrl->pcm_flags &= ~pwrctrl->pcm_flags_cust_clr;
+ }
+ if (pwrctrl->pcm_flags_cust_set != 0U) {
+ pwrctrl->pcm_flags |= pwrctrl->pcm_flags_cust_set;
+ }
+ if (pwrctrl->pcm_flags1_cust_clr != 0U) {
+ pwrctrl->pcm_flags1 &= ~pwrctrl->pcm_flags1_cust_clr;
+ }
+ if (pwrctrl->pcm_flags1_cust_set != 0U) {
+ pwrctrl->pcm_flags1 |= pwrctrl->pcm_flags1_cust_set;
+ }
+
+ mmio_write_32(SPM_SW_FLAG_0, pwrctrl->pcm_flags);
+
+ mmio_write_32(SPM_SW_FLAG_1, pwrctrl->pcm_flags1);
+
+ mmio_write_32(SPM_SW_RSV_7, pwrctrl->pcm_flags);
+
+ mmio_write_32(SPM_SW_RSV_8, pwrctrl->pcm_flags1);
+}
+
+void __spm_get_wakeup_status(struct wake_status *wakesta, unsigned int ext_status)
+{
+ /* get wakeup event */
+ wakesta->tr.comm.r12 = mmio_read_32(SPM_BK_WAKE_EVENT); /* backup of PCM_REG12_DATA */
+ wakesta->r12_ext = mmio_read_32(SPM_WAKEUP_EXT_STA);
+ wakesta->tr.comm.raw_sta = mmio_read_32(SPM_WAKEUP_STA);
+ wakesta->raw_ext_sta = mmio_read_32(SPM_WAKEUP_EXT_STA);
+ wakesta->md32pcm_wakeup_sta = mmio_read_32(MD32PCM_WAKEUP_STA);
+ wakesta->md32pcm_event_sta = mmio_read_32(MD32PCM_EVENT_STA);
+ wakesta->wake_misc = mmio_read_32(SPM_BK_WAKE_MISC); /* backup of SPM_WAKEUP_MISC */
+
+ /* get sleep time */
+ wakesta->tr.comm.timer_out =
+ mmio_read_32(SPM_BK_PCM_TIMER); /* backup of PCM_TIMER_OUT */
+
+ /* get other SYS and co-clock status */
+ wakesta->tr.comm.r13 = mmio_read_32(PCM_REG13_DATA);
+ wakesta->idle_sta = mmio_read_32(SUBSYS_IDLE_STA);
+ wakesta->tr.comm.req_sta0 = mmio_read_32(SRC_REQ_STA_0);
+ wakesta->tr.comm.req_sta1 = mmio_read_32(SRC_REQ_STA_1);
+ wakesta->tr.comm.req_sta2 = mmio_read_32(SRC_REQ_STA_2);
+ wakesta->tr.comm.req_sta3 = mmio_read_32(SRC_REQ_STA_3);
+ wakesta->tr.comm.req_sta4 = mmio_read_32(SRC_REQ_STA_4);
+
+ /* get debug flag for PCM execution check */
+ wakesta->tr.comm.debug_flag = mmio_read_32(PCM_WDT_LATCH_SPARE_0);
+ wakesta->tr.comm.debug_flag1 = mmio_read_32(PCM_WDT_LATCH_SPARE_1);
+
+ if ((ext_status & SPM_INTERNAL_STATUS_HW_S1) != 0U) {
+ wakesta->tr.comm.debug_flag |= (SPM_DBG_DEBUG_IDX_DDREN_WAKE |
+ SPM_DBG_DEBUG_IDX_DDREN_SLEEP);
+ mmio_write_32(PCM_WDT_LATCH_SPARE_0, wakesta->tr.comm.debug_flag);
+ }
+
+ /* get backup SW flag status */
+ wakesta->tr.comm.b_sw_flag0 = mmio_read_32(SPM_SW_RSV_7); /* SPM_SW_RSV_7 */
+ wakesta->tr.comm.b_sw_flag1 = mmio_read_32(SPM_SW_RSV_8); /* SPM_SW_RSV_8 */
+
+ /* get ISR status */
+ wakesta->isr = mmio_read_32(SPM_IRQ_STA);
+
+ /* get SW flag status */
+ wakesta->sw_flag0 = mmio_read_32(SPM_SW_FLAG_0);
+ wakesta->sw_flag1 = mmio_read_32(SPM_SW_FLAG_1);
+
+ /* check abort */
+ wakesta->is_abort = wakesta->tr.comm.debug_flag & DEBUG_ABORT_MASK;
+ wakesta->is_abort |= wakesta->tr.comm.debug_flag1 & DEBUG_ABORT_MASK_1;
+}
+
+void __spm_clean_after_wakeup(void)
+{
+ /*
+ * Copy SPM_WAKEUP_STA to SPM_BK_WAKE_EVENT before clear SPM_WAKEUP_STA
+ *
+ * CPU dormant driver @kernel will copy edge-trig IRQ pending
+ * (recorded @SPM_BK_WAKE_EVENT) to GIC
+ */
+ mmio_write_32(SPM_BK_WAKE_EVENT, mmio_read_32(SPM_WAKEUP_STA) |
+ mmio_read_32(SPM_BK_WAKE_EVENT));
+
+ /* clean CPU wakeup event */
+ mmio_write_32(SPM_CPU_WAKEUP_EVENT, 0U);
+
+ /* clean wakeup event raw status (for edge trigger event) */
+ mmio_write_32(SPM_WAKEUP_EVENT_MASK, 0xefffffff); /* bit[28] for cpu wake up event */
+
+ /* clean ISR status (except TWAM) */
+ mmio_setbits_32(SPM_IRQ_MASK, ISRM_ALL_EXC_TWAM);
+ mmio_write_32(SPM_IRQ_STA, ISRC_ALL_EXC_TWAM);
+ mmio_write_32(SPM_SWINT_CLR, PCM_SW_INT_ALL);
+}
+
+void __spm_set_pcm_wdt(int en)
+{
+ /* enable PCM WDT (normal mode) to start count if needed */
+ if (en != 0) {
+ mmio_clrsetbits_32(PCM_CON1, RG_PCM_WDT_WAKE_LSB, SPM_REGWR_CFG_KEY);
+
+ if (mmio_read_32(PCM_TIMER_VAL) > PCM_TIMER_MAX) {
+ mmio_write_32(PCM_TIMER_VAL, PCM_TIMER_MAX);
+ }
+ mmio_write_32(PCM_WDT_VAL, mmio_read_32(PCM_TIMER_VAL) + PCM_WDT_TIMEOUT);
+ mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY | RG_PCM_WDT_EN_LSB);
+ } else {
+ mmio_clrsetbits_32(PCM_CON1, RG_PCM_WDT_EN_LSB, SPM_REGWR_CFG_KEY);
+ }
+}
+
+void __spm_send_cpu_wakeup_event(void)
+{
+ mmio_write_32(SPM_CPU_WAKEUP_EVENT, 1);
+ /* SPM will clear SPM_CPU_WAKEUP_EVENT */
+}
+
+void __spm_ext_int_wakeup_req_clr(void)
+{
+ mmio_write_32(EXT_INT_WAKEUP_REQ_CLR, mmio_read_32(ROOT_CPUTOP_ADDR));
+
+ /* clear spm2mcupm wakeup interrupt status */
+ mmio_write_32(SPM2CPUEB_CON, 0);
+}
+
+void __spm_clean_before_wfi(void)
+{
+}
+
+void __spm_hw_s1_state_monitor(int en, unsigned int *status)
+{
+ unsigned int reg;
+
+ if (en != 0) {
+ mmio_clrsetbits_32(SPM_ACK_CHK_CON_3, SPM_ACK_CHK_3_CON_CLR_ALL,
+ SPM_ACK_CHK_3_CON_EN);
+ } else {
+ reg = mmio_read_32(SPM_ACK_CHK_CON_3);
+
+ if ((reg & SPM_ACK_CHK_3_CON_RESULT) != 0U) {
+ if (status != NULL) {
+ *status |= SPM_INTERNAL_STATUS_HW_S1;
+ }
+ }
+
+ mmio_clrsetbits_32(SPM_ACK_CHK_CON_3, SPM_ACK_CHK_3_CON_EN,
+ (SPM_ACK_CHK_3_CON_HW_MODE_TRIG | SPM_ACK_CHK_3_CON_CLR_ALL));
+ }
+}
diff --git a/plat/mediatek/drivers/spm/mt8188/mt_spm_internal.h b/plat/mediatek/drivers/spm/mt8188/mt_spm_internal.h
new file mode 100644
index 0000000..c719caf
--- /dev/null
+++ b/plat/mediatek/drivers/spm/mt8188/mt_spm_internal.h
@@ -0,0 +1,668 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_INTERNAL_H
+#define MT_SPM_INTERNAL_H
+
+#include <mt_spm.h>
+
+/* PCM_WDT_VAL */
+#define PCM_WDT_TIMEOUT (30 * 32768) /* 30s */
+/* PCM_TIMER_VAL */
+#define PCM_TIMER_MAX (0xffffffff - PCM_WDT_TIMEOUT)
+
+/* PCM_PWR_IO_EN */
+#define PCM_PWRIO_EN_R0 BIT(0)
+#define PCM_PWRIO_EN_R7 BIT(7)
+#define PCM_RF_SYNC_R0 BIT(16)
+#define PCM_RF_SYNC_R6 BIT(22)
+#define PCM_RF_SYNC_R7 BIT(23)
+
+/* SPM_SWINT */
+#define PCM_SW_INT0 BIT(0)
+#define PCM_SW_INT1 BIT(1)
+#define PCM_SW_INT2 BIT(2)
+#define PCM_SW_INT3 BIT(3)
+#define PCM_SW_INT4 BIT(4)
+#define PCM_SW_INT5 BIT(5)
+#define PCM_SW_INT6 BIT(6)
+#define PCM_SW_INT7 BIT(7)
+#define PCM_SW_INT8 BIT(8)
+#define PCM_SW_INT9 BIT(9)
+#define PCM_SW_INT_ALL (PCM_SW_INT9 | PCM_SW_INT8 | PCM_SW_INT7 | \
+ PCM_SW_INT6 | PCM_SW_INT5 | PCM_SW_INT4 | \
+ PCM_SW_INT3 | PCM_SW_INT2 | PCM_SW_INT1 | \
+ PCM_SW_INT0)
+
+/* SPM_AP_STANDBY_CON */
+#define WFI_OP_AND (1U)
+#define WFI_OP_OR (0U)
+
+/* SPM_IRQ_MASK */
+#define ISRM_TWAM BIT(2)
+#define ISRM_PCM_RETURN BIT(3)
+#define ISRM_RET_IRQ0 BIT(8)
+#define ISRM_RET_IRQ1 BIT(9)
+#define ISRM_RET_IRQ2 BIT(10)
+#define ISRM_RET_IRQ3 BIT(11)
+#define ISRM_RET_IRQ4 BIT(12)
+#define ISRM_RET_IRQ5 BIT(13)
+#define ISRM_RET_IRQ6 BIT(14)
+#define ISRM_RET_IRQ7 BIT(15)
+#define ISRM_RET_IRQ8 BIT(16)
+#define ISRM_RET_IRQ9 BIT(17)
+#define ISRM_RET_IRQ_AUX ((ISRM_RET_IRQ9) | (ISRM_RET_IRQ8) | \
+ (ISRM_RET_IRQ7) | (ISRM_RET_IRQ6) | \
+ (ISRM_RET_IRQ5) | (ISRM_RET_IRQ4) | \
+ (ISRM_RET_IRQ3) | (ISRM_RET_IRQ2) | \
+ (ISRM_RET_IRQ1))
+#define ISRM_ALL_EXC_TWAM ISRM_RET_IRQ_AUX
+#define ISRM_ALL (ISRM_ALL_EXC_TWAM | ISRM_TWAM)
+
+/* SPM_IRQ_STA */
+#define ISRS_TWAM BIT(2)
+#define ISRS_PCM_RETURN BIT(3)
+#define ISRC_TWAM ISRS_TWAM
+#define ISRC_ALL_EXC_TWAM ISRS_PCM_RETURN
+#define ISRC_ALL (ISRC_ALL_EXC_TWAM | ISRC_TWAM)
+
+/* SPM_WAKEUP_MISC */
+#define WAKE_MISC_GIC_WAKEUP (0x3FF)
+#define WAKE_MISC_DVFSRC_IRQ DVFSRC_IRQ_LSB
+#define WAKE_MISC_REG_CPU_WAKEUP SPM_WAKEUP_MISC_REG_CPU_WAKEUP_LSB
+#define WAKE_MISC_PCM_TIMER_EVENT PCM_TIMER_EVENT_LSB
+#define WAKE_MISC_TWAM_IRQ_B TWAM_IRQ_B_LSB
+#define WAKE_MISC_PMSR_IRQ_B_SET0 PMSR_IRQ_B_SET0_LSB
+#define WAKE_MISC_PMSR_IRQ_B_SET1 PMSR_IRQ_B_SET1_LSB
+#define WAKE_MISC_PMSR_IRQ_B_SET2 PMSR_IRQ_B_SET2_LSB
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_0 SPM_ACK_CHK_WAKEUP_0_LSB
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_1 SPM_ACK_CHK_WAKEUP_1_LSB
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_2 SPM_ACK_CHK_WAKEUP_2_LSB
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_3 SPM_ACK_CHK_WAKEUP_3_LSB
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_ALL SPM_ACK_CHK_WAKEUP_ALL_LSB
+#define WAKE_MISC_PMIC_IRQ_ACK PMIC_IRQ_ACK_LSB
+#define WAKE_MISC_PMIC_SCP_IRQ PMIC_SCP_IRQ_LSB
+
+/* MD32PCM ADDR for SPM code fetch */
+#define MD32PCM_BASE (SPM_BASE + 0x0A00)
+#define MD32PCM_CFGREG_SW_RSTN (MD32PCM_BASE + 0x0000)
+#define MD32PCM_DMA0_SRC (MD32PCM_BASE + 0x0200)
+#define MD32PCM_DMA0_DST (MD32PCM_BASE + 0x0204)
+#define MD32PCM_DMA0_WPPT (MD32PCM_BASE + 0x0208)
+#define MD32PCM_DMA0_WPTO (MD32PCM_BASE + 0x020C)
+#define MD32PCM_DMA0_COUNT (MD32PCM_BASE + 0x0210)
+#define MD32PCM_DMA0_CON (MD32PCM_BASE + 0x0214)
+#define MD32PCM_DMA0_START (MD32PCM_BASE + 0x0218)
+#define MD32PCM_DMA0_RLCT (MD32PCM_BASE + 0x0224)
+#define MD32PCM_INTC_IRQ_RAW_STA (MD32PCM_BASE + 0x033C)
+
+/* ABORT MASK for DEBUG FOORTPRINT */
+#define DEBUG_ABORT_MASK (SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_APSRC | \
+ SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_DDREN)
+
+#define DEBUG_ABORT_MASK_1 (SPM_DBG1_DEBUG_IDX_VRCXO_SLEEP_ABORT | \
+ SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_LOW_ABORT | \
+ SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_HIGH_ABORT | \
+ SPM_DBG1_DEBUG_IDX_EMI_SLP_IDLE_ABORT | \
+ SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_LOW_ABORT | \
+ SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_HIGH_ABORT | \
+ SPM_DBG1_DEBUG_IDX_SPM_DVFS_CMD_RDY_ABORT)
+
+#define MCUPM_MBOX_WAKEUP_CPU (0x0C55FD10)
+
+struct pcm_desc {
+ const char *version; /* PCM code version */
+ uint32_t *base; /* binary array base */
+ uintptr_t base_dma; /* dma addr of base */
+ uint32_t pmem_words;
+ uint32_t total_words;
+ uint32_t pmem_start;
+ uint32_t dmem_start;
+};
+
+struct pwr_ctrl {
+ /* for SPM */
+ uint32_t pcm_flags;
+ /* can override pcm_flags */
+ uint32_t pcm_flags_cust;
+ /* set bit of pcm_flags, after pcm_flags_cust */
+ uint32_t pcm_flags_cust_set;
+ /* clr bit of pcm_flags, after pcm_flags_cust */
+ uint32_t pcm_flags_cust_clr;
+ uint32_t pcm_flags1;
+ /* can override pcm_flags1 */
+ uint32_t pcm_flags1_cust;
+ /* set bit of pcm_flags1, after pcm_flags1_cust */
+ uint32_t pcm_flags1_cust_set;
+ /* clr bit of pcm_flags1, after pcm_flags1_cust */
+ uint32_t pcm_flags1_cust_clr;
+ /* @ 1T 32K */
+ uint32_t timer_val;
+ /* @ 1T 32K, can override timer_val */
+ uint32_t timer_val_cust;
+ /* stress for dpidle */
+ uint32_t timer_val_ramp_en;
+ /* stress for suspend */
+ uint32_t timer_val_ramp_en_sec;
+ uint32_t wake_src;
+ /* can override wake_src */
+ uint32_t wake_src_cust;
+ /* disable wdt in suspend */
+ uint8_t wdt_disable;
+
+ /* SPM_AP_STANDBY_CON */
+ /* [0] */
+ uint8_t reg_wfi_op;
+ /* [1] */
+ uint8_t reg_wfi_type;
+ /* [2] */
+ uint8_t reg_mp0_cputop_idle_mask;
+ /* [3] */
+ uint8_t reg_mp1_cputop_idle_mask;
+ /* [4] */
+ uint8_t reg_mcusys_idle_mask;
+ /* [25] */
+ uint8_t reg_md_apsrc_1_sel;
+ /* [26] */
+ uint8_t reg_md_apsrc_0_sel;
+ /* [29] */
+ uint8_t reg_conn_apsrc_sel;
+
+ /* SPM_SRC_REQ */
+ /* [0] */
+ uint8_t reg_spm_apsrc_req;
+ /* [1] */
+ uint8_t reg_spm_f26m_req;
+ /* [3] */
+ uint8_t reg_spm_infra_req;
+ /* [4] */
+ uint8_t reg_spm_vrf18_req;
+ /* [7] */
+ uint8_t reg_spm_ddr_en_req;
+ /* [8] */
+ uint8_t reg_spm_dvfs_req;
+ /* [9] */
+ uint8_t reg_spm_sw_mailbox_req;
+ /* [10] */
+ uint8_t reg_spm_sspm_mailbox_req;
+ /* [11] */
+ uint8_t reg_spm_adsp_mailbox_req;
+ /* [12] */
+ uint8_t reg_spm_scp_mailbox_req;
+
+ /* SPM_SRC_MASK */
+ /* [0] */
+ uint8_t reg_sspm_srcclkena_0_mask_b;
+ /* [1] */
+ uint8_t reg_sspm_infra_req_0_mask_b;
+ /* [2] */
+ uint8_t reg_sspm_apsrc_req_0_mask_b;
+ /* [3] */
+ uint8_t reg_sspm_vrf18_req_0_mask_b;
+ /* [4] */
+ uint8_t reg_sspm_ddr_en_0_mask_b;
+ /* [5] */
+ uint8_t reg_scp_srcclkena_mask_b;
+ /* [6] */
+ uint8_t reg_scp_infra_req_mask_b;
+ /* [7] */
+ uint8_t reg_scp_apsrc_req_mask_b;
+ /* [8] */
+ uint8_t reg_scp_vrf18_req_mask_b;
+ /* [9] */
+ uint8_t reg_scp_ddr_en_mask_b;
+ /* [10] */
+ uint8_t reg_audio_dsp_srcclkena_mask_b;
+ /* [11] */
+ uint8_t reg_audio_dsp_infra_req_mask_b;
+ /* [12] */
+ uint8_t reg_audio_dsp_apsrc_req_mask_b;
+ /* [13] */
+ uint8_t reg_audio_dsp_vrf18_req_mask_b;
+ /* [14] */
+ uint8_t reg_audio_dsp_ddr_en_mask_b;
+ /* [15] */
+ uint8_t reg_apu_srcclkena_mask_b;
+ /* [16] */
+ uint8_t reg_apu_infra_req_mask_b;
+ /* [17] */
+ uint8_t reg_apu_apsrc_req_mask_b;
+ /* [18] */
+ uint8_t reg_apu_vrf18_req_mask_b;
+ /* [19] */
+ uint8_t reg_apu_ddr_en_mask_b;
+ /* [20] */
+ uint8_t reg_cpueb_srcclkena_mask_b;
+ /* [21] */
+ uint8_t reg_cpueb_infra_req_mask_b;
+ /* [22] */
+ uint8_t reg_cpueb_apsrc_req_mask_b;
+ /* [23] */
+ uint8_t reg_cpueb_vrf18_req_mask_b;
+ /* [24] */
+ uint8_t reg_cpueb_ddr_en_mask_b;
+ /* [25] */
+ uint8_t reg_bak_psri_srcclkena_mask_b;
+ /* [26] */
+ uint8_t reg_bak_psri_infra_req_mask_b;
+ /* [27] */
+ uint8_t reg_bak_psri_apsrc_req_mask_b;
+ /* [28] */
+ uint8_t reg_bak_psri_vrf18_req_mask_b;
+ /* [29] */
+ uint8_t reg_bak_psri_ddr_en_mask_b;
+ /* [30] */
+ uint8_t reg_cam_ddren_req_mask_b;
+ /* [31] */
+ uint8_t reg_img_ddren_req_mask_b;
+
+ /* SPM_SRC2_MASK */
+ /* [0] */
+ uint8_t reg_msdc0_srcclkena_mask_b;
+ /* [1] */
+ uint8_t reg_msdc0_infra_req_mask_b;
+ /* [2] */
+ uint8_t reg_msdc0_apsrc_req_mask_b;
+ /* [3] */
+ uint8_t reg_msdc0_vrf18_req_mask_b;
+ /* [4] */
+ uint8_t reg_msdc0_ddr_en_mask_b;
+ /* [5] */
+ uint8_t reg_msdc1_srcclkena_mask_b;
+ /* [6] */
+ uint8_t reg_msdc1_infra_req_mask_b;
+ /* [7] */
+ uint8_t reg_msdc1_apsrc_req_mask_b;
+ /* [8] */
+ uint8_t reg_msdc1_vrf18_req_mask_b;
+ /* [9] */
+ uint8_t reg_msdc1_ddr_en_mask_b;
+ /* [10] */
+ uint8_t reg_msdc2_srcclkena_mask_b;
+ /* [11] */
+ uint8_t reg_msdc2_infra_req_mask_b;
+ /* [12] */
+ uint8_t reg_msdc2_apsrc_req_mask_b;
+ /* [13] */
+ uint8_t reg_msdc2_vrf18_req_mask_b;
+ /* [14] */
+ uint8_t reg_msdc2_ddr_en_mask_b;
+ /* [15] */
+ uint8_t reg_ufs_srcclkena_mask_b;
+ /* [16] */
+ uint8_t reg_ufs_infra_req_mask_b;
+ /* [17] */
+ uint8_t reg_ufs_apsrc_req_mask_b;
+ /* [18] */
+ uint8_t reg_ufs_vrf18_req_mask_b;
+ /* [19] */
+ uint8_t reg_ufs_ddr_en_mask_b;
+ /* [20] */
+ uint8_t reg_usb_srcclkena_mask_b;
+ /* [21] */
+ uint8_t reg_usb_infra_req_mask_b;
+ /* [22] */
+ uint8_t reg_usb_apsrc_req_mask_b;
+ /* [23] */
+ uint8_t reg_usb_vrf18_req_mask_b;
+ /* [24] */
+ uint8_t reg_usb_ddr_en_mask_b;
+ /* [25] */
+ uint8_t reg_pextp_p0_srcclkena_mask_b;
+ /* [26] */
+ uint8_t reg_pextp_p0_infra_req_mask_b;
+ /* [27] */
+ uint8_t reg_pextp_p0_apsrc_req_mask_b;
+ /* [28] */
+ uint8_t reg_pextp_p0_vrf18_req_mask_b;
+ /* [29] */
+ uint8_t reg_pextp_p0_ddr_en_mask_b;
+
+ /* SPM_SRC3_MASK */
+ /* [0] */
+ uint8_t reg_pextp_p1_srcclkena_mask_b;
+ /* [1] */
+ uint8_t reg_pextp_p1_infra_req_mask_b;
+ /* [2] */
+ uint8_t reg_pextp_p1_apsrc_req_mask_b;
+ /* [3] */
+ uint8_t reg_pextp_p1_vrf18_req_mask_b;
+ /* [4] */
+ uint8_t reg_pextp_p1_ddr_en_mask_b;
+ /* [5] */
+ uint8_t reg_gce0_infra_req_mask_b;
+ /* [6] */
+ uint8_t reg_gce0_apsrc_req_mask_b;
+ /* [7] */
+ uint8_t reg_gce0_vrf18_req_mask_b;
+ /* [8] */
+ uint8_t reg_gce0_ddr_en_mask_b;
+ /* [9] */
+ uint8_t reg_gce1_infra_req_mask_b;
+ /* [10] */
+ uint8_t reg_gce1_apsrc_req_mask_b;
+ /* [11] */
+ uint8_t reg_gce1_vrf18_req_mask_b;
+ /* [12] */
+ uint8_t reg_gce1_ddr_en_mask_b;
+ /* [13] */
+ uint8_t reg_spm_srcclkena_reserved_mask_b;
+ /* [14] */
+ uint8_t reg_spm_infra_req_reserved_mask_b;
+ /* [15] */
+ uint8_t reg_spm_apsrc_req_reserved_mask_b;
+ /* [16] */
+ uint8_t reg_spm_vrf18_req_reserved_mask_b;
+ /* [17] */
+ uint8_t reg_spm_ddr_en_reserved_mask_b;
+ /* [18] */
+ uint8_t reg_disp0_apsrc_req_mask_b;
+ /* [19] */
+ uint8_t reg_disp0_ddr_en_mask_b;
+ /* [20] */
+ uint8_t reg_disp1_apsrc_req_mask_b;
+ /* [21] */
+ uint8_t reg_disp1_ddr_en_mask_b;
+ /* [22] */
+ uint8_t reg_disp2_apsrc_req_mask_b;
+ /* [23] */
+ uint8_t reg_disp2_ddr_en_mask_b;
+ /* [24] */
+ uint8_t reg_disp3_apsrc_req_mask_b;
+ /* [25] */
+ uint8_t reg_disp3_ddr_en_mask_b;
+ /* [26] */
+ uint8_t reg_infrasys_apsrc_req_mask_b;
+ /* [27] */
+ uint8_t reg_infrasys_ddr_en_mask_b;
+ /* [28] */
+ uint8_t reg_cg_check_srcclkena_mask_b;
+ /* [29] */
+ uint8_t reg_cg_check_apsrc_req_mask_b;
+ /* [30] */
+ uint8_t reg_cg_check_vrf18_req_mask_b;
+ /* [31] */
+ uint8_t reg_cg_check_ddr_en_mask_b;
+
+ /* SPM_SRC4_MASK */
+ /* [8:0] */
+ uint32_t reg_mcusys_merge_apsrc_req_mask_b;
+ /* [17:9] */
+ uint32_t reg_mcusys_merge_ddr_en_mask_b;
+ /* [19:18] */
+ uint8_t reg_dramc_md32_infra_req_mask_b;
+ /* [21:20] */
+ uint8_t reg_dramc_md32_vrf18_req_mask_b;
+ /* [23:22] */
+ uint8_t reg_dramc_md32_ddr_en_mask_b;
+ /* [24] */
+ uint8_t reg_dvfsrc_event_trigger_mask_b;
+
+ /* SPM_WAKEUP_EVENT_MASK2 */
+ /* [3:0] */
+ uint8_t reg_sc_sw2spm_wakeup_mask_b;
+ /* [4] */
+ uint8_t reg_sc_adsp2spm_wakeup_mask_b;
+ /* [8:5] */
+ uint8_t reg_sc_sspm2spm_wakeup_mask_b;
+ /* [9] */
+ uint8_t reg_sc_scp2spm_wakeup_mask_b;
+ /* [10] */
+ uint8_t reg_csyspwrup_ack_mask;
+ /* [11] */
+ uint8_t reg_csyspwrup_req_mask;
+
+ /* SPM_WAKEUP_EVENT_MASK */
+ /* [31:0] */
+ uint32_t reg_wakeup_event_mask;
+
+ /* SPM_WAKEUP_EVENT_EXT_MASK */
+ /* [31:0] */
+ uint32_t reg_ext_wakeup_event_mask;
+};
+
+/* code gen by spm_pwr_ctrl_atf.pl, need struct pwr_ctrl */
+enum pwr_ctrl_enum {
+ PW_PCM_FLAGS,
+ PW_PCM_FLAGS_CUST,
+ PW_PCM_FLAGS_CUST_SET,
+ PW_PCM_FLAGS_CUST_CLR,
+ PW_PCM_FLAGS1,
+ PW_PCM_FLAGS1_CUST,
+ PW_PCM_FLAGS1_CUST_SET,
+ PW_PCM_FLAGS1_CUST_CLR,
+ PW_TIMER_VAL,
+ PW_TIMER_VAL_CUST,
+ PW_TIMER_VAL_RAMP_EN,
+ PW_TIMER_VAL_RAMP_EN_SEC,
+ PW_WAKE_SRC,
+ PW_WAKE_SRC_CUST,
+ PW_WDT_DISABLE,
+
+ /* SPM_AP_STANDBY_CON */
+ PW_REG_WFI_OP,
+ PW_REG_WFI_TYPE,
+ PW_REG_MP0_CPUTOP_IDLE_MASK,
+ PW_REG_MP1_CPUTOP_IDLE_MASK,
+ PW_REG_MCUSYS_IDLE_MASK,
+ PW_REG_MD_APSRC_1_SEL,
+ PW_REG_MD_APSRC_0_SEL,
+ PW_REG_CONN_APSRC_SEL,
+
+ /* SPM_SRC_REQ */
+ PW_REG_SPM_APSRC_REQ,
+ PW_REG_SPM_F26M_REQ,
+ PW_REG_SPM_INFRA_REQ,
+ PW_REG_SPM_VRF18_REQ,
+ PW_REG_SPM_DDR_EN_REQ,
+ PW_REG_SPM_DVFS_REQ,
+ PW_REG_SPM_SW_MAILBOX_REQ,
+ PW_REG_SPM_SSPM_MAILBOX_REQ,
+ PW_REG_SPM_ADSP_MAILBOX_REQ,
+ PW_REG_SPM_SCP_MAILBOX_REQ,
+
+ /* SPM_SRC_MASK */
+ PW_REG_SSPM_SRCCLKENA_0_MASK_B,
+ PW_REG_SSPM_INFRA_REQ_0_MASK_B,
+ PW_REG_SSPM_APSRC_REQ_0_MASK_B,
+ PW_REG_SSPM_VRF18_REQ_0_MASK_B,
+ PW_REG_SSPM_DDR_EN_0_MASK_B,
+ PW_REG_SCP_SRCCLKENA_MASK_B,
+ PW_REG_SCP_INFRA_REQ_MASK_B,
+ PW_REG_SCP_APSRC_REQ_MASK_B,
+ PW_REG_SCP_VRF18_REQ_MASK_B,
+ PW_REG_SCP_DDR_EN_MASK_B,
+ PW_REG_AUDIO_DSP_SRCCLKENA_MASK_B,
+ PW_REG_AUDIO_DSP_INFRA_REQ_MASK_B,
+ PW_REG_AUDIO_DSP_APSRC_REQ_MASK_B,
+ PW_REG_AUDIO_DSP_VRF18_REQ_MASK_B,
+ PW_REG_AUDIO_DSP_DDR_EN_MASK_B,
+ PW_REG_APU_SRCCLKENA_MASK_B,
+ PW_REG_APU_INFRA_REQ_MASK_B,
+ PW_REG_APU_APSRC_REQ_MASK_B,
+ PW_REG_APU_VRF18_REQ_MASK_B,
+ PW_REG_APU_DDR_EN_MASK_B,
+ PW_REG_CPUEB_SRCCLKENA_MASK_B,
+ PW_REG_CPUEB_INFRA_REQ_MASK_B,
+ PW_REG_CPUEB_APSRC_REQ_MASK_B,
+ PW_REG_CPUEB_VRF18_REQ_MASK_B,
+ PW_REG_CPUEB_DDR_EN_MASK_B,
+ PW_REG_BAK_PSRI_SRCCLKENA_MASK_B,
+ PW_REG_BAK_PSRI_INFRA_REQ_MASK_B,
+ PW_REG_BAK_PSRI_APSRC_REQ_MASK_B,
+ PW_REG_BAK_PSRI_VRF18_REQ_MASK_B,
+ PW_REG_BAK_PSRI_DDR_EN_MASK_B,
+ PW_REG_CAM_DDREN_REQ_MASK_B,
+ PW_REG_IMG_DDREN_REQ_MASK_B,
+
+ /* SPM_SRC2_MASK */
+ PW_REG_MSDC0_SRCCLKENA_MASK_B,
+ PW_REG_MSDC0_INFRA_REQ_MASK_B,
+ PW_REG_MSDC0_APSRC_REQ_MASK_B,
+ PW_REG_MSDC0_VRF18_REQ_MASK_B,
+ PW_REG_MSDC0_DDR_EN_MASK_B,
+ PW_REG_MSDC1_SRCCLKENA_MASK_B,
+ PW_REG_MSDC1_INFRA_REQ_MASK_B,
+ PW_REG_MSDC1_APSRC_REQ_MASK_B,
+ PW_REG_MSDC1_VRF18_REQ_MASK_B,
+ PW_REG_MSDC1_DDR_EN_MASK_B,
+ PW_REG_MSDC2_SRCCLKENA_MASK_B,
+ PW_REG_MSDC2_INFRA_REQ_MASK_B,
+ PW_REG_MSDC2_APSRC_REQ_MASK_B,
+ PW_REG_MSDC2_VRF18_REQ_MASK_B,
+ PW_REG_MSDC2_DDR_EN_MASK_B,
+ PW_REG_UFS_SRCCLKENA_MASK_B,
+ PW_REG_UFS_INFRA_REQ_MASK_B,
+ PW_REG_UFS_APSRC_REQ_MASK_B,
+ PW_REG_UFS_VRF18_REQ_MASK_B,
+ PW_REG_UFS_DDR_EN_MASK_B,
+ PW_REG_USB_SRCCLKENA_MASK_B,
+ PW_REG_USB_INFRA_REQ_MASK_B,
+ PW_REG_USB_APSRC_REQ_MASK_B,
+ PW_REG_USB_VRF18_REQ_MASK_B,
+ PW_REG_USB_DDR_EN_MASK_B,
+ PW_REG_PEXTP_P0_SRCCLKENA_MASK_B,
+ PW_REG_PEXTP_P0_INFRA_REQ_MASK_B,
+ PW_REG_PEXTP_P0_APSRC_REQ_MASK_B,
+ PW_REG_PEXTP_P0_VRF18_REQ_MASK_B,
+ PW_REG_PEXTP_P0_DDR_EN_MASK_B,
+
+ /* SPM_SRC3_MASK */
+ PW_REG_PEXTP_P1_SRCCLKENA_MASK_B,
+ PW_REG_PEXTP_P1_INFRA_REQ_MASK_B,
+ PW_REG_PEXTP_P1_APSRC_REQ_MASK_B,
+ PW_REG_PEXTP_P1_VRF18_REQ_MASK_B,
+ PW_REG_PEXTP_P1_DDR_EN_MASK_B,
+ PW_REG_GCE0_INFRA_REQ_MASK_B,
+ PW_REG_GCE0_APSRC_REQ_MASK_B,
+ PW_REG_GCE0_VRF18_REQ_MASK_B,
+ PW_REG_GCE0_DDR_EN_MASK_B,
+ PW_REG_GCE1_INFRA_REQ_MASK_B,
+ PW_REG_GCE1_APSRC_REQ_MASK_B,
+ PW_REG_GCE1_VRF18_REQ_MASK_B,
+ PW_REG_GCE1_DDR_EN_MASK_B,
+ PW_REG_SPM_SRCCLKENA_RESERVED_MASK_B,
+ PW_REG_SPM_INFRA_REQ_RESERVED_MASK_B,
+ PW_REG_SPM_APSRC_REQ_RESERVED_MASK_B,
+ PW_REG_SPM_VRF18_REQ_RESERVED_MASK_B,
+ PW_REG_SPM_DDR_EN_RESERVED_MASK_B,
+ PW_REG_DISP0_APSRC_REQ_MASK_B,
+ PW_REG_DISP0_DDR_EN_MASK_B,
+ PW_REG_DISP1_APSRC_REQ_MASK_B,
+ PW_REG_DISP1_DDR_EN_MASK_B,
+ PW_REG_DISP2_APSRC_REQ_MASK_B,
+ PW_REG_DISP2_DDR_EN_MASK_B,
+ PW_REG_DISP3_APSRC_REQ_MASK_B,
+ PW_REG_DISP3_DDR_EN_MASK_B,
+ PW_REG_INFRASYS_APSRC_REQ_MASK_B,
+ PW_REG_INFRASYS_DDR_EN_MASK_B,
+ PW_REG_CG_CHECK_SRCCLKENA_MASK_B,
+ PW_REG_CG_CHECK_APSRC_REQ_MASK_B,
+ PW_REG_CG_CHECK_VRF18_REQ_MASK_B,
+ PW_REG_CG_CHECK_DDR_EN_MASK_B,
+
+ /* SPM_SRC4_MASK */
+ PW_REG_MCUSYS_MERGE_APSRC_REQ_MASK_B,
+ PW_REG_MCUSYS_MERGE_DDR_EN_MASK_B,
+ PW_REG_DRAMC_MD32_INFRA_REQ_MASK_B,
+ PW_REG_DRAMC_MD32_VRF18_REQ_MASK_B,
+ PW_REG_DRAMC_MD32_DDR_EN_MASK_B,
+ PW_REG_DVFSRC_EVENT_TRIGGER_MASK_B,
+
+ /* SPM_WAKEUP_EVENT_MASK2 */
+ PW_REG_SC_SW2SPM_WAKEUP_MASK_B,
+ PW_REG_SC_ADSP2SPM_WAKEUP_MASK_B,
+ PW_REG_SC_SSPM2SPM_WAKEUP_MASK_B,
+ PW_REG_SC_SCP2SPM_WAKEUP_MASK_B,
+ PW_REG_CSYSPWRUP_ACK_MASK,
+ PW_REG_CSYSPWRUP_REQ_MASK,
+
+ /* SPM_WAKEUP_EVENT_MASK */
+ PW_REG_WAKEUP_EVENT_MASK,
+
+ /* SPM_WAKEUP_EVENT_EXT_MASK */
+ PW_REG_EXT_WAKEUP_EVENT_MASK,
+ PW_MAX_COUNT,
+};
+
+/* spm_internal.c internal status */
+#define SPM_INTERNAL_STATUS_HW_S1 BIT(0)
+#define SPM_ACK_CHK_3_CON_HW_MODE_TRIG (0x800)
+/* BIT[0]: SW_EN, BIT[4]: STA_EN, BIT[8]: HW_EN */
+#define SPM_ACK_CHK_3_CON_EN (0x110)
+#define SPM_ACK_CHK_3_CON_CLR_ALL (0x2)
+/* BIT[15]: RESULT */
+#define SPM_ACK_CHK_3_CON_RESULT (0x8000)
+
+struct wake_status_trace_comm {
+ uint32_t debug_flag; /* PCM_WDT_LATCH_SPARE_0 */
+ uint32_t debug_flag1; /* PCM_WDT_LATCH_SPARE_1 */
+ uint32_t timer_out; /* SPM_SW_RSV_6*/
+ uint32_t b_sw_flag0; /* SPM_SW_RSV_7 */
+ uint32_t b_sw_flag1; /* SPM_SW_RSV_7 */
+ uint32_t r12; /* SPM_SW_RSV_0 */
+ uint32_t r13; /* PCM_REG13_DATA */
+ uint32_t req_sta0; /* SRC_REQ_STA_0 */
+ uint32_t req_sta1; /* SRC_REQ_STA_1 */
+ uint32_t req_sta2; /* SRC_REQ_STA_2 */
+ uint32_t req_sta3; /* SRC_REQ_STA_3 */
+ uint32_t req_sta4; /* SRC_REQ_STA_4 */
+ uint32_t raw_sta; /* SPM_WAKEUP_STA */
+ uint32_t times_h; /* timestamp high bits */
+ uint32_t times_l; /* timestamp low bits */
+ uint32_t resumetime; /* timestamp low bits */
+};
+
+struct wake_status_trace {
+ struct wake_status_trace_comm comm;
+};
+
+struct wake_status {
+ struct wake_status_trace tr;
+ uint32_t r12_ext; /* SPM_WAKEUP_EXT_STA */
+ uint32_t raw_ext_sta; /* SPM_WAKEUP_EXT_STA */
+ uint32_t md32pcm_wakeup_sta; /* MD32PCM_WAKEUP_STA */
+ uint32_t md32pcm_event_sta; /* MD32PCM_EVENT_STA */
+ uint32_t wake_misc; /* SPM_SW_RSV_5 */
+ uint32_t idle_sta; /* SUBSYS_IDLE_STA */
+ uint32_t sw_flag0; /* SPM_SW_FLAG_0 */
+ uint32_t sw_flag1; /* SPM_SW_FLAG_1 */
+ uint32_t isr; /* SPM_IRQ_STA */
+ uint32_t log_index;
+ uint32_t is_abort;
+};
+
+struct spm_lp_scen {
+ struct pcm_desc *pcmdesc;
+ struct pwr_ctrl *pwrctrl;
+};
+
+void __spm_set_cpu_status(unsigned int cpu);
+void __spm_src_req_update(const struct pwr_ctrl *pwrctrl, unsigned int resource_usage);
+void __spm_set_power_control(const struct pwr_ctrl *pwrctrl);
+void __spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl);
+void __spm_set_pcm_flags(struct pwr_ctrl *pwrctrl);
+void __spm_send_cpu_wakeup_event(void);
+void __spm_get_wakeup_status(struct wake_status *wakesta, unsigned int ext_status);
+void __spm_clean_after_wakeup(void);
+wake_reason_t __spm_output_wake_reason(const struct wake_status *wakesta);
+void __spm_set_pcm_wdt(int en);
+void __spm_ext_int_wakeup_req_clr(void);
+void __spm_hw_s1_state_monitor(int en, unsigned int *status);
+
+static inline void spm_hw_s1_state_monitor_resume(void)
+{
+ __spm_hw_s1_state_monitor(1, NULL);
+}
+
+static inline void spm_hw_s1_state_monitor_pause(unsigned int *status)
+{
+ __spm_hw_s1_state_monitor(0, status);
+}
+
+void __spm_clean_before_wfi(void);
+
+#endif /* MT_SPM_INTERNAL */
diff --git a/plat/mediatek/drivers/spm/mt8188/mt_spm_pmic_wrap.c b/plat/mediatek/drivers/spm/mt8188/mt_spm_pmic_wrap.c
new file mode 100644
index 0000000..97dedf9
--- /dev/null
+++ b/plat/mediatek/drivers/spm/mt8188/mt_spm_pmic_wrap.c
@@ -0,0 +1,152 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stddef.h>
+#include <stdio.h>
+#include <string.h>
+
+#include <common/debug.h>
+#include <lib/mmio.h>
+#include <plat/common/platform.h>
+
+#include <lib/pm/mtk_pm.h>
+#include "mt_spm.h"
+#include "mt_spm_internal.h"
+#include "mt_spm_pmic_wrap.h"
+#include "mt_spm_reg.h"
+#include <platform_def.h>
+
+/* BIT operation */
+#define _BITS_(h, l, v) ((GENMASK(h, l) & ((v) << (l))))
+
+/* PMIC_WRAP */
+#define VCORE_BASE_UV (40000) /* PMIC MT6359 */
+#define VOLT_TO_PMIC_VAL(volt) (((volt) - VCORE_BASE_UV + 625 - 1) / 625)
+
+#define NR_PMIC_WRAP_CMD (NR_IDX_ALL)
+#define SPM_DATA_SHIFT (16)
+
+#define BUCK_VGPU11_ELR0 (0x15B4)
+#define TOP_SPI_CON0 (0x0456)
+#define BUCK_TOP_CON1 (0x1443) /* PMIC MT6315 */
+#define TOP_CON (0x0013) /* PMIC MT6315 */
+#define TOP_DIG_WPK (0x03a9)
+#define TOP_CON_LOCK (0x03a8)
+#define TOP_CLK_CON0 (0x0134) /* PMIC MT6359*/
+
+struct pmic_wrap_cmd {
+ uint32_t cmd_addr;
+ uint32_t cmd_wdata;
+};
+
+struct pmic_wrap_setting {
+ enum pmic_wrap_phase_id phase;
+ struct pmic_wrap_cmd addr[NR_PMIC_WRAP_CMD];
+ struct {
+ struct {
+ uint32_t cmd_addr;
+ uint32_t cmd_wdata;
+ } _[NR_PMIC_WRAP_CMD];
+ const int nr_idx;
+ } set[NR_PMIC_WRAP_PHASE];
+};
+
+static struct pmic_wrap_setting pw = {
+ .phase = NR_PMIC_WRAP_PHASE, /* invalid setting for init */
+ .addr = {{0, 0} },
+ .set[PMIC_WRAP_PHASE_ALLINONE] = {
+ ._[CMD_0] = {BUCK_VGPU11_ELR0, _BITS_(6, 0, VOLT_TO_PMIC_VAL(75000)),},
+ ._[CMD_1] = {BUCK_VGPU11_ELR0, _BITS_(6, 0, VOLT_TO_PMIC_VAL(65000)),},
+ ._[CMD_2] = {BUCK_VGPU11_ELR0, _BITS_(6, 0, VOLT_TO_PMIC_VAL(60000)),},
+ ._[CMD_3] = {BUCK_VGPU11_ELR0, _BITS_(6, 0, VOLT_TO_PMIC_VAL(55000)),},
+ ._[CMD_4] = {TOP_SPI_CON0, _BITS_(0, 0, 1),},
+ ._[CMD_5] = {TOP_SPI_CON0, _BITS_(0, 0, 0),},
+ ._[CMD_6] = {BUCK_TOP_CON1, 0x0,}, /* MT6315-3: VMD NO LP */
+ ._[CMD_7] = {BUCK_TOP_CON1, 0xF,}, /* MT6315-3: VMD LP */
+ ._[CMD_8] = {TOP_CON, 0x3,}, /* MT6315-3: PMIC NO LP */
+ ._[CMD_9] = {TOP_CON, 0x0,}, /* MT6315-3: PMIC LP */
+ ._[CMD_10] = {TOP_DIG_WPK, 0x63,}, /* MT6315-2: PMIC_CON_DIG_WPK */
+ ._[CMD_11] = {TOP_CON_LOCK, 0x15,}, /* MT6315-2: PMIC_CON_UNLOCK */
+ ._[CMD_12] = {TOP_DIG_WPK, 0x0,}, /* MT6315-2: PMIC_CON_DIG_WPK */
+ ._[CMD_13] = {TOP_CON_LOCK, 0x0,}, /* MT6315-2: PMIC_CON_LOCK */
+ ._[CMD_14] = {TOP_CLK_CON0, 0x0040,}, /* MT6359: 6359_LDO_SW_SEL_H */
+ ._[CMD_15] = {TOP_CLK_CON0, 0x0000,}, /* MT6359: 6359_LDO_SW_SEL_L */
+ .nr_idx = NR_IDX_ALL,
+ },
+};
+
+void _mt_spm_pmic_table_init(void)
+{
+ struct pmic_wrap_cmd pwrap_cmd_default[NR_PMIC_WRAP_CMD] = {
+ { (uint32_t)SPM_DVFS_CMD0, (uint32_t)SPM_DVFS_CMD0, },
+ { (uint32_t)SPM_DVFS_CMD1, (uint32_t)SPM_DVFS_CMD1, },
+ { (uint32_t)SPM_DVFS_CMD2, (uint32_t)SPM_DVFS_CMD2, },
+ { (uint32_t)SPM_DVFS_CMD3, (uint32_t)SPM_DVFS_CMD3, },
+ { (uint32_t)SPM_DVFS_CMD4, (uint32_t)SPM_DVFS_CMD4, },
+ { (uint32_t)SPM_DVFS_CMD5, (uint32_t)SPM_DVFS_CMD5, },
+ { (uint32_t)SPM_DVFS_CMD6, (uint32_t)SPM_DVFS_CMD6, },
+ { (uint32_t)SPM_DVFS_CMD7, (uint32_t)SPM_DVFS_CMD7, },
+ { (uint32_t)SPM_DVFS_CMD8, (uint32_t)SPM_DVFS_CMD8, },
+ { (uint32_t)SPM_DVFS_CMD9, (uint32_t)SPM_DVFS_CMD9, },
+ { (uint32_t)SPM_DVFS_CMD10, (uint32_t)SPM_DVFS_CMD10, },
+ { (uint32_t)SPM_DVFS_CMD11, (uint32_t)SPM_DVFS_CMD11, },
+ { (uint32_t)SPM_DVFS_CMD12, (uint32_t)SPM_DVFS_CMD12, },
+ { (uint32_t)SPM_DVFS_CMD13, (uint32_t)SPM_DVFS_CMD13, },
+ { (uint32_t)SPM_DVFS_CMD14, (uint32_t)SPM_DVFS_CMD14, },
+ { (uint32_t)SPM_DVFS_CMD15, (uint32_t)SPM_DVFS_CMD15, },
+ };
+
+ memcpy(pw.addr, pwrap_cmd_default, sizeof(pwrap_cmd_default));
+}
+
+void mt_spm_pmic_wrap_set_phase(enum pmic_wrap_phase_id phase)
+{
+ int idx;
+
+ if ((phase >= NR_PMIC_WRAP_PHASE) || (pw.phase == phase)) {
+ return;
+ }
+
+ if (pw.addr[0].cmd_addr == 0) {
+ _mt_spm_pmic_table_init();
+ }
+
+ pw.phase = phase;
+
+ mmio_write_32(POWERON_CONFIG_EN, SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB);
+ for (idx = 0; idx < pw.set[phase].nr_idx; idx++) {
+ mmio_write_32(pw.addr[idx].cmd_addr,
+ (pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT) |
+ (pw.set[phase]._[idx].cmd_wdata));
+ }
+}
+
+void mt_spm_pmic_wrap_set_cmd(enum pmic_wrap_phase_id phase, unsigned int idx,
+ unsigned int cmd_wdata)
+{
+ /* just set wdata value */
+ if ((phase >= NR_PMIC_WRAP_PHASE) || (idx >= pw.set[phase].nr_idx)) {
+ return;
+ }
+
+ pw.set[phase]._[idx].cmd_wdata = cmd_wdata;
+
+ mmio_write_32(POWERON_CONFIG_EN, SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB);
+ if (pw.phase == phase) {
+ mmio_write_32(pw.addr[idx].cmd_addr,
+ (pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT) | cmd_wdata);
+ }
+}
+
+uint64_t mt_spm_pmic_wrap_get_cmd(enum pmic_wrap_phase_id phase, unsigned int idx)
+{
+ /* just get wdata value */
+ if ((phase >= NR_PMIC_WRAP_PHASE) || (idx >= pw.set[phase].nr_idx)) {
+ return 0;
+ }
+
+ return pw.set[phase]._[idx].cmd_wdata;
+}
diff --git a/plat/mediatek/drivers/spm/mt8188/mt_spm_pmic_wrap.h b/plat/mediatek/drivers/spm/mt8188/mt_spm_pmic_wrap.h
new file mode 100644
index 0000000..3043d36
--- /dev/null
+++ b/plat/mediatek/drivers/spm/mt8188/mt_spm_pmic_wrap.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/****************************************************************
+ * Auto generated by DE, please DO NOT modify this file directly.
+ *****************************************************************/
+
+#ifndef MT_SPM_PMIC_WRAP_H
+#define MT_SPM_PMIC_WRAP_H
+
+enum pmic_wrap_phase_id {
+ PMIC_WRAP_PHASE_ALLINONE = 0,
+ NR_PMIC_WRAP_PHASE,
+};
+
+/* IDX mapping */
+enum {
+ CMD_0 = 0, /* PMIC_WRAP_PHASE_ALLINONE */
+ CMD_1,
+ CMD_2,
+ CMD_3,
+ CMD_4,
+ CMD_5,
+ CMD_6,
+ CMD_7,
+ CMD_8,
+ CMD_9,
+ CMD_10,
+ CMD_11,
+ CMD_12,
+ CMD_13,
+ CMD_14,
+ CMD_15,
+ NR_IDX_ALL,
+};
+
+/* APIs */
+void mt_spm_pmic_wrap_set_phase(enum pmic_wrap_phase_id phase);
+void mt_spm_pmic_wrap_set_cmd(enum pmic_wrap_phase_id phase, unsigned int idx,
+ unsigned int cmd_wdata);
+uint64_t mt_spm_pmic_wrap_get_cmd(enum pmic_wrap_phase_id phase, unsigned int idx);
+void mt_spm_dump_pmic_warp_reg(void);
+
+#endif /* MT_SPM_PMIC_WRAP_H */
diff --git a/plat/mediatek/drivers/spm/mt8188/mt_spm_reg.h b/plat/mediatek/drivers/spm/mt8188/mt_spm_reg.h
new file mode 100644
index 0000000..2c29f75
--- /dev/null
+++ b/plat/mediatek/drivers/spm/mt8188/mt_spm_reg.h
@@ -0,0 +1,2249 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/****************************************************************
+ * Auto generated by DE, please DO NOT modify this file directly.
+ ****************************************************************/
+
+#ifndef MT_SPM_REG_H
+#define MT_SPM_REG_H
+
+#include "pcm_def.h"
+#include "sleep_def.h"
+#include <spm_reg.h>
+
+/* Define and Declare */
+
+/* POWERON_CONFIG_EN (0x10006000+0x000) */
+#define BCLK_CG_EN_LSB (1U << 0) /* 1b */
+#define PROJECT_CODE_LSB (1U << 16) /* 16b */
+/* SPM_POWER_ON_VAL0 (0x10006000+0x004) */
+#define POWER_ON_VAL0_LSB (1U << 0) /* 32b */
+/* SPM_POWER_ON_VAL1 (0x10006000+0x008) */
+#define POWER_ON_VAL1_LSB (1U << 0) /* 32b */
+/* SPM_CLK_CON (0x10006000+0x00C) */
+#define REG_SRCCLKEN0_CTL_LSB (1U << 0) /* 2b */
+#define REG_SRCCLKEN1_CTL_LSB (1U << 2) /* 2b */
+#define SYS_SETTLE_SEL_LSB (1U << 4) /* 1b */
+#define REG_SPM_LOCK_INFRA_DCM_LSB (1U << 5) /* 1b */
+#define REG_SRCCLKEN_MASK_LSB (1U << 6) /* 3b */
+#define REG_MD1_C32RM_EN_LSB (1U << 9) /* 1b */
+#define REG_MD2_C32RM_EN_LSB (1U << 10) /* 1b */
+#define REG_CLKSQ0_SEL_CTRL_LSB (1U << 11) /* 1b */
+#define REG_CLKSQ1_SEL_CTRL_LSB (1U << 12) /* 1b */
+#define REG_SRCCLKEN0_EN_LSB (1U << 13) /* 1b */
+#define REG_SRCCLKEN1_EN_LSB (1U << 14) /* 1b */
+#define SCP_DCM_EN_LSB (1U << 15) /* 1b */
+#define REG_SYSCLK0_SRC_MASK_B_LSB (1U << 16) /* 8b */
+#define REG_SYSCLK1_SRC_MASK_B_LSB (1U << 24) /* 8b */
+/* SPM_CLK_SETTLE (0x10006000+0x010) */
+#define SYSCLK_SETTLE_LSB (1U << 0) /* 28b */
+/* SPM_AP_STANDBY_CON (0x10006000+0x014) */
+#define REG_WFI_OP_LSB (1U << 0) /* 1b */
+#define REG_WFI_TYPE_LSB (1U << 1) /* 1b */
+#define REG_MP0_CPUTOP_IDLE_MASK_LSB (1U << 2) /* 1b */
+#define REG_MP1_CPUTOP_IDLE_MASK_LSB (1U << 3) /* 1b */
+#define REG_MCUSYS_IDLE_MASK_LSB (1U << 4) /* 1b */
+#define REG_MD_APSRC_1_SEL_LSB (1U << 25) /* 1b */
+#define REG_MD_APSRC_0_SEL_LSB (1U << 26) /* 1b */
+#define REG_CONN_APSRC_SEL_LSB (1U << 29) /* 1b */
+/* PCM_CON0 (0x10006000+0x018) */
+#define PCM_CK_EN_LSB (1U << 2) /* 1b */
+#define RG_EN_IM_SLEEP_DVS_LSB (1U << 3) /* 1b */
+#define PCM_CK_FROM_CKSYS_LSB (1U << 4) /* 1b */
+#define PCM_SW_RESET_LSB (1U << 15) /* 1b */
+#define PCM_CON0_PROJECT_CODE_LSB (1U << 16) /* 16b */
+/* PCM_CON1 (0x10006000+0x01C) */
+#define RG_IM_SLAVE_LSB (1U << 0) /* 1b */
+#define RG_IM_SLEEP_LSB (1U << 1) /* 1b */
+#define REG_SPM_SRAM_CTRL_MUX_LSB (1U << 2) /* 1b */
+#define RG_AHBMIF_APBEN_LSB (1U << 3) /* 1b */
+#define RG_IM_PDN_LSB (1U << 4) /* 1b */
+#define RG_PCM_TIMER_EN_LSB (1U << 5) /* 1b */
+#define SPM_EVENT_COUNTER_CLR_LSB (1U << 6) /* 1b */
+#define RG_DIS_MIF_PROT_LSB (1U << 7) /* 1b */
+#define RG_PCM_WDT_EN_LSB (1U << 8) /* 1b */
+#define RG_PCM_WDT_WAKE_LSB (1U << 9) /* 1b */
+#define REG_SPM_SRAM_SLEEP_B_LSB (1U << 10) /* 1b */
+#define REG_SPM_SRAM_ISOINT_B_LSB (1U << 11) /* 1b */
+#define REG_EVENT_LOCK_EN_LSB (1U << 12) /* 1b */
+#define REG_SRCCLKEN_FAST_RESP_LSB (1U << 13) /* 1b */
+#define REG_MD32_APB_INTERNAL_EN_LSB (1U << 14) /* 1b */
+#define RG_PCM_IRQ_MSK_LSB (1U << 15) /* 1b */
+#define PCM_CON1_PROJECT_CODE_LSB (1U << 16) /* 16b */
+/* SPM_POWER_ON_VAL2 (0x10006000+0x020) */
+#define POWER_ON_VAL2_LSB (1U << 0) /* 32b */
+/* SPM_POWER_ON_VAL3 (0x10006000+0x024) */
+#define POWER_ON_VAL3_LSB (1U << 0) /* 32b */
+/* PCM_REG_DATA_INI (0x10006000+0x028) */
+#define PCM_REG_DATA_INI_LSB (1U << 0) /* 32b */
+/* PCM_PWR_IO_EN (0x10006000+0x02C) */
+#define PCM_PWR_IO_EN_LSB (1U << 0) /* 8b */
+#define RG_RF_SYNC_EN_LSB (1U << 16) /* 8b */
+/* PCM_TIMER_VAL (0x10006000+0x030) */
+#define REG_PCM_TIMER_VAL_LSB (1U << 0) /* 32b */
+/* PCM_WDT_VAL (0x10006000+0x034) */
+#define RG_PCM_WDT_VAL_LSB (1U << 0) /* 32b */
+/* SPM_SW_RST_CON (0x10006000+0x040) */
+#define SPM_SW_RST_CON_LSB (1U << 0) /* 16b */
+#define SPM_SW_RST_CON_PROJECT_CODE_LSB (1U << 16) /* 16b */
+/* SPM_SW_RST_CON_SET (0x10006000+0x044) */
+#define SPM_SW_RST_CON_SET_LSB (1U << 0) /* 16b */
+#define SPM_SW_RST_CON_SET_PROJECT_CODE_LSB (1U << 16) /* 16b */
+/* SPM_SW_RST_CON_CLR (0x10006000+0x048) */
+#define SPM_SW_RST_CON_CLR_LSB (1U << 0) /* 16b */
+#define SPM_SW_RST_CON_CLR_PROJECT_CODE_LSB (1U << 16) /* 16b */
+/* VS1_PSR_MASK_B (0x10006000+0x04C) */
+#define VS1_OPP0_PSR_MASK_B_LSB (1U << 0) /* 8b */
+#define VS1_OPP1_PSR_MASK_B_LSB (1U << 8) /* 8b */
+/* VS2_PSR_MASK_B (0x10006000+0x050) */
+#define VS2_OPP0_PSR_MASK_B_LSB (1U << 0) /* 8b */
+#define VS2_OPP1_PSR_MASK_B_LSB (1U << 8) /* 8b */
+#define VS2_OPP2_PSR_MASK_B_LSB (1U << 16) /* 8b */
+/* MD32_CLK_CON (0x10006000+0x084) */
+#define REG_MD32_26M_CK_SEL_LSB (1U << 0) /* 1b */
+#define REG_MD32_DCM_EN_LSB (1U << 1) /* 1b */
+/* SPM_SRAM_RSV_CON (0x10006000+0x088) */
+#define SPM_SRAM_SLEEP_B_ECO_EN_LSB (1U << 0) /* 1b */
+/* SPM_SWINT (0x10006000+0x08C) */
+#define SPM_SWINT_LSB (1U << 0) /* 32b */
+/* SPM_SWINT_SET (0x10006000+0x090) */
+#define SPM_SWINT_SET_LSB (1U << 0) /* 32b */
+/* SPM_SWINT_CLR (0x10006000+0x094) */
+#define SPM_SWINT_CLR_LSB (1U << 0) /* 32b */
+/* SPM_SCP_MAILBOX (0x10006000+0x098) */
+#define SPM_SCP_MAILBOX_LSB (1U << 0) /* 32b */
+/* SCP_SPM_MAILBOX (0x10006000+0x09C) */
+#define SCP_SPM_MAILBOX_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_CON (0x10006000+0x0A0) */
+#define REG_TWAM_ENABLE_LSB (1U << 0) /* 1b */
+#define REG_TWAM_SPEED_MODE_EN_LSB (1U << 1) /* 1b */
+#define REG_TWAM_SW_RST_LSB (1U << 2) /* 1b */
+#define REG_TWAM_IRQ_MASK_LSB (1U << 3) /* 1b */
+#define REG_TWAM_MON_TYPE_0_LSB (1U << 4) /* 2b */
+#define REG_TWAM_MON_TYPE_1_LSB (1U << 6) /* 2b */
+#define REG_TWAM_MON_TYPE_2_LSB (1U << 8) /* 2b */
+#define REG_TWAM_MON_TYPE_3_LSB (1U << 10) /* 2b */
+/* SPM_TWAM_WINDOW_LEN (0x10006000+0x0A4) */
+#define REG_TWAM_WINDOW_LEN_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_IDLE_SEL (0x10006000+0x0A8) */
+#define REG_TWAM_SIG_SEL_0_LSB (1U << 0) /* 7b */
+#define REG_TWAM_SIG_SEL_1_LSB (1U << 8) /* 7b */
+#define REG_TWAM_SIG_SEL_2_LSB (1U << 16) /* 7b */
+#define REG_TWAM_SIG_SEL_3_LSB (1U << 24) /* 7b */
+/* SPM_SCP_IRQ (0x10006000+0x0AC) */
+#define SC_SPM2SCP_WAKEUP_LSB (1U << 0) /* 1b */
+#define SC_SCP2SPM_WAKEUP_LSB (1U << 4) /* 1b */
+/* SPM_CPU_WAKEUP_EVENT (0x10006000+0x0B0) */
+#define REG_CPU_WAKEUP_LSB (1U << 0) /* 1b */
+/* SPM_IRQ_MASK (0x10006000+0x0B4) */
+#define REG_SPM_IRQ_MASK_LSB (1U << 0) /* 32b */
+/* DDR_EN_DBC (0x10006000+0x0B4) */
+#define REG_ALL_DDR_EN_DBC_EN_LSB (1U << 16) /* 1b */
+/* SPM_SRC_REQ (0x10006000+0x0B8) */
+#define REG_SPM_APSRC_REQ_LSB (1U << 0) /* 1b */
+#define REG_SPM_F26M_REQ_LSB (1U << 1) /* 1b */
+#define REG_SPM_INFRA_REQ_LSB (1U << 3) /* 1b */
+#define REG_SPM_VRF18_REQ_LSB (1U << 4) /* 1b */
+#define REG_SPM_DDR_EN_REQ_LSB (1U << 7) /* 1b */
+#define REG_SPM_DVFS_REQ_LSB (1U << 8) /* 1b */
+#define REG_SPM_SW_MAILBOX_REQ_LSB (1U << 9) /* 1b */
+#define REG_SPM_SSPM_MAILBOX_REQ_LSB (1U << 10) /* 1b */
+#define REG_SPM_ADSP_MAILBOX_REQ_LSB (1U << 11) /* 1b */
+#define REG_SPM_SCP_MAILBOX_REQ_LSB (1U << 12) /* 1b */
+/* SPM_SRC_MASK (0x10006000+0x0BC) */
+#define REG_MD_SRCCLKENA_0_MASK_B_LSB (1U << 0) /* 1b */
+#define REG_MD_SRCCLKENA2INFRA_REQ_0_MASK_B_LSB (1U << 1) /* 1b */
+#define REG_MD_APSRC2INFRA_REQ_0_MASK_B_LSB (1U << 2) /* 1b */
+#define REG_MD_APSRC_REQ_0_MASK_B_LSB (1U << 3) /* 1b */
+#define REG_MD_VRF18_REQ_0_MASK_B_LSB (1U << 4) /* 1b */
+#define REG_MD_DDR_EN_0_MASK_B_LSB (1U << 5) /* 1b */
+#define REG_MD_SRCCLKENA_1_MASK_B_LSB (1U << 6) /* 1b */
+#define REG_MD_SRCCLKENA2INFRA_REQ_1_MASK_B_LSB (1U << 7) /* 1b */
+#define REG_MD_APSRC2INFRA_REQ_1_MASK_B_LSB (1U << 8) /* 1b */
+#define REG_MD_APSRC_REQ_1_MASK_B_LSB (1U << 9) /* 1b */
+#define REG_MD_VRF18_REQ_1_MASK_B_LSB (1U << 10) /* 1b */
+#define REG_MD_DDR_EN_1_MASK_B_LSB (1U << 11) /* 1b */
+#define REG_CONN_SRCCLKENA_MASK_B_LSB (1U << 12) /* 1b */
+#define REG_CONN_SRCCLKENB_MASK_B_LSB (1U << 13) /* 1b */
+#define REG_CONN_INFRA_REQ_MASK_B_LSB (1U << 14) /* 1b */
+#define REG_CONN_APSRC_REQ_MASK_B_LSB (1U << 15) /* 1b */
+#define REG_CONN_VRF18_REQ_MASK_B_LSB (1U << 16) /* 1b */
+#define REG_CONN_DDR_EN_MASK_B_LSB (1U << 17) /* 1b */
+#define REG_CONN_VFE28_MASK_B_LSB (1U << 18) /* 1b */
+#define REG_SRCCLKENI0_SRCCLKENA_MASK_B_LSB (1U << 19) /* 1b */
+#define REG_SRCCLKENI0_INFRA_REQ_MASK_B_LSB (1U << 20) /* 1b */
+#define REG_SRCCLKENI1_SRCCLKENA_MASK_B_LSB (1U << 21) /* 1b */
+#define REG_SRCCLKENI1_INFRA_REQ_MASK_B_LSB (1U << 22) /* 1b */
+#define REG_SRCCLKENI2_SRCCLKENA_MASK_B_LSB (1U << 23) /* 1b */
+#define REG_SRCCLKENI2_INFRA_REQ_MASK_B_LSB (1U << 24) /* 1b */
+#define REG_INFRASYS_APSRC_REQ_MASK_B_LSB (1U << 25) /* 1b */
+#define REG_INFRASYS_DDR_EN_MASK_B_LSB (1U << 26) /* 1b */
+#define REG_MD32_SRCCLKENA_MASK_B_LSB (1U << 27) /* 1b */
+#define REG_MD32_INFRA_REQ_MASK_B_LSB (1U << 28) /* 1b */
+#define REG_MD32_APSRC_REQ_MASK_B_LSB (1U << 29) /* 1b */
+#define REG_MD32_VRF18_REQ_MASK_B_LSB (1U << 30) /* 1b */
+#define REG_MD32_DDR_EN_MASK_B_LSB (1U << 31) /* 1b */
+/* SPM_SRC2_MASK (0x10006000+0x0C0) */
+#define REG_SCP_SRCCLKENA_MASK_B_LSB (1U << 0) /* 1b */
+#define REG_SCP_INFRA_REQ_MASK_B_LSB (1U << 1) /* 1b */
+#define REG_SCP_APSRC_REQ_MASK_B_LSB (1U << 2) /* 1b */
+#define REG_SCP_VRF18_REQ_MASK_B_LSB (1U << 3) /* 1b */
+#define REG_SCP_DDR_EN_MASK_B_LSB (1U << 4) /* 1b */
+#define REG_AUDIO_DSP_SRCCLKENA_MASK_B_LSB (1U << 5) /* 1b */
+#define REG_AUDIO_DSP_INFRA_REQ_MASK_B_LSB (1U << 6) /* 1b */
+#define REG_AUDIO_DSP_APSRC_REQ_MASK_B_LSB (1U << 7) /* 1b */
+#define REG_AUDIO_DSP_VRF18_REQ_MASK_B_LSB (1U << 8) /* 1b */
+#define REG_AUDIO_DSP_DDR_EN_MASK_B_LSB (1U << 9) /* 1b */
+#define REG_UFS_SRCCLKENA_MASK_B_LSB (1U << 10) /* 1b */
+#define REG_UFS_INFRA_REQ_MASK_B_LSB (1U << 11) /* 1b */
+#define REG_UFS_APSRC_REQ_MASK_B_LSB (1U << 12) /* 1b */
+#define REG_UFS_VRF18_REQ_MASK_B_LSB (1U << 13) /* 1b */
+#define REG_UFS_DDR_EN_MASK_B_LSB (1U << 14) /* 1b */
+#define REG_DISP0_APSRC_REQ_MASK_B_LSB (1U << 15) /* 1b */
+#define REG_DISP0_DDR_EN_MASK_B_LSB (1U << 16) /* 1b */
+#define REG_DISP1_APSRC_REQ_MASK_B_LSB (1U << 17) /* 1b */
+#define REG_DISP1_DDR_EN_MASK_B_LSB (1U << 18) /* 1b */
+#define REG_GCE_INFRA_REQ_MASK_B_LSB (1U << 19) /* 1b */
+#define REG_GCE_APSRC_REQ_MASK_B_LSB (1U << 20) /* 1b */
+#define REG_GCE_VRF18_REQ_MASK_B_LSB (1U << 21) /* 1b */
+#define REG_GCE_DDR_EN_MASK_B_LSB (1U << 22) /* 1b */
+#define REG_APU_SRCCLKENA_MASK_B_LSB (1U << 23) /* 1b */
+#define REG_APU_INFRA_REQ_MASK_B_LSB (1U << 24) /* 1b */
+#define REG_APU_APSRC_REQ_MASK_B_LSB (1U << 25) /* 1b */
+#define REG_APU_VRF18_REQ_MASK_B_LSB (1U << 26) /* 1b */
+#define REG_APU_DDR_EN_MASK_B_LSB (1U << 27) /* 1b */
+#define REG_CG_CHECK_SRCCLKENA_MASK_B_LSB (1U << 28) /* 1b */
+#define REG_CG_CHECK_APSRC_REQ_MASK_B_LSB (1U << 29) /* 1b */
+#define REG_CG_CHECK_VRF18_REQ_MASK_B_LSB (1U << 30) /* 1b */
+#define REG_CG_CHECK_DDR_EN_MASK_B_LSB (1U << 31) /* 1b */
+/* SPM_SRC3_MASK (0x10006000+0x0C4) */
+#define REG_DVFSRC_EVENT_TRIGGER_MASK_B_LSB (1U << 0) /* 1b */
+#define REG_SW2SPM_INT0_MASK_B_LSB (1U << 1) /* 1b */
+#define REG_SW2SPM_INT1_MASK_B_LSB (1U << 2) /* 1b */
+#define REG_SW2SPM_INT2_MASK_B_LSB (1U << 3) /* 1b */
+#define REG_SW2SPM_INT3_MASK_B_LSB (1U << 4) /* 1b */
+#define REG_SC_ADSP2SPM_WAKEUP_MASK_B_LSB (1U << 5) /* 1b */
+#define REG_SC_SSPM2SPM_WAKEUP_MASK_B_LSB (1U << 6) /* 4b */
+#define REG_SC_SCP2SPM_WAKEUP_MASK_B_LSB (1U << 10) /* 1b */
+#define REG_CSYSPWRREQ_MASK_LSB (1U << 11) /* 1b */
+#define REG_SPM_SRCCLKENA_RESERVED_MASK_B_LSB (1U << 12) /* 1b */
+#define REG_SPM_INFRA_REQ_RESERVED_MASK_B_LSB (1U << 13) /* 1b */
+#define REG_SPM_APSRC_REQ_RESERVED_MASK_B_LSB (1U << 14) /* 1b */
+#define REG_SPM_VRF18_REQ_RESERVED_MASK_B_LSB (1U << 15) /* 1b */
+#define REG_SPM_DDR_EN_RESERVED_MASK_B_LSB (1U << 16) /* 1b */
+#define REG_MCUPM_SRCCLKENA_MASK_B_LSB (1U << 17) /* 1b */
+#define REG_MCUPM_INFRA_REQ_MASK_B_LSB (1U << 18) /* 1b */
+#define REG_MCUPM_APSRC_REQ_MASK_B_LSB (1U << 19) /* 1b */
+#define REG_MCUPM_VRF18_REQ_MASK_B_LSB (1U << 20) /* 1b */
+#define REG_MCUPM_DDR_EN_MASK_B_LSB (1U << 21) /* 1b */
+#define REG_MSDC0_SRCCLKENA_MASK_B_LSB (1U << 22) /* 1b */
+#define REG_MSDC0_INFRA_REQ_MASK_B_LSB (1U << 23) /* 1b */
+#define REG_MSDC0_APSRC_REQ_MASK_B_LSB (1U << 24) /* 1b */
+#define REG_MSDC0_VRF18_REQ_MASK_B_LSB (1U << 25) /* 1b */
+#define REG_MSDC0_DDR_EN_MASK_B_LSB (1U << 26) /* 1b */
+#define REG_MSDC1_SRCCLKENA_MASK_B_LSB (1U << 27) /* 1b */
+#define REG_MSDC1_INFRA_REQ_MASK_B_LSB (1U << 28) /* 1b */
+#define REG_MSDC1_APSRC_REQ_MASK_B_LSB (1U << 29) /* 1b */
+#define REG_MSDC1_VRF18_REQ_MASK_B_LSB (1U << 30) /* 1b */
+#define REG_MSDC1_DDR_EN_MASK_B_LSB (1U << 31) /* 1b */
+/* SPM_SRC4_MASK (0x10006000+0x0C8) */
+#define CCIF_EVENT_MASK_B_LSB (1U << 0) /* 16b */
+#define REG_BAK_PSRI_SRCCLKENA_MASK_B_LSB (1U << 16) /* 1b */
+#define REG_BAK_PSRI_INFRA_REQ_MASK_B_LSB (1U << 17) /* 1b */
+#define REG_BAK_PSRI_APSRC_REQ_MASK_B_LSB (1U << 18) /* 1b */
+#define REG_BAK_PSRI_VRF18_REQ_MASK_B_LSB (1U << 19) /* 1b */
+#define REG_BAK_PSRI_DDR_EN_MASK_B_LSB (1U << 20) /* 1b */
+#define REG_DRAMC0_MD32_INFRA_REQ_MASK_B_LSB (1U << 21) /* 1b */
+#define REG_DRAMC0_MD32_VRF18_REQ_MASK_B_LSB (1U << 22) /* 1b */
+#define REG_DRAMC1_MD32_INFRA_REQ_MASK_B_LSB (1U << 23) /* 1b */
+#define REG_DRAMC1_MD32_VRF18_REQ_MASK_B_LSB (1U << 24) /* 1b */
+#define REG_CONN_SRCCLKENB2PWRAP_MASK_B_LSB (1U << 25) /* 1b */
+#define REG_DRAMC0_MD32_WAKEUP_MASK_LSB (1U << 26) /* 1b */
+#define REG_DRAMC1_MD32_WAKEUP_MASK_LSB (1U << 27) /* 1b */
+/* SPM_SRC5_MASK (0x10006000+0x0CC) */
+#define REG_MCUSYS_MERGE_APSRC_REQ_MASK_B_LSB (1U << 0) /* 9b */
+#define REG_MCUSYS_MERGE_DDR_EN_MASK_B_LSB (1U << 9) /* 9b */
+/* SPM_WAKEUP_EVENT_MASK (0x10006000+0x0D0) */
+#define REG_WAKEUP_EVENT_MASK_LSB (1U << 0) /* 32b */
+/* SPM_WAKEUP_EVENT_EXT_MASK (0x10006000+0x0D4) */
+#define REG_EXT_WAKEUP_EVENT_MASK_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_EVENT_CLEAR (0x10006000+0x0D8) */
+#define SPM_TWAM_EVENT_CLEAR_LSB (1U << 0) /* 1b */
+/* SCP_CLK_CON (0x10006000+0x0DC) */
+#define REG_SCP_26M_CK_SEL_LSB (1U << 0) /* 1b */
+#define REG_SCP_DCM_EN_LSB (1U << 1) /* 1b */
+#define SCP_SECURE_V_REQ_MASK_LSB (1U << 2) /* 1b */
+#define SCP_SLP_REQ_LSB (1U << 3) /* 1b */
+#define SCP_SLP_ACK_LSB (1U << 4) /* 1b */
+/* SPM_RESOURCE_ACK_CON0 (0x10006000+0x0F0) */
+#define REG_MD_SRCCLKENA_ACK_0_MASK_LSB (1U << 0) /* 1b */
+#define REG_MD_INFRA_ACK_0_MASK_LSB (1U << 1) /* 1b */
+#define REG_MD_APSRC_ACK_0_MASK_LSB (1U << 2) /* 1b */
+#define REG_MD_VRF18_ACK_0_MASK_LSB (1U << 3) /* 1b */
+#define REG_MD_DDR_EN_ACK_0_MASK_LSB (1U << 4) /* 1b */
+#define REG_MD_SRCCLKENA_ACK_1_MASK_LSB (1U << 5) /* 1b */
+#define REG_MD_INFRA_ACK_1_MASK_LSB (1U << 6) /* 1b */
+#define REG_MD_APSRC_ACK_1_MASK_LSB (1U << 7) /* 1b */
+#define REG_MD_VRF18_ACK_1_MASK_LSB (1U << 8) /* 1b */
+#define REG_MD_DDR_EN_ACK_1_MASK_LSB (1U << 9) /* 1b */
+#define REG_CONN_SRCCLKENA_ACK_MASK_LSB (1U << 10) /* 1b */
+#define REG_CONN_INFRA_ACK_MASK_LSB (1U << 11) /* 1b */
+#define REG_CONN_APSRC_ACK_MASK_LSB (1U << 12) /* 1b */
+#define REG_CONN_VRF18_ACK_MASK_LSB (1U << 13) /* 1b */
+#define REG_CONN_DDR_EN_ACK_MASK_LSB (1U << 14) /* 1b */
+#define REG_MD32_SRCCLKENA_ACK_MASK_LSB (1U << 15) /* 1b */
+#define REG_MD32_INFRA_ACK_MASK_LSB (1U << 16) /* 1b */
+#define REG_MD32_APSRC_ACK_MASK_LSB (1U << 17) /* 1b */
+#define REG_MD32_VRF18_ACK_MASK_LSB (1U << 18) /* 1b */
+#define REG_MD32_DDR_EN_ACK_MASK_LSB (1U << 19) /* 1b */
+#define REG_SCP_SRCCLKENA_ACK_MASK_LSB (1U << 20) /* 1b */
+#define REG_SCP_INFRA_ACK_MASK_LSB (1U << 21) /* 1b */
+#define REG_SCP_APSRC_ACK_MASK_LSB (1U << 22) /* 1b */
+#define REG_SCP_VRF18_ACK_MASK_LSB (1U << 23) /* 1b */
+#define REG_SCP_DDR_EN_ACK_MASK_LSB (1U << 24) /* 1b */
+#define REG_AUDIO_DSP_SRCCLKENA_ACK_MASK_LSB (1U << 25) /* 1b */
+#define REG_AUDIO_DSP_INFRA_ACK_MASK_LSB (1U << 26) /* 1b */
+#define REG_AUDIO_DSP_APSRC_ACK_MASK_LSB (1U << 27) /* 1b */
+#define REG_AUDIO_DSP_VRF18_ACK_MASK_LSB (1U << 28) /* 1b */
+#define REG_AUDIO_DSP_DDR_EN_ACK_MASK_LSB (1U << 29) /* 1b */
+#define REG_DISP0_DDR_EN_ACK_MASK_LSB (1U << 30) /* 1b */
+#define REG_DISP1_APSRC_ACK_MASK_LSB (1U << 31) /* 1b */
+/* SPM_RESOURCE_ACK_CON1 (0x10006000+0x0F4) */
+#define REG_UFS_SRCCLKENA_ACK_MASK_LSB (1U << 0) /* 1b */
+#define REG_UFS_INFRA_ACK_MASK_LSB (1U << 1) /* 1b */
+#define REG_UFS_APSRC_ACK_MASK_LSB (1U << 2) /* 1b */
+#define REG_UFS_VRF18_ACK_MASK_LSB (1U << 3) /* 1b */
+#define REG_UFS_DDR_EN_ACK_MASK_LSB (1U << 4) /* 1b */
+#define REG_APU_SRCCLKENA_ACK_MASK_LSB (1U << 5) /* 1b */
+#define REG_APU_INFRA_ACK_MASK_LSB (1U << 6) /* 1b */
+#define REG_APU_APSRC_ACK_MASK_LSB (1U << 7) /* 1b */
+#define REG_APU_VRF18_ACK_MASK_LSB (1U << 8) /* 1b */
+#define REG_APU_DDR_EN_ACK_MASK_LSB (1U << 9) /* 1b */
+#define REG_MCUPM_SRCCLKENA_ACK_MASK_LSB (1U << 10) /* 1b */
+#define REG_MCUPM_INFRA_ACK_MASK_LSB (1U << 11) /* 1b */
+#define REG_MCUPM_APSRC_ACK_MASK_LSB (1U << 12) /* 1b */
+#define REG_MCUPM_VRF18_ACK_MASK_LSB (1U << 13) /* 1b */
+#define REG_MCUPM_DDR_EN_ACK_MASK_LSB (1U << 14) /* 1b */
+#define REG_MSDC0_SRCCLKENA_ACK_MASK_LSB (1U << 15) /* 1b */
+#define REG_MSDC0_INFRA_ACK_MASK_LSB (1U << 16) /* 1b */
+#define REG_MSDC0_APSRC_ACK_MASK_LSB (1U << 17) /* 1b */
+#define REG_MSDC0_VRF18_ACK_MASK_LSB (1U << 18) /* 1b */
+#define REG_MSDC0_DDR_EN_ACK_MASK_LSB (1U << 19) /* 1b */
+#define REG_MSDC1_SRCCLKENA_ACK_MASK_LSB (1U << 20) /* 1b */
+#define REG_MSDC1_INFRA_ACK_MASK_LSB (1U << 21) /* 1b */
+#define REG_MSDC1_APSRC_ACK_MASK_LSB (1U << 22) /* 1b */
+#define REG_MSDC1_VRF18_ACK_MASK_LSB (1U << 23) /* 1b */
+#define REG_MSDC1_DDR_EN_ACK_MASK_LSB (1U << 24) /* 1b */
+#define REG_DISP0_APSRC_ACK_MASK_LSB (1U << 25) /* 1b */
+#define REG_DISP1_DDR_EN_ACK_MASK_LSB (1U << 26) /* 1b */
+#define REG_GCE_INFRA_ACK_MASK_LSB (1U << 27) /* 1b */
+#define REG_GCE_APSRC_ACK_MASK_LSB (1U << 28) /* 1b */
+#define REG_GCE_VRF18_ACK_MASK_LSB (1U << 29) /* 1b */
+#define REG_GCE_DDR_EN_ACK_MASK_LSB (1U << 30) /* 1b */
+/* SPM_RESOURCE_ACK_CON2 (0x10006000+0x0F8) */
+#define SPM_F26M_ACK_WAIT_CYCLE_LSB (1U << 0) /* 8b */
+#define SPM_INFRA_ACK_WAIT_CYCLE_LSB (1U << 8) /* 8b */
+#define SPM_APSRC_ACK_WAIT_CYCLE_LSB (1U << 16) /* 8b */
+#define SPM_VRF18_ACK_WAIT_CYCLE_LSB (1U << 24) /* 8b */
+/* SPM_RESOURCE_ACK_CON3 (0x10006000+0x0FC) */
+#define SPM_DDR_EN_ACK_WAIT_CYCLE_LSB (1U << 0) /* 8b */
+#define REG_BAK_PSRI_SRCCLKENA_ACK_MASK_LSB (1U << 8) /* 1b */
+#define REG_BAK_PSRI_INFRA_ACK_MASK_LSB (1U << 9) /* 1b */
+#define REG_BAK_PSRI_APSRC_ACK_MASK_LSB (1U << 10) /* 1b */
+#define REG_BAK_PSRI_VRF18_ACK_MASK_LSB (1U << 11) /* 1b */
+#define REG_BAK_PSRI_DDR_EN_ACK_MASK_LSB (1U << 12) /* 1b */
+/* PCM_REG0_DATA (0x10006000+0x100) */
+#define PCM_REG0_RF_LSB (1U << 0) /* 32b */
+/* PCM_REG2_DATA (0x10006000+0x104) */
+#define PCM_REG2_RF_LSB (1U << 0) /* 32b */
+/* PCM_REG6_DATA (0x10006000+0x108) */
+#define PCM_REG6_RF_LSB (1U << 0) /* 32b */
+/* PCM_REG7_DATA (0x10006000+0x10C) */
+#define PCM_REG7_RF_LSB (1U << 0) /* 32b */
+/* PCM_REG13_DATA (0x10006000+0x110) */
+#define PCM_REG13_RF_LSB (1U << 0) /* 32b */
+/* SRC_REQ_STA_0 (0x10006000+0x114) */
+#define MD_SRCCLKENA_0_LSB (1U << 0) /* 1b */
+#define MD_SRCCLKENA2INFRA_REQ_0_LSB (1U << 1) /* 1b */
+#define MD_APSRC2INFRA_REQ_0_LSB (1U << 2) /* 1b */
+#define MD_APSRC_REQ_0_LSB (1U << 3) /* 1b */
+#define MD_VRF18_REQ_0_LSB (1U << 4) /* 1b */
+#define MD_DDR_EN_0_LSB (1U << 5) /* 1b */
+#define MD_SRCCLKENA_1_LSB (1U << 6) /* 1b */
+#define MD_SRCCLKENA2INFRA_REQ_1_LSB (1U << 7) /* 1b */
+#define MD_APSRC2INFRA_REQ_1_LSB (1U << 8) /* 1b */
+#define MD_APSRC_REQ_1_LSB (1U << 9) /* 1b */
+#define MD_VRF18_REQ_1_LSB (1U << 10) /* 1b */
+#define MD_DDR_EN_1_LSB (1U << 11) /* 1b */
+#define CONN_SRCCLKENA_LSB (1U << 12) /* 1b */
+#define CONN_SRCCLKENB_LSB (1U << 13) /* 1b */
+#define CONN_INFRA_REQ_LSB (1U << 14) /* 1b */
+#define CONN_APSRC_REQ_LSB (1U << 15) /* 1b */
+#define CONN_VRF18_REQ_LSB (1U << 16) /* 1b */
+#define CONN_DDR_EN_LSB (1U << 17) /* 1b */
+#define SRCCLKENI_LSB (1U << 18) /* 3b */
+#define MD32_SRCCLKENA_LSB (1U << 21) /* 1b */
+#define MD32_INFRA_REQ_LSB (1U << 22) /* 1b */
+#define MD32_APSRC_REQ_LSB (1U << 23) /* 1b */
+#define MD32_VRF18_REQ_LSB (1U << 24) /* 1b */
+#define MD32_DDR_EN_LSB (1U << 25) /* 1b */
+#define DISP0_APSRC_REQ_LSB (1U << 26) /* 1b */
+#define DISP0_DDR_EN_LSB (1U << 27) /* 1b */
+#define DISP1_APSRC_REQ_LSB (1U << 28) /* 1b */
+#define DISP1_DDR_EN_LSB (1U << 29) /* 1b */
+#define DVFSRC_EVENT_TRIGGER_LSB (1U << 30) /* 1b */
+/* SRC_REQ_STA_1 (0x10006000+0x118) */
+#define SCP_SRCCLKENA_LSB (1U << 0) /* 1b */
+#define SCP_INFRA_REQ_LSB (1U << 1) /* 1b */
+#define SCP_APSRC_REQ_LSB (1U << 2) /* 1b */
+#define SCP_VRF18_REQ_LSB (1U << 3) /* 1b */
+#define SCP_DDR_EN_LSB (1U << 4) /* 1b */
+#define AUDIO_DSP_SRCCLKENA_LSB (1U << 5) /* 1b */
+#define AUDIO_DSP_INFRA_REQ_LSB (1U << 6) /* 1b */
+#define AUDIO_DSP_APSRC_REQ_LSB (1U << 7) /* 1b */
+#define AUDIO_DSP_VRF18_REQ_LSB (1U << 8) /* 1b */
+#define AUDIO_DSP_DDR_EN_LSB (1U << 9) /* 1b */
+#define UFS_SRCCLKENA_LSB (1U << 10) /* 1b */
+#define UFS_INFRA_REQ_LSB (1U << 11) /* 1b */
+#define UFS_APSRC_REQ_LSB (1U << 12) /* 1b */
+#define UFS_VRF18_REQ_LSB (1U << 13) /* 1b */
+#define UFS_DDR_EN_LSB (1U << 14) /* 1b */
+#define GCE_INFRA_REQ_LSB (1U << 15) /* 1b */
+#define GCE_APSRC_REQ_LSB (1U << 16) /* 1b */
+#define GCE_VRF18_REQ_LSB (1U << 17) /* 1b */
+#define GCE_DDR_EN_LSB (1U << 18) /* 1b */
+#define INFRASYS_APSRC_REQ_LSB (1U << 19) /* 1b */
+#define INFRASYS_DDR_EN_LSB (1U << 20) /* 1b */
+#define MSDC0_SRCCLKENA_LSB (1U << 21) /* 1b */
+#define MSDC0_INFRA_REQ_LSB (1U << 22) /* 1b */
+#define MSDC0_APSRC_REQ_LSB (1U << 23) /* 1b */
+#define MSDC0_VRF18_REQ_LSB (1U << 24) /* 1b */
+#define MSDC0_DDR_EN_LSB (1U << 25) /* 1b */
+#define MSDC1_SRCCLKENA_LSB (1U << 26) /* 1b */
+#define MSDC1_INFRA_REQ_LSB (1U << 27) /* 1b */
+#define MSDC1_APSRC_REQ_LSB (1U << 28) /* 1b */
+#define MSDC1_VRF18_REQ_LSB (1U << 29) /* 1b */
+#define MSDC1_DDR_EN_LSB (1U << 30) /* 1b */
+/* SRC_REQ_STA_2 (0x10006000+0x11C) */
+#define MCUSYS_MERGE_DDR_EN_LSB (1U << 0) /* 9b */
+#define EMI_SELF_REFRESH_CH_LSB (1U << 9) /* 2b */
+#define SW2SPM_INT_LSB (1U << 11) /* 4b */
+#define SC_ADSP2SPM_WAKEUP_LSB (1U << 15) /* 1b */
+#define SC_SSPM2SPM_WAKEUP_LSB (1U << 16) /* 4b */
+#define SRC_REQ_STA_2_SC_SCP2SPM_WAKEUP_LSB (1U << 20) /* 1b */
+#define SPM_SRCCLKENA_RESERVED_LSB (1U << 21) /* 1b */
+#define SPM_INFRA_REQ_RESERVED_LSB (1U << 22) /* 1b */
+#define SPM_APSRC_REQ_RESERVED_LSB (1U << 23) /* 1b */
+#define SPM_VRF18_REQ_RESERVED_LSB (1U << 24) /* 1b */
+#define SPM_DDR_EN_RESERVED_LSB (1U << 25) /* 1b */
+#define MCUPM_SRCCLKENA_LSB (1U << 26) /* 1b */
+#define MCUPM_INFRA_REQ_LSB (1U << 27) /* 1b */
+#define MCUPM_APSRC_REQ_LSB (1U << 28) /* 1b */
+#define MCUPM_VRF18_REQ_LSB (1U << 29) /* 1b */
+#define MCUPM_DDR_EN_LSB (1U << 30) /* 1b */
+/* PCM_TIMER_OUT (0x10006000+0x120) */
+#define PCM_TIMER_LSB (1U << 0) /* 32b */
+/* PCM_WDT_OUT (0x10006000+0x124) */
+#define PCM_WDT_TIMER_VAL_OUT_LSB (1U << 0) /* 32b */
+/* SPM_IRQ_STA (0x10006000+0x128) */
+#define TWAM_IRQ_LSB (1U << 2) /* 1b */
+#define PCM_IRQ_LSB (1U << 3) /* 1b */
+/* SRC_REQ_STA_4 (0x10006000+0x12C) */
+#define APU_SRCCLKENA_LSB (1U << 0) /* 1b */
+#define APU_INFRA_REQ_LSB (1U << 1) /* 1b */
+#define APU_APSRC_REQ_LSB (1U << 2) /* 1b */
+#define APU_VRF18_REQ_LSB (1U << 3) /* 1b */
+#define APU_DDR_EN_LSB (1U << 4) /* 1b */
+#define BAK_PSRI_SRCCLKENA_LSB (1U << 5) /* 1b */
+#define BAK_PSRI_INFRA_REQ_LSB (1U << 6) /* 1b */
+#define BAK_PSRI_APSRC_REQ_LSB (1U << 7) /* 1b */
+#define BAK_PSRI_VRF18_REQ_LSB (1U << 8) /* 1b */
+#define BAK_PSRI_DDR_EN_LSB (1U << 9) /* 1b */
+/* MD32PCM_WAKEUP_STA (0x10006000+0x130) */
+#define MD32PCM_WAKEUP_STA_LSB (1U << 0) /* 32b */
+/* MD32PCM_EVENT_STA (0x10006000+0x134) */
+#define MD32PCM_EVENT_STA_LSB (1U << 0) /* 32b */
+/* SPM_WAKEUP_STA (0x10006000+0x138) */
+#define F32K_WAKEUP_EVENT_L_LSB (1U << 0) /* 16b */
+#define ASYN_WAKEUP_EVENT_L_LSB (1U << 16) /* 16b */
+/* SPM_WAKEUP_EXT_STA (0x10006000+0x13C) */
+#define EXT_WAKEUP_EVENT_LSB (1U << 0) /* 32b */
+/* SPM_WAKEUP_MISC (0x10006000+0x140) */
+#define GIC_WAKEUP_LSB (1U << 0) /* 10b */
+#define DVFSRC_IRQ_LSB (1U << 16) /* 1b */
+#define SPM_WAKEUP_MISC_REG_CPU_WAKEUP_LSB (1U << 17) /* 1b */
+#define PCM_TIMER_EVENT_LSB (1U << 18) /* 1b */
+#define PMIC_EINT_OUT_B_LSB (1U << 19) /* 2b */
+#define TWAM_IRQ_B_LSB (1U << 21) /* 1b */
+#define PMSR_IRQ_B_SET0_LSB (1U << 22) /* 1b */
+#define PMSR_IRQ_B_SET1_LSB (1U << 23) /* 1b */
+#define PMSR_IRQ_B_SET2_LSB (1U << 24) /* 1b */
+#define SPM_ACK_CHK_WAKEUP_0_LSB (1U << 25) /* 1b */
+#define SPM_ACK_CHK_WAKEUP_1_LSB (1U << 26) /* 1b */
+#define SPM_ACK_CHK_WAKEUP_2_LSB (1U << 27) /* 1b */
+#define SPM_ACK_CHK_WAKEUP_3_LSB (1U << 28) /* 1b */
+#define SPM_ACK_CHK_WAKEUP_ALL_LSB (1U << 29) /* 1b */
+#define PMIC_IRQ_ACK_LSB (1U << 30) /* 1b */
+#define PMIC_SCP_IRQ_LSB (1U << 31) /* 1b */
+/* MM_DVFS_HALT (0x10006000+0x144) */
+#define MM_DVFS_HALT_LSB (1U << 0) /* 5b */
+/* BUS_PROTECT_RDY (0x10006000+0x150) */
+#define PROTECT_READY_LSB (1U << 0) /* 32b */
+/* BUS_PROTECT1_RDY (0x10006000+0x154) */
+#define PROTECT1_READY_LSB (1U << 0) /* 32b */
+/* BUS_PROTECT2_RDY (0x10006000+0x158) */
+#define PROTECT2_READY_LSB (1U << 0) /* 32b */
+/* BUS_PROTECT3_RDY (0x10006000+0x15C) */
+#define PROTECT3_READY_LSB (1U << 0) /* 32b */
+/* SUBSYS_IDLE_STA (0x10006000+0x160) */
+#define SUBSYS_IDLE_SIGNALS_LSB (1U << 0) /* 32b */
+/* PCM_STA (0x10006000+0x164) */
+#define PCM_CK_SEL_O_LSB (1U << 0) /* 4b */
+#define EXT_SRC_STA_LSB (1U << 4) /* 3b */
+/* SRC_REQ_STA_3 (0x10006000+0x168) */
+#define CCIF_EVENT_RAW_STATUS_LSB (1U << 0) /* 16b */
+#define F26M_STATE_LSB (1U << 16) /* 1b */
+#define INFRA_STATE_LSB (1U << 17) /* 1b */
+#define APSRC_STATE_LSB (1U << 18) /* 1b */
+#define VRF18_STATE_LSB (1U << 19) /* 1b */
+#define DDR_EN_STATE_LSB (1U << 20) /* 1b */
+#define DVFS_STATE_LSB (1U << 21) /* 1b */
+#define SW_MAILBOX_STATE_LSB (1U << 22) /* 1b */
+#define SSPM_MAILBOX_STATE_LSB (1U << 23) /* 1b */
+#define ADSP_MAILBOX_STATE_LSB (1U << 24) /* 1b */
+#define SCP_MAILBOX_STATE_LSB (1U << 25) /* 1b */
+/* PWR_STATUS (0x10006000+0x16C) */
+#define PWR_STATUS_LSB (1U << 0) /* 32b */
+/* PWR_STATUS_2ND (0x10006000+0x170) */
+#define PWR_STATUS_2ND_LSB (1U << 0) /* 32b */
+/* CPU_PWR_STATUS (0x10006000+0x174) */
+#define MP0_SPMC_PWR_ON_ACK_CPU0_LSB (1U << 0) /* 1b */
+#define MP0_SPMC_PWR_ON_ACK_CPU1_LSB (1U << 1) /* 1b */
+#define MP0_SPMC_PWR_ON_ACK_CPU2_LSB (1U << 2) /* 1b */
+#define MP0_SPMC_PWR_ON_ACK_CPU3_LSB (1U << 3) /* 1b */
+#define MP0_SPMC_PWR_ON_ACK_CPU4_LSB (1U << 4) /* 1b */
+#define MP0_SPMC_PWR_ON_ACK_CPU5_LSB (1U << 5) /* 1b */
+#define MP0_SPMC_PWR_ON_ACK_CPU6_LSB (1U << 6) /* 1b */
+#define MP0_SPMC_PWR_ON_ACK_CPU7_LSB (1U << 7) /* 1b */
+#define MP0_SPMC_PWR_ON_ACK_CPUTOP_LSB (1U << 8) /* 1b */
+#define MCUSYS_SPMC_PWR_ON_ACK_LSB (1U << 9) /* 1b */
+/* OTHER_PWR_STATUS (0x10006000+0x178) */
+#define OTHER_PWR_STATUS_LSB (1U << 0) /* 32b */
+/* SPM_VTCXO_EVENT_COUNT_STA (0x10006000+0x17C) */
+#define SPM_VTCXO_SLEEP_COUNT_LSB (1U << 0) /* 16b */
+#define SPM_VTCXO_WAKE_COUNT_LSB (1U << 16) /* 16b */
+/* SPM_INFRA_EVENT_COUNT_STA (0x10006000+0x180) */
+#define SPM_INFRA_SLEEP_COUNT_LSB (1U << 0) /* 16b */
+#define SPM_INFRA_WAKE_COUNT_LSB (1U << 16) /* 16b */
+/* SPM_VRF18_EVENT_COUNT_STA (0x10006000+0x184) */
+#define SPM_VRF18_SLEEP_COUNT_LSB (1U << 0) /* 16b */
+#define SPM_VRF18_WAKE_COUNT_LSB (1U << 16) /* 16b */
+/* SPM_APSRC_EVENT_COUNT_STA (0x10006000+0x188) */
+#define SPM_APSRC_SLEEP_COUNT_LSB (1U << 0) /* 16b */
+#define SPM_APSRC_WAKE_COUNT_LSB (1U << 16) /* 16b */
+/* SPM_DDREN_EVENT_COUNT_STA (0x10006000+0x18C) */
+#define SPM_DDREN_SLEEP_COUNT_LSB (1U << 0) /* 16b */
+#define SPM_DDREN_WAKE_COUNT_LSB (1U << 16) /* 16b */
+/* MD32PCM_STA (0x10006000+0x190) */
+#define MD32PCM_HALT_LSB (1U << 0) /* 1b */
+#define MD32PCM_GATED_LSB (1U << 1) /* 1b */
+/* MD32PCM_PC (0x10006000+0x194) */
+#define MON_PC_LSB (1U << 0) /* 32b */
+/* DVFSRC_EVENT_STA (0x10006000+0x1A4) */
+#define DVFSRC_EVENT_LSB (1U << 0) /* 32b */
+/* BUS_PROTECT4_RDY (0x10006000+0x1A8) */
+#define PROTECT4_READY_LSB (1U << 0) /* 32b */
+/* BUS_PROTECT5_RDY (0x10006000+0x1AC) */
+#define PROTECT5_READY_LSB (1U << 0) /* 32b */
+/* BUS_PROTECT6_RDY (0x10006000+0x1B0) */
+#define PROTECT6_READY_LSB (1U << 0) /* 32b */
+/* BUS_PROTECT7_RDY (0x10006000+0x1B4) */
+#define PROTECT7_READY_LSB (1U << 0) /* 32b */
+/* BUS_PROTECT8_RDY (0x10006000+0x1B8) */
+#define PROTECT8_READY_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_LAST_STA0 (0x10006000+0x1D0) */
+#define LAST_IDLE_CNT_0_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_LAST_STA1 (0x10006000+0x1D4) */
+#define LAST_IDLE_CNT_1_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_LAST_STA2 (0x10006000+0x1D8) */
+#define LAST_IDLE_CNT_2_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_LAST_STA3 (0x10006000+0x1DC) */
+#define LAST_IDLE_CNT_3_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_CURR_STA0 (0x10006000+0x1E0) */
+#define CURRENT_IDLE_CNT_0_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_CURR_STA1 (0x10006000+0x1E4) */
+#define CURRENT_IDLE_CNT_1_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_CURR_STA2 (0x10006000+0x1E8) */
+#define CURRENT_IDLE_CNT_2_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_CURR_STA3 (0x10006000+0x1EC) */
+#define CURRENT_IDLE_CNT_3_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_TIMER_OUT (0x10006000+0x1F0) */
+#define TWAM_TIMER_LSB (1U << 0) /* 32b */
+/* SPM_CG_CHECK_STA (0x10006000+0x1F4) */
+#define SPM_CG_CHECK_SLEEP_REQ_0_LSB (1U << 0) /* 1b */
+#define SPM_CG_CHECK_SLEEP_REQ_1_LSB (1U << 1) /* 1b */
+#define SPM_CG_CHECK_SLEEP_REQ_2_LSB (1U << 2) /* 1b */
+/* SPM_DVFS_STA (0x10006000+0x1F8) */
+#define TARGET_DVFS_LEVEL_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_OPP_STA (0x10006000+0x1FC) */
+#define TARGET_DVFS_OPP_LSB (1U << 0) /* 5b */
+#define CURRENT_DVFS_OPP_LSB (1U << 5) /* 5b */
+#define RELAY_DVFS_OPP_LSB (1U << 10) /* 5b */
+/* SPM_MCUSYS_PWR_CON (0x10006000+0x200) */
+#define MCUSYS_SPMC_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MCUSYS_SPMC_PWR_ON_LSB (1U << 2) /* 1b */
+#define MCUSYS_SPMC_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MCUSYS_SPMC_RESETPWRON_CONFIG_LSB (1U << 5) /* 1b */
+#define MCUSYS_SPMC_DORMANT_EN_LSB (1U << 6) /* 1b */
+#define MCUSYS_VPROC_EXT_OFF_LSB (1U << 7) /* 1b */
+#define SPM_MCUSYS_PWR_CON_MCUSYS_SPMC_PWR_ON_ACK_LSB (1U << 31) /* 1b */
+/* SPM_CPUTOP_PWR_CON (0x10006000+0x204) */
+#define MP0_SPMC_PWR_RST_B_CPUTOP_LSB (1U << 0) /* 1b */
+#define MP0_SPMC_PWR_ON_CPUTOP_LSB (1U << 2) /* 1b */
+#define MP0_SPMC_PWR_CLK_DIS_CPUTOP_LSB (1U << 4) /* 1b */
+#define MP0_SPMC_RESETPWRON_CONFIG_CPUTOP_LSB (1U << 5) /* 1b */
+#define MP0_SPMC_DORMANT_EN_CPUTOP_LSB (1U << 6) /* 1b */
+#define MP0_VPROC_EXT_OFF_LSB (1U << 7) /* 1b */
+#define MP0_VSRAM_EXT_OFF_LSB (1U << 8) /* 1b */
+#define SPM_CPUTOP_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPUTOP_LSB (1U << 31) /* 1b */
+/* SPM_CPU0_PWR_CON (0x10006000+0x208) */
+#define MP0_SPMC_PWR_RST_B_CPU0_LSB (1U << 0) /* 1b */
+#define MP0_SPMC_PWR_ON_CPU0_LSB (1U << 2) /* 1b */
+#define MP0_SPMC_RESETPWRON_CONFIG_CPU0_LSB (1U << 5) /* 1b */
+#define MP0_VPROC_EXT_OFF_CPU0_LSB (1U << 7) /* 1b */
+#define SPM_CPU0_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU0_LSB (1U << 31) /* 1b */
+/* SPM_CPU1_PWR_CON (0x10006000+0x20C) */
+#define MP0_SPMC_PWR_RST_B_CPU1_LSB (1U << 0) /* 1b */
+#define MP0_SPMC_PWR_ON_CPU1_LSB (1U << 2) /* 1b */
+#define MP0_SPMC_RESETPWRON_CONFIG_CPU1_LSB (1U << 5) /* 1b */
+#define MP0_VPROC_EXT_OFF_CPU1_LSB (1U << 7) /* 1b */
+#define SPM_CPU1_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU1_LSB (1U << 31) /* 1b */
+/* SPM_CPU2_PWR_CON (0x10006000+0x210) */
+#define MP0_SPMC_PWR_RST_B_CPU2_LSB (1U << 0) /* 1b */
+#define MP0_SPMC_PWR_ON_CPU2_LSB (1U << 2) /* 1b */
+#define MP0_SPMC_RESETPWRON_CONFIG_CPU2_LSB (1U << 5) /* 1b */
+#define MP0_VPROC_EXT_OFF_CPU2_LSB (1U << 7) /* 1b */
+#define SPM_CPU2_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU2_LSB (1U << 31) /* 1b */
+/* SPM_CPU3_PWR_CON (0x10006000+0x214) */
+#define MP0_SPMC_PWR_RST_B_CPU3_LSB (1U << 0) /* 1b */
+#define MP0_SPMC_PWR_ON_CPU3_LSB (1U << 2) /* 1b */
+#define MP0_SPMC_RESETPWRON_CONFIG_CPU3_LSB (1U << 5) /* 1b */
+#define MP0_VPROC_EXT_OFF_CPU3_LSB (1U << 7) /* 1b */
+#define SPM_CPU3_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU3_LSB (1U << 31) /* 1b */
+/* SPM_CPU4_PWR_CON (0x10006000+0x218) */
+#define MP0_SPMC_PWR_RST_B_CPU4_LSB (1U << 0) /* 1b */
+#define MP0_SPMC_PWR_ON_CPU4_LSB (1U << 2) /* 1b */
+#define MP0_SPMC_RESETPWRON_CONFIG_CPU4_LSB (1U << 5) /* 1b */
+#define MP0_VPROC_EXT_OFF_CPU4_LSB (1U << 7) /* 1b */
+#define SPM_CPU4_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU4_LSB (1U << 31) /* 1b */
+/* SPM_CPU5_PWR_CON (0x10006000+0x21C) */
+#define MP0_SPMC_PWR_RST_B_CPU5_LSB (1U << 0) /* 1b */
+#define MP0_SPMC_PWR_ON_CPU5_LSB (1U << 2) /* 1b */
+#define MP0_SPMC_RESETPWRON_CONFIG_CPU5_LSB (1U << 5) /* 1b */
+#define MP0_VPROC_EXT_OFF_CPU5_LSB (1U << 7) /* 1b */
+#define SPM_CPU5_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU5_LSB (1U << 31) /* 1b */
+/* SPM_CPU6_PWR_CON (0x10006000+0x220) */
+#define MP0_SPMC_PWR_RST_B_CPU6_LSB (1U << 0) /* 1b */
+#define MP0_SPMC_PWR_ON_CPU6_LSB (1U << 2) /* 1b */
+#define MP0_SPMC_RESETPWRON_CONFIG_CPU6_LSB (1U << 5) /* 1b */
+#define MP0_VPROC_EXT_OFF_CPU6_LSB (1U << 7) /* 1b */
+#define SPM_CPU6_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU6_LSB (1U << 31) /* 1b */
+/* SPM_CPU7_PWR_CON (0x10006000+0x224) */
+#define MP0_SPMC_PWR_RST_B_CPU7_LSB (1U << 0) /* 1b */
+#define MP0_SPMC_PWR_ON_CPU7_LSB (1U << 2) /* 1b */
+#define MP0_SPMC_RESETPWRON_CONFIG_CPU7_LSB (1U << 5) /* 1b */
+#define MP0_VPROC_EXT_OFF_CPU7_LSB (1U << 7) /* 1b */
+#define SPM_CPU7_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU7_LSB (1U << 31) /* 1b */
+/* ARMPLL_CLK_CON (0x10006000+0x22C) */
+#define SC_ARM_FHC_PAUSE_LSB (1U << 0) /* 6b */
+#define SC_ARM_CK_OFF_LSB (1U << 6) /* 6b */
+#define SC_ARMPLL_OFF_LSB (1U << 12) /* 1b */
+#define SC_ARMBPLL_OFF_LSB (1U << 13) /* 1b */
+#define SC_ARMBPLL1_OFF_LSB (1U << 14) /* 1b */
+#define SC_ARMBPLL2_OFF_LSB (1U << 15) /* 1b */
+#define SC_ARMBPLL3_OFF_LSB (1U << 16) /* 1b */
+#define SC_CCIPLL_CKOFF_LSB (1U << 17) /* 1b */
+#define SC_ARMDDS_OFF_LSB (1U << 18) /* 1b */
+#define SC_ARMBPLL_S_OFF_LSB (1U << 19) /* 1b */
+#define SC_ARMBPLL1_S_OFF_LSB (1U << 20) /* 1b */
+#define SC_ARMBPLL2_S_OFF_LSB (1U << 21) /* 1b */
+#define SC_ARMBPLL3_S_OFF_LSB (1U << 22) /* 1b */
+#define SC_CCIPLL_PWROFF_LSB (1U << 23) /* 1b */
+#define SC_ARMPLLOUT_OFF_LSB (1U << 24) /* 1b */
+#define SC_ARMBPLLOUT_OFF_LSB (1U << 25) /* 1b */
+#define SC_ARMBPLLOUT1_OFF_LSB (1U << 26) /* 1b */
+#define SC_ARMBPLLOUT2_OFF_LSB (1U << 27) /* 1b */
+#define SC_ARMBPLLOUT3_OFF_LSB (1U << 28) /* 1b */
+#define SC_CCIPLL_OUT_OFF_LSB (1U << 29) /* 1b */
+/* MCUSYS_IDLE_STA (0x10006000+0x230) */
+#define ARMBUS_IDLE_TO_26M_LSB (1U << 0) /* 1b */
+#define MP0_CLUSTER_IDLE_TO_PWR_OFF_LSB (1U << 1) /* 1b */
+#define MCUSYS_DDR_EN_0_LSB (1U << 2) /* 1b */
+#define MCUSYS_DDR_EN_1_LSB (1U << 3) /* 1b */
+#define MCUSYS_DDR_EN_2_LSB (1U << 4) /* 1b */
+#define MCUSYS_DDR_EN_3_LSB (1U << 5) /* 1b */
+#define MCUSYS_DDR_EN_4_LSB (1U << 6) /* 1b */
+#define MCUSYS_DDR_EN_5_LSB (1U << 7) /* 1b */
+#define MCUSYS_DDR_EN_6_LSB (1U << 8) /* 1b */
+#define MCUSYS_DDR_EN_7_LSB (1U << 9) /* 1b */
+#define MP0_CPU_IDLE_TO_PWR_OFF_LSB (1U << 16) /* 8b */
+#define WFI_AF_SEL_LSB (1U << 24) /* 8b */
+/* GIC_WAKEUP_STA (0x10006000+0x234) */
+#define GIC_WAKEUP_STA_GIC_WAKEUP_LSB (1U << 10) /* 10b */
+/* CPU_SPARE_CON (0x10006000+0x238) */
+#define CPU_SPARE_CON_LSB (1U << 0) /* 32b */
+/* CPU_SPARE_CON_SET (0x10006000+0x23C) */
+#define CPU_SPARE_CON_SET_LSB (1U << 0) /* 32b */
+/* CPU_SPARE_CON_CLR (0x10006000+0x240) */
+#define CPU_SPARE_CON_CLR_LSB (1U << 0) /* 32b */
+/* ARMPLL_CLK_SEL (0x10006000+0x244) */
+#define ARMPLL_CLK_SEL_LSB (1U << 0) /* 15b */
+/* EXT_INT_WAKEUP_REQ (0x10006000+0x248) */
+#define EXT_INT_WAKEUP_REQ_LSB (1U << 0) /* 10b */
+/* EXT_INT_WAKEUP_REQ_SET (0x10006000+0x24C) */
+#define EXT_INT_WAKEUP_REQ_SET_LSB (1U << 0) /* 10b */
+/* EXT_INT_WAKEUP_REQ_CLR (0x10006000+0x250) */
+#define EXT_INT_WAKEUP_REQ_CLR_LSB (1U << 0) /* 10b */
+/* MP0_CPU0_IRQ_MASK (0x10006000+0x260) */
+#define MP0_CPU0_IRQ_MASK_LSB (1U << 0) /* 1b */
+#define MP0_CPU0_AUX_LSB (1U << 8) /* 11b */
+/* MP0_CPU1_IRQ_MASK (0x10006000+0x264) */
+#define MP0_CPU1_IRQ_MASK_LSB (1U << 0) /* 1b */
+#define MP0_CPU1_AUX_LSB (1U << 8) /* 11b */
+/* MP0_CPU2_IRQ_MASK (0x10006000+0x268) */
+#define MP0_CPU2_IRQ_MASK_LSB (1U << 0) /* 1b */
+#define MP0_CPU2_AUX_LSB (1U << 8) /* 11b */
+/* MP0_CPU3_IRQ_MASK (0x10006000+0x26C) */
+#define MP0_CPU3_IRQ_MASK_LSB (1U << 0) /* 1b */
+#define MP0_CPU3_AUX_LSB (1U << 8) /* 11b */
+/* MP1_CPU0_IRQ_MASK (0x10006000+0x270) */
+#define MP1_CPU0_IRQ_MASK_LSB (1U << 0) /* 1b */
+#define MP1_CPU0_AUX_LSB (1U << 8) /* 11b */
+/* MP1_CPU1_IRQ_MASK (0x10006000+0x274) */
+#define MP1_CPU1_IRQ_MASK_LSB (1U << 0) /* 1b */
+#define MP1_CPU1_AUX_LSB (1U << 8) /* 11b */
+/* MP1_CPU2_IRQ_MASK (0x10006000+0x278) */
+#define MP1_CPU2_IRQ_MASK_LSB (1U << 0) /* 1b */
+#define MP1_CPU2_AUX_LSB (1U << 8) /* 11b */
+/* MP1_CPU3_IRQ_MASK (0x10006000+0x27C) */
+#define MP1_CPU3_IRQ_MASK_LSB (1U << 0) /* 1b */
+#define MP1_CPU3_AUX_LSB (1U << 8) /* 11b */
+/* MP0_CPU0_WFI_EN (0x10006000+0x280) */
+#define MP0_CPU0_WFI_EN_LSB (1U << 0) /* 1b */
+/* MP0_CPU1_WFI_EN (0x10006000+0x284) */
+#define MP0_CPU1_WFI_EN_LSB (1U << 0) /* 1b */
+/* MP0_CPU2_WFI_EN (0x10006000+0x288) */
+#define MP0_CPU2_WFI_EN_LSB (1U << 0) /* 1b */
+/* MP0_CPU3_WFI_EN (0x10006000+0x28C) */
+#define MP0_CPU3_WFI_EN_LSB (1U << 0) /* 1b */
+/* MP0_CPU4_WFI_EN (0x10006000+0x290) */
+#define MP0_CPU4_WFI_EN_LSB (1U << 0) /* 1b */
+/* MP0_CPU5_WFI_EN (0x10006000+0x294) */
+#define MP0_CPU5_WFI_EN_LSB (1U << 0) /* 1b */
+/* MP0_CPU6_WFI_EN (0x10006000+0x298) */
+#define MP0_CPU6_WFI_EN_LSB (1U << 0) /* 1b */
+/* MP0_CPU7_WFI_EN (0x10006000+0x29C) */
+#define MP0_CPU7_WFI_EN_LSB (1U << 0) /* 1b */
+/* ROOT_CPUTOP_ADDR (0x10006000+0x2A0) */
+#define ROOT_CPUTOP_ADDR_LSB (1U << 0) /* 32b */
+/* ROOT_CORE_ADDR (0x10006000+0x2A4) */
+#define ROOT_CORE_ADDR_LSB (1U << 0) /* 32b */
+/* SPM2SW_MAILBOX_0 (0x10006000+0x2D0) */
+#define SPM2SW_MAILBOX_0_LSB (1U << 0) /* 32b */
+/* SPM2SW_MAILBOX_1 (0x10006000+0x2D4) */
+#define SPM2SW_MAILBOX_1_LSB (1U << 0) /* 32b */
+/* SPM2SW_MAILBOX_2 (0x10006000+0x2D8) */
+#define SPM2SW_MAILBOX_2_LSB (1U << 0) /* 32b */
+/* SPM2SW_MAILBOX_3 (0x10006000+0x2DC) */
+#define SPM2SW_MAILBOX_3_LSB (1U << 0) /* 32b */
+/* SW2SPM_INT (0x10006000+0x2E0) */
+#define SW2SPM_INT_SW2SPM_INT_LSB (1U << 0) /* 4b */
+/* SW2SPM_INT_SET (0x10006000+0x2E4) */
+#define SW2SPM_INT_SET_LSB (1U << 0) /* 4b */
+/* SW2SPM_INT_CLR (0x10006000+0x2E8) */
+#define SW2SPM_INT_CLR_LSB (1U << 0) /* 4b */
+/* SW2SPM_MAILBOX_0 (0x10006000+0x2EC) */
+#define SW2SPM_MAILBOX_0_LSB (1U << 0) /* 32b */
+/* SW2SPM_MAILBOX_1 (0x10006000+0x2F0) */
+#define SW2SPM_MAILBOX_1_LSB (1U << 0) /* 32b */
+/* SW2SPM_MAILBOX_2 (0x10006000+0x2F4) */
+#define SW2SPM_MAILBOX_2_LSB (1U << 0) /* 32b */
+/* SW2SPM_MAILBOX_3 (0x10006000+0x2F8) */
+#define SW2SPM_MAILBOX_3_LSB (1U << 0) /* 32b */
+/* SW2SPM_CFG (0x10006000+0x2FC) */
+#define SWU2SPM_INT_MASK_B_LSB (1U << 0) /* 4b */
+/* MD1_PWR_CON (0x10006000+0x300) */
+#define MD1_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MD1_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MD1_PWR_ON_LSB (1U << 2) /* 1b */
+#define MD1_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MD1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MD1_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_MD1_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* CONN_PWR_CON (0x10006000+0x304) */
+#define CONN_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define CONN_PWR_ISO_LSB (1U << 1) /* 1b */
+#define CONN_PWR_ON_LSB (1U << 2) /* 1b */
+#define CONN_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define CONN_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+/* MFG0_PWR_CON (0x10006000+0x308) */
+#define MFG0_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MFG0_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MFG0_PWR_ON_LSB (1U << 2) /* 1b */
+#define MFG0_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MFG0_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MFG0_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_MFG0_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* MFG1_PWR_CON (0x10006000+0x30C) */
+#define MFG1_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MFG1_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MFG1_PWR_ON_LSB (1U << 2) /* 1b */
+#define MFG1_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MFG1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MFG1_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_MFG1_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* MFG2_PWR_CON (0x10006000+0x310) */
+#define MFG2_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MFG2_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MFG2_PWR_ON_LSB (1U << 2) /* 1b */
+#define MFG2_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MFG2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MFG2_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_MFG2_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* MFG3_PWR_CON (0x10006000+0x314) */
+#define MFG3_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MFG3_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MFG3_PWR_ON_LSB (1U << 2) /* 1b */
+#define MFG3_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MFG3_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MFG3_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_MFG3_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* MFG4_PWR_CON (0x10006000+0x318) */
+#define MFG4_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MFG4_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MFG4_PWR_ON_LSB (1U << 2) /* 1b */
+#define MFG4_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MFG4_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MFG4_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_MFG4_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* MFG5_PWR_CON (0x10006000+0x31C) */
+#define MFG5_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MFG5_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MFG5_PWR_ON_LSB (1U << 2) /* 1b */
+#define MFG5_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MFG5_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MFG5_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_MFG5_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* MFG6_PWR_CON (0x10006000+0x320) */
+#define MFG6_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MFG6_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MFG6_PWR_ON_LSB (1U << 2) /* 1b */
+#define MFG6_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MFG6_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MFG6_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_MFG6_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* IFR_PWR_CON (0x10006000+0x324) */
+#define IFR_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define IFR_PWR_ISO_LSB (1U << 1) /* 1b */
+#define IFR_PWR_ON_LSB (1U << 2) /* 1b */
+#define IFR_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define IFR_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define IFR_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_IFR_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* IFR_SUB_PWR_CON (0x10006000+0x328) */
+#define IFR_SUB_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define IFR_SUB_PWR_ISO_LSB (1U << 1) /* 1b */
+#define IFR_SUB_PWR_ON_LSB (1U << 2) /* 1b */
+#define IFR_SUB_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define IFR_SUB_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define IFR_SUB_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_IFR_SUB_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* DPY_PWR_CON (0x10006000+0x32C) */
+#define DPY_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define DPY_PWR_ISO_LSB (1U << 1) /* 1b */
+#define DPY_PWR_ON_LSB (1U << 2) /* 1b */
+#define DPY_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define DPY_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define DPY_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_DPY_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* ISP_PWR_CON (0x10006000+0x330) */
+#define ISP_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define ISP_PWR_ISO_LSB (1U << 1) /* 1b */
+#define ISP_PWR_ON_LSB (1U << 2) /* 1b */
+#define ISP_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define ISP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define ISP_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_ISP_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* ISP2_PWR_CON (0x10006000+0x334) */
+#define ISP2_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define ISP2_PWR_ISO_LSB (1U << 1) /* 1b */
+#define ISP2_PWR_ON_LSB (1U << 2) /* 1b */
+#define ISP2_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define ISP2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define ISP2_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_ISP2_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* IPE_PWR_CON (0x10006000+0x338) */
+#define IPE_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define IPE_PWR_ISO_LSB (1U << 1) /* 1b */
+#define IPE_PWR_ON_LSB (1U << 2) /* 1b */
+#define IPE_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define IPE_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define IPE_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_IPE_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* VDE_PWR_CON (0x10006000+0x33C) */
+#define VDE_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define VDE_PWR_ISO_LSB (1U << 1) /* 1b */
+#define VDE_PWR_ON_LSB (1U << 2) /* 1b */
+#define VDE_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define VDE_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define VDE_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_VDE_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* VDE2_PWR_CON (0x10006000+0x340) */
+#define VDE2_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define VDE2_PWR_ISO_LSB (1U << 1) /* 1b */
+#define VDE2_PWR_ON_LSB (1U << 2) /* 1b */
+#define VDE2_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define VDE2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define VDE2_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_VDE2_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* VEN_PWR_CON (0x10006000+0x344) */
+#define VEN_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define VEN_PWR_ISO_LSB (1U << 1) /* 1b */
+#define VEN_PWR_ON_LSB (1U << 2) /* 1b */
+#define VEN_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define VEN_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define VEN_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_VEN_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* VEN_CORE1_PWR_CON (0x10006000+0x348) */
+#define VEN_CORE1_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define VEN_CORE1_PWR_ISO_LSB (1U << 1) /* 1b */
+#define VEN_CORE1_PWR_ON_LSB (1U << 2) /* 1b */
+#define VEN_CORE1_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define VEN_CORE1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define VEN_CORE1_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_VEN_CORE1_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* MDP_PWR_CON (0x10006000+0x34C) */
+#define MDP_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MDP_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MDP_PWR_ON_LSB (1U << 2) /* 1b */
+#define MDP_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MDP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MDP_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_MDP_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* DIS_PWR_CON (0x10006000+0x350) */
+#define DIS_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define DIS_PWR_ISO_LSB (1U << 1) /* 1b */
+#define DIS_PWR_ON_LSB (1U << 2) /* 1b */
+#define DIS_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define DIS_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define DIS_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_DIS_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* AUDIO_PWR_CON (0x10006000+0x354) */
+#define AUDIO_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define AUDIO_PWR_ISO_LSB (1U << 1) /* 1b */
+#define AUDIO_PWR_ON_LSB (1U << 2) /* 1b */
+#define AUDIO_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define AUDIO_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define AUDIO_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_AUDIO_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* ADSP_PWR_CON (0x10006000+0x358) */
+#define ADSP_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define ADSP_PWR_ISO_LSB (1U << 1) /* 1b */
+#define ADSP_PWR_ON_LSB (1U << 2) /* 1b */
+#define ADSP_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define ADSP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define ADSP_SRAM_CKISO_LSB (1U << 5) /* 1b */
+#define ADSP_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */
+#define ADSP_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define ADSP_SRAM_SLEEP_B_LSB (1U << 9) /* 1b */
+#define SC_ADSP_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+#define SC_ADSP_SRAM_SLEEP_B_ACK_LSB (1U << 13) /* 1b */
+/* CAM_PWR_CON (0x10006000+0x35C) */
+#define CAM_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define CAM_PWR_ISO_LSB (1U << 1) /* 1b */
+#define CAM_PWR_ON_LSB (1U << 2) /* 1b */
+#define CAM_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define CAM_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define CAM_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_CAM_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* CAM_RAWA_PWR_CON (0x10006000+0x360) */
+#define CAM_RAWA_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define CAM_RAWA_PWR_ISO_LSB (1U << 1) /* 1b */
+#define CAM_RAWA_PWR_ON_LSB (1U << 2) /* 1b */
+#define CAM_RAWA_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define CAM_RAWA_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define CAM_RAWA_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_CAM_RAWA_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* CAM_RAWB_PWR_CON (0x10006000+0x364) */
+#define CAM_RAWB_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define CAM_RAWB_PWR_ISO_LSB (1U << 1) /* 1b */
+#define CAM_RAWB_PWR_ON_LSB (1U << 2) /* 1b */
+#define CAM_RAWB_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define CAM_RAWB_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define CAM_RAWB_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_CAM_RAWB_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* CAM_RAWC_PWR_CON (0x10006000+0x368) */
+#define CAM_RAWC_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define CAM_RAWC_PWR_ISO_LSB (1U << 1) /* 1b */
+#define CAM_RAWC_PWR_ON_LSB (1U << 2) /* 1b */
+#define CAM_RAWC_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define CAM_RAWC_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define CAM_RAWC_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_CAM_RAWC_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* SYSRAM_CON (0x10006000+0x36C) */
+#define SYSRAM_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define SYSRAM_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define SYSRAM_SRAM_SLEEP_B_LSB (1U << 4) /* 4b */
+#define SYSRAM_SRAM_PDN_LSB (1U << 16) /* 4b */
+/* SYSROM_CON (0x10006000+0x370) */
+#define SYSROM_SRAM_PDN_LSB (1U << 0) /* 6b */
+/* SSPM_SRAM_CON (0x10006000+0x374) */
+#define SSPM_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define SSPM_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define SSPM_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */
+#define SSPM_SRAM_PDN_LSB (1U << 16) /* 1b */
+/* SCP_SRAM_CON (0x10006000+0x378) */
+#define SCP_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define SCP_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define SCP_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */
+#define SCP_SRAM_PDN_LSB (1U << 16) /* 1b */
+/* DPY_SHU_SRAM_CON (0x10006000+0x37C) */
+#define DPY_SHU_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define DPY_SHU_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define DPY_SHU_SRAM_SLEEP_B_LSB (1U << 4) /* 2b */
+#define DPY_SHU_SRAM_PDN_LSB (1U << 16) /* 2b */
+/* UFS_SRAM_CON (0x10006000+0x380) */
+#define UFS_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define UFS_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define UFS_SRAM_SLEEP_B_LSB (1U << 4) /* 5b */
+#define UFS_SRAM_PDN_LSB (1U << 16) /* 5b */
+/* DEVAPC_IFR_SRAM_CON (0x10006000+0x384) */
+#define DEVAPC_IFR_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define DEVAPC_IFR_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define DEVAPC_IFR_SRAM_SLEEP_B_LSB (1U << 4) /* 6b */
+#define DEVAPC_IFR_SRAM_PDN_LSB (1U << 16) /* 6b */
+/* DEVAPC_SUBIFR_SRAM_CON (0x10006000+0x388) */
+#define DEVAPC_SUBIFR_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define DEVAPC_SUBIFR_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define DEVAPC_SUBIFR_SRAM_SLEEP_B_LSB (1U << 4) /* 6b */
+#define DEVAPC_SUBIFR_SRAM_PDN_LSB (1U << 16) /* 6b */
+/* DEVAPC_ACP_SRAM_CON (0x10006000+0x38C) */
+#define DEVAPC_ACP_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define DEVAPC_ACP_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define DEVAPC_ACP_SRAM_SLEEP_B_LSB (1U << 4) /* 6b */
+#define DEVAPC_ACP_SRAM_PDN_LSB (1U << 16) /* 6b */
+/* USB_SRAM_CON (0x10006000+0x390) */
+#define USB_SRAM_PDN_LSB (1U << 0) /* 7b */
+/* DUMMY_SRAM_CON (0x10006000+0x394) */
+#define DUMMY_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define DUMMY_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define DUMMY_SRAM_SLEEP_B_LSB (1U << 4) /* 8b */
+#define DUMMY_SRAM_PDN_LSB (1U << 16) /* 8b */
+/* MD_EXT_BUCK_ISO_CON (0x10006000+0x398) */
+#define VMODEM_EXT_BUCK_ISO_LSB (1U << 0) /* 1b */
+#define VMD_EXT_BUCK_ISO_LSB (1U << 1) /* 1b */
+/* EXT_BUCK_ISO (0x10006000+0x39C) */
+#define VIMVO_EXT_BUCK_ISO_LSB (1U << 0) /* 1b */
+#define GPU_EXT_BUCK_ISO_LSB (1U << 1) /* 1b */
+#define IPU_EXT_BUCK_ISO_LSB (1U << 5) /* 3b */
+/* DXCC_SRAM_CON (0x10006000+0x3A0) */
+#define DXCC_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define DXCC_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define DXCC_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */
+#define DXCC_SRAM_PDN_LSB (1U << 16) /* 1b */
+/* MSDC_SRAM_CON (0x10006000+0x3A4) */
+#define MSDC_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define MSDC_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define MSDC_SRAM_SLEEP_B_LSB (1U << 4) /* 5b */
+#define MSDC_SRAM_PDN_LSB (1U << 16) /* 5b */
+/* DEBUGTOP_SRAM_CON (0x10006000+0x3A8) */
+#define DEBUGTOP_SRAM_PDN_LSB (1U << 0) /* 1b */
+/* DP_TX_PWR_CON (0x10006000+0x3AC) */
+#define DP_TX_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define DP_TX_PWR_ISO_LSB (1U << 1) /* 1b */
+#define DP_TX_PWR_ON_LSB (1U << 2) /* 1b */
+#define DP_TX_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define DP_TX_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define DP_TX_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_DP_TX_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* DPMAIF_SRAM_CON (0x10006000+0x3B0) */
+#define DPMAIF_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define DPMAIF_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define DPMAIF_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */
+#define DPMAIF_SRAM_PDN_LSB (1U << 16) /* 1b */
+/* DPY_SHU2_SRAM_CON (0x10006000+0x3B4) */
+#define DPY_SHU2_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define DPY_SHU2_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define DPY_SHU2_SRAM_SLEEP_B_LSB (1U << 4) /* 2b */
+#define DPY_SHU2_SRAM_PDN_LSB (1U << 16) /* 2b */
+/* DRAMC_MCU2_SRAM_CON (0x10006000+0x3B8) */
+#define DRAMC_MCU2_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define DRAMC_MCU2_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define DRAMC_MCU2_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */
+#define DRAMC_MCU2_SRAM_PDN_LSB (1U << 16) /* 1b */
+/* DRAMC_MCU_SRAM_CON (0x10006000+0x3BC) */
+#define DRAMC_MCU_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define DRAMC_MCU_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define DRAMC_MCU_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */
+#define DRAMC_MCU_SRAM_PDN_LSB (1U << 16) /* 1b */
+/* MCUPM_SRAM_CON (0x10006000+0x3C0) */
+#define MCUPM_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define MCUPM_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define MCUPM_SRAM_SLEEP_B_LSB (1U << 4) /* 8b */
+#define MCUPM_SRAM_PDN_LSB (1U << 16) /* 8b */
+/* DPY2_PWR_CON (0x10006000+0x3C4) */
+#define DPY2_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define DPY2_PWR_ISO_LSB (1U << 1) /* 1b */
+#define DPY2_PWR_ON_LSB (1U << 2) /* 1b */
+#define DPY2_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define DPY2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define DPY2_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_DPY2_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* SPM_MEM_CK_SEL (0x10006000+0x400) */
+#define SC_MEM_CK_SEL_LSB (1U << 0) /* 1b */
+#define SPM2CKSYS_MEM_CK_MUX_UPDATE_LSB (1U << 1) /* 1b */
+/* SPM_BUS_PROTECT_MASK_B (0x10006000+0X404) */
+#define SPM_BUS_PROTECT_MASK_B_LSB (1U << 0) /* 32b */
+/* SPM_BUS_PROTECT1_MASK_B (0x10006000+0x408) */
+#define SPM_BUS_PROTECT1_MASK_B_LSB (1U << 0) /* 32b */
+/* SPM_BUS_PROTECT2_MASK_B (0x10006000+0x40C) */
+#define SPM_BUS_PROTECT2_MASK_B_LSB (1U << 0) /* 32b */
+/* SPM_BUS_PROTECT3_MASK_B (0x10006000+0x410) */
+#define SPM_BUS_PROTECT3_MASK_B_LSB (1U << 0) /* 32b */
+/* SPM_BUS_PROTECT4_MASK_B (0x10006000+0x414) */
+#define SPM_BUS_PROTECT4_MASK_B_LSB (1U << 0) /* 32b */
+/* SPM_EMI_BW_MODE (0x10006000+0x418) */
+#define EMI_BW_MODE_LSB (1U << 0) /* 1b */
+#define EMI_BOOST_MODE_LSB (1U << 1) /* 1b */
+#define EMI_BW_MODE_2_LSB (1U << 2) /* 1b */
+#define EMI_BOOST_MODE_2_LSB (1U << 3) /* 1b */
+/* AP2MD_PEER_WAKEUP (0x10006000+0x41C) */
+#define AP2MD_PEER_WAKEUP_LSB (1U << 0) /* 1b */
+/* ULPOSC_CON (0x10006000+0x420) */
+#define ULPOSC_EN_LSB (1U << 0) /* 1b */
+#define ULPOSC_RST_LSB (1U << 1) /* 1b */
+#define ULPOSC_CG_EN_LSB (1U << 2) /* 1b */
+#define ULPOSC_CLK_SEL_LSB (1U << 3) /* 1b */
+/* SPM2MM_CON (0x10006000+0x424) */
+#define SPM2MM_FORCE_ULTRA_LSB (1U << 0) /* 1b */
+#define SPM2MM_DBL_OSTD_ACT_LSB (1U << 1) /* 1b */
+#define SPM2MM_ULTRAREQ_LSB (1U << 2) /* 1b */
+#define SPM2MD_ULTRAREQ_LSB (1U << 3) /* 1b */
+#define SPM2ISP_ULTRAREQ_LSB (1U << 4) /* 1b */
+#define MM2SPM_FORCE_ULTRA_ACK_D2T_LSB (1U << 16) /* 1b */
+#define MM2SPM_DBL_OSTD_ACT_ACK_D2T_LSB (1U << 17) /* 1b */
+#define SPM2ISP_ULTRAACK_D2T_LSB (1U << 18) /* 1b */
+#define SPM2MM_ULTRAACK_D2T_LSB (1U << 19) /* 1b */
+#define SPM2MD_ULTRAACK_D2T_LSB (1U << 20) /* 1b */
+/* SPM_BUS_PROTECT5_MASK_B (0x10006000+0x428) */
+#define SPM_BUS_PROTECT5_MASK_B_LSB (1U << 0) /* 32b */
+/* SPM2MCUPM_CON (0x10006000+0x42C) */
+#define SPM2MCUPM_SW_RST_B_LSB (1U << 0) /* 1b */
+#define SPM2MCUPM_SW_INT_LSB (1U << 1) /* 1b */
+/* AP_MDSRC_REQ (0x10006000+0x430) */
+#define AP_MDSMSRC_REQ_LSB (1U << 0) /* 1b */
+#define AP_L1SMSRC_REQ_LSB (1U << 1) /* 1b */
+#define AP_MD2SRC_REQ_LSB (1U << 2) /* 1b */
+#define AP_MDSMSRC_ACK_LSB (1U << 4) /* 1b */
+#define AP_L1SMSRC_ACK_LSB (1U << 5) /* 1b */
+#define AP_MD2SRC_ACK_LSB (1U << 6) /* 1b */
+/* SPM2EMI_ENTER_ULPM (0x10006000+0x434) */
+#define SPM2EMI_ENTER_ULPM_LSB (1U << 0) /* 1b */
+/* SPM2MD_DVFS_CON (0x10006000+0x438) */
+#define SPM2MD_DVFS_CON_LSB (1U << 0) /* 32b */
+/* MD2SPM_DVFS_CON (0x10006000+0x43C) */
+#define MD2SPM_DVFS_CON_LSB (1U << 0) /* 32b */
+/* SPM_BUS_PROTECT6_MASK_B (0x10006000+0X440) */
+#define SPM_BUS_PROTECT6_MASK_B_LSB (1U << 0) /* 32b */
+/* SPM_BUS_PROTECT7_MASK_B (0x10006000+0x444) */
+#define SPM_BUS_PROTECT7_MASK_B_LSB (1U << 0) /* 32b */
+/* SPM_BUS_PROTECT8_MASK_B (0x10006000+0x448) */
+#define SPM_BUS_PROTECT8_MASK_B_LSB (1U << 0) /* 32b */
+/* SPM_PLL_CON (0x10006000+0x44C) */
+#define SC_MAINPLLOUT_OFF_LSB (1U << 0) /* 1b */
+#define SC_UNIPLLOUT_OFF_LSB (1U << 1) /* 1b */
+#define SC_MAINPLL_OFF_LSB (1U << 4) /* 1b */
+#define SC_UNIPLL_OFF_LSB (1U << 5) /* 1b */
+#define SC_MAINPLL_S_OFF_LSB (1U << 8) /* 1b */
+#define SC_UNIPLL_S_OFF_LSB (1U << 9) /* 1b */
+#define SC_SMI_CK_OFF_LSB (1U << 16) /* 1b */
+#define SC_MD32K_CK_OFF_LSB (1U << 17) /* 1b */
+#define SC_CKSQ1_OFF_LSB (1U << 18) /* 1b */
+#define SC_AXI_MEM_CK_OFF_LSB (1U << 19) /* 1b */
+/* CPU_DVFS_REQ (0x10006000+0x450) */
+#define CPU_DVFS_REQ_LSB (1U << 0) /* 32b */
+/* SPM_DRAM_MCU_SW_CON_0 (0x10006000+0x454) */
+#define SW_DDR_PST_REQ_LSB (1U << 0) /* 2b */
+#define SW_DDR_PST_ABORT_REQ_LSB (1U << 2) /* 2b */
+/* SPM_DRAM_MCU_SW_CON_1 (0x10006000+0x458) */
+#define SW_DDR_PST_CH0_LSB (1U << 0) /* 32b */
+/* SPM_DRAM_MCU_SW_CON_2 (0x10006000+0x45C) */
+#define SW_DDR_PST_CH1_LSB (1U << 0) /* 32b */
+/* SPM_DRAM_MCU_SW_CON_3 (0x10006000+0x460) */
+#define SW_DDR_RESERVED_CH0_LSB (1U << 0) /* 32b */
+/* SPM_DRAM_MCU_SW_CON_4 (0x10006000+0x464) */
+#define SW_DDR_RESERVED_CH1_LSB (1U << 0) /* 32b */
+/* SPM_DRAM_MCU_STA_0 (0x10006000+0x468) */
+#define SC_DDR_PST_ACK_LSB (1U << 0) /* 2b */
+#define SC_DDR_PST_ABORT_ACK_LSB (1U << 2) /* 2b */
+/* SPM_DRAM_MCU_STA_1 (0x10006000+0x46C) */
+#define SC_DDR_CUR_PST_STA_CH0_LSB (1U << 0) /* 32b */
+/* SPM_DRAM_MCU_STA_2 (0x10006000+0x470) */
+#define SC_DDR_CUR_PST_STA_CH1_LSB (1U << 0) /* 32b */
+/* SPM_DRAM_MCU_SW_SEL_0 (0x10006000+0x474) */
+#define SW_DDR_PST_REQ_SEL_LSB (1U << 0) /* 2b */
+#define SW_DDR_PST_SEL_LSB (1U << 2) /* 2b */
+#define SW_DDR_PST_ABORT_REQ_SEL_LSB (1U << 4) /* 2b */
+#define SW_DDR_RESERVED_SEL_LSB (1U << 6) /* 2b */
+#define SW_DDR_PST_ACK_SEL_LSB (1U << 8) /* 2b */
+#define SW_DDR_PST_ABORT_ACK_SEL_LSB (1U << 10) /* 2b */
+/* RELAY_DVFS_LEVEL (0x10006000+0x478) */
+#define RELAY_DVFS_LEVEL_LSB (1U << 0) /* 32b */
+/* DRAMC_DPY_CLK_SW_CON_0 (0x10006000+0x480) */
+#define SW_PHYPLL_EN_LSB (1U << 0) /* 2b */
+#define SW_DPY_VREF_EN_LSB (1U << 2) /* 2b */
+#define SW_DPY_DLL_CK_EN_LSB (1U << 4) /* 2b */
+#define SW_DPY_DLL_EN_LSB (1U << 6) /* 2b */
+#define SW_DPY_2ND_DLL_EN_LSB (1U << 8) /* 2b */
+#define SW_MEM_CK_OFF_LSB (1U << 10) /* 2b */
+#define SW_DMSUS_OFF_LSB (1U << 12) /* 2b */
+#define SW_DPY_MODE_SW_LSB (1U << 14) /* 2b */
+#define SW_EMI_CLK_OFF_LSB (1U << 16) /* 2b */
+#define SW_DDRPHY_FB_CK_EN_LSB (1U << 18) /* 2b */
+#define SW_DR_GATE_RETRY_EN_LSB (1U << 20) /* 2b */
+#define SW_DPHY_PRECAL_UP_LSB (1U << 24) /* 2b */
+#define SW_DPY_BCLK_ENABLE_LSB (1U << 26) /* 2b */
+#define SW_TX_TRACKING_DIS_LSB (1U << 28) /* 2b */
+#define SW_DPHY_RXDLY_TRACKING_EN_LSB (1U << 30) /* 2b */
+/* DRAMC_DPY_CLK_SW_CON_1 (0x10006000+0x484) */
+#define SW_SHU_RESTORE_LSB (1U << 0) /* 2b */
+#define SW_DMYRD_MOD_LSB (1U << 2) /* 2b */
+#define SW_DMYRD_INTV_LSB (1U << 4) /* 2b */
+#define SW_DMYRD_EN_LSB (1U << 6) /* 2b */
+#define SW_DRS_DIS_REQ_LSB (1U << 8) /* 2b */
+#define SW_DR_SRAM_LOAD_LSB (1U << 10) /* 2b */
+#define SW_DR_SRAM_RESTORE_LSB (1U << 12) /* 2b */
+#define SW_DR_SHU_LEVEL_SRAM_LATCH_LSB (1U << 14) /* 2b */
+#define SW_TX_TRACK_RETRY_EN_LSB (1U << 16) /* 2b */
+#define SW_DPY_MIDPI_EN_LSB (1U << 18) /* 2b */
+#define SW_DPY_PI_RESETB_EN_LSB (1U << 20) /* 2b */
+#define SW_DPY_MCK8X_EN_LSB (1U << 22) /* 2b */
+#define SW_DR_SHU_LEVEL_SRAM_CH0_LSB (1U << 24) /* 4b */
+#define SW_DR_SHU_LEVEL_SRAM_CH1_LSB (1U << 28) /* 4b */
+/* DRAMC_DPY_CLK_SW_CON_2 (0x10006000+0x488) */
+#define SW_DR_SHU_LEVEL_LSB (1U << 0) /* 2b */
+#define SW_DR_SHU_EN_LSB (1U << 2) /* 1b */
+#define SW_DR_SHORT_QUEUE_LSB (1U << 3) /* 1b */
+#define SW_PHYPLL_MODE_SW_LSB (1U << 4) /* 1b */
+#define SW_PHYPLL2_MODE_SW_LSB (1U << 5) /* 1b */
+#define SW_PHYPLL_SHU_EN_LSB (1U << 6) /* 1b */
+#define SW_PHYPLL2_SHU_EN_LSB (1U << 7) /* 1b */
+#define SW_DR_RESERVED_0_LSB (1U << 24) /* 2b */
+#define SW_DR_RESERVED_1_LSB (1U << 26) /* 2b */
+#define SW_DR_RESERVED_2_LSB (1U << 28) /* 2b */
+#define SW_DR_RESERVED_3_LSB (1U << 30) /* 2b */
+/* DRAMC_DPY_CLK_SW_CON_3 (0x10006000+0x48C) */
+#define SC_DR_SHU_EN_ACK_LSB (1U << 0) /* 4b */
+#define SC_EMI_CLK_OFF_ACK_LSB (1U << 4) /* 4b */
+#define SC_DR_SHORT_QUEUE_ACK_LSB (1U << 8) /* 4b */
+#define SC_DRAMC_DFS_STA_LSB (1U << 12) /* 4b */
+#define SC_DRS_DIS_ACK_LSB (1U << 16) /* 4b */
+#define SC_DR_SRAM_LOAD_ACK_LSB (1U << 20) /* 4b */
+#define SC_DR_SRAM_PLL_LOAD_ACK_LSB (1U << 24) /* 4b */
+#define SC_DR_SRAM_RESTORE_ACK_LSB (1U << 28) /* 4b */
+/* DRAMC_DPY_CLK_SW_SEL_0 (0x10006000+0x490) */
+#define SW_PHYPLL_EN_SEL_LSB (1U << 0) /* 2b */
+#define SW_DPY_VREF_EN_SEL_LSB (1U << 2) /* 2b */
+#define SW_DPY_DLL_CK_EN_SEL_LSB (1U << 4) /* 2b */
+#define SW_DPY_DLL_EN_SEL_LSB (1U << 6) /* 2b */
+#define SW_DPY_2ND_DLL_EN_SEL_LSB (1U << 8) /* 2b */
+#define SW_MEM_CK_OFF_SEL_LSB (1U << 10) /* 2b */
+#define SW_DMSUS_OFF_SEL_LSB (1U << 12) /* 2b */
+#define SW_DPY_MODE_SW_SEL_LSB (1U << 14) /* 2b */
+#define SW_EMI_CLK_OFF_SEL_LSB (1U << 16) /* 2b */
+#define SW_DDRPHY_FB_CK_EN_SEL_LSB (1U << 18) /* 2b */
+#define SW_DR_GATE_RETRY_EN_SEL_LSB (1U << 20) /* 2b */
+#define SW_DPHY_PRECAL_UP_SEL_LSB (1U << 24) /* 2b */
+#define SW_DPY_BCLK_ENABLE_SEL_LSB (1U << 26) /* 2b */
+#define SW_TX_TRACKING_DIS_SEL_LSB (1U << 28) /* 2b */
+#define SW_DPHY_RXDLY_TRACKING_EN_SEL_LSB (1U << 30) /* 2b */
+/* DRAMC_DPY_CLK_SW_SEL_1 (0x10006000+0x494) */
+#define SW_SHU_RESTORE_SEL_LSB (1U << 0) /* 2b */
+#define SW_DMYRD_MOD_SEL_LSB (1U << 2) /* 2b */
+#define SW_DMYRD_INTV_SEL_LSB (1U << 4) /* 2b */
+#define SW_DMYRD_EN_SEL_LSB (1U << 6) /* 2b */
+#define SW_DRS_DIS_REQ_SEL_LSB (1U << 8) /* 2b */
+#define SW_DR_SRAM_LOAD_SEL_LSB (1U << 10) /* 2b */
+#define SW_DR_SRAM_RESTORE_SEL_LSB (1U << 12) /* 2b */
+#define SW_DR_SHU_LEVEL_SRAM_LATCH_SEL_LSB (1U << 14) /* 2b */
+#define SW_TX_TRACK_RETRY_EN_SEL_LSB (1U << 16) /* 2b */
+#define SW_DPY_MIDPI_EN_SEL_LSB (1U << 18) /* 2b */
+#define SW_DPY_PI_RESETB_EN_SEL_LSB (1U << 20) /* 2b */
+#define SW_DPY_MCK8X_EN_SEL_LSB (1U << 22) /* 2b */
+#define SW_DR_SHU_LEVEL_SRAM_SEL_LSB (1U << 24) /* 2b */
+/* DRAMC_DPY_CLK_SW_SEL_2 (0x10006000+0x498) */
+#define SW_DR_SHU_LEVEL_SEL_LSB (1U << 0) /* 1b */
+#define SW_DR_SHU_EN_SEL_LSB (1U << 2) /* 1b */
+#define SW_DR_SHORT_QUEUE_SEL_LSB (1U << 3) /* 1b */
+#define SW_PHYPLL_MODE_SW_SEL_LSB (1U << 4) /* 1b */
+#define SW_PHYPLL2_MODE_SW_SEL_LSB (1U << 5) /* 1b */
+#define SW_PHYPLL_SHU_EN_SEL_LSB (1U << 6) /* 1b */
+#define SW_PHYPLL2_SHU_EN_SEL_LSB (1U << 7) /* 1b */
+#define SW_DR_RESERVED_0_SEL_LSB (1U << 24) /* 2b */
+#define SW_DR_RESERVED_1_SEL_LSB (1U << 26) /* 2b */
+#define SW_DR_RESERVED_2_SEL_LSB (1U << 28) /* 2b */
+#define SW_DR_RESERVED_3_SEL_LSB (1U << 30) /* 2b */
+/* DRAMC_DPY_CLK_SW_SEL_3 (0x10006000+0x49C) */
+#define SC_DR_SHU_EN_ACK_SEL_LSB (1U << 0) /* 4b */
+#define SC_EMI_CLK_OFF_ACK_SEL_LSB (1U << 4) /* 4b */
+#define SC_DR_SHORT_QUEUE_ACK_SEL_LSB (1U << 8) /* 4b */
+#define SC_DRAMC_DFS_STA_SEL_LSB (1U << 12) /* 4b */
+#define SC_DRS_DIS_ACK_SEL_LSB (1U << 16) /* 4b */
+#define SC_DR_SRAM_LOAD_ACK_SEL_LSB (1U << 20) /* 4b */
+#define SC_DR_SRAM_PLL_LOAD_ACK_SEL_LSB (1U << 24) /* 4b */
+#define SC_DR_SRAM_RESTORE_ACK_SEL_LSB (1U << 28) /* 4b */
+/* DRAMC_DPY_CLK_SPM_CON (0x10006000+0x4A0) */
+#define SC_DMYRD_EN_MOD_SEL_PCM_LSB (1U << 0) /* 1b */
+#define SC_DMYRD_INTV_SEL_PCM_LSB (1U << 1) /* 1b */
+#define SC_DMYRD_EN_PCM_LSB (1U << 2) /* 1b */
+#define SC_DRS_DIS_REQ_PCM_LSB (1U << 3) /* 1b */
+#define SC_DR_SHU_LEVEL_SRAM_PCM_LSB (1U << 4) /* 4b */
+#define SC_DR_GATE_RETRY_EN_PCM_LSB (1U << 8) /* 1b */
+#define SC_DR_SHORT_QUEUE_PCM_LSB (1U << 9) /* 1b */
+#define SC_DPY_MIDPI_EN_PCM_LSB (1U << 10) /* 1b */
+#define SC_DPY_PI_RESETB_EN_PCM_LSB (1U << 11) /* 1b */
+#define SC_DPY_MCK8X_EN_PCM_LSB (1U << 12) /* 1b */
+#define SC_DR_RESERVED_0_PCM_LSB (1U << 13) /* 1b */
+#define SC_DR_RESERVED_1_PCM_LSB (1U << 14) /* 1b */
+#define SC_DR_RESERVED_2_PCM_LSB (1U << 15) /* 1b */
+#define SC_DR_RESERVED_3_PCM_LSB (1U << 16) /* 1b */
+#define SC_DMDRAMCSHU_ACK_ALL_LSB (1U << 24) /* 1b */
+#define SC_EMI_CLK_OFF_ACK_ALL_LSB (1U << 25) /* 1b */
+#define SC_DR_SHORT_QUEUE_ACK_ALL_LSB (1U << 26) /* 1b */
+#define SC_DRAMC_DFS_STA_ALL_LSB (1U << 27) /* 1b */
+#define SC_DRS_DIS_ACK_ALL_LSB (1U << 28) /* 1b */
+#define SC_DR_SRAM_LOAD_ACK_ALL_LSB (1U << 29) /* 1b */
+#define SC_DR_SRAM_PLL_LOAD_ACK_ALL_LSB (1U << 30) /* 1b */
+#define SC_DR_SRAM_RESTORE_ACK_ALL_LSB (1U << 31) /* 1b */
+/* SPM_DVFS_LEVEL (0x10006000+0x4A4) */
+#define SPM_DVFS_LEVEL_LSB (1U << 0) /* 32b */
+/* SPM_CIRQ_CON (0x10006000+0x4A8) */
+#define CIRQ_CLK_SEL_LSB (1U << 0) /* 1b */
+/* SPM_DVFS_MISC (0x10006000+0x4AC) */
+#define MSDC_DVFS_REQUEST_LSB (1U << 0) /* 1b */
+#define SPM2EMI_SLP_PROT_EN_LSB (1U << 1) /* 1b */
+#define SPM_DVFS_FORCE_ENABLE_LSB (1U << 2) /* 1b */
+#define FORCE_DVFS_WAKE_LSB (1U << 3) /* 1b */
+#define SPM_DVFSRC_ENABLE_LSB (1U << 4) /* 1b */
+#define SPM_DVFS_DONE_LSB (1U << 5) /* 1b */
+#define DVFSRC_IRQ_WAKEUP_EVENT_MASK_LSB (1U << 6) /* 1b */
+#define SPM2RC_EVENT_ABORT_LSB (1U << 7) /* 1b */
+#define EMI_SLP_IDLE_LSB (1U << 14) /* 1b */
+#define SDIO_READY_TO_SPM_LSB (1U << 15) /* 1b */
+/* SPM_VS1_VS2_RC_CON (0x10006000+0x4B0) */
+#define VS1_INIT_LEVEL_LSB (1U << 0) /* 2b */
+#define VS1_INIT_LSB (1U << 2) /* 1b */
+#define VS1_CURR_LEVEL_LSB (1U << 3) /* 2b */
+#define VS1_NEXT_LEVEL_LSB (1U << 5) /* 2b */
+#define VS1_VOTE_LEVEL_LSB (1U << 7) /* 2b */
+#define VS1_TRIGGER_LSB (1U << 9) /* 1b */
+#define VS2_INIT_LEVEL_LSB (1U << 10) /* 3b */
+#define VS2_INIT_LSB (1U << 13) /* 1b */
+#define VS2_CURR_LEVEL_LSB (1U << 14) /* 3b */
+#define VS2_NEXT_LEVEL_LSB (1U << 17) /* 3b */
+#define VS2_VOTE_LEVEL_LSB (1U << 20) /* 3b */
+#define VS2_TRIGGER_LSB (1U << 23) /* 1b */
+#define VS1_FORCE_LSB (1U << 24) /* 1b */
+#define VS2_FORCE_LSB (1U << 25) /* 1b */
+#define VS1_VOTE_LEVEL_FORCE_LSB (1U << 26) /* 2b */
+#define VS2_VOTE_LEVEL_FORCE_LSB (1U << 28) /* 3b */
+/* RG_MODULE_SW_CG_0_MASK_REQ_0 (0x10006000+0x4B4) */
+#define RG_MODULE_SW_CG_0_MASK_REQ_0_LSB (1U << 0) /* 32b */
+/* RG_MODULE_SW_CG_0_MASK_REQ_1 (0x10006000+0x4B8) */
+#define RG_MODULE_SW_CG_0_MASK_REQ_1_LSB (1U << 0) /* 32b */
+/* RG_MODULE_SW_CG_0_MASK_REQ_2 (0x10006000+0x4BC) */
+#define RG_MODULE_SW_CG_0_MASK_REQ_2_LSB (1U << 0) /* 32b */
+/* RG_MODULE_SW_CG_1_MASK_REQ_0 (0x10006000+0x4C0) */
+#define RG_MODULE_SW_CG_1_MASK_REQ_0_LSB (1U << 0) /* 32b */
+/* RG_MODULE_SW_CG_1_MASK_REQ_1 (0x10006000+0x4C4) */
+#define RG_MODULE_SW_CG_1_MASK_REQ_1_LSB (1U << 0) /* 32b */
+/* RG_MODULE_SW_CG_1_MASK_REQ_2 (0x10006000+0x4C8) */
+#define RG_MODULE_SW_CG_1_MASK_REQ_2_LSB (1U << 0) /* 32b */
+/* RG_MODULE_SW_CG_2_MASK_REQ_0 (0x10006000+0x4CC) */
+#define RG_MODULE_SW_CG_2_MASK_REQ_0_LSB (1U << 0) /* 32b */
+/* RG_MODULE_SW_CG_2_MASK_REQ_1 (0x10006000+0x4D0) */
+#define RG_MODULE_SW_CG_2_MASK_REQ_1_LSB (1U << 0) /* 32b */
+/* RG_MODULE_SW_CG_2_MASK_REQ_2 (0x10006000+0x4D4) */
+#define RG_MODULE_SW_CG_2_MASK_REQ_2_LSB (1U << 0) /* 32b */
+/* RG_MODULE_SW_CG_3_MASK_REQ_0 (0x10006000+0x4D8) */
+#define RG_MODULE_SW_CG_3_MASK_REQ_0_LSB (1U << 0) /* 32b */
+/* RG_MODULE_SW_CG_3_MASK_REQ_1 (0x10006000+0x4DC) */
+#define RG_MODULE_SW_CG_3_MASK_REQ_1_LSB (1U << 0) /* 32b */
+/* RG_MODULE_SW_CG_3_MASK_REQ_2 (0x10006000+0x4E0) */
+#define RG_MODULE_SW_CG_3_MASK_REQ_2_LSB (1U << 0) /* 32b */
+/* PWR_STATUS_MASK_REQ_0 (0x10006000+0x4E4) */
+#define PWR_STATUS_MASK_REQ_0_LSB (1U << 0) /* 32b */
+/* PWR_STATUS_MASK_REQ_1 (0x10006000+0x4E8) */
+#define PWR_STATUS_MASK_REQ_1_LSB (1U << 0) /* 32b */
+/* PWR_STATUS_MASK_REQ_2 (0x10006000+0x4EC) */
+#define PWR_STATUS_MASK_REQ_2_LSB (1U << 0) /* 32b */
+/* SPM_CG_CHECK_CON (0x10006000+0x4F0) */
+#define APMIXEDSYS_BUSY_MASK_REQ_0_LSB (1U << 0) /* 5b */
+#define APMIXEDSYS_BUSY_MASK_REQ_1_LSB (1U << 8) /* 5b */
+#define APMIXEDSYS_BUSY_MASK_REQ_2_LSB (1U << 16) /* 5b */
+#define AUDIOSYS_BUSY_MASK_REQ_0_LSB (1U << 24) /* 1b */
+#define AUDIOSYS_BUSY_MASK_REQ_1_LSB (1U << 25) /* 1b */
+#define AUDIOSYS_BUSY_MASK_REQ_2_LSB (1U << 26) /* 1b */
+#define SSUSB_BUSY_MASK_REQ_0_LSB (1U << 27) /* 1b */
+#define SSUSB_BUSY_MASK_REQ_1_LSB (1U << 28) /* 1b */
+#define SSUSB_BUSY_MASK_REQ_2_LSB (1U << 29) /* 1b */
+/* SPM_SRC_RDY_STA (0x10006000+0x4F4) */
+#define SPM_INFRA_INTERNAL_ACK_LSB (1U << 0) /* 1b */
+#define SPM_VRF18_INTERNAL_ACK_LSB (1U << 1) /* 1b */
+/* SPM_DVS_DFS_LEVEL (0x10006000+0x4F8) */
+#define SPM_DFS_LEVEL_LSB (1U << 0) /* 16b */
+#define SPM_DVS_LEVEL_LSB (1U << 16) /* 16b */
+/* SPM_FORCE_DVFS (0x10006000+0x4FC) */
+#define FORCE_DVFS_LEVEL_LSB (1U << 0) /* 32b */
+/* SRCLKEN_RC_CFG (0x10006000+0x500) */
+#define SRCLKEN_RC_CFG_LSB (1U << 0) /* 32b */
+/* RC_CENTRAL_CFG1 (0x10006000+0x504) */
+#define RC_CENTRAL_CFG1_LSB (1U << 0) /* 32b */
+/* RC_CENTRAL_CFG2 (0x10006000+0x508) */
+#define RC_CENTRAL_CFG2_LSB (1U << 0) /* 32b */
+/* RC_CMD_ARB_CFG (0x10006000+0x50C) */
+#define RC_CMD_ARB_CFG_LSB (1U << 0) /* 32b */
+/* RC_PMIC_RCEN_ADDR (0x10006000+0x510) */
+#define RC_PMIC_RCEN_ADDR_LSB (1U << 0) /* 16b */
+#define RC_PMIC_RCEN_RESERVE_LSB (1U << 16) /* 16b */
+/* RC_PMIC_RCEN_SET_CLR_ADDR (0x10006000+0x514) */
+#define RC_PMIC_RCEN_SET_ADDR_LSB (1U << 0) /* 16b */
+#define RC_PMIC_RCEN_CLR_ADDR_LSB (1U << 16) /* 16b */
+/* RC_DCXO_FPM_CFG (0x10006000+0x518) */
+#define RC_DCXO_FPM_CFG_LSB (1U << 0) /* 32b */
+/* RC_CENTRAL_CFG3 (0x10006000+0x51C) */
+#define RC_CENTRAL_CFG3_LSB (1U << 0) /* 32b */
+/* RC_M00_SRCLKEN_CFG (0x10006000+0x520) */
+#define RC_M00_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
+/* RC_M01_SRCLKEN_CFG (0x10006000+0x524) */
+#define RC_M01_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
+/* RC_M02_SRCLKEN_CFG (0x10006000+0x528) */
+#define RC_M02_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
+/* RC_M03_SRCLKEN_CFG (0x10006000+0x52C) */
+#define RC_M03_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
+/* RC_M04_SRCLKEN_CFG (0x10006000+0x530) */
+#define RC_M04_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
+/* RC_M05_SRCLKEN_CFG (0x10006000+0x534) */
+#define RC_M05_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
+/* RC_M06_SRCLKEN_CFG (0x10006000+0x538) */
+#define RC_M06_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
+/* RC_M07_SRCLKEN_CFG (0x10006000+0x53C) */
+#define RC_M07_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
+/* RC_M08_SRCLKEN_CFG (0x10006000+0x540) */
+#define RC_M08_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
+/* RC_M09_SRCLKEN_CFG (0x10006000+0x544) */
+#define RC_M09_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
+/* RC_M10_SRCLKEN_CFG (0x10006000+0x548) */
+#define RC_M10_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
+/* RC_M11_SRCLKEN_CFG (0x10006000+0x54C) */
+#define RC_M11_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
+/* RC_M12_SRCLKEN_CFG (0x10006000+0x550) */
+#define RC_M12_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
+/* RC_SRCLKEN_SW_CON_CFG (0x10006000+0x554) */
+#define RC_SRCLKEN_SW_CON_CFG_LSB (1U << 0) /* 32b */
+/* RC_CENTRAL_CFG4 (0x10006000+0x558) */
+#define RC_CENTRAL_CFG4_LSB (1U << 0) /* 32b */
+/* RC_PROTOCOL_CHK_CFG (0x10006000+0x560) */
+#define RC_PROTOCOL_CHK_CFG_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_CFG (0x10006000+0x564) */
+#define RC_DEBUG_CFG_LSB (1U << 0) /* 32b */
+/* RC_MISC_0 (0x10006000+0x5B4) */
+#define SRCCLKENO_LSB (1U << 0) /* 2b */
+#define PCM_SRCCLKENO_LSB (1U << 3) /* 2b */
+#define RC_VREQ_LSB (1U << 5) /* 1b */
+#define RC_SPM_SRCCLKENO_0_ACK_LSB (1U << 6) /* 1b */
+/* RC_SPM_CTRL (0x10006000+0x448) */
+#define SPM_AP_26M_RDY_LSB (1U << 0) /* 1b */
+#define KEEP_RC_SPI_ACTIVE_LSB (1U << 1) /* 1b */
+#define SPM2RC_DMY_CTRL_LSB (1U << 2) /* 6b */
+/* SUBSYS_INTF_CFG (0x10006000+0x5BC) */
+#define SRCLKEN_FPM_MASK_B_LSB (1U << 0) /* 13b */
+#define SRCLKEN_BBLPM_MASK_B_LSB (1U << 16) /* 13b */
+/* PCM_WDT_LATCH_25 (0x10006000+0x5C0) */
+#define PCM_WDT_LATCH_25_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_26 (0x10006000+0x5C4) */
+#define PCM_WDT_LATCH_26_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_27 (0x10006000+0x5C8) */
+#define PCM_WDT_LATCH_27_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_28 (0x10006000+0x5CC) */
+#define PCM_WDT_LATCH_28_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_29 (0x10006000+0x5D0) */
+#define PCM_WDT_LATCH_29_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_30 (0x10006000+0x5D4) */
+#define PCM_WDT_LATCH_30_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_31 (0x10006000+0x5D8) */
+#define PCM_WDT_LATCH_31_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_32 (0x10006000+0x5DC) */
+#define PCM_WDT_LATCH_32_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_33 (0x10006000+0x5E0) */
+#define PCM_WDT_LATCH_33_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_34 (0x10006000+0x5E4) */
+#define PCM_WDT_LATCH_34_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_35 (0x10006000+0x5EC) */
+#define PCM_WDT_LATCH_35_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_36 (0x10006000+0x5F0) */
+#define PCM_WDT_LATCH_36_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_37 (0x10006000+0x5F4) */
+#define PCM_WDT_LATCH_37_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_38 (0x10006000+0x5F8) */
+#define PCM_WDT_LATCH_38_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_39 (0x10006000+0x5FC) */
+#define PCM_WDT_LATCH_39_LSB (1U << 0) /* 32b */
+/* SPM_SW_FLAG_0 (0x10006000+0x600) */
+#define SPM_SW_FLAG_LSB (1U << 0) /* 32b */
+/* SPM_SW_DEBUG_0 (0x10006000+0x604) */
+#define SPM_SW_DEBUG_0_LSB (1U << 0) /* 32b */
+/* SPM_SW_FLAG_1 (0x10006000+0x608) */
+#define SPM_SW_FLAG_1_LSB (1U << 0) /* 32b */
+/* SPM_SW_DEBUG_1 (0x10006000+0x60C) */
+#define SPM_SW_DEBUG_1_LSB (1U << 0) /* 32b */
+/* SPM_SW_RSV_0 (0x10006000+0x610) */
+#define SPM_SW_RSV_0_LSB (1U << 0) /* 32b */
+/* SPM_SW_RSV_1 (0x10006000+0x614) */
+#define SPM_SW_RSV_1_LSB (1U << 0) /* 32b */
+/* SPM_SW_RSV_2 (0x10006000+0x618) */
+#define SPM_SW_RSV_2_LSB (1U << 0) /* 32b */
+/* SPM_SW_RSV_3 (0x10006000+0x61C) */
+#define SPM_SW_RSV_3_LSB (1U << 0) /* 32b */
+/* SPM_SW_RSV_4 (0x10006000+0x620) */
+#define SPM_SW_RSV_4_LSB (1U << 0) /* 32b */
+/* SPM_SW_RSV_5 (0x10006000+0x624) */
+#define SPM_SW_RSV_5_LSB (1U << 0) /* 32b */
+/* SPM_SW_RSV_6 (0x10006000+0x628) */
+#define SPM_SW_RSV_6_LSB (1U << 0) /* 32b */
+/* SPM_SW_RSV_7 (0x10006000+0x62C) */
+#define SPM_SW_RSV_7_LSB (1U << 0) /* 32b */
+/* SPM_SW_RSV_8 (0x10006000+0x630) */
+#define SPM_SW_RSV_8_LSB (1U << 0) /* 32b */
+/* SPM_BK_WAKE_EVENT (0x10006000+0x634) */
+#define SPM_BK_WAKE_EVENT_LSB (1U << 0) /* 32b */
+/* SPM_BK_VTCXO_DUR (0x10006000+0x638) */
+#define SPM_BK_VTCXO_DUR_LSB (1U << 0) /* 32b */
+/* SPM_BK_WAKE_MISC (0x10006000+0x63C) */
+#define SPM_BK_WAKE_MISC_LSB (1U << 0) /* 32b */
+/* SPM_BK_PCM_TIMER (0x10006000+0x640) */
+#define SPM_BK_PCM_TIMER_LSB (1U << 0) /* 32b */
+/* SPM_RSV_CON_0 (0x10006000+0x650) */
+#define SPM_RSV_CON_0_LSB (1U << 0) /* 32b */
+/* SPM_RSV_CON_1 (0x10006000+0x654) */
+#define SPM_RSV_CON_1_LSB (1U << 0) /* 32b */
+/* SPM_RSV_STA_0 (0x10006000+0x658) */
+#define SPM_RSV_STA_0_LSB (1U << 0) /* 32b */
+/* SPM_RSV_STA_1 (0x10006000+0x65C) */
+#define SPM_RSV_STA_1_LSB (1U << 0) /* 32b */
+/* SPM_SPARE_CON (0x10006000+0x660) */
+#define SPM_SPARE_CON_LSB (1U << 0) /* 32b */
+/* SPM_SPARE_CON_SET (0x10006000+0x664) */
+#define SPM_SPARE_CON_SET_LSB (1U << 0) /* 32b */
+/* SPM_SPARE_CON_CLR (0x10006000+0x668) */
+#define SPM_SPARE_CON_CLR_LSB (1U << 0) /* 32b */
+/* SPM_CROSS_WAKE_M00_REQ (0x10006000+0x66C) */
+#define SPM_CROSS_WAKE_M00_REQ_LSB (1U << 0) /* 4b */
+#define SPM_CROSS_WAKE_M00_CHK_LSB (1U << 4) /* 4b */
+/* SPM_CROSS_WAKE_M01_REQ (0x10006000+0x670) */
+#define SPM_CROSS_WAKE_M01_REQ_LSB (1U << 0) /* 4b */
+#define SPM_CROSS_WAKE_M01_CHK_LSB (1U << 4) /* 4b */
+/* SPM_CROSS_WAKE_M02_REQ (0x10006000+0x674) */
+#define SPM_CROSS_WAKE_M02_REQ_LSB (1U << 0) /* 4b */
+#define SPM_CROSS_WAKE_M02_CHK_LSB (1U << 4) /* 4b */
+/* SPM_CROSS_WAKE_M03_REQ (0x10006000+0x678) */
+#define SPM_CROSS_WAKE_M03_REQ_LSB (1U << 0) /* 4b */
+#define SPM_CROSS_WAKE_M03_CHK_LSB (1U << 4) /* 4b */
+/* SCP_VCORE_LEVEL (0x10006000+0x67C) */
+#define SCP_VCORE_LEVEL_LSB (1U << 0) /* 16b */
+/* SC_MM_CK_SEL_CON (0x10006000+0x680) */
+#define SC_MM_CK_SEL_LSB (1U << 0) /* 4b */
+#define SC_MM_CK_SEL_EN_LSB (1U << 4) /* 1b */
+/* SPARE_ACK_MASK (0x10006000+0x684) */
+#define SPARE_ACK_MASK_B_LSB (1U << 0) /* 32b */
+/* SPM_DV_CON_0 (0x10006000+0x68C) */
+#define SPM_DV_CON_0_LSB (1U << 0) /* 32b */
+/* SPM_DV_CON_1 (0x10006000+0x690) */
+#define SPM_DV_CON_1_LSB (1U << 0) /* 32b */
+/* SPM_DV_STA (0x10006000+0x694) */
+#define SPM_DV_STA_LSB (1U << 0) /* 32b */
+/* CONN_XOWCN_DEBUG_EN (0x10006000+0x698) */
+#define CONN_XOWCN_DEBUG_EN_LSB (1U << 0) /* 1b */
+/* SPM_SEMA_M0 (0x10006000+0x69C) */
+#define SPM_SEMA_M0_LSB (1U << 0) /* 8b */
+/* SPM_SEMA_M1 (0x10006000+0x6A0) */
+#define SPM_SEMA_M1_LSB (1U << 0) /* 8b */
+/* SPM_SEMA_M2 (0x10006000+0x6A4) */
+#define SPM_SEMA_M2_LSB (1U << 0) /* 8b */
+/* SPM_SEMA_M3 (0x10006000+0x6A8) */
+#define SPM_SEMA_M3_LSB (1U << 0) /* 8b */
+/* SPM_SEMA_M4 (0x10006000+0x6AC) */
+#define SPM_SEMA_M4_LSB (1U << 0) /* 8b */
+/* SPM_SEMA_M5 (0x10006000+0x6B0) */
+#define SPM_SEMA_M5_LSB (1U << 0) /* 8b */
+/* SPM_SEMA_M6 (0x10006000+0x6B4) */
+#define SPM_SEMA_M6_LSB (1U << 0) /* 8b */
+/* SPM_SEMA_M7 (0x10006000+0x6B8) */
+#define SPM_SEMA_M7_LSB (1U << 0) /* 8b */
+/* SPM2ADSP_MAILBOX (0x10006000+0x6BC) */
+#define SPM2ADSP_MAILBOX_LSB (1U << 0) /* 32b */
+/* ADSP2SPM_MAILBOX (0x10006000+0x6C0) */
+#define ADSP2SPM_MAILBOX_LSB (1U << 0) /* 32b */
+/* SPM_ADSP_IRQ (0x10006000+0x6C4) */
+#define SC_SPM2ADSP_WAKEUP_LSB (1U << 0) /* 1b */
+#define SPM_ADSP_IRQ_SC_ADSP2SPM_WAKEUP_LSB (1U << 4) /* 1b */
+/* SPM_MD32_IRQ (0x10006000+0x6C8) */
+#define SC_SPM2SSPM_WAKEUP_LSB (1U << 0) /* 4b */
+#define SPM_MD32_IRQ_SC_SSPM2SPM_WAKEUP_LSB (1U << 4) /* 4b */
+/* SPM2PMCU_MAILBOX_0 (0x10006000+0x6CC) */
+#define SPM2PMCU_MAILBOX_0_LSB (1U << 0) /* 32b */
+/* SPM2PMCU_MAILBOX_1 (0x10006000+0x6D0) */
+#define SPM2PMCU_MAILBOX_1_LSB (1U << 0) /* 32b */
+/* SPM2PMCU_MAILBOX_2 (0x10006000+0x6D4) */
+#define SPM2PMCU_MAILBOX_2_LSB (1U << 0) /* 32b */
+/* SPM2PMCU_MAILBOX_3 (0x10006000+0x6D8) */
+#define SPM2PMCU_MAILBOX_3_LSB (1U << 0) /* 32b */
+/* PMCU2SPM_MAILBOX_0 (0x10006000+0x6DC) */
+#define PMCU2SPM_MAILBOX_0_LSB (1U << 0) /* 32b */
+/* PMCU2SPM_MAILBOX_1 (0x10006000+0x6E0) */
+#define PMCU2SPM_MAILBOX_1_LSB (1U << 0) /* 32b */
+/* PMCU2SPM_MAILBOX_2 (0x10006000+0x6E4) */
+#define PMCU2SPM_MAILBOX_2_LSB (1U << 0) /* 32b */
+/* PMCU2SPM_MAILBOX_3 (0x10006000+0x6E8) */
+#define PMCU2SPM_MAILBOX_3_LSB (1U << 0) /* 32b */
+/* UFS_PSRI_SW (0x10006000+0x6EC) */
+#define UFS_PSRI_SW_LSB (1U << 0) /* 1b */
+/* UFS_PSRI_SW_SET (0x10006000+0x6F0) */
+#define UFS_PSRI_SW_SET_LSB (1U << 0) /* 1b */
+/* UFS_PSRI_SW_CLR (0x10006000+0x6F4) */
+#define UFS_PSRI_SW_CLR_LSB (1U << 0) /* 1b */
+/* SPM_AP_SEMA (0x10006000+0x6F8) */
+#define SPM_AP_SEMA_LSB (1U << 0) /* 1b */
+/* SPM_SPM_SEMA (0x10006000+0x6FC) */
+#define SPM_SPM_SEMA_LSB (1U << 0) /* 1b */
+/* SPM_DVFS_CON (0x10006000+0x700) */
+#define SPM_DVFS_CON_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CON_STA (0x10006000+0x704) */
+#define SPM_DVFS_CON_STA_LSB (1U << 0) /* 32b */
+/* SPM_PMIC_SPMI_CON (0x10006000+0x708) */
+#define SPM_PMIC_SPMI_CMD_LSB (1U << 0) /* 2b */
+#define SPM_PMIC_SPMI_SLAVEID_LSB (1U << 2) /* 4b */
+#define SPM_PMIC_SPMI_PMIFID_LSB (1U << 6) /* 1b */
+#define SPM_PMIC_SPMI_DBCNT_LSB (1U << 7) /* 1b */
+/* SPM_DVFS_CMD0 (0x10006000+0x710) */
+#define SPM_DVFS_CMD0_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD1 (0x10006000+0x714) */
+#define SPM_DVFS_CMD1_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD2 (0x10006000+0x718) */
+#define SPM_DVFS_CMD2_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD3 (0x10006000+0x71C) */
+#define SPM_DVFS_CMD3_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD4 (0x10006000+0x720) */
+#define SPM_DVFS_CMD4_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD5 (0x10006000+0x724) */
+#define SPM_DVFS_CMD5_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD6 (0x10006000+0x728) */
+#define SPM_DVFS_CMD6_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD7 (0x10006000+0x72C) */
+#define SPM_DVFS_CMD7_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD8 (0x10006000+0x730) */
+#define SPM_DVFS_CMD8_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD9 (0x10006000+0x734) */
+#define SPM_DVFS_CMD9_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD10 (0x10006000+0x738) */
+#define SPM_DVFS_CMD10_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD11 (0x10006000+0x73C) */
+#define SPM_DVFS_CMD11_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD12 (0x10006000+0x740) */
+#define SPM_DVFS_CMD12_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD13 (0x10006000+0x744) */
+#define SPM_DVFS_CMD13_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD14 (0x10006000+0x748) */
+#define SPM_DVFS_CMD14_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD15 (0x10006000+0x74C) */
+#define SPM_DVFS_CMD15_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD16 (0x10006000+0x750) */
+#define SPM_DVFS_CMD16_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD17 (0x10006000+0x754) */
+#define SPM_DVFS_CMD17_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD18 (0x10006000+0x758) */
+#define SPM_DVFS_CMD18_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD19 (0x10006000+0x75C) */
+#define SPM_DVFS_CMD19_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD20 (0x10006000+0x760) */
+#define SPM_DVFS_CMD20_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD21 (0x10006000+0x764) */
+#define SPM_DVFS_CMD21_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD22 (0x10006000+0x768) */
+#define SPM_DVFS_CMD22_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD23 (0x10006000+0x76C) */
+#define SPM_DVFS_CMD23_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_VALUE_L (0x10006000+0x770) */
+#define SYS_TIMER_VALUE_L_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_VALUE_H (0x10006000+0x774) */
+#define SYS_TIMER_VALUE_H_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_START_L (0x10006000+0x778) */
+#define SYS_TIMER_START_L_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_START_H (0x10006000+0x77C) */
+#define SYS_TIMER_START_H_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_L_00 (0x10006000+0x780) */
+#define SYS_TIMER_LATCH_L_00_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_H_00 (0x10006000+0x784) */
+#define SYS_TIMER_LATCH_H_00_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_L_01 (0x10006000+0x788) */
+#define SYS_TIMER_LATCH_L_01_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_H_01 (0x10006000+0x78C) */
+#define SYS_TIMER_LATCH_H_01_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_L_02 (0x10006000+0x790) */
+#define SYS_TIMER_LATCH_L_02_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_H_02 (0x10006000+0x794) */
+#define SYS_TIMER_LATCH_H_02_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_L_03 (0x10006000+0x798) */
+#define SYS_TIMER_LATCH_L_03_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_H_03 (0x10006000+0x79C) */
+#define SYS_TIMER_LATCH_H_03_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_L_04 (0x10006000+0x7A0) */
+#define SYS_TIMER_LATCH_L_04_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_H_04 (0x10006000+0x7A4) */
+#define SYS_TIMER_LATCH_H_04_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_L_05 (0x10006000+0x7A8) */
+#define SYS_TIMER_LATCH_L_05_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_H_05 (0x10006000+0x7AC) */
+#define SYS_TIMER_LATCH_H_05_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_L_06 (0x10006000+0x7B0) */
+#define SYS_TIMER_LATCH_L_06_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_H_06 (0x10006000+0x7B4) */
+#define SYS_TIMER_LATCH_H_06_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_L_07 (0x10006000+0x7B8) */
+#define SYS_TIMER_LATCH_L_07_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_H_07 (0x10006000+0x7BC) */
+#define SYS_TIMER_LATCH_H_07_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_L_08 (0x10006000+0x7C0) */
+#define SYS_TIMER_LATCH_L_08_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_H_08 (0x10006000+0x7C4) */
+#define SYS_TIMER_LATCH_H_08_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_L_09 (0x10006000+0x7C8) */
+#define SYS_TIMER_LATCH_L_09_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_H_09 (0x10006000+0x7CC) */
+#define SYS_TIMER_LATCH_H_09_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_L_10 (0x10006000+0x7D0) */
+#define SYS_TIMER_LATCH_L_10_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_H_10 (0x10006000+0x7D4) */
+#define SYS_TIMER_LATCH_H_10_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_L_11 (0x10006000+0x7D8) */
+#define SYS_TIMER_LATCH_L_11_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_H_11 (0x10006000+0x7DC) */
+#define SYS_TIMER_LATCH_H_11_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_L_12 (0x10006000+0x7E0) */
+#define SYS_TIMER_LATCH_L_12_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_H_12 (0x10006000+0x7E4) */
+#define SYS_TIMER_LATCH_H_12_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_L_13 (0x10006000+0x7E8) */
+#define SYS_TIMER_LATCH_L_13_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_H_13 (0x10006000+0x7EC) */
+#define SYS_TIMER_LATCH_H_13_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_L_14 (0x10006000+0x7F0) */
+#define SYS_TIMER_LATCH_L_14_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_H_14 (0x10006000+0x7F4) */
+#define SYS_TIMER_LATCH_H_14_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_L_15 (0x10006000+0x7F8) */
+#define SYS_TIMER_LATCH_L_15_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_H_15 (0x10006000+0x7FC) */
+#define SYS_TIMER_LATCH_H_15_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_0 (0x10006000+0x800) */
+#define PCM_WDT_LATCH_0_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_1 (0x10006000+0x804) */
+#define PCM_WDT_LATCH_1_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_2 (0x10006000+0x808) */
+#define PCM_WDT_LATCH_2_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_3 (0x10006000+0x80C) */
+#define PCM_WDT_LATCH_3_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_4 (0x10006000+0x810) */
+#define PCM_WDT_LATCH_4_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_5 (0x10006000+0x814) */
+#define PCM_WDT_LATCH_5_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_6 (0x10006000+0x818) */
+#define PCM_WDT_LATCH_6_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_7 (0x10006000+0x81C) */
+#define PCM_WDT_LATCH_7_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_8 (0x10006000+0x820) */
+#define PCM_WDT_LATCH_8_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_9 (0x10006000+0x824) */
+#define PCM_WDT_LATCH_9_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_10 (0x10006000+0x828) */
+#define PCM_WDT_LATCH_10_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_11 (0x10006000+0x82C) */
+#define PCM_WDT_LATCH_11_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_12 (0x10006000+0x830) */
+#define PCM_WDT_LATCH_12_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_13 (0x10006000+0x834) */
+#define PCM_WDT_LATCH_13_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_14 (0x10006000+0x838) */
+#define PCM_WDT_LATCH_14_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_15 (0x10006000+0x83C) */
+#define PCM_WDT_LATCH_15_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_16 (0x10006000+0x840) */
+#define PCM_WDT_LATCH_16_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_17 (0x10006000+0x844) */
+#define PCM_WDT_LATCH_17_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_18 (0x10006000+0x848) */
+#define PCM_WDT_LATCH_18_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_SPARE_0 (0x10006000+0x84C) */
+#define PCM_WDT_LATCH_SPARE_0_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_SPARE_1 (0x10006000+0x850) */
+#define PCM_WDT_LATCH_SPARE_1_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_SPARE_2 (0x10006000+0x854) */
+#define PCM_WDT_LATCH_SPARE_2_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_CONN_0 (0x10006000+0x870) */
+#define PCM_WDT_LATCH_CONN_0_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_CONN_1 (0x10006000+0x874) */
+#define PCM_WDT_LATCH_CONN_1_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_CONN_2 (0x10006000+0x878) */
+#define PCM_WDT_LATCH_CONN_2_LSB (1U << 0) /* 32b */
+/* DRAMC_GATING_ERR_LATCH_CH0_0 (0x10006000+0x8A0) */
+#define DRAMC_GATING_ERR_LATCH_CH0_0_LSB (1U << 0) /* 32b */
+/* DRAMC_GATING_ERR_LATCH_CH0_1 (0x10006000+0x8A4) */
+#define DRAMC_GATING_ERR_LATCH_CH0_1_LSB (1U << 0) /* 32b */
+/* DRAMC_GATING_ERR_LATCH_CH0_2 (0x10006000+0x8A8) */
+#define DRAMC_GATING_ERR_LATCH_CH0_2_LSB (1U << 0) /* 32b */
+/* DRAMC_GATING_ERR_LATCH_CH0_3 (0x10006000+0x8AC) */
+#define DRAMC_GATING_ERR_LATCH_CH0_3_LSB (1U << 0) /* 32b */
+/* DRAMC_GATING_ERR_LATCH_CH0_4 (0x10006000+0x8B0) */
+#define DRAMC_GATING_ERR_LATCH_CH0_4_LSB (1U << 0) /* 32b */
+/* DRAMC_GATING_ERR_LATCH_CH0_5 (0x10006000+0x8B4) */
+#define DRAMC_GATING_ERR_LATCH_CH0_5_LSB (1U << 0) /* 32b */
+/* DRAMC_GATING_ERR_LATCH_CH0_6 (0x10006000+0x8B8) */
+#define DRAMC_GATING_ERR_LATCH_CH0_6_LSB (1U << 0) /* 32b */
+/* DRAMC_GATING_ERR_LATCH_SPARE_0 (0x10006000+0x8F4) */
+#define DRAMC_GATING_ERR_LATCH_SPARE_0_LSB (1U << 0) /* 32b */
+/* SPM_ACK_CHK_CON_0 (0x10006000+0x900) */
+#define SPM_ACK_CHK_SW_EN_0_LSB (1U << 0) /* 1b */
+#define SPM_ACK_CHK_CLR_ALL_0_LSB (1U << 1) /* 1b */
+#define SPM_ACK_CHK_CLR_TIMER_0_LSB (1U << 2) /* 1b */
+#define SPM_ACK_CHK_CLR_IRQ_0_LSB (1U << 3) /* 1b */
+#define SPM_ACK_CHK_STA_EN_0_LSB (1U << 4) /* 1b */
+#define SPM_ACK_CHK_WAKEUP_EN_0_LSB (1U << 5) /* 1b */
+#define SPM_ACK_CHK_WDT_EN_0_LSB (1U << 6) /* 1b */
+#define SPM_ACK_CHK_LOCK_PC_TRACE_EN_0_LSB (1U << 7) /* 1b */
+#define SPM_ACK_CHK_HW_EN_0_LSB (1U << 8) /* 1b */
+#define SPM_ACK_CHK_HW_MODE_0_LSB (1U << 9) /* 3b */
+#define SPM_ACK_CHK_FAIL_0_LSB (1U << 15) /* 1b */
+/* SPM_ACK_CHK_PC_0 (0x10006000+0x904) */
+#define SPM_ACK_CHK_HW_TRIG_PC_VAL_0_LSB (1U << 0) /* 16b */
+#define SPM_ACK_CHK_HW_TARG_PC_VAL_0_LSB (1U << 16) /* 16b */
+/* SPM_ACK_CHK_SEL_0 (0x10006000+0x908) */
+#define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_0_LSB (1U << 0) /* 5b */
+#define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_0_LSB (1U << 5) /* 3b */
+#define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_0_LSB (1U << 16) /* 5b */
+#define SPM_ACK_CHK_HW_TARG_GROUP_SEL_0_LSB (1U << 21) /* 3b */
+/* SPM_ACK_CHK_TIMER_0 (0x10006000+0x90C) */
+#define SPM_ACK_CHK_TIMER_VAL_0_LSB (1U << 0) /* 16b */
+#define SPM_ACK_CHK_TIMER_0_LSB (1U << 16) /* 16b */
+/* SPM_ACK_CHK_STA_0 (0x10006000+0x910) */
+#define SPM_ACK_CHK_STA_0_LSB (1U << 0) /* 32b */
+/* SPM_ACK_CHK_SWINT_0 (0x10006000+0x914) */
+#define SPM_ACK_CHK_SWINT_EN_0_LSB (1U << 0) /* 32b */
+/* SPM_ACK_CHK_CON_1 (0x10006000+0x920) */
+#define SPM_ACK_CHK_SW_EN_1_LSB (1U << 0) /* 1b */
+#define SPM_ACK_CHK_CLR_ALL_1_LSB (1U << 1) /* 1b */
+#define SPM_ACK_CHK_CLR_TIMER_1_LSB (1U << 2) /* 1b */
+#define SPM_ACK_CHK_CLR_IRQ_1_LSB (1U << 3) /* 1b */
+#define SPM_ACK_CHK_STA_EN_1_LSB (1U << 4) /* 1b */
+#define SPM_ACK_CHK_WAKEUP_EN_1_LSB (1U << 5) /* 1b */
+#define SPM_ACK_CHK_WDT_EN_1_LSB (1U << 6) /* 1b */
+#define SPM_ACK_CHK_LOCK_PC_TRACE_EN_1_LSB (1U << 7) /* 1b */
+#define SPM_ACK_CHK_HW_EN_1_LSB (1U << 8) /* 1b */
+#define SPM_ACK_CHK_HW_MODE_1_LSB (1U << 9) /* 3b */
+#define SPM_ACK_CHK_FAIL_1_LSB (1U << 15) /* 1b */
+/* SPM_ACK_CHK_PC_1 (0x10006000+0x924) */
+#define SPM_ACK_CHK_HW_TRIG_PC_VAL_1_LSB (1U << 0) /* 16b */
+#define SPM_ACK_CHK_HW_TARG_PC_VAL_1_LSB (1U << 16) /* 16b */
+/* SPM_ACK_CHK_SEL_1 (0x10006000+0x928) */
+#define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_1_LSB (1U << 0) /* 5b */
+#define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_1_LSB (1U << 5) /* 3b */
+#define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_1_LSB (1U << 16) /* 5b */
+#define SPM_ACK_CHK_HW_TARG_GROUP_SEL_1_LSB (1U << 21) /* 3b */
+/* SPM_ACK_CHK_TIMER_1 (0x10006000+0x92C) */
+#define SPM_ACK_CHK_TIMER_VAL_1_LSB (1U << 0) /* 16b */
+#define SPM_ACK_CHK_TIMER_1_LSB (1U << 16) /* 16b */
+/* SPM_ACK_CHK_STA_1 (0x10006000+0x930) */
+#define SPM_ACK_CHK_STA_1_LSB (1U << 0) /* 32b */
+/* SPM_ACK_CHK_SWINT_1 (0x10006000+0x934) */
+#define SPM_ACK_CHK_SWINT_EN_1_LSB (1U << 0) /* 32b */
+/* SPM_ACK_CHK_CON_2 (0x10006000+0x940) */
+#define SPM_ACK_CHK_SW_EN_2_LSB (1U << 0) /* 1b */
+#define SPM_ACK_CHK_CLR_ALL_2_LSB (1U << 1) /* 1b */
+#define SPM_ACK_CHK_CLR_TIMER_2_LSB (1U << 2) /* 1b */
+#define SPM_ACK_CHK_CLR_IRQ_2_LSB (1U << 3) /* 1b */
+#define SPM_ACK_CHK_STA_EN_2_LSB (1U << 4) /* 1b */
+#define SPM_ACK_CHK_WAKEUP_EN_2_LSB (1U << 5) /* 1b */
+#define SPM_ACK_CHK_WDT_EN_2_LSB (1U << 6) /* 1b */
+#define SPM_ACK_CHK_LOCK_PC_TRACE_EN_2_LSB (1U << 7) /* 1b */
+#define SPM_ACK_CHK_HW_EN_2_LSB (1U << 8) /* 1b */
+#define SPM_ACK_CHK_HW_MODE_2_LSB (1U << 9) /* 3b */
+#define SPM_ACK_CHK_FAIL_2_LSB (1U << 15) /* 1b */
+/* SPM_ACK_CHK_PC_2 (0x10006000+0x944) */
+#define SPM_ACK_CHK_HW_TRIG_PC_VAL_2_LSB (1U << 0) /* 16b */
+#define SPM_ACK_CHK_HW_TARG_PC_VAL_2_LSB (1U << 16) /* 16b */
+/* SPM_ACK_CHK_SEL_2 (0x10006000+0x948) */
+#define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_2_LSB (1U << 0) /* 5b */
+#define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_2_LSB (1U << 5) /* 3b */
+#define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_2_LSB (1U << 16) /* 5b */
+#define SPM_ACK_CHK_HW_TARG_GROUP_SEL_2_LSB (1U << 21) /* 3b */
+/* SPM_ACK_CHK_TIMER_2 (0x10006000+0x94C) */
+#define SPM_ACK_CHK_TIMER_VAL_2_LSB (1U << 0) /* 16b */
+#define SPM_ACK_CHK_TIMER_2_LSB (1U << 16) /* 16b */
+/* SPM_ACK_CHK_STA_2 (0x10006000+0x950) */
+#define SPM_ACK_CHK_STA_2_LSB (1U << 0) /* 32b */
+/* SPM_ACK_CHK_SWINT_2 (0x10006000+0x954) */
+#define SPM_ACK_CHK_SWINT_EN_2_LSB (1U << 0) /* 32b */
+/* SPM_ACK_CHK_CON_3 (0x10006000+0x960) */
+#define SPM_ACK_CHK_SW_EN_3_LSB (1U << 0) /* 1b */
+#define SPM_ACK_CHK_CLR_ALL_3_LSB (1U << 1) /* 1b */
+#define SPM_ACK_CHK_CLR_TIMER_3_LSB (1U << 2) /* 1b */
+#define SPM_ACK_CHK_CLR_IRQ_3_LSB (1U << 3) /* 1b */
+#define SPM_ACK_CHK_STA_EN_3_LSB (1U << 4) /* 1b */
+#define SPM_ACK_CHK_WAKEUP_EN_3_LSB (1U << 5) /* 1b */
+#define SPM_ACK_CHK_WDT_EN_3_LSB (1U << 6) /* 1b */
+#define SPM_ACK_CHK_LOCK_PC_TRACE_EN_3_LSB (1U << 7) /* 1b */
+#define SPM_ACK_CHK_HW_EN_3_LSB (1U << 8) /* 1b */
+#define SPM_ACK_CHK_HW_MODE_3_LSB (1U << 9) /* 3b */
+#define SPM_ACK_CHK_FAIL_3_LSB (1U << 15) /* 1b */
+/* SPM_ACK_CHK_PC_3 (0x10006000+0x964) */
+#define SPM_ACK_CHK_HW_TRIG_PC_VAL_3_LSB (1U << 0) /* 16b */
+#define SPM_ACK_CHK_HW_TARG_PC_VAL_3_LSB (1U << 16) /* 16b */
+/* SPM_ACK_CHK_SEL_3 (0x10006000+0x968) */
+#define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_3_LSB (1U << 0) /* 5b */
+#define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_3_LSB (1U << 5) /* 3b */
+#define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_3_LSB (1U << 16) /* 5b */
+#define SPM_ACK_CHK_HW_TARG_GROUP_SEL_3_LSB (1U << 21) /* 3b */
+/* SPM_ACK_CHK_TIMER_3 (0x10006000+0x96C) */
+#define SPM_ACK_CHK_TIMER_VAL_3_LSB (1U << 0) /* 16b */
+#define SPM_ACK_CHK_TIMER_3_LSB (1U << 16) /* 16b */
+/* SPM_ACK_CHK_STA_3 (0x10006000+0x970) */
+#define SPM_ACK_CHK_STA_3_LSB (1U << 0) /* 32b */
+/* SPM_ACK_CHK_SWINT_3 (0x10006000+0x974) */
+#define SPM_ACK_CHK_SWINT_EN_3_LSB (1U << 0) /* 32b */
+/* SPM_COUNTER_0 (0x10006000+0x978) */
+#define SPM_COUNTER_VAL_0_LSB (1U << 0) /* 14b */
+#define SPM_COUNTER_OUT_0_LSB (1U << 14) /* 14b */
+#define SPM_COUNTER_EN_0_LSB (1U << 28) /* 1b */
+#define SPM_COUNTER_CLR_0_LSB (1U << 29) /* 1b */
+#define SPM_COUNTER_TIMEOUT_0_LSB (1U << 30) /* 1b */
+#define SPM_COUNTER_WAKEUP_EN_0_LSB (1U << 31) /* 1b */
+/* SPM_COUNTER_1 (0x10006000+0x97C) */
+#define SPM_COUNTER_VAL_1_LSB (1U << 0) /* 14b */
+#define SPM_COUNTER_OUT_1_LSB (1U << 14) /* 14b */
+#define SPM_COUNTER_EN_1_LSB (1U << 28) /* 1b */
+#define SPM_COUNTER_CLR_1_LSB (1U << 29) /* 1b */
+#define SPM_COUNTER_TIMEOUT_1_LSB (1U << 30) /* 1b */
+#define SPM_COUNTER_WAKEUP_EN_1_LSB (1U << 31) /* 1b */
+/* SPM_COUNTER_2 (0x10006000+0x980) */
+#define SPM_COUNTER_VAL_2_LSB (1U << 0) /* 14b */
+#define SPM_COUNTER_OUT_2_LSB (1U << 14) /* 14b */
+#define SPM_COUNTER_EN_2_LSB (1U << 28) /* 1b */
+#define SPM_COUNTER_CLR_2_LSB (1U << 29) /* 1b */
+#define SPM_COUNTER_TIMEOUT_2_LSB (1U << 30) /* 1b */
+#define SPM_COUNTER_WAKEUP_EN_2_LSB (1U << 31) /* 1b */
+/* SYS_TIMER_CON (0x10006000+0x98C) */
+#define SYS_TIMER_START_EN_LSB (1U << 0) /* 1b */
+#define SYS_TIMER_LATCH_EN_LSB (1U << 1) /* 1b */
+#define SYS_TIMER_ID_LSB (1U << 8) /* 8b */
+#define SYS_TIMER_VALID_LSB (1U << 31) /* 1b */
+/* RC_FSM_STA_0 (0x10006000+0xE00) */
+#define RC_FSM_STA_0_LSB (1U << 0) /* 32b */
+/* RC_CMD_STA_0 (0x10006000+0xE04) */
+#define RC_CMD_STA_0_LSB (1U << 0) /* 32b */
+/* RC_CMD_STA_1 (0x10006000+0xE08) */
+#define RC_CMD_STA_1_LSB (1U << 0) /* 32b */
+/* RC_SPI_STA_0 (0x10006000+0xE0C) */
+#define RC_SPI_STA_0_LSB (1U << 0) /* 32b */
+/* RC_PI_PO_STA_0 (0x10006000+0xE10) */
+#define RC_PI_PO_STA_0_LSB (1U << 0) /* 32b */
+/* RC_M00_REQ_STA_0 (0x10006000+0xE14) */
+#define RC_M00_REQ_STA_0_LSB (1U << 0) /* 32b */
+/* RC_M01_REQ_STA_0 (0x10006000+0xE1C) */
+#define RC_M01_REQ_STA_0_LSB (1U << 0) /* 32b */
+/* RC_M02_REQ_STA_0 (0x10006000+0xE20) */
+#define RC_M02_REQ_STA_0_LSB (1U << 0) /* 32b */
+/* RC_M03_REQ_STA_0 (0x10006000+0xE24) */
+#define RC_M03_REQ_STA_0_LSB (1U << 0) /* 32b */
+/* RC_M04_REQ_STA_0 (0x10006000+0xE28) */
+#define RC_M04_REQ_STA_0_LSB (1U << 0) /* 32b */
+/* RC_M05_REQ_STA_0 (0x10006000+0xE2C) */
+#define RC_M05_REQ_STA_0_LSB (1U << 0) /* 32b */
+/* RC_M06_REQ_STA_0 (0x10006000+0xE30) */
+#define RC_M06_REQ_STA_0_LSB (1U << 0) /* 32b */
+/* RC_M07_REQ_STA_0 (0x10006000+0xE34) */
+#define RC_M07_REQ_STA_0_LSB (1U << 0) /* 32b */
+/* RC_M08_REQ_STA_0 (0x10006000+0xE38) */
+#define RC_M08_REQ_STA_0_LSB (1U << 0) /* 32b */
+/* RC_M09_REQ_STA_0 (0x10006000+0xE3C) */
+#define RC_M09_REQ_STA_0_LSB (1U << 0) /* 32b */
+/* RC_M10_REQ_STA_0 (0x10006000+0xE40) */
+#define RC_M10_REQ_STA_0_LSB (1U << 0) /* 32b */
+/* RC_M11_REQ_STA_0 (0x10006000+0xE44) */
+#define RC_M11_REQ_STA_0_LSB (1U << 0) /* 32b */
+/* RC_M12_REQ_STA_0 (0x10006000+0xE48) */
+#define RC_M12_REQ_STA_0_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_STA_0 (0x10006000+0xE4C) */
+#define RC_DEBUG_STA_0_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_TRACE_0_LSB (0x10006000+0xE50) */
+#define RO_PMRC_TRACE_00_LSB_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_TRACE_0_MSB (0x10006000+0xE54) */
+#define RO_PMRC_TRACE_00_MSB_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_TRACE_1_LSB (0x10006000+0xE5C) */
+#define RO_PMRC_TRACE_01_LSB_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_TRACE_1_MSB (0x10006000+0xE60) */
+#define RO_PMRC_TRACE_01_MSB_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_TRACE_2_LSB (0x10006000+0xE64) */
+#define RO_PMRC_TRACE_02_LSB_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_TRACE_2_MSB (0x10006000+0xE6C) */
+#define RO_PMRC_TRACE_02_MSB_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_TRACE_3_LSB (0x10006000+0xE70) */
+#define RO_PMRC_TRACE_03_LSB_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_TRACE_3_MSB (0x10006000+0xE74) */
+#define RO_PMRC_TRACE_03_MSB_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_TRACE_4_LSB (0x10006000+0xE78) */
+#define RO_PMRC_TRACE_04_LSB_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_TRACE_4_MSB (0x10006000+0xE7C) */
+#define RO_PMRC_TRACE_04_MSB_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_TRACE_5_LSB (0x10006000+0xE80) */
+#define RO_PMRC_TRACE_05_LSB_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_TRACE_5_MSB (0x10006000+0xE84) */
+#define RO_PMRC_TRACE_05_MSB_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_TRACE_6_LSB (0x10006000+0xE88) */
+#define RO_PMRC_TRACE_06_LSB_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_TRACE_6_MSB (0x10006000+0xE8C) */
+#define RO_PMRC_TRACE_06_MSB_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_TRACE_7_LSB (0x10006000+0xE90) */
+#define RO_PMRC_TRACE_07_LSB_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_TRACE_7_MSB (0x10006000+0xE94) */
+#define RO_PMRC_TRACE_07_MSB_LSB (1U << 0) /* 32b */
+/* RC_SYS_TIMER_LATCH_0_LSB (0x10006000+0xE98) */
+#define RC_SYS_TIMER_LATCH_L_00_LSB (1U << 0) /* 32b */
+/* RC_SYS_TIMER_LATCH_0_MSB (0x10006000+0xE9C) */
+#define RC_SYS_TIMER_LATCH_H_00_LSB (1U << 0) /* 32b */
+/* RC_SYS_TIMER_LATCH_1_LSB (0x10006000+0xEA0) */
+#define RC_SYS_TIMER_LATCH_L_01_LSB (1U << 0) /* 32b */
+/* RC_SYS_TIMER_LATCH_1_MSB (0x10006000+0xEA4) */
+#define RC_SYS_TIMER_LATCH_H_01_LSB (1U << 0) /* 32b */
+/* RC_SYS_TIMER_LATCH_2_LSB (0x10006000+0xEA8) */
+#define RC_SYS_TIMER_LATCH_L_02_LSB (1U << 0) /* 32b */
+/* RC_SYS_TIMER_LATCH_2_MSB (0x10006000+0xEAC) */
+#define RC_SYS_TIMER_LATCH_H_02_LSB (1U << 0) /* 32b */
+/* RC_SYS_TIMER_LATCH_3_LSB (0x10006000+0xEB0) */
+#define RC_SYS_TIMER_LATCH_L_03_LSB (1U << 0) /* 32b */
+/* RC_SYS_TIMER_LATCH_3_MSB (0x10006000+0xEB4) */
+#define RC_SYS_TIMER_LATCH_H_03_LSB (1U << 0) /* 32b */
+/* RC_SYS_TIMER_LATCH_4_LSB (0x10006000+0xEB8) */
+#define RC_SYS_TIMER_LATCH_L_04_LSB (1U << 0) /* 32b */
+/* RC_SYS_TIMER_LATCH_4_MSB (0x10006000+0xEBC) */
+#define RC_SYS_TIMER_LATCH_H_04_LSB (1U << 0) /* 32b */
+/* RC_SYS_TIMER_LATCH_5_LSB (0x10006000+0xEC0) */
+#define RC_SYS_TIMER_LATCH_L_05_LSB (1U << 0) /* 32b */
+/* RC_SYS_TIMER_LATCH_5_MSB (0x10006000+0xEC4) */
+#define RC_SYS_TIMER_LATCH_H_05_LSB (1U << 0) /* 32b */
+/* RC_SYS_TIMER_LATCH_6_LSB (0x10006000+0xEC8) */
+#define RC_SYS_TIMER_LATCH_L_06_LSB (1U << 0) /* 32b */
+/* RC_SYS_TIMER_LATCH_6_MSB (0x10006000+0xECC) */
+#define RC_SYS_TIMER_LATCH_H_06_LSB (1U << 0) /* 32b */
+/* RC_SYS_TIMER_LATCH_7_LSB (0x10006000+0xED0) */
+#define RC_SYS_TIMER_LATCH_L_07_LSB (1U << 0) /* 32b */
+/* RC_SYS_TIMER_LATCH_7_MSB (0x10006000+0xED4) */
+#define RC_SYS_TIMER_LATCH_H_07_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_19 (0x10006000+0xED8) */
+#define PCM_WDT_LATCH_19_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_20 (0x10006000+0xEDC) */
+#define PCM_WDT_LATCH_20_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_21 (0x10006000+0xEE0) */
+#define PCM_WDT_LATCH_21_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_22 (0x10006000+0xEE4) */
+#define PCM_WDT_LATCH_22_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_23 (0x10006000+0xEE8) */
+#define PCM_WDT_LATCH_23_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_24 (0x10006000+0xEEC) */
+#define PCM_WDT_LATCH_24_LSB (1U << 0) /* 32b */
+/* PMSR_LAST_DAT (0x10006000+0xF00) */
+#define PMSR_LAST_DAT_LSB (1U << 0) /* 32b */
+/* PMSR_LAST_CNT (0x10006000+0xF04) */
+#define PMSR_LAST_CMD_LSB (1U << 0) /* 30b */
+#define PMSR_LAST_REQ_LSB (1U << 30) /* 1b */
+/* PMSR_LAST_ACK (0x10006000+0xF08) */
+#define PMSR_LAST_ACK_LSB (1U << 0) /* 1b */
+/* SPM_PMSR_SEL_CON0 (0x10006000+0xF10) */
+#define REG_PMSR_SIG_SEL_0_LSB (1U << 0) /* 8b */
+#define REG_PMSR_SIG_SEL_1_LSB (1U << 8) /* 8b */
+#define REG_PMSR_SIG_SEL_2_LSB (1U << 16) /* 8b */
+#define REG_PMSR_SIG_SEL_3_LSB (1U << 24) /* 8b */
+/* SPM_PMSR_SEL_CON1 (0x10006000+0xF14) */
+#define REG_PMSR_SIG_SEL_4_LSB (1U << 0) /* 8b */
+#define REG_PMSR_SIG_SEL_5_LSB (1U << 8) /* 8b */
+#define REG_PMSR_SIG_SEL_6_LSB (1U << 16) /* 8b */
+#define REG_PMSR_SIG_SEL_7_LSB (1U << 24) /* 8b */
+/* SPM_PMSR_SEL_CON2 (0x10006000+0xF18) */
+#define REG_PMSR_SIG_SEL_8_LSB (1U << 0) /* 8b */
+#define REG_PMSR_SIG_SEL_9_LSB (1U << 8) /* 8b */
+#define REG_PMSR_SIG_SEL_10_LSB (1U << 16) /* 8b */
+#define REG_PMSR_SIG_SEL_11_LSB (1U << 24) /* 8b */
+/* SPM_PMSR_SEL_CON3 (0x10006000+0xF1C) */
+#define REG_PMSR_SIG_SEL_12_LSB (1U << 0) /* 8b */
+#define REG_PMSR_SIG_SEL_13_LSB (1U << 8) /* 8b */
+#define REG_PMSR_SIG_SEL_14_LSB (1U << 16) /* 8b */
+#define REG_PMSR_SIG_SEL_15_LSB (1U << 24) /* 8b */
+/* SPM_PMSR_SEL_CON4 (0x10006000+0xF20) */
+#define REG_PMSR_SIG_SEL_16_LSB (1U << 0) /* 8b */
+#define REG_PMSR_SIG_SEL_17_LSB (1U << 8) /* 8b */
+#define REG_PMSR_SIG_SEL_18_LSB (1U << 16) /* 8b */
+#define REG_PMSR_SIG_SEL_19_LSB (1U << 24) /* 8b */
+/* SPM_PMSR_SEL_CON5 (0x10006000+0xF24) */
+#define REG_PMSR_SIG_SEL_20_LSB (1U << 0) /* 8b */
+#define REG_PMSR_SIG_SEL_21_LSB (1U << 8) /* 8b */
+#define REG_PMSR_SIG_SEL_22_LSB (1U << 16) /* 8b */
+#define REG_PMSR_SIG_SEL_23_LSB (1U << 24) /* 8b */
+/* SPM_PMSR_SEL_CON6 (0x10006000+0xF28) */
+#define REG_PMSR_SIG_SEL_24_LSB (1U << 0) /* 8b */
+#define REG_PMSR_SIG_SEL_25_LSB (1U << 8) /* 8b */
+#define REG_PMSR_SIG_SEL_26_LSB (1U << 16) /* 8b */
+#define REG_PMSR_SIG_SEL_27_LSB (1U << 24) /* 8b */
+/* SPM_PMSR_SEL_CON7 (0x10006000+0xF2C) */
+#define REG_PMSR_SIG_SEL_28_LSB (1U << 0) /* 8b */
+#define REG_PMSR_SIG_SEL_29_LSB (1U << 8) /* 8b */
+#define REG_PMSR_SIG_SEL_30_LSB (1U << 16) /* 8b */
+#define REG_PMSR_SIG_SEL_31_LSB (1U << 24) /* 8b */
+/* SPM_PMSR_SEL_CON8 (0x10006000+0xF30) */
+#define REG_PMSR_SIG_SEL_32_LSB (1U << 0) /* 8b */
+#define REG_PMSR_SIG_SEL_33_LSB (1U << 8) /* 8b */
+#define REG_PMSR_SIG_SEL_34_LSB (1U << 16) /* 8b */
+#define REG_PMSR_SIG_SEL_35_LSB (1U << 24) /* 8b */
+/* SPM_PMSR_SEL_CON9 (0x10006000+0xF34) */
+#define REG_PMSR_SIG_SEL_36_LSB (1U << 0) /* 8b */
+#define REG_PMSR_SIG_SEL_37_LSB (1U << 8) /* 8b */
+#define REG_PMSR_SIG_SEL_38_LSB (1U << 16) /* 8b */
+#define REG_PMSR_SIG_SEL_39_LSB (1U << 24) /* 8b */
+/* SPM_PMSR_SEL_CON10 (0x10006000+0xF3C) */
+#define REG_PMSR_SIG_SEL_40_LSB (1U << 0) /* 8b */
+#define REG_PMSR_SIG_SEL_41_LSB (1U << 8) /* 8b */
+#define REG_PMSR_SIG_SEL_42_LSB (1U << 16) /* 8b */
+#define REG_PMSR_SIG_SEL_43_LSB (1U << 24) /* 8b */
+/* SPM_PMSR_SEL_CON11 (0x10006000+0xF40) */
+#define REG_PMSR_SIG_SEL_44_LSB (1U << 0) /* 8b */
+#define REG_PMSR_SIG_SEL_45_LSB (1U << 8) /* 8b */
+#define REG_PMSR_SIG_SEL_46_LSB (1U << 16) /* 8b */
+#define REG_PMSR_SIG_SEL_47_LSB (1U << 24) /* 8b */
+/* SPM_PMSR_TIEMR_STA0 (0x10006000+0xFB8) */
+#define PMSR_TIMER_SET0_LSB (1U << 0) /* 32b */
+/* SPM_PMSR_TIEMR_STA1 (0x10006000+0xFBC) */
+#define PMSR_TIMER_SET1_LSB (1U << 0) /* 32b */
+/* SPM_PMSR_TIEMR_STA2 (0x10006000+0xFC0) */
+#define PMSR_TIMER_SET2_LSB (1U << 0) /* 32b */
+/* SPM_PMSR_GENERAL_CON0 (0x10006000+0xFC4) */
+#define PMSR_ENABLE_SET0_LSB (1U << 0) /* 1b */
+#define PMSR_ENABLE_SET1_LSB (1U << 1) /* 1b */
+#define PMSR_ENABLE_SET2_LSB (1U << 2) /* 1b */
+#define PMSR_IRQ_CLR_SET0_LSB (1U << 3) /* 1b */
+#define PMSR_IRQ_CLR_SET1_LSB (1U << 4) /* 1b */
+#define PMSR_IRQ_CLR_SET2_LSB (1U << 5) /* 1b */
+#define PMSR_SPEED_MODE_EN_SET0_LSB (1U << 6) /* 1b */
+#define PMSR_SPEED_MODE_EN_SET1_LSB (1U << 7) /* 1b */
+#define PMSR_SPEED_MODE_EN_SET2_LSB (1U << 8) /* 1b */
+#define PMSR_EVENT_CLR_SET0_LSB (1U << 9) /* 1b */
+#define PMSR_EVENT_CLR_SET1_LSB (1U << 10) /* 1b */
+#define PMSR_EVENT_CLR_SET2_LSB (1U << 11) /* 1b */
+#define REG_PMSR_IRQ_MASK_SET0_LSB (1U << 12) /* 1b */
+#define REG_PMSR_IRQ_MASK_SET1_LSB (1U << 13) /* 1b */
+#define REG_PMSR_IRQ_MASK_SET2_LSB (1U << 14) /* 1b */
+#define REG_PMSR_IRQ_WAKEUP_EVENT_MASK_SET0_LSB (1U << 15) /* 1b */
+#define REG_PMSR_IRQ_WAKEUP_EVENT_MASK_SET1_LSB (1U << 16) /* 1b */
+#define REG_PMSR_IRQ_WAKEUP_EVENT_MASK_SET2_LSB (1U << 17) /* 1b */
+#define PMSR_GEN_SW_RST_EN_LSB (1U << 18) /* 1b */
+#define PMSR_MODULE_ENABLE_LSB (1U << 19) /* 1b */
+#define PMSR_MODE_LSB (1U << 20) /* 2b */
+#define SPM_PMSR_GENERAL_CON0_PMSR_IRQ_B_SET0_LSB (1U << 29) /* 1b */
+#define SPM_PMSR_GENERAL_CON0_PMSR_IRQ_B_SET1_LSB (1U << 30) /* 1b */
+#define SPM_PMSR_GENERAL_CON0_PMSR_IRQ_B_SET2_LSB (1U << 31) /* 1b */
+/* SPM_PMSR_GENERAL_CON1 (0x10006000+0xFC8) */
+#define PMSR_COUNTER_THRES_LSB (1U << 0) /* 32b */
+/* SPM_PMSR_GENERAL_CON2 (0x10006000+0xFCC) */
+#define PMSR_DEBUG_IN_0_MASK_B_LSB (1U << 0) /* 32b */
+/* SPM_PMSR_GENERAL_CON3 (0x10006000+0xFD0) */
+#define PMSR_DEBUG_IN_1_MASK_B_LSB (1U << 0) /* 32b */
+/* SPM_PMSR_GENERAL_CON4 (0x10006000+0xFD4) */
+#define PMSR_DEBUG_IN_2_MASK_B_LSB (1U << 0) /* 32b */
+/* SPM_PMSR_GENERAL_CON5 (0x10006000+0xFD8) */
+#define PMSR_DEBUG_IN_3_MASK_B_LSB (1U << 0) /* 32b */
+/* SPM_PMSR_SW_RESET (0x10006000+0xFDC) */
+#define PMSR_SW_RST_EN_SET0_LSB (1U << 0) /* 1b */
+#define PMSR_SW_RST_EN_SET1_LSB (1U << 1) /* 1b */
+#define PMSR_SW_RST_EN_SET2_LSB (1U << 2) /* 1b */
+/* SPM_PMSR_MON_CON0 (0x10006000+0xFE0) */
+#define REG_PMSR_MON_TYPE_0_LSB (1U << 0) /* 2b */
+#define REG_PMSR_MON_TYPE_1_LSB (1U << 2) /* 2b */
+#define REG_PMSR_MON_TYPE_2_LSB (1U << 4) /* 2b */
+#define REG_PMSR_MON_TYPE_3_LSB (1U << 6) /* 2b */
+#define REG_PMSR_MON_TYPE_4_LSB (1U << 8) /* 2b */
+#define REG_PMSR_MON_TYPE_5_LSB (1U << 10) /* 2b */
+#define REG_PMSR_MON_TYPE_6_LSB (1U << 12) /* 2b */
+#define REG_PMSR_MON_TYPE_7_LSB (1U << 14) /* 2b */
+#define REG_PMSR_MON_TYPE_8_LSB (1U << 16) /* 2b */
+#define REG_PMSR_MON_TYPE_9_LSB (1U << 18) /* 2b */
+#define REG_PMSR_MON_TYPE_10_LSB (1U << 20) /* 2b */
+#define REG_PMSR_MON_TYPE_11_LSB (1U << 22) /* 2b */
+#define REG_PMSR_MON_TYPE_12_LSB (1U << 24) /* 2b */
+#define REG_PMSR_MON_TYPE_13_LSB (1U << 26) /* 2b */
+#define REG_PMSR_MON_TYPE_14_LSB (1U << 28) /* 2b */
+#define REG_PMSR_MON_TYPE_15_LSB (1U << 30) /* 2b */
+/* SPM_PMSR_MON_CON1 (0x10006000+0xFE4) */
+#define REG_PMSR_MON_TYPE_16_LSB (1U << 0) /* 2b */
+#define REG_PMSR_MON_TYPE_17_LSB (1U << 2) /* 2b */
+#define REG_PMSR_MON_TYPE_18_LSB (1U << 4) /* 2b */
+#define REG_PMSR_MON_TYPE_19_LSB (1U << 6) /* 2b */
+#define REG_PMSR_MON_TYPE_20_LSB (1U << 8) /* 2b */
+#define REG_PMSR_MON_TYPE_21_LSB (1U << 10) /* 2b */
+#define REG_PMSR_MON_TYPE_22_LSB (1U << 12) /* 2b */
+#define REG_PMSR_MON_TYPE_23_LSB (1U << 14) /* 2b */
+#define REG_PMSR_MON_TYPE_24_LSB (1U << 16) /* 2b */
+#define REG_PMSR_MON_TYPE_25_LSB (1U << 18) /* 2b */
+#define REG_PMSR_MON_TYPE_26_LSB (1U << 20) /* 2b */
+#define REG_PMSR_MON_TYPE_27_LSB (1U << 22) /* 2b */
+#define REG_PMSR_MON_TYPE_28_LSB (1U << 24) /* 2b */
+#define REG_PMSR_MON_TYPE_29_LSB (1U << 26) /* 2b */
+#define REG_PMSR_MON_TYPE_30_LSB (1U << 28) /* 2b */
+#define REG_PMSR_MON_TYPE_31_LSB (1U << 30) /* 2b */
+/* SPM_PMSR_MON_CON2 (0x10006000+0xFE8) */
+#define REG_PMSR_MON_TYPE_32_LSB (1U << 0) /* 2b */
+#define REG_PMSR_MON_TYPE_33_LSB (1U << 2) /* 2b */
+#define REG_PMSR_MON_TYPE_34_LSB (1U << 4) /* 2b */
+#define REG_PMSR_MON_TYPE_35_LSB (1U << 6) /* 2b */
+#define REG_PMSR_MON_TYPE_36_LSB (1U << 8) /* 2b */
+#define REG_PMSR_MON_TYPE_37_LSB (1U << 10) /* 2b */
+#define REG_PMSR_MON_TYPE_38_LSB (1U << 12) /* 2b */
+#define REG_PMSR_MON_TYPE_39_LSB (1U << 14) /* 2b */
+#define REG_PMSR_MON_TYPE_40_LSB (1U << 16) /* 2b */
+#define REG_PMSR_MON_TYPE_41_LSB (1U << 18) /* 2b */
+#define REG_PMSR_MON_TYPE_42_LSB (1U << 20) /* 2b */
+#define REG_PMSR_MON_TYPE_43_LSB (1U << 22) /* 2b */
+#define REG_PMSR_MON_TYPE_44_LSB (1U << 24) /* 2b */
+#define REG_PMSR_MON_TYPE_45_LSB (1U << 26) /* 2b */
+#define REG_PMSR_MON_TYPE_46_LSB (1U << 28) /* 2b */
+#define REG_PMSR_MON_TYPE_47_LSB (1U << 30) /* 2b */
+/* SPM_PMSR_LEN_CON0 (0x10006000+0xFEC) */
+#define REG_PMSR_WINDOW_LEN_SET0_LSB (1U << 0) /* 32b */
+/* SPM_PMSR_LEN_CON1 (0x10006000+0xFF0) */
+#define REG_PMSR_WINDOW_LEN_SET1_LSB (1U << 0) /* 32b */
+/* SPM_PMSR_LEN_CON2 (0x10006000+0xFF4) */
+#define REG_PMSR_WINDOW_LEN_SET2_LSB (1U << 0) /* 32b */
+
+#define SPM_PROJECT_CODE (0xb16)
+#define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16)
+
+#endif /* MT_SPM_REG_H */
diff --git a/plat/mediatek/drivers/spm/mt8188/mt_spm_suspend.c b/plat/mediatek/drivers/spm/mt8188/mt_spm_suspend.c
new file mode 100644
index 0000000..18047e6
--- /dev/null
+++ b/plat/mediatek/drivers/spm/mt8188/mt_spm_suspend.c
@@ -0,0 +1,429 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#ifndef MTK_PLAT_SPM_UART_UNSUPPORT
+#include <drivers/uart.h>
+#endif
+#include <lib/mmio.h>
+#ifndef MTK_PLAT_CIRQ_UNSUPPORT
+#include <mtk_cirq.h>
+#endif
+#include <constraints/mt_spm_rc_internal.h>
+#include <drivers/spm/mt_spm_resource_req.h>
+#include <lib/pm/mtk_pm.h>
+#include <lpm/mt_lp_api.h>
+#include <mt_spm.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_reg.h>
+#include <mt_spm_suspend.h>
+#include <pcm_def.h>
+
+#define SPM_SUSPEND_SLEEP_PCM_FLAG \
+ (SPM_FLAG_DISABLE_INFRA_PDN | \
+ SPM_FLAG_DISABLE_VCORE_DVS | \
+ SPM_FLAG_DISABLE_VCORE_DFS | \
+ SPM_FLAG_KEEP_CSYSPWRACK_HIGH | \
+ SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP | \
+ SPM_FLAG_SRAM_SLEEP_CTRL)
+
+#define SPM_SUSPEND_SLEEP_PCM_FLAG1 (SPM_FLAG1_DISABLE_PWRAP_CLK_SWITCH)
+
+#define SPM_SUSPEND_PCM_FLAG \
+ (SPM_FLAG_DISABLE_VCORE_DVS | \
+ SPM_FLAG_DISABLE_VCORE_DFS | \
+ SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP | \
+ SPM_FLAG_SRAM_SLEEP_CTRL)
+
+#define SPM_SUSPEND_PCM_FLAG1 (SPM_FLAG1_DISABLE_PWRAP_CLK_SWITCH)
+
+/* Suspend spm power control */
+#define __WAKE_SRC_FOR_SUSPEND_COMMON__ ( \
+ (R12_PCM_TIMER) | \
+ (R12_KP_IRQ_B) | \
+ (R12_APWDT_EVENT_B) | \
+ (R12_MSDC_WAKEUP_B) | \
+ (R12_EINT_EVENT_B) | \
+ (R12_SBD_INTR_WAKEUP_B) | \
+ (R12_SSPM2SPM_WAKEUP_B) | \
+ (R12_SCP2SPM_WAKEUP_B) | \
+ (R12_ADSP2SPM_WAKEUP_B) | \
+ (R12_USBX_CDSC_B) | \
+ (R12_USBX_POWERDWN_B) | \
+ (R12_SYS_TIMER_EVENT_B) | \
+ (R12_EINT_EVENT_SECURE_B) | \
+ (R12_ECE_INT_HDMI_B) | \
+ (R12_SYS_CIRQ_IRQ_B) | \
+ (R12_PCIE_WAKEUPEVENT_B) | \
+ (R12_SPM_CPU_WAKEUPEVENT_B) | \
+ (R12_APUSYS_WAKE_HOST_B))
+
+#if defined(CFG_MICROTRUST_TEE_SUPPORT)
+#define WAKE_SRC_FOR_SUSPEND (__WAKE_SRC_FOR_SUSPEND_COMMON__)
+#else
+#define WAKE_SRC_FOR_SUSPEND (__WAKE_SRC_FOR_SUSPEND_COMMON__ | R12_SEJ_EVENT_B)
+#endif
+
+static struct pwr_ctrl suspend_ctrl = {
+ .wake_src = WAKE_SRC_FOR_SUSPEND,
+
+ /* SPM_AP_STANDBY_CON */
+ /* [0] */
+ .reg_wfi_op = 0,
+ /* [1] */
+ .reg_wfi_type = 0,
+ /* [2] */
+ .reg_mp0_cputop_idle_mask = 0,
+ /* [3] */
+ .reg_mp1_cputop_idle_mask = 0,
+ /* [4] */
+ .reg_mcusys_idle_mask = 0,
+ /* [25] */
+ .reg_md_apsrc_1_sel = 0,
+ /* [26] */
+ .reg_md_apsrc_0_sel = 0,
+ /* [29] */
+ .reg_conn_apsrc_sel = 0,
+
+ /* SPM_SRC_REQ */
+ /* [0] */
+ .reg_spm_apsrc_req = 0,
+ /* [1] */
+ .reg_spm_f26m_req = 0,
+ /* [3] */
+ .reg_spm_infra_req = 0,
+ /* [4] */
+ .reg_spm_vrf18_req = 0,
+ /* [7] */
+ .reg_spm_ddr_en_req = 0,
+ /* [8] */
+ .reg_spm_dvfs_req = 0,
+ /* [9] */
+ .reg_spm_sw_mailbox_req = 0,
+ /* [10] */
+ .reg_spm_sspm_mailbox_req = 0,
+ /* [11] */
+ .reg_spm_adsp_mailbox_req = 0,
+ /* [12] */
+ .reg_spm_scp_mailbox_req = 0,
+
+ /* SPM_SRC_MASK */
+ /* [0] */
+ .reg_sspm_srcclkena_0_mask_b = 1,
+ /* [1] */
+ .reg_sspm_infra_req_0_mask_b = 1,
+ /* [2] */
+ .reg_sspm_apsrc_req_0_mask_b = 0,
+ /* [3] */
+ .reg_sspm_vrf18_req_0_mask_b = 0,
+ /* [4] */
+ .reg_sspm_ddr_en_0_mask_b = 0,
+ /* [5] */
+ .reg_scp_srcclkena_mask_b = 1,
+ /* [6] */
+ .reg_scp_infra_req_mask_b = 1,
+ /* [7] */
+ .reg_scp_apsrc_req_mask_b = 1,
+ /* [8] */
+ .reg_scp_vrf18_req_mask_b = 1,
+ /* [9] */
+ .reg_scp_ddr_en_mask_b = 1,
+ /* [10] */
+ .reg_audio_dsp_srcclkena_mask_b = 1,
+ /* [11] */
+ .reg_audio_dsp_infra_req_mask_b = 1,
+ /* [12] */
+ .reg_audio_dsp_apsrc_req_mask_b = 1,
+ /* [13] */
+ .reg_audio_dsp_vrf18_req_mask_b = 1,
+ /* [14] */
+ .reg_audio_dsp_ddr_en_mask_b = 1,
+ /* [15] */
+ .reg_apu_srcclkena_mask_b = 1,
+ /* [16] */
+ .reg_apu_infra_req_mask_b = 1,
+ /* [17] */
+ .reg_apu_apsrc_req_mask_b = 0,
+ /* [18] */
+ .reg_apu_vrf18_req_mask_b = 1,
+ /* [19] */
+ .reg_apu_ddr_en_mask_b = 1,
+ /* [20] */
+ .reg_cpueb_srcclkena_mask_b = 1,
+ /* [21] */
+ .reg_cpueb_infra_req_mask_b = 1,
+ /* [22] */
+ .reg_cpueb_apsrc_req_mask_b = 1,
+ /* [23] */
+ .reg_cpueb_vrf18_req_mask_b = 1,
+ /* [24] */
+ .reg_cpueb_ddr_en_mask_b = 1,
+ /* [25] */
+ .reg_bak_psri_srcclkena_mask_b = 0,
+ /* [26] */
+ .reg_bak_psri_infra_req_mask_b = 0,
+ /* [27] */
+ .reg_bak_psri_apsrc_req_mask_b = 0,
+ /* [28] */
+ .reg_bak_psri_vrf18_req_mask_b = 0,
+ /* [29] */
+ .reg_bak_psri_ddr_en_mask_b = 0,
+ /* [30] */
+ .reg_cam_ddren_req_mask_b = 0,
+ /* [31] */
+ .reg_img_ddren_req_mask_b = 0,
+
+ /* SPM_SRC2_MASK */
+ /* [0] */
+ .reg_msdc0_srcclkena_mask_b = 1,
+ /* [1] */
+ .reg_msdc0_infra_req_mask_b = 1,
+ /* [2] */
+ .reg_msdc0_apsrc_req_mask_b = 1,
+ /* [3] */
+ .reg_msdc0_vrf18_req_mask_b = 1,
+ /* [4] */
+ .reg_msdc0_ddr_en_mask_b = 1,
+ /* [5] */
+ .reg_msdc1_srcclkena_mask_b = 1,
+ /* [6] */
+ .reg_msdc1_infra_req_mask_b = 1,
+ /* [7] */
+ .reg_msdc1_apsrc_req_mask_b = 1,
+ /* [8] */
+ .reg_msdc1_vrf18_req_mask_b = 1,
+ /* [9] */
+ .reg_msdc1_ddr_en_mask_b = 1,
+ /* [10] */
+ .reg_msdc2_srcclkena_mask_b = 1,
+ /* [11] */
+ .reg_msdc2_infra_req_mask_b = 1,
+ /* [12] */
+ .reg_msdc2_apsrc_req_mask_b = 1,
+ /* [13] */
+ .reg_msdc2_vrf18_req_mask_b = 1,
+ /* [14] */
+ .reg_msdc2_ddr_en_mask_b = 1,
+ /* [15] */
+ .reg_ufs_srcclkena_mask_b = 1,
+ /* [16] */
+ .reg_ufs_infra_req_mask_b = 1,
+ /* [17] */
+ .reg_ufs_apsrc_req_mask_b = 1,
+ /* [18] */
+ .reg_ufs_vrf18_req_mask_b = 1,
+ /* [19] */
+ .reg_ufs_ddr_en_mask_b = 1,
+ /* [20] */
+ .reg_usb_srcclkena_mask_b = 1,
+ /* [21] */
+ .reg_usb_infra_req_mask_b = 1,
+ /* [22] */
+ .reg_usb_apsrc_req_mask_b = 1,
+ /* [23] */
+ .reg_usb_vrf18_req_mask_b = 1,
+ /* [24] */
+ .reg_usb_ddr_en_mask_b = 1,
+ /* [25] */
+ .reg_pextp_p0_srcclkena_mask_b = 1,
+ /* [26] */
+ .reg_pextp_p0_infra_req_mask_b = 1,
+ /* [27] */
+ .reg_pextp_p0_apsrc_req_mask_b = 1,
+ /* [28] */
+ .reg_pextp_p0_vrf18_req_mask_b = 1,
+ /* [29] */
+ .reg_pextp_p0_ddr_en_mask_b = 1,
+
+ /* SPM_SRC3_MASK */
+ /* [0] */
+ .reg_pextp_p1_srcclkena_mask_b = 1,
+ /* [1] */
+ .reg_pextp_p1_infra_req_mask_b = 1,
+ /* [2] */
+ .reg_pextp_p1_apsrc_req_mask_b = 1,
+ /* [3] */
+ .reg_pextp_p1_vrf18_req_mask_b = 1,
+ /* [4] */
+ .reg_pextp_p1_ddr_en_mask_b = 1,
+ /* [5] */
+ .reg_gce0_infra_req_mask_b = 1,
+ /* [6] */
+ .reg_gce0_apsrc_req_mask_b = 1,
+ /* [7] */
+ .reg_gce0_vrf18_req_mask_b = 1,
+ /* [8] */
+ .reg_gce0_ddr_en_mask_b = 1,
+ /* [9] */
+ .reg_gce1_infra_req_mask_b = 1,
+ /* [10] */
+ .reg_gce1_apsrc_req_mask_b = 1,
+ /* [11] */
+ .reg_gce1_vrf18_req_mask_b = 1,
+ /* [12] */
+ .reg_gce1_ddr_en_mask_b = 1,
+ /* [13] */
+ .reg_spm_srcclkena_reserved_mask_b = 1,
+ /* [14] */
+ .reg_spm_infra_req_reserved_mask_b = 1,
+ /* [15] */
+ .reg_spm_apsrc_req_reserved_mask_b = 1,
+ /* [16] */
+ .reg_spm_vrf18_req_reserved_mask_b = 1,
+ /* [17] */
+ .reg_spm_ddr_en_reserved_mask_b = 1,
+ /* [18] */
+ .reg_disp0_apsrc_req_mask_b = 1,
+ /* [19] */
+ .reg_disp0_ddr_en_mask_b = 1,
+ /* [20] */
+ .reg_disp1_apsrc_req_mask_b = 1,
+ /* [21] */
+ .reg_disp1_ddr_en_mask_b = 1,
+ /* [22] */
+ .reg_disp2_apsrc_req_mask_b = 1,
+ /* [23] */
+ .reg_disp2_ddr_en_mask_b = 1,
+ /* [24] */
+ .reg_disp3_apsrc_req_mask_b = 1,
+ /* [25] */
+ .reg_disp3_ddr_en_mask_b = 1,
+ /* [26] */
+ .reg_infrasys_apsrc_req_mask_b = 0,
+ /* [27] */
+ .reg_infrasys_ddr_en_mask_b = 1,
+
+ /* [28] */
+ .reg_cg_check_srcclkena_mask_b = 1,
+ /* [29] */
+ .reg_cg_check_apsrc_req_mask_b = 1,
+ /* [30] */
+ .reg_cg_check_vrf18_req_mask_b = 1,
+ /* [31] */
+ .reg_cg_check_ddr_en_mask_b = 1,
+
+ /* SPM_SRC4_MASK */
+ /* [8:0] */
+ .reg_mcusys_merge_apsrc_req_mask_b = 0,
+ /* [17:9] */
+ .reg_mcusys_merge_ddr_en_mask_b = 0,
+ /* [19:18] */
+ .reg_dramc_md32_infra_req_mask_b = 3,
+ /* [21:20] */
+ .reg_dramc_md32_vrf18_req_mask_b = 3,
+ /* [23:22] */
+ .reg_dramc_md32_ddr_en_mask_b = 0,
+ /* [24] */
+ .reg_dvfsrc_event_trigger_mask_b = 1,
+
+ /* SPM_WAKEUP_EVENT_MASK2 */
+ /* [3:0] */
+ .reg_sc_sw2spm_wakeup_mask_b = 0,
+ /* [4] */
+ .reg_sc_adsp2spm_wakeup_mask_b = 0,
+ /* [8:5] */
+ .reg_sc_sspm2spm_wakeup_mask_b = 0,
+ /* [9] */
+ .reg_sc_scp2spm_wakeup_mask_b = 0,
+ /* [10] */
+ .reg_csyspwrup_ack_mask = 0,
+ /* [11] */
+ .reg_csyspwrup_req_mask = 1,
+
+ /* SPM_WAKEUP_EVENT_MASK */
+ /* [31:0] */
+ .reg_wakeup_event_mask = 0xC1382213,
+
+ /* SPM_WAKEUP_EVENT_EXT_MASK */
+ /* [31:0] */
+ .reg_ext_wakeup_event_mask = 0xFFFFFFFF,
+
+ /*sw flag setting */
+ .pcm_flags = SPM_SUSPEND_PCM_FLAG,
+ .pcm_flags1 = SPM_SUSPEND_PCM_FLAG1,
+};
+
+struct spm_lp_scen __spm_suspend = {
+ .pwrctrl = &suspend_ctrl,
+};
+
+int mt_spm_suspend_mode_set(int mode, void *prv)
+{
+ if (mode == MT_SPM_SUSPEND_SLEEP) {
+ suspend_ctrl.pcm_flags = SPM_SUSPEND_SLEEP_PCM_FLAG;
+ suspend_ctrl.pcm_flags1 = SPM_SUSPEND_SLEEP_PCM_FLAG1;
+ } else {
+ suspend_ctrl.pcm_flags = SPM_SUSPEND_PCM_FLAG;
+ suspend_ctrl.pcm_flags1 = SPM_SUSPEND_PCM_FLAG1;
+ }
+ return 0;
+}
+
+int mt_spm_suspend_enter(int state_id, unsigned int ext_opand, unsigned int reosuce_req)
+{
+ int ret = 0;
+
+ /* if FMAudio, ADSP is active, change to sleep suspend mode */
+ if ((ext_opand & MT_SPM_EX_OP_SET_SUSPEND_MODE) != 0U) {
+ mt_spm_suspend_mode_set(MT_SPM_SUSPEND_SLEEP, NULL);
+ }
+
+ if ((ext_opand & MT_SPM_EX_OP_PERI_ON) != 0U) {
+ suspend_ctrl.pcm_flags |= SPM_FLAG_PERI_ON_IN_SUSPEND;
+ } else {
+ suspend_ctrl.pcm_flags &= ~SPM_FLAG_PERI_ON_IN_SUSPEND;
+ }
+
+ if ((ext_opand & MT_SPM_EX_OP_INFRA_ON) != 0U) {
+ suspend_ctrl.pcm_flags |= SPM_FLAG_DISABLE_INFRA_PDN;
+ } else {
+ suspend_ctrl.pcm_flags &= ~SPM_FLAG_DISABLE_INFRA_PDN;
+ }
+
+#ifndef MTK_PLAT_SPM_UART_UNSUPPORT
+ /* Notify UART to sleep */
+ mtk_uart_save();
+#endif
+
+ ret = spm_conservation(state_id, ext_opand, &__spm_suspend, reosuce_req);
+ if (ret == 0) {
+ struct mt_lp_publish_event event = {
+ .id = MT_LPM_PUBEVENTS_SYS_POWER_OFF,
+ .val.u32 = 0U,
+ };
+
+ MT_LP_SUSPEND_PUBLISH_EVENT(&event);
+ }
+ return ret;
+}
+
+void mt_spm_suspend_resume(int state_id, unsigned int ext_opand, struct wake_status **status)
+{
+ struct mt_lp_publish_event event = {
+ .id = MT_LPM_PUBEVENTS_SYS_POWER_ON,
+ .val.u32 = 0U,
+ };
+
+ struct wake_status *st = NULL;
+
+ spm_conservation_finish(state_id, ext_opand, &__spm_suspend, &st);
+
+#ifndef MTK_PLAT_SPM_UART_UNSUPPORT
+ /* Notify UART to wakeup */
+ mtk_uart_restore();
+#endif
+
+ /* If FMAudio, ADSP is active, change back to suspend mode and counting in resume */
+ if ((ext_opand & MT_SPM_EX_OP_SET_SUSPEND_MODE) != 0U) {
+ mt_spm_suspend_mode_set(MT_SPM_SUSPEND_SYSTEM_PDN, NULL);
+ }
+
+ if (status != NULL) {
+ *status = st;
+ }
+ MT_LP_SUSPEND_PUBLISH_EVENT(&event);
+}
diff --git a/plat/mediatek/drivers/spm/mt8188/mt_spm_suspend.h b/plat/mediatek/drivers/spm/mt8188/mt_spm_suspend.h
new file mode 100644
index 0000000..37f621d
--- /dev/null
+++ b/plat/mediatek/drivers/spm/mt8188/mt_spm_suspend.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_SUSPEND_H
+#define MT_SPM_SUSPEND_H
+
+#include <mt_spm_internal.h>
+
+struct suspend_dbg_ctrl {
+ uint32_t sleep_suspend_cnt;
+};
+
+enum mt_spm_suspend_mode {
+ MT_SPM_SUSPEND_SYSTEM_PDN = 0,
+ MT_SPM_SUSPEND_SLEEP,
+};
+
+int mt_spm_suspend_mode_set(int mode, void *prv);
+int mt_spm_suspend_enter(int state_id, unsigned int ext_opand, unsigned int reosuce_req);
+void mt_spm_suspend_resume(int state_id, unsigned int ext_opand, struct wake_status **status);
+
+#endif
diff --git a/plat/mediatek/drivers/spm/mt8188/pcm_def.h b/plat/mediatek/drivers/spm/mt8188/pcm_def.h
new file mode 100644
index 0000000..976c167
--- /dev/null
+++ b/plat/mediatek/drivers/spm/mt8188/pcm_def.h
@@ -0,0 +1,180 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PCM_DEF_H
+#define PCM_DEF_H
+
+/*
+ * Auto generated by DE, please DO NOT modify this file directly.
+ */
+
+/* --- R0 Define --- */
+#define R0_SC_26M_CK_OFF (1U << 0)
+#define R0_SC_TX_TRACK_RETRY_EN (1U << 1)
+#define R0_SC_MEM_CK_OFF (1U << 2)
+#define R0_SC_AXI_CK_OFF (1U << 3)
+#define R0_SC_DR_SRAM_LOAD (1U << 4)
+#define R0_SC_MD26M_CK_OFF (1U << 5)
+#define R0_SC_DPY_MODE_SW (1U << 6)
+#define R0_SC_DMSUS_OFF (1U << 7)
+#define R0_SC_DPY_2ND_DLL_EN (1U << 8)
+#define R0_SC_DR_SRAM_RESTORE (1U << 9)
+#define R0_SC_MPLLOUT_OFF (1U << 10)
+#define R0_SC_TX_TRACKING_DIS (1U << 11)
+#define R0_SC_DPY_DLL_EN (1U << 12)
+#define R0_SC_DPY_DLL_CK_EN (1U << 13)
+#define R0_SC_DPY_VREF_EN (1U << 14)
+#define R0_SC_PHYPLL_EN (1U << 15)
+#define R0_SC_DDRPHY_FB_CK_EN (1U << 16)
+#define R0_SC_DPY_BCLK_ENABLE (1U << 17)
+#define R0_SC_MPLL_OFF (1U << 18)
+#define R0_SC_SHU_RESTORE (1U << 19)
+#define R0_SC_CKSQ0_OFF (1U << 20)
+#define R0_SC_DR_SHU_LEVEL_SRAM_LATCH (1U << 21)
+#define R0_SC_DR_SHU_EN (1U << 22)
+#define R0_SC_DPHY_PRECAL_UP (1U << 23)
+#define R0_SC_MPLL_S_OFF (1U << 24)
+#define R0_SC_DPHY_RXDLY_TRACKING_EN (1U << 25)
+#define R0_SC_PHYPLL_SHU_EN (1U << 26)
+#define R0_SC_PHYPLL2_SHU_EN (1U << 27)
+#define R0_SC_PHYPLL_MODE_SW (1U << 28)
+#define R0_SC_PHYPLL2_MODE_SW (1U << 29)
+#define R0_SC_DR_SHU_LEVEL0 (1U << 30)
+#define R0_SC_DR_SHU_LEVEL1 (1U << 31)
+/* --- R7 Define --- */
+#define R7_PWRAP_SLEEP_REQ (1U << 0)
+#define R7_EMI_CLK_OFF_REQ (1U << 1)
+#define R7_PCM_BUS_PROTECT_REQ (1U << 2)
+#define R7_SPM_CK_UPDATE (1U << 3)
+#define R7_SPM_CK_SEL0 (1U << 4)
+#define R7_SPM_CK_SEL1 (1U << 5)
+#define R7_SPM_LEAVE_DEEPIDLE_REQ (1U << 6)
+#define R7_SC_FHC_PAUSE_MPLL (1U << 7)
+#define R7_SC_26M_CK_SEL (1U << 8)
+#define R7_PCM_TIMER_SET (1U << 9)
+#define R7_PCM_TIMER_CLR (1U << 10)
+#define R7_SPM_LEAVE_SUSPEND_REQ (1U << 11)
+#define R7_CSYSPWRUPACK (1U << 12)
+#define R7_PCM_IM_SLP_EN (1U << 13)
+#define R7_SRCCLKENO0 (1U << 14)
+#define R7_FORCE_DDR_EN_WAKE (1U << 15)
+#define R7_SPM_APSRC_INTERNAL_ACK (1U << 16)
+#define R7_CPU_SYS_TIMER_CLK_SEL (1U << 17)
+#define R7_SC_AXI_DCM_DIS (1U << 18)
+#define R7_SC_FHC_PAUSE_MEM (1U << 19)
+#define R7_SC_FHC_PAUSE_MAIN (1U << 20)
+#define R7_SRCCLKENO1 (1U << 21)
+#define R7_PCM_WDT_KICK_P (1U << 22)
+#define R7_SPM2EMI_S1_MODE_ASYNC (1U << 23)
+#define R7_SC_DDR_PST_REQ_PCM (1U << 24)
+#define R7_SC_DDR_PST_ABORT_REQ_PCM (1U << 25)
+#define R7_PMIC_IRQ_REQ_EN (1U << 26)
+#define R7_FORCE_F26M_WAKE (1U << 27)
+#define R7_FORCE_APSRC_WAKE (1U << 28)
+#define R7_FORCE_INFRA_WAKE (1U << 29)
+#define R7_FORCE_VRF18_WAKE (1U << 30)
+#define R7_SPM_DDR_EN_INTERNAL_ACK (1U << 31)
+/* --- R12 Define --- */
+#define R12_PCM_TIMER (1U << 0)
+#define R12_TWAM_IRQ_B (1U << 1)
+#define R12_KP_IRQ_B (1U << 2)
+#define R12_APWDT_EVENT_B (1U << 3)
+#define R12_APXGPT1_EVENT_B (1U << 4)
+#define R12_MSDC_WAKEUP_B (1U << 5)
+#define R12_EINT_EVENT_B (1U << 6)
+#define R12_NOT_USED_7 (1U << 7)
+#define R12_SBD_INTR_WAKEUP_B (1U << 8)
+#define R12_LOWBATTERY_IRQ_B (1U << 9)
+#define R12_SSPM2SPM_WAKEUP_B (1U << 10)
+#define R12_SCP2SPM_WAKEUP_B (1U << 11)
+#define R12_ADSP2SPM_WAKEUP_B (1U << 12)
+#define R12_PCM_WDT_WAKEUP_B (1U << 13)
+#define R12_USBX_CDSC_B (1U << 14)
+#define R12_USBX_POWERDWN_B (1U << 15)
+#define R12_SYS_TIMER_EVENT_B (1U << 16)
+#define R12_EINT_EVENT_SECURE_B (1U << 17)
+#define R12_ECE_INT_HDMI_B (1U << 18)
+#define R12_I2C_IRQ_B (1U << 19)
+#define R12_AFE_IRQ_MCU_B (1U << 20)
+#define R12_THERM_CTRL_EVENT_B (1U << 21)
+#define R12_SYS_CIRQ_IRQ_B (1U << 22)
+#define R12_NOT_USED_23 (1U << 23)
+#define R12_CSYSPWREQ_B (1U << 24)
+#define R12_NOT_USED_25 (1U << 25)
+#define R12_PCIE_WAKEUPEVENT_B (1U << 26)
+#define R12_SEJ_EVENT_B (1U << 27)
+#define R12_SPM_CPU_WAKEUPEVENT_B (1U << 28)
+#define R12_APUSYS_WAKE_HOST_B (1U << 29)
+#define R12_NOT_USED_30 (1U << 30)
+#define R12_NOT_USED_31 (1U << 31)
+/* --- R12ext Define --- */
+#define R12EXT_26M_WAKE (1U << 0)
+#define R12EXT_26M_SLEEP (1U << 1)
+#define R12EXT_INFRA_WAKE (1U << 2)
+#define R12EXT_INFRA_SLEEP (1U << 3)
+#define R12EXT_APSRC_WAKE (1U << 4)
+#define R12EXT_APSRC_SLEEP (1U << 5)
+#define R12EXT_VRF18_WAKE (1U << 6)
+#define R12EXT_VRF18_SLEEP (1U << 7)
+#define R12EXT_DVFS_WAKE (1U << 8)
+#define R12EXT_DDREN_WAKE (1U << 9)
+#define R12EXT_DDREN_SLEEP (1U << 10)
+#define R12EXT_MCU_PM_WFI (1U << 11)
+#define R12EXT_SSPM_IDLE (1U << 12)
+#define R12EXT_CONN_SRCCLKENB (1U << 13)
+#define R12EXT_DRAMC_SSPM_WFI_MERGE (1U << 14)
+#define R12EXT_SW_MAILBOX_WAKE (1U << 15)
+#define R12EXT_SSPM_MAILBOX_WAKE (1U << 16)
+#define R12EXT_ADSP_MAILBOX_WAKE (1U << 17)
+#define R12EXT_SCP_MAILBOX_WAKE (1U << 18)
+#define R12EXT_SPM_LEAVE_SUSPEND_ACK (1U << 19)
+#define R12EXT_SPM_LEAVE_DEEPIDLE_ACK (1U << 20)
+#define R12EXT_VS1_TRIGGER (1U << 21)
+#define R12EXT_VS2_TRIGGER (1U << 22)
+#define R12EXT_COROSS_REQ_APU (1U << 23)
+#define R12EXT_CROSS_REQ_L3 (1U << 24)
+#define R12EXT_DDR_PST_ACK (1U << 25)
+#define R12EXT_BIT26 (1U << 26)
+#define R12EXT_BIT27 (1U << 27)
+#define R12EXT_BIT28 (1U << 28)
+#define R12EXT_BIT29 (1U << 29)
+#define R12EXT_BIT30 (1U << 30)
+#define R12EXT_BIT31 (1U << 31)
+/* --- R13 Define --- */
+#define R13_SRCCLKENI0 (1U << 0)
+#define R13_SRCCLKENI1 (1U << 1)
+#define R13_MD_SRCCLKENA_0 (1U << 2)
+#define R13_MD_APSRC_REQ_0 (1U << 3)
+#define R13_CONN_DDR_EN (1U << 4)
+#define R13_MD_SRCCLKENA_1 (1U << 5)
+#define R13_SSPM_SRCCLKENA (1U << 6)
+#define R13_SSPM_APSRC_REQ (1U << 7)
+#define R13_MD1_STATE (1U << 8)
+#define R13_BIT9 (1U << 9)
+#define R13_MM_STATE (1U << 10)
+#define R13_SSPM_STATE (1U << 11)
+#define R13_MD_DDR_EN_0 (1U << 12)
+#define R13_CONN_STATE (1U << 13)
+#define R13_CONN_SRCCLKENA (1U << 14)
+#define R13_CONN_APSRC_REQ (1U << 15)
+#define R13_SC_DDR_PST_ACK_ALL (1U << 16)
+#define R13_SC_DDR_PST_ABORT_ACK_ALL (1U << 17)
+#define R13_SCP_STATE (1U << 18)
+#define R13_CSYSPWRUPREQ (1U << 19)
+#define R13_PWRAP_SLEEP_ACK (1U << 20)
+#define R13_SC_EMI_CLK_OFF_ACK_ALL (1U << 21)
+#define R13_AUDIO_DSP_STATE (1U << 22)
+#define R13_SC_DMDRAMCSHU_ACK_ALL (1U << 23)
+#define R13_CONN_SRCCLKENB (1U << 24)
+#define R13_SC_DR_SRAM_LOAD_ACK_ALL (1U << 25)
+#define R13_SUBSYS_IDLE_SIGNALS0 (1U << 26)
+#define R13_DVFS_STATE (1U << 27)
+#define R13_SC_DR_SRAM_PLL_LOAD_ACK_ALL (1U << 28)
+#define R13_SC_DR_SRAM_RESTORE_ACK_ALL (1U << 29)
+#define R13_MD_VRF18_REQ_0 (1U << 30)
+#define R13_DDR_EN_STATE (1U << 31)
+
+#endif /* PCM_DEF_H */
diff --git a/plat/mediatek/drivers/spm/mt8188/rules.mk b/plat/mediatek/drivers/spm/mt8188/rules.mk
new file mode 100644
index 0000000..a04e91f
--- /dev/null
+++ b/plat/mediatek/drivers/spm/mt8188/rules.mk
@@ -0,0 +1,64 @@
+#
+# Copyright (c) 2023, MediaTek Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+LOCAL_DIR := $(call GET_LOCAL_DIR)
+MODULE := spm_${MTK_SOC}
+
+define GET_UPPER_DIR
+$(shell dirname ${LOCAL_DIR})
+endef
+UPPER_DIR := $(call GET_UPPER_DIR)
+
+MT_SPM_FEATURE_SUPPORT := y
+MT_SPM_CIRQ_FEATURE_SUPPORT := n
+MT_SPMFW_SPM_SRAM_SLEEP_SUPPORT := n
+MT_SPM_SSPM_NOTIFIER_SUPPORT := y
+MT_SPM_UART_SUSPEND_SUPPORT := n
+MT_SPM_RGU_SUPPORT := n
+
+LOCAL_SRCS-y := ${LOCAL_DIR}/mt_spm.c
+LOCAL_SRCS-y += ${LOCAL_DIR}/mt_spm_conservation.c
+LOCAL_SRCS-y += ${LOCAL_DIR}/mt_spm_internal.c
+LOCAL_SRCS-y += ${LOCAL_DIR}/mt_spm_pmic_wrap.c
+LOCAL_SRCS-${MT_SPM_FEATURE_SUPPORT} += ${LOCAL_DIR}/mt_spm_cond.c
+LOCAL_SRCS-${MT_SPM_FEATURE_SUPPORT} += ${LOCAL_DIR}/mt_spm_idle.c
+LOCAL_SRCS-${MT_SPM_FEATURE_SUPPORT} += ${LOCAL_DIR}/mt_spm_suspend.c
+LOCAL_SRCS-${MT_SPM_FEATURE_SUPPORT} += ${LOCAL_DIR}/constraints/mt_spm_rc_api.c
+LOCAL_SRCS-${MT_SPM_FEATURE_SUPPORT} += ${LOCAL_DIR}/constraints/mt_spm_rc_bus26m.c
+LOCAL_SRCS-${MT_SPM_FEATURE_SUPPORT} += ${LOCAL_DIR}/constraints/mt_spm_rc_cpu_buck_ldo.c
+LOCAL_SRCS-${MT_SPM_FEATURE_SUPPORT} += ${LOCAL_DIR}/constraints/mt_spm_rc_dram.c
+LOCAL_SRCS-${MT_SPM_FEATURE_SUPPORT} += ${LOCAL_DIR}/constraints/mt_spm_rc_syspll.c
+LOCAL_SRCS-${MT_SPM_SSPM_NOTIFIER_SUPPORT} += ${UPPER_DIR}/version/notifier/v1/mt_spm_sspm_notifier.c
+
+ifeq (${MT_SPM_FEATURE_SUPPORT},n)
+$(eval $(call add_define,MTK_PLAT_SPM_UNSUPPORT))
+endif
+
+ifeq (${MT_SPM_CIRQ_FEATURE_SUPPORT},n)
+$(eval $(call add_define,MTK_PLAT_CIRQ_UNSUPPORT))
+endif
+
+ifeq (${MT_SPMFW_SPM_SRAM_SLEEP_SUPPORT},n)
+$(eval $(call add_define,MTK_PLAT_SPM_SRAM_SLP_UNSUPPORT))
+endif
+
+ifeq (${MT_SPM_SSPM_NOTIFIER_SUPPORT},n)
+$(eval $(call add_define,MTK_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT))
+endif
+
+ifeq (${MT_SPM_UART_SUSPEND_SUPPORT},n)
+$(eval $(call add_define,MTK_PLAT_SPM_UART_UNSUPPORT))
+endif
+
+ifeq ($(MTK_VOLTAGE_BIN_VCORE),y)
+$(eval $(call add_define,MTK_VOLTAGE_BIN_VCORE_SUPPORT))
+endif
+
+ifeq ($(MT_SPM_RGU_SUPPORT),n)
+$(eval $(call add_define,MTK_PLAT_SPM_RGU_UNSUPPORT))
+endif
+
+$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))
diff --git a/plat/mediatek/drivers/spm/mt8188/sleep_def.h b/plat/mediatek/drivers/spm/mt8188/sleep_def.h
new file mode 100644
index 0000000..09a575b
--- /dev/null
+++ b/plat/mediatek/drivers/spm/mt8188/sleep_def.h
@@ -0,0 +1,154 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SLEEP_DEF_H
+#define SLEEP_DEF_H
+
+/*
+ * Auto generated by DE, please DO NOT modify this file directly.
+ */
+
+/* --- SPM Flag Define --- */
+#define SPM_FLAG_DISABLE_CPU_PDN (1U << 0)
+#define SPM_FLAG_DISABLE_INFRA_PDN (1U << 1)
+#define SPM_FLAG_DISABLE_DDRPHY_PDN (1U << 2)
+#define SPM_FLAG_DISABLE_VCORE_DVS (1U << 3)
+#define SPM_FLAG_DISABLE_VCORE_DFS (1U << 4)
+#define SPM_FLAG_DISABLE_COMMON_SCENARIO (1U << 5)
+#define SPM_FLAG_DISABLE_BUS_CLK_OFF (1U << 6)
+#define SPM_FLAG_DISABLE_ARMPLL_OFF (1U << 7)
+#define SPM_FLAG_KEEP_CSYSPWRACK_HIGH (1U << 8)
+#define SPM_FLAG_ENABLE_LVTS_WORKAROUND (1U << 9)
+#define SPM_FLAG_RUN_COMMON_SCENARIO (1U << 10)
+#define SPM_FLAG_PERI_ON_IN_SUSPEND (1U << 11)
+#define SPM_FLAG_ENABLE_SPM_DBG_WDT_DUMP (1U << 12)
+#define SPM_FLAG_USE_SRCCLKENO2 (1U << 13)
+#define SPM_FLAG_ENABLE_6315_CTRL (1U << 14)
+#define SPM_FLAG_ENABLE_TIA_WORKAROUND (1U << 15)
+#define SPM_FLAG_DISABLE_SYSRAM_SLEEP (1U << 16)
+#define SPM_FLAG_DISABLE_SSPM_SRAM_SLEEP (1U << 17)
+#define SPM_FLAG_DISABLE_MCUPM_SRAM_SLEEP (1U << 18)
+#define SPM_FLAG_DISABLE_DRAMC_ISSUE_CMD (1U << 19)
+#define SPM_FLAG_ENABLE_VOLTAGE_BIN (1U << 20)
+#define SPM_FLAG_RESERVED_BIT21 (1U << 21)
+#define SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP (1U << 22)
+#define SPM_FLAG_DISABLE_DRAMC_MD32_BACKUP (1U << 23)
+#define SPM_FLAG_RESERVED_BIT24 (1U << 24)
+#define SPM_FLAG_RESERVED_BIT25 (1U << 25)
+#define SPM_FLAG_RESERVED_BIT26 (1U << 26)
+#define SPM_FLAG_VTCXO_STATE (1U << 27)
+#define SPM_FLAG_INFRA_STATE (1U << 28)
+#define SPM_FLAG_APSRC_STATE (1U << 29)
+#define SPM_FLAG_VRF18_STATE (1U << 30)
+#define SPM_FLAG_DDREN_STATE (1U << 31)
+/* --- SPM Flag1 Define --- */
+#define SPM_FLAG1_DISABLE_AXI_BUS_TO_26M (1U << 0)
+#define SPM_FLAG1_DISABLE_SYSPLL_OFF (1U << 1)
+#define SPM_FLAG1_DISABLE_PWRAP_CLK_SWITCH (1U << 2)
+#define SPM_FLAG1_DISABLE_ULPOSC_OFF (1U << 3)
+#define SPM_FLAG1_FW_SET_ULPOSC_ON (1U << 4)
+#define SPM_FLAG1_RESERVED_BIT5 (1U << 5)
+#define SPM_FLAG1_ENABLE_REKICK (1U << 6)
+#define SPM_FLAG1_RESERVED_BIT7 (1U << 7)
+#define SPM_FLAG1_RESERVED_BIT8 (1U << 8)
+#define SPM_FLAG1_RESERVED_BIT9 (1U << 9)
+#define SPM_FLAG1_DISABLE_SRCLKEN_LOW (1U << 10)
+#define SPM_FLAG1_DISABLE_SCP_CLK_SWITCH (1U << 11)
+#define SPM_FLAG1_RESERVED_BIT12 (1U << 12)
+#define SPM_FLAG1_RESERVED_BIT13 (1U << 13)
+#define SPM_FLAG1_RESERVED_BIT14 (1U << 14)
+#define SPM_FLAG1_RESERVED_BIT15 (1U << 15)
+#define SPM_FLAG1_RESERVED_BIT16 (1U << 16)
+#define SPM_FLAG1_RESERVED_BIT17 (1U << 17)
+#define SPM_FLAG1_RESERVED_BIT18 (1U << 18)
+#define SPM_FLAG1_RESERVED_BIT19 (1U << 19)
+#define SPM_FLAG1_DISABLE_DEVAPC_SRAM_SLEEP (1U << 20)
+#define SPM_FLAG1_RESERVED_BIT21 (1U << 21)
+#define SPM_FLAG1_ENABLE_VS1_VOTER (1U << 22)
+#define SPM_FLAG1_ENABLE_VS2_VOTER (1U << 23)
+#define SPM_FLAG1_DISABLE_SCP_VREQ_MASK_CONTROL (1U << 24)
+#define SPM_FLAG1_RESERVED_BIT25 (1U << 25)
+#define SPM_FLAG1_RESERVED_BIT26 (1U << 26)
+#define SPM_FLAG1_RESERVED_BIT27 (1U << 27)
+#define SPM_FLAG1_RESERVED_BIT28 (1U << 28)
+#define SPM_FLAG1_RESERVED_BIT29 (1U << 29)
+#define SPM_FLAG1_RESERVED_BIT30 (1U << 30)
+#define SPM_FLAG1_RESERVED_BIT31 (1U << 31)
+/* --- SPM DEBUG Define --- */
+#define SPM_DBG_DEBUG_IDX_26M_WAKE (1U << 0)
+#define SPM_DBG_DEBUG_IDX_26M_SLEEP (1U << 1)
+#define SPM_DBG_DEBUG_IDX_INFRA_WAKE (1U << 2)
+#define SPM_DBG_DEBUG_IDX_INFRA_SLEEP (1U << 3)
+#define SPM_DBG_DEBUG_IDX_APSRC_WAKE (1U << 4)
+#define SPM_DBG_DEBUG_IDX_APSRC_SLEEP (1U << 5)
+#define SPM_DBG_DEBUG_IDX_VRF18_WAKE (1U << 6)
+#define SPM_DBG_DEBUG_IDX_VRF18_SLEEP (1U << 7)
+#define SPM_DBG_DEBUG_IDX_DDREN_WAKE (1U << 8)
+#define SPM_DBG_DEBUG_IDX_DDREN_SLEEP (1U << 9)
+#define SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_APSRC (1U << 10)
+#define SPM_DBG_DEBUG_IDX_MCUPM_SRAM_STATE (1U << 11)
+#define SPM_DBG_DEBUG_IDX_SSPM_SRAM_STATE (1U << 12)
+#define SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_DDREN (1U << 13)
+#define SPM_DBG_DEBUG_IDX_DRAMC_MCU_SRAM_STATE (1U << 14)
+#define SPM_DBG_DEBUG_IDX_SYSRAM_SLP (1U << 15)
+#define SPM_DBG_DEBUG_IDX_SYSRAM_ON (1U << 16)
+#define SPM_DBG_DEBUG_IDX_MCUPM_SRAM_SLP (1U << 17)
+#define SPM_DBG_DEBUG_IDX_MCUPM_SRAM_ON (1U << 18)
+#define SPM_DBG_DEBUG_IDX_SSPM_SRAM_SLP (1U << 19)
+#define SPM_DBG_DEBUG_IDX_SSPM_SRAM_ON (1U << 20)
+#define SPM_DBG_DEBUG_IDX_DRAMC_MCU_SRAM_SLP (1U << 21)
+#define SPM_DBG_DEBUG_IDX_DRAMC_MCU_SRAM_ON (1U << 22)
+#define SPM_DBG_DEBUG_IDX_SCP_VCORE_0P575V (1U << 23)
+#define SPM_DBG_DEBUG_IDX_SCP_VCORE_0P600V (1U << 24)
+#define SPM_DBG_DEBUG_IDX_SCP_VCORE_0P650V (1U << 25)
+#define SPM_DBG_DEBUG_IDX_SCP_VCORE_0P725V (1U << 26)
+#define SPM_DBG_DEBUG_IDX_SPM_GO_WAKEUP_NOW (1U << 27)
+#define SPM_DBG_DEBUG_IDX_VTCXO_STATE (1U << 28)
+#define SPM_DBG_DEBUG_IDX_INFRA_STATE (1U << 29)
+#define SPM_DBG_DEBUG_IDX_VRR18_STATE (1U << 30)
+#define SPM_DBG_DEBUG_IDX_APSRC_STATE (1U << 31)
+/* --- SPM DEBUG1 Define --- */
+#define SPM_DBG1_DEBUG_IDX_CURRENT_IS_LP (1U << 0)
+#define SPM_DBG1_DEBUG_IDX_VCORE_DVFS_START (1U << 1)
+#define SPM_DBG1_DEBUG_IDX_SYSPLL_OFF (1U << 2)
+#define SPM_DBG1_DEBUG_IDX_SYSPLL_ON (1U << 3)
+#define SPM_DBG1_DEBUG_IDX_CURRENT_IS_VCORE_DVFS (1U << 4)
+#define SPM_DBG1_DEBUG_IDX_INFRA_MTCMOS_OFF (1U << 5)
+#define SPM_DBG1_DEBUG_IDX_INFRA_MTCMOS_ON (1U << 6)
+#define SPM_DBG1_DEBUG_IDX_VRCXO_SLEEP_ABORT (1U << 7)
+#define SPM_DBG1_RESERVED_BIT8 (1U << 8)
+#define SPM_DBG1_DEBUG_IDX_INFRA_SUB_MTCMOS_OFF (1U << 9)
+#define SPM_DBG1_DEBUG_IDX_INFRA_SUB_MTCMOS_ON (1U << 10)
+#define SPM_DBG1_DEBUG_IDX_PWRAP_CLK_TO_ULPOSC (1U << 11)
+#define SPM_DBG1_DEBUG_IDX_PWRAP_CLK_TO_26M (1U << 12)
+#define SPM_DBG1_DEBUG_IDX_SCP_CLK_TO_32K (1U << 13)
+#define SPM_DBG1_DEBUG_IDX_SCP_CLK_TO_26M (1U << 14)
+#define SPM_DBG1_DEBUG_IDX_BUS_CLK_OFF (1U << 15)
+#define SPM_DBG1_DEBUG_IDX_BUS_CLK_ON (1U << 16)
+#define SPM_DBG1_DEBUG_IDX_SRCLKEN2_LOW (1U << 17)
+#define SPM_DBG1_DEBUG_IDX_SRCLKEN2_HIGH (1U << 18)
+#define SPM_DBG1_RESERVED_BIT19 (1U << 19)
+#define SPM_DBG1_DEBUG_IDX_ULPOSC_IS_OFF_BUT_SHOULD_ON (1U << 20)
+#define SPM_DBG1_DEBUG_IDX_6315_LOW (1U << 21)
+#define SPM_DBG1_DEBUG_IDX_6315_HIGH (1U << 22)
+#define SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_LOW_ABORT (1U << 23)
+#define SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_HIGH_ABORT (1U << 24)
+#define SPM_DBG1_DEBUG_IDX_EMI_SLP_IDLE_ABORT (1U << 25)
+#define SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_LOW_ABORT (1U << 26)
+#define SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_HIGH_ABORT (1U << 27)
+#define SPM_DBG1_DEBUG_IDX_SPM_DVFS_CMD_RDY_ABORT (1U << 28)
+#define SPM_DBG1_RESERVED_BIT29 (1U << 29)
+#define SPM_DBG1_RESERVED_BIT30 (1U << 30)
+#define SPM_DBG1_RESERVED_BIT31 (1U << 31)
+
+/*
+ * Macro and Inline
+ */
+#define is_cpu_pdn(flags) ((flags) & SPM_FLAG_DIS_CPU_PDN == 0)
+#define is_infra_pdn(flags) ((flags) & SPM_FLAG_DIS_INFRA_PDN == 0)
+#define is_ddrphy_pdn(flags) ((flags) & SPM_FLAG_DIS_DDRPHY_PDN == 0)
+
+#endif /* SLEEP_DEF_H */
diff --git a/plat/mediatek/drivers/spm/rules.mk b/plat/mediatek/drivers/spm/rules.mk
new file mode 100644
index 0000000..b7128db
--- /dev/null
+++ b/plat/mediatek/drivers/spm/rules.mk
@@ -0,0 +1,20 @@
+#
+# Copyright (c) 2023, MediaTek Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+LOCAL_DIR := $(call GET_LOCAL_DIR)
+MODULE := spm
+
+$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))
+
+ifneq ($(CONFIG_MTK_SPM_VERSION),)
+PLAT_INCLUDES += -I${LOCAL_DIR}/$(MTK_SOC)
+PLAT_INCLUDES += -I${LOCAL_DIR}/version/notifier/inc
+
+SUB_RULES-y += ${LOCAL_DIR}/$(CONFIG_MTK_SPM_VERSION)
+$(eval $(call add_define,SPM_PLAT_IMPL))
+endif
+
+$(eval $(call INCLUDE_MAKEFILE,$(SUB_RULES-y)))
diff --git a/plat/mediatek/drivers/spm/version/notifier/inc/mt_spm_notifier.h b/plat/mediatek/drivers/spm/version/notifier/inc/mt_spm_notifier.h
new file mode 100644
index 0000000..4d12624
--- /dev/null
+++ b/plat/mediatek/drivers/spm/version/notifier/inc/mt_spm_notifier.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_NOTIFIER_H
+#define MT_SPM_NOTIFIER_H
+
+enum mt_spm_sspm_notify_id {
+ MT_SPM_NOTIFY_LP_ENTER = 0,
+ MT_SPM_NOTIFY_LP_LEAVE,
+ MT_SPM_NOTIFY_SUSPEND_VCORE_VOLTAGE,
+};
+
+#ifdef MTK_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+static inline int mt_spm_sspm_notify_u32(int type, unsigned int val)
+{
+ (void)type;
+ (void)val;
+ return 0;
+}
+#else
+int mt_spm_sspm_notify_u32(int type, unsigned int val);
+#endif
+
+#endif /* MT_SPM_NOTIFIER_H */
diff --git a/plat/mediatek/drivers/spm/version/notifier/v1/mt_spm_sspm_intc.h b/plat/mediatek/drivers/spm/version/notifier/v1/mt_spm_sspm_intc.h
new file mode 100644
index 0000000..e57a966
--- /dev/null
+++ b/plat/mediatek/drivers/spm/version/notifier/v1/mt_spm_sspm_intc.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_SSPM_INTC_H
+#define MT_SPM_SSPM_INTC_H
+
+#include <mt_spm_reg.h>
+
+#define MT_SPM_SSPM_INTC_SEL_0 (0x10)
+#define MT_SPM_SSPM_INTC_SEL_1 (0x20)
+#define MT_SPM_SSPM_INTC_SEL_2 (0x40)
+#define MT_SPM_SSPM_INTC_SEL_3 (0x80)
+
+#define MT_SPM_SSPM_INTC_TRIGGER(id, sg) (((0x10 << (id)) | (sg << (id))) & 0xFF)
+
+#define MT_SPM_SSPM_INTC0_HIGH MT_SPM_SSPM_INTC_TRIGGER(0, 1)
+#define MT_SPM_SSPM_INTC0_LOW MT_SPM_SSPM_INTC_TRIGGER(0, 0)
+
+#define MT_SPM_SSPM_INTC1_HIGH MT_SPM_SSPM_INTC_TRIGGER(1, 1)
+#define MT_SPM_SSPM_INTC1_LOW MT_SPM_SSPM_INTC_TRIGGER(1, 0)
+
+#define MT_SPM_SSPM_INTC2_HIGH MT_SPM_SSPM_INTC_TRIGGER(2, 1)
+#define MT_SPM_SSPM_INTC2_LOW MT_SPM_SSPM_INTC_TRIGGER(2, 0)
+
+#define MT_SPM_SSPM_INTC3_HIGH MT_SPM_SSPM_INTC_TRIGGER(3, 1)
+#define MT_SPM_SSPM_INTC3_LOW MT_SPM_SSPM_INTC_TRIGGER(3, 0)
+
+#define DO_SPM_SSPM_LP_SUSPEND() mmio_write_32(SPM_MD32_IRQ, MT_SPM_SSPM_INTC0_HIGH)
+
+#define DO_SPM_SSPM_LP_RESUME() mmio_write_32(SPM_MD32_IRQ, MT_SPM_SSPM_INTC0_LOW)
+
+#endif /* MT_SPM_SSPM_INTC_H */
diff --git a/plat/mediatek/drivers/spm/version/notifier/v1/mt_spm_sspm_notifier.c b/plat/mediatek/drivers/spm/version/notifier/v1/mt_spm_sspm_notifier.c
new file mode 100644
index 0000000..081988f
--- /dev/null
+++ b/plat/mediatek/drivers/spm/version/notifier/v1/mt_spm_sspm_notifier.c
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <lib/mmio.h>
+#include "mt_spm_notifier.h"
+#include "mt_spm_sspm_intc.h"
+#include <platform_def.h>
+
+#define MT_SPM_SSPM_MBOX_OFF(x) (SSPM_MBOX_3_BASE + x)
+#define MT_SPM_MBOX(slot) MT_SPM_SSPM_MBOX_OFF((slot << 2UL))
+
+/* LOOKUP SSPM_MBOX_SPM_LP1 */
+#define SSPM_MBOX_SPM_LP_LOOKUP1 MT_SPM_MBOX(0)
+/* LOOKUP SSPM_MBOX_SPM_LP2 */
+#define SSPM_MBOX_SPM_LP_LOOKUP2 MT_SPM_MBOX(1)
+
+#define SSPM_MBOX_SPM_LP1 MT_SPM_MBOX(2)
+#define SSPM_MBOX_SPM_LP2 MT_SPM_MBOX(3)
+
+int mt_spm_sspm_notify_u32(int type, unsigned int val)
+{
+ switch (type) {
+ case MT_SPM_NOTIFY_LP_ENTER:
+ mmio_write_32(SSPM_MBOX_SPM_LP1, val);
+ DO_SPM_SSPM_LP_SUSPEND();
+ break;
+ case MT_SPM_NOTIFY_LP_LEAVE:
+ mmio_write_32(SSPM_MBOX_SPM_LP1, val);
+ DO_SPM_SSPM_LP_RESUME();
+ break;
+ default:
+ panic();
+ break;
+ }
+ return 0;
+}
diff --git a/plat/mediatek/drivers/usb/mt8188/mt_usb.c b/plat/mediatek/drivers/usb/mt8188/mt_usb.c
new file mode 100644
index 0000000..c9e7a56
--- /dev/null
+++ b/plat/mediatek/drivers/usb/mt8188/mt_usb.c
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch_helpers.h>
+#include <common/debug.h>
+#include <lib/mtk_init/mtk_init.h>
+#include <lpm/mt_lp_api.h>
+#include <platform_def.h>
+
+int mt_usb_init(void)
+{
+ INFO("[%s] mt_usb initialization\n", __func__);
+
+ /* Keep infra and peri on to support wake-up from USB */
+ mtk_usb_update(LPM_USB_ENTER);
+
+ return 0;
+}
+MTK_PLAT_SETUP_0_INIT(mt_usb_init);
diff --git a/plat/mediatek/drivers/usb/rules.mk b/plat/mediatek/drivers/usb/rules.mk
new file mode 100644
index 0000000..f8c43f1
--- /dev/null
+++ b/plat/mediatek/drivers/usb/rules.mk
@@ -0,0 +1,13 @@
+#
+# Copyright (c) 2023, MediaTek Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+LOCAL_DIR := $(call GET_LOCAL_DIR)
+
+MODULE := usb
+
+LOCAL_SRCS-y := $(LOCAL_DIR)/$(MTK_SOC)/mt_usb.c
+
+$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))
diff --git a/plat/mediatek/include/drivers/spm/mt_spm_resource_req.h b/plat/mediatek/include/drivers/spm/mt_spm_resource_req.h
new file mode 100644
index 0000000..890bacc
--- /dev/null
+++ b/plat/mediatek/include/drivers/spm/mt_spm_resource_req.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_RESOURCE_REQ_H
+#define MT_SPM_RESOURCE_REQ_H
+
+/* SPM resource request internal bit */
+#define MT_SPM_BIT_XO_FPM (0U)
+#define MT_SPM_BIT_26M (1U)
+#define MT_SPM_BIT_INFRA (2U)
+#define MT_SPM_BIT_SYSPLL (3U)
+#define MT_SPM_BIT_DRAM_S0 (4U)
+#define MT_SPM_BIT_DRAM_S1 (5U)
+
+/* SPM resource request internal bit_mask */
+#define MT_SPM_XO_FPM BIT(MT_SPM_BIT_XO_FPM)
+#define MT_SPM_26M BIT(MT_SPM_BIT_26M)
+#define MT_SPM_INFRA BIT(MT_SPM_BIT_INFRA)
+#define MT_SPM_SYSPLL BIT(MT_SPM_BIT_SYSPLL)
+#define MT_SPM_DRAM_S0 BIT(MT_SPM_BIT_DRAM_S0)
+#define MT_SPM_DRAM_S1 BIT(MT_SPM_BIT_DRAM_S1)
+
+#endif /* MT_SPM_RESOURCE_REQ_H */
diff --git a/plat/mediatek/include/lpm/mt_lp_api.h b/plat/mediatek/include/lpm/mt_lp_api.h
new file mode 100644
index 0000000..00a2802
--- /dev/null
+++ b/plat/mediatek/include/lpm/mt_lp_api.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_LP_API_H
+#define MT_LP_API_H
+
+#include <lpm/mt_lp_rm.h>
+
+#if MTK_PUBEVENT_ENABLE
+#include <vendor_pubsub_events.h>
+#endif
+
+/* Ufs clk enum for PLAT_RC_CLKBUF_STATUS */
+enum rc_update_ex_ufs_ref_clk {
+ UFS_REF_CLK_OFF = 0,
+ UFS_REF_CLK_ON,
+};
+
+/* Enum for flight mode */
+enum rc_update_ex_flight_mode {
+ FLIGHT_MODE_OFF = 0,
+ FLIGHT_MODE_ON,
+};
+
+struct mt_lpm_pubevent_data {
+ unsigned int u32;
+};
+
+enum mt_lpm_pubevents_id {
+ MT_LPM_PUBEVENTS_BBLPM_ENTER,
+ MT_LPM_PUBEVENTS_BBLPM_LEAVE,
+ MT_LPM_PUBEVENTS_TARGET_CORE,
+ MT_LPM_PUBEVENTS_SYS_POWER_OFF,
+ MT_LPM_PUBEVENTS_SYS_POWER_ON,
+};
+
+struct mt_lp_publish_event {
+ unsigned int id;
+ struct mt_lpm_pubevent_data val;
+};
+
+#if MTK_PUBEVENT_ENABLE
+#define MT_LP_PUBLISH_EVENT(x) ({\
+ PUBLISH_EVENT_ARG(lpm_publish_event, (const void *)(x)); })
+#define MT_LP_SUSPEND_PUBLISH_EVENT(x) ({\
+ PUBLISH_EVENT_ARG(suspend_publish_event, (const void *)(x)); })
+
+#define MT_LP_SUBSCRIBE_SUSPEND(func) SUBSCRIBE_TO_EVENT(suspend_publish_event, func)
+#define MT_LP_SUBSCRIBE_LPM(func) SUBSCRIBE_TO_EVENT(lpm_publish_event, func)
+#else
+#define MT_LP_PUBLISH_EVENT(x) ({ (void)x; })
+#define MT_LP_SUSPEND_PUBLISH_EVENT(x) ({ (void)x; })
+#define MT_LP_SUBSCRIBE_SUSPEND(func)
+#define MT_LP_SUBSCRIBE_LPM(func)
+#endif
+
+/* MTK low power API types for audio */
+enum mt_lp_api_audio_type {
+ AUDIO_AFE_ENTER,
+ AUDIO_AFE_LEAVE,
+ AUDIO_DSP_ENTER,
+ AUDIO_DSP_LEAVE,
+};
+
+/* MTK low power API types for usb */
+enum mt_lp_api_usb_type {
+ LPM_USB_ENTER,
+ LPM_USB_LEAVE,
+};
+
+int mt_audio_update(int type);
+int mtk_usb_update(int type);
+
+#endif /* MT_LP_API_H */
diff --git a/plat/mediatek/include/lpm/mt_lp_rm.h b/plat/mediatek/include/lpm/mt_lp_rm.h
new file mode 100644
index 0000000..bf99489
--- /dev/null
+++ b/plat/mediatek/include/lpm/mt_lp_rm.h
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2020-2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_LP_RM_H
+#define MT_LP_RM_H
+
+#include <stdbool.h>
+
+#define MT_RM_STATUS_OK (0)
+#define MT_RM_STATUS_BAD (-1)
+#define MT_RM_STATUS_STOP (-2)
+
+enum PLAT_MT_LPM_RC_TYPE {
+ PLAT_RC_UPDATE_CONDITION,
+ PLAT_RC_STATUS,
+ PLAT_RC_UPDATE_REMAIN_IRQS,
+ PLAT_RC_IS_FMAUDIO,
+ PLAT_RC_IS_ADSP,
+ PLAT_RC_ENTER_CNT,
+ PLAT_RC_CLKBUF_STATUS,
+ PLAT_RC_UFS_STATUS,
+ PLAT_RC_IS_USB_PERI,
+ PLAT_RC_IS_USB_INFRA,
+ PLAT_RC_MAX,
+};
+
+enum plat_mt_lpm_hw_ctrl_type {
+ PLAT_AP_MDSRC_REQ,
+ PLAT_AP_MDSRC_ACK,
+ PLAT_AP_IS_MD_SLEEP,
+ PLAT_AP_MDSRC_SETTLE,
+ PLAT_AP_GPUEB_PLL_CONTROL,
+ PLAT_AP_GPUEB_GET_PWR_STATUS,
+ PLAT_AP_HW_CTRL_MAX,
+};
+
+struct mt_resource_constraint {
+ int level;
+ int (*init)(void);
+ bool (*is_valid)(unsigned int cpu, int stateid);
+ int (*update)(int stateid, int type, const void *p);
+ int (*run)(unsigned int cpu, int stateid);
+ int (*reset)(unsigned int cpu, int stateid);
+ int (*get_status)(unsigned int type, void *priv);
+ unsigned int (*allow)(int stateid);
+};
+
+struct mt_resource_manager {
+ int (*update)(struct mt_resource_constraint **con, unsigned int num,
+ int stateid, void *priv);
+ struct mt_resource_constraint **consts;
+};
+
+extern int mt_lp_rm_register(struct mt_resource_manager *rm);
+extern int mt_lp_rm_do_constraint(unsigned int constraint_id, unsigned int cpuid, int stateid);
+extern int mt_lp_rm_find_constraint(unsigned int idx, unsigned int cpuid,
+ int stateid, void *priv);
+extern int mt_lp_rm_find_and_run_constraint(unsigned int idx, unsigned int cpuid,
+ int stateid, void *priv);
+extern int mt_lp_rm_reset_constraint(unsigned int idx, unsigned int cpuid, int stateid);
+extern int mt_lp_rm_do_update(int stateid, int type, void const *p);
+extern int mt_lp_rm_get_status(unsigned int type, void *priv);
+
+#endif /* MT_LP_RM_H */
diff --git a/plat/mediatek/include/lpm/mt_lp_rq.h b/plat/mediatek/include/lpm/mt_lp_rq.h
new file mode 100644
index 0000000..2c4908c
--- /dev/null
+++ b/plat/mediatek/include/lpm/mt_lp_rq.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_LP_RQ_H
+#define MT_LP_RQ_H
+
+/* Determine the generic resource request public type */
+#define MT_LP_RQ_XO_FPM BIT(0)
+#define MT_LP_RQ_26M BIT(1)
+#define MT_LP_RQ_INFRA BIT(2)
+#define MT_LP_RQ_SYSPLL BIT(3)
+#define MT_LP_RQ_DRAM BIT(4)
+#define MT_LP_RQ_ALL (0xFFFFFFFF)
+
+struct mt_lp_resource_user {
+ /* Determine the resource user mask */
+ unsigned int umask;
+ /* Determine the resource request user identify */
+ unsigned int uid;
+ /* Request the resource */
+ int (*request)(struct mt_lp_resource_user *this, unsigned int resource);
+ /* Release the resource */
+ int (*release)(struct mt_lp_resource_user *this);
+};
+
+int mt_lp_resource_user_register(char *uname, struct mt_lp_resource_user *ru);
+
+#endif /* MT_LP_RQ_H */
diff --git a/plat/mediatek/include/lpm/mt_lp_rqm.h b/plat/mediatek/include/lpm/mt_lp_rqm.h
new file mode 100644
index 0000000..c30f762
--- /dev/null
+++ b/plat/mediatek/include/lpm/mt_lp_rqm.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_LP_RQM_H
+#define MT_LP_RQM_H
+
+#include "mt_lp_rq.h"
+
+enum plat_mt_lpm_rq_update_type {
+ PLAT_RQ_USER_NUM,
+ PLAT_RQ_USER_VALID,
+ PLAT_RQ_USER_REQ,
+ PLAT_RQ_USER_REL,
+ PLAT_RQ_PER_USER_NAME,
+ PLAT_RQ_REQ_NUM,
+ PLAT_RQ_REQ_USAGE,
+};
+
+/* Determine the request valid */
+#define MT_LP_RQ_VALID (0x1)
+#define MT_LP_RQ_INVALID (0x0)
+
+/* Determine the request user opertions */
+#define MT_LP_RQ_USER_INVALID (-1)
+#define MT_LP_RQ_USER_MAX (32)
+#define MT_LP_RQ_USER_NAME_LEN (4)
+#define MT_LP_RQ_USER_CHAR_U (8)
+
+/* Determine the request update flag */
+#define MT_LP_RQ_FLAG_DONE (0)
+#define MT_LP_RQ_FLAG_NEED_UPDATE BIT(6)
+
+/* Determine the resource update id */
+#define MT_LP_RQ_ID_ALL_USAGE (-1)
+
+/* Determine the return status */
+#define MT_LP_RQ_STA_OK (0)
+#define MT_LP_RQ_STA_BAD (-1)
+
+struct mt_lp_res_req {
+ /* Determine the resource req public identify */
+ const unsigned int res_id;
+ /* Determine the resource bitwise internal control */
+ const unsigned int res_rq;
+ /* Determine the users per bit for current resource usage */
+ unsigned int res_usage;
+};
+
+struct mt_resource_req_manager {
+ /* Determine the set of resources */
+ struct mt_lp_res_req **res;
+};
+
+struct resource_req_status {
+ /* Determine the status id */
+ unsigned int id;
+ /* Determine the status value */
+ unsigned int val;
+};
+
+int mt_lp_resource_request_manager_register(struct mt_resource_req_manager *rqm);
+int mt_lp_rq_update_status(int type, void *p);
+int mt_lp_rq_get_status(int type, void *p);
+
+#endif /* MT_LP_RQM_H */
diff --git a/plat/mediatek/include/lpm/mt_lpm_smc.h b/plat/mediatek/include/lpm/mt_lpm_smc.h
new file mode 100644
index 0000000..0117ca9
--- /dev/null
+++ b/plat/mediatek/include/lpm/mt_lpm_smc.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_LPM_SMC_H
+#define MT_LPM_SMC_H
+
+/*
+ * MTK LPM smc user format:
+ * bit[31:24]: magic number
+ * bit[23:16]: user number
+ * bit[15:00]: user id
+ */
+
+#define MT_LPM_SMC_MAGIC (0xDA000000)
+#define MT_LPM_SMC_MAGIC_MASK (0xFF000000)
+#define MT_LPM_SMC_USER_MASK (0xFF)
+#define MT_LPM_SMC_USER_SHIFT (16)
+
+#define MT_LPM_SMC_USER_ID_MASK (0x0000FFFF)
+
+/*
+ * cpu_pm is used for MCDI to read/write CPC information
+ * spm_dbg is used for spm related debug information
+ * spm is used for spm related settings
+ * cpu_pm_lp is used for MCDI setting irq_remain
+ */
+enum mt_lpm_smc_user_id {
+ MT_LPM_SMC_USER_CPU_PM = 0,
+ MT_LPM_SMC_USER_SPM_DBG,
+ MT_LPM_SMC_USER_SPM,
+ MT_LPM_SMC_USER_CPU_PM_LP,
+ MT_LPM_SMC_USER_SECURE_CPU_PM,
+ MT_LPM_SMC_USER_SECURE_SPM_DBG,
+ MT_LPM_SMC_USER_SECURE_SPM,
+ MT_LPM_SMC_USER_MAX,
+};
+
+#define IS_MT_LPM_SMC(smcid) ((smcid & MT_LPM_SMC_MAGIC_MASK) == MT_LPM_SMC_MAGIC)
+
+/* get real user id */
+#define MT_LPM_SMC_USER(id) ((id >> MT_LPM_SMC_USER_SHIFT) & MT_LPM_SMC_USER_MASK)
+#define MT_LPM_SMC_USER_ID(uid) (uid & MT_LPM_SMC_USER_ID_MASK)
+
+/* sink user id to smc's user id */
+#define MT_LPM_SMC_USER_SINK(user, uid) (((uid & MT_LPM_SMC_USER_ID_MASK) |\
+ ((user & MT_LPM_SMC_USER_MASK) << MT_LPM_SMC_USER_SHIFT)) |\
+ MT_LPM_SMC_MAGIC)
+
+/* sink cpu pm's smc id */
+#define MT_LPM_SMC_USER_ID_CPU_PM(uid) MT_LPM_SMC_USER_SINK(MT_LPM_SMC_USER_CPU_PM, uid)
+/* sink spm's smc id */
+#define MT_LPM_SMC_USER_ID_SPM(uid) MT_LPM_SMC_USER_SINK(MT_LPM_SMC_USER_SPM, uid)
+
+/* sink cpu pm's user id */
+#define MT_LPM_SMC_USER_CPU_PM(uid) MT_LPM_SMC_USER_ID_CPU_PM(uid)
+
+/* sink spm's user id */
+#define MT_LPM_SMC_USER_SPM(uid) MT_LPM_SMC_USER_ID_SPM(uid)
+
+/* behavior */
+#define MT_LPM_SMC_ACT_SET BIT(0)
+#define MT_LPM_SMC_ACT_CLR BIT(1)
+#define MT_LPM_SMC_ACT_GET BIT(2)
+#define MT_LPM_SMC_ACT_PUSH BIT(3)
+#define MT_LPM_SMC_ACT_POP BIT(4)
+#define MT_LPM_SMC_ACT_SUBMIT BIT(5)
+
+/* compatible action for legacy smc from lk */
+#define MT_LPM_SMC_ACT_COMPAT BIT(31)
+
+enum mt_lpm_spmc_compat_id {
+ MT_LPM_SPMC_COMPAT_LK_FW_INIT,
+ MT_LPM_SPMC_COMPAT_LK_MCDI_WDT_DUMP,
+};
+
+#endif /* MT_LPM_SMC_H */
diff --git a/plat/mediatek/mt8186/drivers/spm/mt_spm_cond.c b/plat/mediatek/mt8186/drivers/spm/mt_spm_cond.c
index a420e16..14a84b2 100644
--- a/plat/mediatek/mt8186/drivers/spm/mt_spm_cond.c
+++ b/plat/mediatek/mt8186/drivers/spm/mt_spm_cond.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2022-2023, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -148,7 +148,8 @@
(((mmio_read_32(SPM_PWR_STATUS) & mask) == 0U) && \
((mmio_read_32(SPM_PWR_STATUS_2ND) & mask) == 0U))
-int mt_spm_cond_update(struct mt_resource_constraint **con, int stateid, void *priv)
+int mt_spm_cond_update(struct mt_resource_constraint **con, unsigned int num,
+ int stateid, void *priv)
{
int res;
uint32_t i;
diff --git a/plat/mediatek/mt8186/drivers/spm/mt_spm_cond.h b/plat/mediatek/mt8186/drivers/spm/mt_spm_cond.h
index 24c39ba..28a3020 100644
--- a/plat/mediatek/mt8186/drivers/spm/mt_spm_cond.h
+++ b/plat/mediatek/mt8186/drivers/spm/mt_spm_cond.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2022-2023, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -54,7 +54,7 @@
const struct mt_spm_cond_tables *dest,
struct mt_spm_cond_tables *res);
-extern int mt_spm_cond_update(struct mt_resource_constraint **con,
+extern int mt_spm_cond_update(struct mt_resource_constraint **con, unsigned int num,
int stateid, void *priv);
#endif /* MT_SPM_CONDIT_H */
diff --git a/plat/mediatek/mt8186/platform.mk b/plat/mediatek/mt8186/platform.mk
index 68f4a1f..2bd2fb4 100644
--- a/plat/mediatek/mt8186/platform.mk
+++ b/plat/mediatek/mt8186/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2021-2022, MediaTek Inc. All rights reserved.
+# Copyright (c) 2021-2023, MediaTek Inc. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -8,7 +8,6 @@
MTK_PLAT_SOC := ${MTK_PLAT}/${PLAT}
PLAT_INCLUDES := -I${MTK_PLAT}/common/ \
- -I${MTK_PLAT}/common/lpm \
-I${MTK_PLAT}/drivers/cirq/ \
-I${MTK_PLAT}/drivers/gic600/ \
-I${MTK_PLAT}/drivers/gpio/ \
@@ -18,6 +17,7 @@
-I${MTK_PLAT}/drivers/timer/ \
-I${MTK_PLAT}/drivers/uart/ \
-I${MTK_PLAT}/include/ \
+ -I${MTK_PLAT}/include/lpm \
-I${MTK_PLAT_SOC}/drivers/spm/ \
-I${MTK_PLAT_SOC}/drivers/dcm/ \
-I${MTK_PLAT_SOC}/drivers/dfd/ \
diff --git a/plat/mediatek/mt8188/include/platform_def.h b/plat/mediatek/mt8188/include/platform_def.h
index 156a7e2..34d4637 100644
--- a/plat/mediatek/mt8188/include/platform_def.h
+++ b/plat/mediatek/mt8188/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2022-2023, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -22,6 +22,8 @@
#define MTK_DEV_RNG1_BASE (IO_PHYS)
#define MTK_DEV_RNG1_SIZE (0x10000000)
+#define TOPCKGEN_BASE (IO_PHYS)
+
/*******************************************************************************
* AUDIO related constants
******************************************************************************/
@@ -57,6 +59,8 @@
/*******************************************************************************
* Infra IOMMU related constants
******************************************************************************/
+#define INFRACFG_AO_BASE (IO_PHYS + 0x00001000)
+#define INFRACFG_AO_MEM_BASE (IO_PHYS + 0x00002000)
#define PERICFG_AO_BASE (IO_PHYS + 0x01003000)
#define PERICFG_AO_REG_SIZE (0x1000)
@@ -108,6 +112,33 @@
#define SMI_LARB_REG_RNG_SIZE (0x1000)
/*******************************************************************************
+ * SPM related constants
+ ******************************************************************************/
+#define SPM_BASE (IO_PHYS + 0x00006000)
+
+/*******************************************************************************
+ * APMIXEDSYS related constants
+ ******************************************************************************/
+#define APMIXEDSYS (IO_PHYS + 0x0000C000)
+
+/*******************************************************************************
+ * VPPSYS related constants
+ ******************************************************************************/
+#define VPPSYS0_BASE (IO_PHYS + 0x04000000)
+#define VPPSYS1_BASE (IO_PHYS + 0x04f00000)
+
+/*******************************************************************************
+ * VDOSYS related constants
+ ******************************************************************************/
+#define VDOSYS0_BASE (IO_PHYS + 0x0C01D000)
+#define VDOSYS1_BASE (IO_PHYS + 0x0C100000)
+
+/*******************************************************************************
+ * SSPM_MBOX_3 related constants
+ ******************************************************************************/
+#define SSPM_MBOX_3_BASE (IO_PHYS + 0x00480000)
+
+/*******************************************************************************
* DP related constants
******************************************************************************/
#define EDP_SEC_BASE (IO_PHYS + 0x0C504000)
diff --git a/plat/mediatek/mt8188/plat_config.mk b/plat/mediatek/mt8188/plat_config.mk
index 137318e..2e3392f 100644
--- a/plat/mediatek/mt8188/plat_config.mk
+++ b/plat/mediatek/mt8188/plat_config.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2022, MediaTek Inc. All rights reserved.
+# Copyright (c) 2022-2023, MediaTek Inc. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -41,6 +41,8 @@
CONFIG_MTK_CPU_PM_ARCH := 3_2
CONFIG_MTK_SMP_EN := y
CONFIG_MTK_CPU_SUSPEND_EN := y
+CONFIG_MTK_SPM_VERSION := mt8188
+CONFIG_MTK_SUPPORT_SYSTEM_SUSPEND := y
CPU_PM_TINYSYS_SUPPORT := y
MTK_PUBEVENT_ENABLE := y
diff --git a/plat/mediatek/mt8188/platform.mk b/plat/mediatek/mt8188/platform.mk
index b6a17aa..85ceeb9 100644
--- a/plat/mediatek/mt8188/platform.mk
+++ b/plat/mediatek/mt8188/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2022, MediaTek Inc. All rights reserved.
+# Copyright (c) 2022-2023, MediaTek Inc. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -39,7 +39,9 @@
MODULES-y += $(MTK_PLAT)/drivers/pmic_wrap
MODULES-y += $(MTK_PLAT)/drivers/ptp3
MODULES-y += $(MTK_PLAT)/drivers/rtc
+MODULES-y += $(MTK_PLAT)/drivers/spm
MODULES-y += $(MTK_PLAT)/drivers/timer
+MODULES-y += $(MTK_PLAT)/drivers/usb
MODULES-y += $(MTK_PLAT)/helpers
MODULES-y += $(MTK_PLAT)/topology
diff --git a/plat/mediatek/mt8192/drivers/spm/mt_spm_cond.c b/plat/mediatek/mt8192/drivers/spm/mt_spm_cond.c
index 2d67fdf..4332b70 100644
--- a/plat/mediatek/mt8192/drivers/spm/mt_spm_cond.c
+++ b/plat/mediatek/mt8192/drivers/spm/mt_spm_cond.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2020-2023, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -155,7 +155,7 @@
(((mmio_read_32(SPM_PWR_STATUS) & mask) == 0U) && \
((mmio_read_32(SPM_PWR_STATUS_2ND) & mask) == 0U))
-int mt_spm_cond_update(struct mt_resource_constraint **con,
+int mt_spm_cond_update(struct mt_resource_constraint **con, unsigned int num,
int stateid, void *priv)
{
int res;
diff --git a/plat/mediatek/mt8192/drivers/spm/mt_spm_cond.h b/plat/mediatek/mt8192/drivers/spm/mt_spm_cond.h
index 91ebdd9..ffd5f3f 100644
--- a/plat/mediatek/mt8192/drivers/spm/mt_spm_cond.h
+++ b/plat/mediatek/mt8192/drivers/spm/mt_spm_cond.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2020-2023, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -51,6 +51,6 @@
const struct mt_spm_cond_tables *src,
const struct mt_spm_cond_tables *dest,
struct mt_spm_cond_tables *res);
-extern int mt_spm_cond_update(struct mt_resource_constraint **con,
+extern int mt_spm_cond_update(struct mt_resource_constraint **con, unsigned int num,
int stateid, void *priv);
#endif /* MT_SPM_CONDIT_H */
diff --git a/plat/mediatek/mt8192/platform.mk b/plat/mediatek/mt8192/platform.mk
index a19fc45..4afd157 100644
--- a/plat/mediatek/mt8192/platform.mk
+++ b/plat/mediatek/mt8192/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2020-2022, MediaTek Inc. All rights reserved.
+# Copyright (c) 2020-2023, MediaTek Inc. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -8,7 +8,6 @@
MTK_PLAT_SOC := ${MTK_PLAT}/${PLAT}
PLAT_INCLUDES := -I${MTK_PLAT}/common/ \
- -I${MTK_PLAT}/common/lpm/ \
-I${MTK_PLAT}/drivers/cirq/ \
-I${MTK_PLAT}/drivers/gic600/ \
-I${MTK_PLAT}/drivers/gpio/ \
@@ -18,6 +17,7 @@
-I${MTK_PLAT}/drivers/timer/ \
-I${MTK_PLAT}/drivers/uart/ \
-I${MTK_PLAT}/include/ \
+ -I${MTK_PLAT}/include/lpm/ \
-I${MTK_PLAT_SOC}/include/ \
-I${MTK_PLAT_SOC}/drivers/ \
-I${MTK_PLAT_SOC}/drivers/apusys/ \
diff --git a/plat/mediatek/mt8195/drivers/spm/mt_spm_cond.c b/plat/mediatek/mt8195/drivers/spm/mt_spm_cond.c
index c80faf5..0ca0e1d 100644
--- a/plat/mediatek/mt8195/drivers/spm/mt_spm_cond.c
+++ b/plat/mediatek/mt8195/drivers/spm/mt_spm_cond.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2021-2023, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -171,7 +171,7 @@
(((mmio_read_32(SPM_PWR_STATUS) & mask) == 0U) && \
((mmio_read_32(SPM_PWR_STATUS_2ND) & mask) == 0U))
-int mt_spm_cond_update(struct mt_resource_constraint **con,
+int mt_spm_cond_update(struct mt_resource_constraint **con, unsigned int num,
int stateid, void *priv)
{
int res;
diff --git a/plat/mediatek/mt8195/drivers/spm/mt_spm_cond.h b/plat/mediatek/mt8195/drivers/spm/mt_spm_cond.h
index e471b55..83007af 100644
--- a/plat/mediatek/mt8195/drivers/spm/mt_spm_cond.h
+++ b/plat/mediatek/mt8195/drivers/spm/mt_spm_cond.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2021-2023, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -68,6 +68,6 @@
const struct mt_spm_cond_tables *src,
const struct mt_spm_cond_tables *dest,
struct mt_spm_cond_tables *res);
-extern int mt_spm_cond_update(struct mt_resource_constraint **con,
+extern int mt_spm_cond_update(struct mt_resource_constraint **con, unsigned int num,
int stateid, void *priv);
#endif /* MT_SPM_CONDIT_H */
diff --git a/plat/mediatek/mt8195/platform.mk b/plat/mediatek/mt8195/platform.mk
index 07d39cb..48dafa3 100644
--- a/plat/mediatek/mt8195/platform.mk
+++ b/plat/mediatek/mt8195/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2021-2022, MediaTek Inc. All rights reserved.
+# Copyright (c) 2021-2023, MediaTek Inc. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -8,7 +8,6 @@
MTK_PLAT_SOC := ${MTK_PLAT}/${PLAT}
PLAT_INCLUDES := -I${MTK_PLAT}/common/ \
- -I${MTK_PLAT}/common/lpm/ \
-I${MTK_PLAT}/drivers/cirq/ \
-I${MTK_PLAT}/drivers/dp/ \
-I${MTK_PLAT}/drivers/gic600/ \
@@ -20,6 +19,7 @@
-I${MTK_PLAT}/drivers/timer/ \
-I${MTK_PLAT}/drivers/uart/ \
-I${MTK_PLAT}/include/ \
+ -I${MTK_PLAT}/include/lpm/ \
-I${MTK_PLAT_SOC}/drivers/apusys/ \
-I${MTK_PLAT_SOC}/drivers/dcm \
-I${MTK_PLAT_SOC}/drivers/dfd \
diff --git a/plat/nvidia/tegra/soc/t186/plat_memctrl.c b/plat/nvidia/tegra/soc/t186/plat_memctrl.c
index 81de674..2533013 100644
--- a/plat/nvidia/tegra/soc/t186/plat_memctrl.c
+++ b/plat/nvidia/tegra/soc/t186/plat_memctrl.c
@@ -20,7 +20,7 @@
/*******************************************************************************
* Array to hold stream_id override config register offsets
******************************************************************************/
-const static uint32_t tegra186_streamid_override_regs[] = {
+static const uint32_t tegra186_streamid_override_regs[] = {
MC_STREAMID_OVERRIDE_CFG_SDMMCRA,
MC_STREAMID_OVERRIDE_CFG_SDMMCRAA,
MC_STREAMID_OVERRIDE_CFG_SDMMCR,
@@ -34,7 +34,7 @@
/*******************************************************************************
* Array to hold the security configs for stream IDs
******************************************************************************/
-const static mc_streamid_security_cfg_t tegra186_streamid_sec_cfgs[] = {
+static const mc_streamid_security_cfg_t tegra186_streamid_sec_cfgs[] = {
mc_make_sec_cfg(SCEW, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(AFIR, NON_SECURE, OVERRIDE, DISABLE),
mc_make_sec_cfg(AFIW, NON_SECURE, OVERRIDE, DISABLE),
@@ -112,7 +112,7 @@
/*******************************************************************************
* Array to hold the transaction override configs
******************************************************************************/
-const static mc_txn_override_cfg_t tegra186_txn_override_cfgs[] = {
+static const mc_txn_override_cfg_t tegra186_txn_override_cfgs[] = {
mc_make_txn_override_cfg(BPMPW, CGID_TAG_ADR),
mc_make_txn_override_cfg(EQOSW, CGID_TAG_ADR),
mc_make_txn_override_cfg(NVJPGSWR, CGID_TAG_ADR),
diff --git a/plat/nxp/common/nv_storage/plat_nv_storage.c b/plat/nxp/common/nv_storage/plat_nv_storage.c
index af3b966..97d777e 100644
--- a/plat/nxp/common/nv_storage/plat_nv_storage.c
+++ b/plat/nxp/common/nv_storage/plat_nv_storage.c
@@ -93,7 +93,7 @@
uint8_t ready_to_write_val[sizeof(nv_app_data_t)];
uintptr_t nv_base_addr = NV_STORAGE_BASE_ADDR;
- assert((nv_base_addr + data_offset + data_size) > (nv_base_addr + F_SECTOR_ERASE_SZ));
+ assert((nv_base_addr + data_offset + data_size) <= (nv_base_addr + F_SECTOR_ERASE_SZ));
ret = fspi_init(NXP_FLEXSPI_ADDR, NXP_FLEXSPI_FLASH_ADDR);
diff --git a/plat/nxp/common/psci/plat_psci.c b/plat/nxp/common/psci/plat_psci.c
index 9281e97..f6dd7b3 100644
--- a/plat/nxp/common/psci/plat_psci.c
+++ b/plat/nxp/common/psci/plat_psci.c
@@ -350,7 +350,7 @@
else if (SOC_SYSTEM_STANDBY)
state->pwr_domain_state[PLAT_MAX_LVL] =
PLAT_MAX_RET_STATE;
- /* intentional fall-thru condition */
+ /* fallthrough */
case PWR_STATE_LVL_SYS:
if (pwrdn && SOC_SYSTEM_PWR_DWN)
state->pwr_domain_state[PLAT_SYS_LVL] =
@@ -358,7 +358,7 @@
else if (SOC_SYSTEM_STANDBY)
state->pwr_domain_state[PLAT_SYS_LVL] =
PLAT_MAX_RET_STATE;
- /* intentional fall-thru condition */
+ /* fallthrough */
case PWR_STATE_LVL_CLSTR:
if (pwrdn && SOC_CLUSTER_PWR_DWN)
state->pwr_domain_state[PLAT_CLSTR_LVL] =
@@ -366,7 +366,7 @@
else if (SOC_CLUSTER_STANDBY)
state->pwr_domain_state[PLAT_CLSTR_LVL] =
PLAT_MAX_RET_STATE;
- /* intentional fall-thru condition */
+ /* fallthrough */
case PWR_STATE_LVL_CORE:
stat = PSCI_E_SUCCESS;
diff --git a/plat/nxp/soc-ls1028a/soc.def b/plat/nxp/soc-ls1028a/soc.def
index c23c1bb..93275b3 100644
--- a/plat/nxp/soc-ls1028a/soc.def
+++ b/plat/nxp/soc-ls1028a/soc.def
@@ -70,8 +70,8 @@
BL2_HDR_LOC := 0x1800A000
# SoC ERRATAS to be enabled
-ERRATA_SOC_A008850 := 1
+# DDR ERRATA
ERRATA_DDR_A009803 := 1
ERRATA_DDR_A009942 := 1
ERRATA_DDR_A010165 := 1
diff --git a/plat/nxp/soc-ls1043a/soc.c b/plat/nxp/soc-ls1043a/soc.c
index 7badf8c..3e821d0 100644
--- a/plat/nxp/soc-ls1043a/soc.c
+++ b/plat/nxp/soc-ls1043a/soc.c
@@ -21,9 +21,7 @@
#ifdef POLICY_FUSE_PROVISION
#include <nxp_gpio.h>
#endif
-#if TRUSTED_BOARD_BOOT
#include <nxp_smmu.h>
-#endif
#include <nxp_timer.h>
#include <plat_console.h>
#include <plat_gic.h>
@@ -174,6 +172,12 @@
get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster);
plat_ls_interconnect_enter_coherency(num_clusters);
+ /*
+ * Unlock write access for SMMU SMMU_CBn_ACTLR in all Non-secure contexts.
+ */
+ smmu_cache_unlock(NXP_SMMU_ADDR);
+ INFO("SMMU Cache Unlocking is Configured.\n");
+
#if TRUSTED_BOARD_BOOT
uint32_t mode;
diff --git a/plat/nxp/soc-ls1043a/soc.mk b/plat/nxp/soc-ls1043a/soc.mk
index b6ce14e..0ebb377 100644
--- a/plat/nxp/soc-ls1043a/soc.mk
+++ b/plat/nxp/soc-ls1043a/soc.mk
@@ -19,8 +19,8 @@
# For Security Features
DISABLE_FUSE_WRITE := 1
-ifeq (${TRUSTED_BOARD_BOOT}, 1)
$(eval $(call SET_NXP_MAKE_FLAG,SMMU_NEEDED,BL2))
+ifeq (${TRUSTED_BOARD_BOOT}, 1)
$(eval $(call SET_NXP_MAKE_FLAG,SFP_NEEDED,BL2))
$(eval $(call SET_NXP_MAKE_FLAG,SNVS_NEEDED,BL2))
SECURE_BOOT := yes
diff --git a/plat/nxp/soc-ls1046a/soc.c b/plat/nxp/soc-ls1046a/soc.c
index d17e672..6dfea89 100644
--- a/plat/nxp/soc-ls1046a/soc.c
+++ b/plat/nxp/soc-ls1046a/soc.c
@@ -21,9 +21,7 @@
#ifdef POLICY_FUSE_PROVISION
#include <nxp_gpio.h>
#endif
-#if TRUSTED_BOARD_BOOT
#include <nxp_smmu.h>
-#endif
#include <nxp_timer.h>
#include <plat_console.h>
#include <plat_gic.h>
@@ -168,6 +166,12 @@
get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster);
plat_ls_interconnect_enter_coherency(num_clusters);
+ /*
+ * Unlock write access for SMMU SMMU_CBn_ACTLR in all Non-secure contexts.
+ */
+ smmu_cache_unlock(NXP_SMMU_ADDR);
+ INFO("SMMU Cache Unlocking is Configured.\n");
+
#if TRUSTED_BOARD_BOOT
uint32_t mode;
diff --git a/plat/nxp/soc-ls1046a/soc.def b/plat/nxp/soc-ls1046a/soc.def
index e6b37c0..50fc9c9 100644
--- a/plat/nxp/soc-ls1046a/soc.def
+++ b/plat/nxp/soc-ls1046a/soc.def
@@ -41,11 +41,11 @@
DDRPHY := NXP
# Area of OCRAM reserved by ROM code
-NXP_ROM_RSVD := 0x5900
+NXP_ROM_RSVD := 0x8000
# Max Size of CSF header. Required to define BL2 TEXT LIMIT in soc.def
# Input to CST create_hdr_esbc tool
-CSF_HDR_SZ := 0x3000
+CSF_HDR_SZ := 0x4000
# In IMAGE_BL2, compile time flag for handling Cache coherency
# with CAAM for BL2 running from OCRAM
diff --git a/plat/nxp/soc-ls1046a/soc.mk b/plat/nxp/soc-ls1046a/soc.mk
index 8207dcd..7644027 100644
--- a/plat/nxp/soc-ls1046a/soc.mk
+++ b/plat/nxp/soc-ls1046a/soc.mk
@@ -19,8 +19,8 @@
# For Security Features
DISABLE_FUSE_WRITE := 1
-ifeq (${TRUSTED_BOARD_BOOT}, 1)
$(eval $(call SET_NXP_MAKE_FLAG,SMMU_NEEDED,BL2))
+ifeq (${TRUSTED_BOARD_BOOT}, 1)
$(eval $(call SET_NXP_MAKE_FLAG,SFP_NEEDED,BL2))
$(eval $(call SET_NXP_MAKE_FLAG,SNVS_NEEDED,BL2))
SECURE_BOOT := yes
diff --git a/plat/nxp/soc-ls1088a/ls1088aqds/ddr_init.c b/plat/nxp/soc-ls1088a/ls1088aqds/ddr_init.c
index b7397ba..705463b 100644
--- a/plat/nxp/soc-ls1088a/ls1088aqds/ddr_init.c
+++ b/plat/nxp/soc-ls1088a/ls1088aqds/ddr_init.c
@@ -78,7 +78,5 @@
ERROR("DDR init failed.\n");
}
- erratum_a008850_post();
-
return dram_size;
}
diff --git a/plat/nxp/soc-ls1088a/ls1088ardb/ddr_init.c b/plat/nxp/soc-ls1088a/ls1088ardb/ddr_init.c
index c88583f..107871a 100644
--- a/plat/nxp/soc-ls1088a/ls1088ardb/ddr_init.c
+++ b/plat/nxp/soc-ls1088a/ls1088ardb/ddr_init.c
@@ -80,7 +80,5 @@
ERROR("DDR init failed.\n");
}
- erratum_a008850_post();
-
return dram_size;
}
diff --git a/plat/nxp/soc-ls1088a/soc.c b/plat/nxp/soc-ls1088a/soc.c
index 5f9f313..02d62ea 100644
--- a/plat/nxp/soc-ls1088a/soc.c
+++ b/plat/nxp/soc-ls1088a/soc.c
@@ -17,9 +17,7 @@
#include <lib/mmio.h>
#include <lib/xlat_tables/xlat_tables_v2.h>
#include <ls_interconnect.h>
-#if TRUSTED_BOARD_BOOT
#include <nxp_smmu.h>
-#endif
#include <nxp_timer.h>
#include <plat_console.h>
#include <plat_gic.h>
@@ -254,6 +252,12 @@
MT_DEVICE | MT_RW | MT_NS);
}
+ /*
+ * Unlock write access for SMMU SMMU_CBn_ACTLR in all Non-secure contexts.
+ */
+ smmu_cache_unlock(NXP_SMMU_ADDR);
+ INFO("SMMU Cache Unlocking is Configured.\n");
+
#if TRUSTED_BOARD_BOOT
uint32_t mode;
diff --git a/plat/nxp/soc-ls1088a/soc.def b/plat/nxp/soc-ls1088a/soc.def
index 25d0847..17c59ff 100644
--- a/plat/nxp/soc-ls1088a/soc.def
+++ b/plat/nxp/soc-ls1088a/soc.def
@@ -62,7 +62,6 @@
BL2_BASE := 0x1800a000
# SoC ERRATUM to be enabled
-ERRATA_SOC_A008850 := 1
# ARM Erratum
ERRATA_A53_855873 := 1
diff --git a/plat/nxp/soc-ls1088a/soc.mk b/plat/nxp/soc-ls1088a/soc.mk
index 83ac9d0..6e39461 100644
--- a/plat/nxp/soc-ls1088a/soc.mk
+++ b/plat/nxp/soc-ls1088a/soc.mk
@@ -23,12 +23,12 @@
# For Security Features
DISABLE_FUSE_WRITE := 1
+$(eval $(call SET_NXP_MAKE_FLAG,SMMU_NEEDED,BL2))
ifeq (${TRUSTED_BOARD_BOOT}, 1)
ifeq (${GENERATE_COT},1)
# Save Keys to be used by DDR FIP image
SAVE_KEYS=1
endif
-$(eval $(call SET_NXP_MAKE_FLAG,SMMU_NEEDED,BL2))
$(eval $(call SET_NXP_MAKE_FLAG,SFP_NEEDED,BL2))
$(eval $(call SET_NXP_MAKE_FLAG,SNVS_NEEDED,BL2))
# Used by create_pbl tool to
diff --git a/plat/nxp/soc-lx2160a/include/soc.h b/plat/nxp/soc-lx2160a/include/soc.h
index 7cc4a03..b781ff8 100644
--- a/plat/nxp/soc-lx2160a/include/soc.h
+++ b/plat/nxp/soc-lx2160a/include/soc.h
@@ -54,8 +54,31 @@
/* SVR Definition (not include major and minor rev) */
#define SVR_LX2160A 0x873601
+#define SVR_LX2160E 0x873610
+#define SVR_LX2160C 0x873600
+#define SVR_LX2160N 0x873611
#define SVR_LX2120A 0x873621
+#define SVR_LX2120E 0x873630
+#define SVR_LX2120C 0x873620
+#define SVR_LX2120N 0x873631
#define SVR_LX2080A 0x873603
+#define SVR_LX2080E 0x873612
+#define SVR_LX2080C 0x873602
+#define SVR_LX2080N 0x873613
+
+/* SVR Definition of SoC LX2162A. */
+#define SVR_LX2162A 0x873609
+#define SVR_LX2162E 0x873618
+#define SVR_LX2162C 0x873608
+#define SVR_LX2162N 0x873619
+#define SVR_LX2122A 0x873629
+#define SVR_LX2122E 0x873638
+#define SVR_LX2122C 0x873628
+#define SVR_LX2122N 0x873639
+#define SVR_LX2082A 0x87360b
+#define SVR_LX2082E 0x87361a
+#define SVR_LX2082C 0x87360a
+#define SVR_LX2082N 0x87361b
/* Number of cores in platform */
/* Used by common code for array initialization */
diff --git a/plat/nxp/soc-lx2160a/soc.c b/plat/nxp/soc-lx2160a/soc.c
index 2209fda..427189d 100644
--- a/plat/nxp/soc-lx2160a/soc.c
+++ b/plat/nxp/soc-lx2160a/soc.c
@@ -23,9 +23,7 @@
#ifdef POLICY_FUSE_PROVISION
#include <nxp_gpio.h>
#endif
-#if TRUSTED_BOARD_BOOT
#include <nxp_smmu.h>
-#endif
#include <nxp_timer.h>
#include <plat_console.h>
#include <plat_gic.h>
@@ -37,6 +35,9 @@
#include <errata.h>
#include <ls_interrupt_mgmt.h>
+#ifdef CONFIG_OCRAM_ECC_EN
+#include <ocram.h>
+#endif
#include "plat_common.h"
#ifdef NXP_NV_SW_MAINT_LAST_EXEC_DATA
#include <plat_nv_storage.h>
@@ -48,9 +49,32 @@
#include "soc.h"
static struct soc_type soc_list[] = {
+ /* SoC LX2160A */
SOC_ENTRY(LX2160A, LX2160A, 8, 2),
+ SOC_ENTRY(LX2160E, LX2160E, 8, 2),
+ SOC_ENTRY(LX2160C, LX2160C, 8, 2),
+ SOC_ENTRY(LX2160N, LX2160N, 8, 2),
SOC_ENTRY(LX2080A, LX2080A, 8, 1),
+ SOC_ENTRY(LX2080E, LX2080E, 8, 1),
+ SOC_ENTRY(LX2080C, LX2080C, 8, 1),
+ SOC_ENTRY(LX2080N, LX2080N, 8, 1),
SOC_ENTRY(LX2120A, LX2120A, 6, 2),
+ SOC_ENTRY(LX2120E, LX2120E, 6, 2),
+ SOC_ENTRY(LX2120C, LX2120C, 6, 2),
+ SOC_ENTRY(LX2120N, LX2120N, 6, 2),
+ /* SoC LX2162A */
+ SOC_ENTRY(LX2162A, LX2162A, 8, 2),
+ SOC_ENTRY(LX2162E, LX2162E, 8, 2),
+ SOC_ENTRY(LX2162C, LX2162C, 8, 2),
+ SOC_ENTRY(LX2162N, LX2162N, 8, 2),
+ SOC_ENTRY(LX2082A, LX2082A, 8, 1),
+ SOC_ENTRY(LX2082E, LX2082E, 8, 1),
+ SOC_ENTRY(LX2082C, LX2082C, 8, 1),
+ SOC_ENTRY(LX2082N, LX2082N, 8, 1),
+ SOC_ENTRY(LX2122A, LX2122A, 6, 2),
+ SOC_ENTRY(LX2122E, LX2122E, 6, 2),
+ SOC_ENTRY(LX2122C, LX2122C, 6, 2),
+ SOC_ENTRY(LX2122N, LX2122N, 6, 2),
};
static dcfg_init_info_t dcfg_init_data = {
@@ -215,6 +239,9 @@
******************************************************************************/
void soc_early_init(void)
{
+#ifdef CONFIG_OCRAM_ECC_EN
+ ocram_init(NXP_OCRAM_ADDR, NXP_OCRAM_SIZE);
+#endif
dcfg_init(&dcfg_init_data);
#ifdef POLICY_FUSE_PROVISION
gpio_init(&gpio_init_data);
@@ -257,6 +284,12 @@
sfp_init(NXP_SFP_ADDR);
#endif
+ /*
+ * Unlock write access for SMMU SMMU_CBn_ACTLR in all Non-secure contexts.
+ */
+ smmu_cache_unlock(NXP_SMMU_ADDR);
+ INFO("SMMU Cache Unlocking is Configured.\n");
+
#if TRUSTED_BOARD_BOOT
uint32_t mode;
@@ -451,8 +484,8 @@
/* low-level init of the soc */
soc_init_start();
- soc_init_percpu();
_init_global_data();
+ soc_init_percpu();
_initialize_psci();
if (ccn_get_part0_id(NXP_CCN_ADDR) != CCN_508_PART0_ID) {
diff --git a/plat/nxp/soc-lx2160a/soc.def b/plat/nxp/soc-lx2160a/soc.def
index 81d6744..0442962 100644
--- a/plat/nxp/soc-lx2160a/soc.def
+++ b/plat/nxp/soc-lx2160a/soc.def
@@ -114,3 +114,6 @@
# enable dynamic memory mapping
PLAT_XLAT_TABLES_DYNAMIC := 1
+
+# OCRAM ECC Enabled
+OCRAM_ECC_EN := yes
diff --git a/plat/nxp/soc-lx2160a/soc.mk b/plat/nxp/soc-lx2160a/soc.mk
index 75a3af2..239442c 100644
--- a/plat/nxp/soc-lx2160a/soc.mk
+++ b/plat/nxp/soc-lx2160a/soc.mk
@@ -36,12 +36,12 @@
# For Security Features
DISABLE_FUSE_WRITE := 1
+$(eval $(call SET_NXP_MAKE_FLAG,SMMU_NEEDED,BL2))
ifeq (${TRUSTED_BOARD_BOOT}, 1)
ifeq (${GENERATE_COT},1)
# Save Keys to be used by DDR FIP image
SAVE_KEYS=1
endif
-$(eval $(call SET_NXP_MAKE_FLAG,SMMU_NEEDED,BL2))
$(eval $(call SET_NXP_MAKE_FLAG,SFP_NEEDED,BL2))
$(eval $(call SET_NXP_MAKE_FLAG,SNVS_NEEDED,BL2))
# Used by create_pbl tool to
diff --git a/plat/qemu/common/qemu_bl2_mem_params_desc.c b/plat/qemu/common/qemu_bl2_mem_params_desc.c
index 5af3a22..bb1797d 100644
--- a/plat/qemu/common/qemu_bl2_mem_params_desc.c
+++ b/plat/qemu/common/qemu_bl2_mem_params_desc.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -9,6 +9,18 @@
#include <common/desc_image_load.h>
#include <plat/common/platform.h>
+#define SP_PKG_ENTRY(id) \
+ { \
+ .image_id = (id), \
+ SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY, VERSION_2, \
+ entry_point_info_t, \
+ SECURE | NON_EXECUTABLE), \
+ SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY, \
+ VERSION_2, image_info_t, \
+ IMAGE_ATTRIB_SKIP_LOADING), \
+ .next_handoff_image_id = INVALID_IMAGE_ID, \
+ }
+
/*******************************************************************************
* Following descriptor provides BL image/ep information that gets used
* by BL2 to load the images and also subset of this information is
@@ -122,6 +134,48 @@
#endif
.next_handoff_image_id = INVALID_IMAGE_ID,
},
+
+#if defined(SPD_spmd)
+ /* Fill TOS_FW_CONFIG related information */
+ {
+ .image_id = TOS_FW_CONFIG_ID,
+ SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
+ VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
+ SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
+ VERSION_2, image_info_t, 0),
+ .image_info.image_base = TOS_FW_CONFIG_BASE,
+ .image_info.image_max_size = TOS_FW_CONFIG_LIMIT -
+ TOS_FW_CONFIG_BASE,
+ .next_handoff_image_id = INVALID_IMAGE_ID,
+ },
+
+#if SPMD_SPM_AT_SEL2
+ /* Fill TB_FW_CONFIG related information */
+ {
+ .image_id = TB_FW_CONFIG_ID,
+ SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
+ VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
+ SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
+ VERSION_2, image_info_t, 0),
+ .image_info.image_base = TB_FW_CONFIG_BASE,
+ .image_info.image_max_size = TB_FW_CONFIG_LIMIT - TB_FW_CONFIG_BASE,
+ .next_handoff_image_id = INVALID_IMAGE_ID,
+ },
+
+ /*
+ * Empty entries for SP packages to be filled in according to
+ * TB_FW_CONFIG.
+ */
+ SP_PKG_ENTRY(SP_PKG1_ID),
+ SP_PKG_ENTRY(SP_PKG2_ID),
+ SP_PKG_ENTRY(SP_PKG3_ID),
+ SP_PKG_ENTRY(SP_PKG4_ID),
+ SP_PKG_ENTRY(SP_PKG5_ID),
+ SP_PKG_ENTRY(SP_PKG6_ID),
+ SP_PKG_ENTRY(SP_PKG7_ID),
+ SP_PKG_ENTRY(SP_PKG8_ID),
+#endif
+#endif
# endif /* QEMU_LOAD_BL32 */
/* Fill BL33 related information */
diff --git a/plat/qemu/common/qemu_bl2_setup.c b/plat/qemu/common/qemu_bl2_setup.c
index 2c0da15..be55877 100644
--- a/plat/qemu/common/qemu_bl2_setup.c
+++ b/plat/qemu/common/qemu_bl2_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -16,6 +16,7 @@
#include <common/debug.h>
#include <common/desc_image_load.h>
#include <common/fdt_fixup.h>
+#include <common/fdt_wrappers.h>
#include <lib/optee_utils.h>
#include <lib/utils.h>
#include <plat/common/platform.h>
@@ -140,6 +141,48 @@
return spsr;
}
+#if defined(SPD_spmd) && SPMD_SPM_AT_SEL2
+static int load_sps_from_tb_fw_config(struct image_info *image_info)
+{
+ void *dtb = (void *)image_info->image_base;
+ const char *compat_str = "arm,sp";
+ const struct fdt_property *uuid;
+ uint32_t load_addr;
+ const char *name;
+ int sp_node;
+ int node;
+
+ node = fdt_node_offset_by_compatible(dtb, -1, compat_str);
+ if (node < 0) {
+ ERROR("Can't find %s in TB_FW_CONFIG", compat_str);
+ return -1;
+ }
+
+ fdt_for_each_subnode(sp_node, dtb, node) {
+ name = fdt_get_name(dtb, sp_node, NULL);
+ if (name == NULL) {
+ ERROR("Can't get name of node in dtb\n");
+ return -1;
+ }
+ uuid = fdt_get_property(dtb, sp_node, "uuid", NULL);
+ if (uuid == NULL) {
+ ERROR("Can't find property uuid in node %s", name);
+ return -1;
+ }
+ if (fdt_read_uint32(dtb, sp_node, "load-address",
+ &load_addr) < 0) {
+ ERROR("Can't read load-address in node %s", name);
+ return -1;
+ }
+ if (qemu_io_register_sp_pkg(name, uuid->data, load_addr) < 0) {
+ return -1;
+ }
+ }
+
+ return 0;
+}
+#endif /*defined(SPD_spmd) && SPMD_SPM_AT_SEL2*/
+
static int qemu_bl2_handle_post_image_load(unsigned int image_id)
{
int err = 0;
@@ -149,8 +192,7 @@
bl_mem_params_node_t *paged_mem_params = NULL;
#endif
#if defined(SPD_spmd)
- unsigned int mode_rw = MODE_RW_64;
- uint64_t pagable_part = 0;
+ bl_mem_params_node_t *bl32_mem_params = NULL;
#endif
assert(bl_mem_params);
@@ -170,17 +212,18 @@
if (err != 0) {
WARN("OPTEE header parse error.\n");
}
-#if defined(SPD_spmd)
- mode_rw = bl_mem_params->ep_info.args.arg0;
- pagable_part = bl_mem_params->ep_info.args.arg1;
-#endif
#endif
-#if defined(SPD_spmd)
- bl_mem_params->ep_info.args.arg0 = ARM_PRELOADED_DTB_BASE;
- bl_mem_params->ep_info.args.arg1 = pagable_part;
- bl_mem_params->ep_info.args.arg2 = mode_rw;
- bl_mem_params->ep_info.args.arg3 = 0;
+#if defined(SPMC_OPTEE)
+ /*
+ * Explicit zeroes to unused registers since they may have
+ * been populated by parse_optee_header() above.
+ *
+ * OP-TEE expects system DTB in x2 and TOS_FW_CONFIG in x0,
+ * the latter is filled in below for TOS_FW_CONFIG_ID and
+ * applies to any other SPMC too.
+ */
+ bl_mem_params->ep_info.args.arg2 = ARM_PRELOADED_DTB_BASE;
#elif defined(SPD_opteed)
/*
* OP-TEE expect to receive DTB address in x2.
@@ -224,6 +267,19 @@
bl_mem_params->ep_info.spsr = qemu_get_spsr_for_bl33_entry();
break;
+#ifdef SPD_spmd
+#if SPMD_SPM_AT_SEL2
+ case TB_FW_CONFIG_ID:
+ err = load_sps_from_tb_fw_config(&bl_mem_params->image_info);
+ break;
+#endif
+ case TOS_FW_CONFIG_ID:
+ /* An SPMC expects TOS_FW_CONFIG in x0/r0 */
+ bl32_mem_params = get_bl_mem_params_node(BL32_IMAGE_ID);
+ bl32_mem_params->ep_info.args.arg0 =
+ bl_mem_params->image_info.image_base;
+ break;
+#endif
default:
/* Do nothing in default case */
break;
diff --git a/plat/qemu/common/qemu_common.c b/plat/qemu/common/qemu_common.c
index 0c184f4..23ac581 100644
--- a/plat/qemu/common/qemu_common.c
+++ b/plat/qemu/common/qemu_common.c
@@ -10,6 +10,7 @@
#include <arch_helpers.h>
#include <common/bl_common.h>
#include <lib/xlat_tables/xlat_tables_v2.h>
+#include <services/el3_spmc_ffa_memory.h>
#include <plat/common/platform.h>
#include "qemu_private.h"
@@ -100,7 +101,7 @@
#if SPM_MM
MAP_NS_DRAM0,
QEMU_SPM_BUF_EL3_MMAP,
-#else
+#elif !SPMC_AT_EL3
MAP_BL32_MEM,
#endif
{0}
@@ -167,3 +168,30 @@
return get_mbedtls_heap_helper(heap_addr, heap_size);
}
#endif
+
+#if SPMC_AT_EL3
+/*
+ * When using the EL3 SPMC implementation allocate the datastore
+ * for tracking shared memory descriptors in normal memory.
+ */
+#define PLAT_SPMC_SHMEM_DATASTORE_SIZE 64 * 1024
+
+uint8_t plat_spmc_shmem_datastore[PLAT_SPMC_SHMEM_DATASTORE_SIZE];
+
+int plat_spmc_shmem_datastore_get(uint8_t **datastore, size_t *size)
+{
+ *datastore = plat_spmc_shmem_datastore;
+ *size = PLAT_SPMC_SHMEM_DATASTORE_SIZE;
+ return 0;
+}
+
+int plat_spmc_shmem_begin(struct ffa_mtd *desc)
+{
+ return 0;
+}
+
+int plat_spmc_shmem_reclaim(struct ffa_mtd *desc)
+{
+ return 0;
+}
+#endif
diff --git a/plat/qemu/common/qemu_io_storage.c b/plat/qemu/common/qemu_io_storage.c
index 1107e44..4c61b14 100644
--- a/plat/qemu/common/qemu_io_storage.c
+++ b/plat/qemu/common/qemu_io_storage.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -11,6 +11,8 @@
#include <common/bl_common.h>
#include <common/debug.h>
+#include <common/desc_image_load.h>
+#include <common/uuid.h>
#include <drivers/io/io_driver.h>
#include <drivers/io/io_encrypted.h>
#include <drivers/io/io_fip.h>
@@ -20,10 +22,14 @@
#include <lib/semihosting.h>
#include <tools_share/firmware_image_package.h>
+#include "qemu_private.h"
+
/* Semihosting filenames */
#define BL2_IMAGE_NAME "bl2.bin"
#define BL31_IMAGE_NAME "bl31.bin"
#define BL32_IMAGE_NAME "bl32.bin"
+#define TB_FW_CONFIG_NAME "tb_fw_config.dtb"
+#define TOS_FW_CONFIG_NAME "tos_fw_config.dtb"
#define BL32_EXTRA1_IMAGE_NAME "bl32_extra1.bin"
#define BL32_EXTRA2_IMAGE_NAME "bl32_extra2.bin"
#define BL33_IMAGE_NAME "bl33.bin"
@@ -78,6 +84,14 @@
.uuid = UUID_SECURE_PAYLOAD_BL32_EXTRA2,
};
+static const io_uuid_spec_t tb_fw_config_uuid_spec = {
+ .uuid = UUID_TB_FW_CONFIG,
+};
+
+static const io_uuid_spec_t tos_fw_config_uuid_spec = {
+ .uuid = UUID_TOS_FW_CONFIG,
+};
+
static const io_uuid_spec_t bl33_uuid_spec = {
.uuid = UUID_NON_TRUSTED_FIRMWARE_BL33,
};
@@ -137,6 +151,14 @@
.path = BL32_EXTRA2_IMAGE_NAME,
.mode = FOPEN_MODE_RB
},
+ [TB_FW_CONFIG_ID] = {
+ .path = TB_FW_CONFIG_NAME,
+ .mode = FOPEN_MODE_RB
+ },
+ [TOS_FW_CONFIG_ID] = {
+ .path = TOS_FW_CONFIG_NAME,
+ .mode = FOPEN_MODE_RB
+ },
[BL33_IMAGE_ID] = {
.path = BL33_IMAGE_NAME,
.mode = FOPEN_MODE_RB
@@ -252,6 +274,16 @@
open_fip
},
#endif
+ [TB_FW_CONFIG_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&tb_fw_config_uuid_spec,
+ open_fip
+ },
+ [TOS_FW_CONFIG_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&tos_fw_config_uuid_spec,
+ open_fip
+ },
[BL33_IMAGE_ID] = {
&fip_dev_handle,
(uintptr_t)&bl33_uuid_spec,
@@ -301,6 +333,80 @@
#endif /* TRUSTED_BOARD_BOOT */
};
+#if defined(SPD_spmd)
+static struct sp_pkg {
+ struct plat_io_policy policy;
+ io_file_spec_t sh_file_spec;
+ uint8_t uuid[UUID_BYTES_LENGTH];
+ char path[80];
+} sp_pkgs[MAX_SP_IDS];
+static unsigned int sp_pkg_count;
+
+int qemu_io_register_sp_pkg(const char *name, const char *uuid,
+ uintptr_t load_addr)
+{
+ struct sp_pkg *pkg;
+ bl_mem_params_node_t *mem_params;
+
+ if (sp_pkg_count == MAX_SP_IDS) {
+ INFO("Reached Max number of SPs\n");
+ return -1;
+ }
+ mem_params = get_bl_mem_params_node(SP_PKG1_ID + sp_pkg_count);
+ if (mem_params == NULL) {
+ ERROR("Can't find SP_PKG ID %u (SP_PKG%u_ID)\n",
+ SP_PKG1_ID + sp_pkg_count, sp_pkg_count);
+ return -1;
+ }
+ pkg = sp_pkgs + sp_pkg_count;
+
+ if (read_uuid(pkg->uuid, (char *)uuid)) {
+ return -1;
+ }
+
+ strlcpy(pkg->path, name, sizeof(pkg->path));
+ strlcat(pkg->path, ".pkg", sizeof(pkg->path));
+
+ pkg->policy.dev_handle = &fip_dev_handle;
+ pkg->policy.image_spec = (uintptr_t)&pkg->uuid;
+ pkg->policy.check = open_fip;
+ pkg->sh_file_spec.path = pkg->path;
+ pkg->sh_file_spec.mode = FOPEN_MODE_RB;
+
+ mem_params->image_info.image_base = load_addr;
+ mem_params->image_info.image_max_size = SZ_4M;
+ mem_params->image_info.h.attr &= ~IMAGE_ATTRIB_SKIP_LOADING;
+
+ sp_pkg_count++;
+
+ return 0;
+}
+#endif /*SPD_spmd*/
+
+static const io_file_spec_t *get_io_file_spec(unsigned int image_id)
+{
+#if defined(SPD_spmd)
+ if (image_id >= SP_PKG1_ID && image_id <= SP_PKG8_ID) {
+ return &sp_pkgs[image_id - SP_PKG1_ID].sh_file_spec;
+ }
+#endif
+
+ assert(image_id < ARRAY_SIZE(sh_file_spec));
+ return &sh_file_spec[image_id];
+}
+
+static const struct plat_io_policy *get_io_policy(unsigned int image_id)
+{
+#if defined(SPD_spmd)
+ if (image_id >= SP_PKG1_ID && image_id <= SP_PKG8_ID) {
+ return &sp_pkgs[image_id - SP_PKG1_ID].policy;
+ }
+#endif
+
+ assert(image_id < ARRAY_SIZE(policies));
+ return &policies[image_id];
+}
+
static int open_fip(const uintptr_t spec)
{
int result;
@@ -413,11 +519,13 @@
static int get_alt_image_source(unsigned int image_id, uintptr_t *dev_handle,
uintptr_t *image_spec)
{
- int result = open_semihosting((const uintptr_t)&sh_file_spec[image_id]);
+ const io_file_spec_t *spec = get_io_file_spec(image_id);
+ int result;
+ result = open_semihosting((const uintptr_t)spec);
if (result == 0) {
*dev_handle = sh_dev_handle;
- *image_spec = (uintptr_t)&sh_file_spec[image_id];
+ *image_spec = (uintptr_t)spec;
}
return result;
@@ -430,12 +538,9 @@
int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle,
uintptr_t *image_spec)
{
+ const struct plat_io_policy *policy = get_io_policy(image_id);
int result;
- const struct plat_io_policy *policy;
-
- assert(image_id < ARRAY_SIZE(policies));
- policy = &policies[image_id];
result = policy->check(policy->image_spec);
if (result == 0) {
*image_spec = policy->image_spec;
diff --git a/plat/qemu/common/qemu_private.h b/plat/qemu/common/qemu_private.h
index c313cb6..159c44f 100644
--- a/plat/qemu/common/qemu_private.h
+++ b/plat/qemu/common/qemu_private.h
@@ -26,6 +26,8 @@
unsigned long coh_start, unsigned long coh_limit);
void plat_qemu_io_setup(void);
+int qemu_io_register_sp_pkg(const char *name, const char *uuid,
+ uintptr_t load_addr);
unsigned int plat_qemu_calc_core_pos(u_register_t mpidr);
void qemu_console_init(void);
diff --git a/plat/qemu/common/qemu_spmd_manifest.c b/plat/qemu/common/qemu_spmd_manifest.c
deleted file mode 100644
index fd46e26..0000000
--- a/plat/qemu/common/qemu_spmd_manifest.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <assert.h>
-
-#include <services/spm_core_manifest.h>
-
-#include <plat/common/platform.h>
-#include <platform_def.h>
-
-int plat_spm_core_manifest_load(spmc_manifest_attribute_t *manifest,
- const void *pm_addr)
-{
- entry_point_info_t *ep_info = bl31_plat_get_next_image_ep_info(SECURE);
-
- assert(ep_info != NULL);
- assert(manifest != NULL);
-
- manifest->major_version = 1;
- manifest->minor_version = 0;
- manifest->exec_state = ep_info->args.arg2;
- manifest->load_address = BL32_BASE;
- manifest->entrypoint = BL32_BASE;
- manifest->binary_size = BL32_LIMIT - BL32_BASE;
- manifest->spmc_id = 0x8000;
-
- return 0;
-}
diff --git a/plat/qemu/qemu/include/platform_def.h b/plat/qemu/qemu/include/platform_def.h
index a22fbe5..803f8e2 100644
--- a/plat/qemu/qemu/include/platform_def.h
+++ b/plat/qemu/qemu/include/platform_def.h
@@ -118,6 +118,11 @@
#define BL_RAM_BASE (SHARED_RAM_BASE + SHARED_RAM_SIZE)
#define BL_RAM_SIZE (SEC_SRAM_SIZE - SHARED_RAM_SIZE)
+#define TB_FW_CONFIG_BASE BL_RAM_BASE
+#define TB_FW_CONFIG_LIMIT (TB_FW_CONFIG_BASE + PAGE_SIZE)
+#define TOS_FW_CONFIG_BASE TB_FW_CONFIG_LIMIT
+#define TOS_FW_CONFIG_LIMIT (TOS_FW_CONFIG_BASE + PAGE_SIZE)
+
/*
* BL1 specific defines.
*
@@ -183,8 +188,8 @@
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
-#define MAX_MMAP_REGIONS 11
-#define MAX_XLAT_TABLES 6
+#define MAX_MMAP_REGIONS (11 + MAX_MMAP_REGIONS_SPMC)
+#define MAX_XLAT_TABLES (6 + MAX_XLAT_TABLES_SPMC)
#define MAX_IO_DEVICES 4
#define MAX_IO_HANDLES 4
@@ -275,4 +280,32 @@
*/
#define PLAT_EVENT_LOG_MAX_SIZE UL(0x400)
+#if SPMC_AT_EL3
+/*
+ * Number of Secure Partitions supported.
+ * SPMC at EL3, uses this count to configure the maximum number of
+ * supported secure partitions.
+ */
+#define SECURE_PARTITION_COUNT 1
+
+/*
+ * Number of Logical Partitions supported.
+ * SPMC at EL3, uses this count to configure the maximum number of
+ * supported logical partitions.
+ */
+#define MAX_EL3_LP_DESCS_COUNT 0
+
+/*
+ * Number of Normal World Partitions supported.
+ * SPMC at EL3, uses this count to configure the maximum number of
+ * supported normal world partitions.
+ */
+#define NS_PARTITION_COUNT 1
+
+#define MAX_MMAP_REGIONS_SPMC 2
+#define MAX_XLAT_TABLES_SPMC 4
+#else
+#define MAX_MMAP_REGIONS_SPMC 0
+#define MAX_XLAT_TABLES_SPMC 0
+#endif
#endif /* PLATFORM_DEF_H */
diff --git a/plat/qemu/qemu/platform.mk b/plat/qemu/qemu/platform.mk
index 6becc32..4cbce9d 100644
--- a/plat/qemu/qemu/platform.mk
+++ b/plat/qemu/qemu/platform.mk
@@ -109,7 +109,6 @@
endif
BL2_SOURCES += plat/qemu/qemu/qemu_measured_boot.c \
- plat/qemu/qemu/qemu_common_measured_boot.c \
plat/qemu/qemu/qemu_helpers.c \
${EVENT_LOG_SOURCES}
@@ -162,7 +161,8 @@
${PLAT_QEMU_COMMON_PATH}/qemu_image_load.c \
common/fdt_fixup.c \
common/fdt_wrappers.c \
- common/desc_image_load.c
+ common/desc_image_load.c \
+ common/uuid.c
ifeq ($(add-lib-optee),yes)
BL2_SOURCES += lib/optee/optee_utils.c
@@ -211,8 +211,17 @@
${PLAT_QEMU_COMMON_PATH}/qemu_bl31_setup.c \
${QEMU_GIC_SOURCES}
+# Pointer Authentication sources
+ifeq (${ENABLE_PAUTH}, 1)
+PLAT_BL_COMMON_SOURCES += plat/arm/common/aarch64/arm_pauth.c \
+ lib/extensions/pauth/pauth_helpers.S
+endif
+
ifeq (${SPD},spmd)
-BL31_SOURCES += plat/qemu/common/qemu_spmd_manifest.c
+BL31_SOURCES += plat/common/plat_spmd_manifest.c \
+ common/uuid.c \
+ ${LIBFDT_SRCS} \
+ ${FDT_WRAPPERS_SOURCES}
endif
endif
@@ -231,6 +240,20 @@
else
$(eval $(call TOOL_ADD_IMG,bl32_extra2,--tos-fw-extra2))
endif
+endif
+
+ifneq ($(QEMU_TB_FW_CONFIG_DTS),)
+FDT_SOURCES += ${QEMU_TB_FW_CONFIG_DTS}
+QEMU_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${QEMU_TB_FW_CONFIG_DTS})).dtb
+# Add the TB_FW_CONFIG to FIP
+$(eval $(call TOOL_ADD_PAYLOAD,${QEMU_TB_FW_CONFIG},--tb-fw-config,${QEMU_TB_FW_CONFIG}))
+endif
+
+ifneq ($(QEMU_TOS_FW_CONFIG_DTS),)
+FDT_SOURCES += ${QEMU_TOS_FW_CONFIG_DTS}
+QEMU_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${QEMU_TOS_FW_CONFIG_DTS})).dtb
+# Add the TOS_FW_CONFIG to FIP
+$(eval $(call TOOL_ADD_PAYLOAD,${QEMU_TOS_FW_CONFIG},--tos-fw-config,${QEMU_TOS_FW_CONFIG}))
endif
SEPARATE_CODE_AND_RODATA := 1
diff --git a/plat/qemu/qemu/qemu_common_measured_boot.c b/plat/qemu/qemu/qemu_common_measured_boot.c
deleted file mode 100644
index 41f7f87..0000000
--- a/plat/qemu/qemu/qemu_common_measured_boot.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Copyright (c) 2022, Linaro.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <assert.h>
-#include <stdint.h>
-
-#include <common/desc_image_load.h>
-#include <drivers/measured_boot/event_log/event_log.h>
-#include <plat/common/platform.h>
-
-extern event_log_metadata_t qemu_event_log_metadata[];
-
-const event_log_metadata_t *plat_event_log_get_metadata(void)
-{
- return qemu_event_log_metadata;
-}
-
-int plat_mboot_measure_image(unsigned int image_id, image_info_t *image_data)
-{
- /* Calculate image hash and record data in Event Log */
- int err = event_log_measure_and_record(image_data->image_base,
- image_data->image_size,
- image_id);
- if (err != 0) {
- ERROR("%s%s image id %u (%i)\n",
- "Failed to ", "record", image_id, err);
- return err;
- }
-
- return 0;
-}
diff --git a/plat/qemu/qemu/qemu_measured_boot.c b/plat/qemu/qemu/qemu_measured_boot.c
index d9e475a..122bb23 100644
--- a/plat/qemu/qemu/qemu_measured_boot.c
+++ b/plat/qemu/qemu/qemu_measured_boot.c
@@ -9,6 +9,7 @@
#include <drivers/measured_boot/event_log/event_log.h>
#include <plat/common/common_def.h>
+#include <plat/common/platform.h>
#include <tools_share/tbbr_oid.h>
#include "../common/qemu_private.h"
@@ -17,8 +18,8 @@
static uint8_t event_log[PLAT_EVENT_LOG_MAX_SIZE];
static uint64_t event_log_base;
-/* FVP table with platform specific image IDs, names and PCRs */
-const event_log_metadata_t qemu_event_log_metadata[] = {
+/* QEMU table with platform specific image IDs, names and PCRs */
+static const event_log_metadata_t qemu_event_log_metadata[] = {
{ BL31_IMAGE_ID, EVLOG_BL31_STRING, PCR_0 },
{ BL32_IMAGE_ID, EVLOG_BL32_STRING, PCR_0 },
{ BL32_EXTRA1_IMAGE_ID, EVLOG_BL32_EXTRA1_STRING, PCR_0 },
@@ -101,3 +102,19 @@
dump_event_log((uint8_t *)event_log_base, event_log_cur_size);
}
+
+int plat_mboot_measure_image(unsigned int image_id, image_info_t *image_data)
+{
+ /* Calculate image hash and record data in Event Log */
+ int err = event_log_measure_and_record(image_data->image_base,
+ image_data->image_size,
+ image_id,
+ qemu_event_log_metadata);
+ if (err != 0) {
+ ERROR("%s%s image id %u (%i)\n",
+ "Failed to ", "record", image_id, err);
+ return err;
+ }
+
+ return 0;
+}
diff --git a/plat/qemu/qemu_sbsa/platform.mk b/plat/qemu/qemu_sbsa/platform.mk
index 5a6b1e1..2393b39 100644
--- a/plat/qemu/qemu_sbsa/platform.mk
+++ b/plat/qemu/qemu_sbsa/platform.mk
@@ -123,5 +123,6 @@
ARM_PRELOADED_DTB_BASE := PLAT_QEMU_DT_BASE
$(eval $(call add_define,ARM_PRELOADED_DTB_BASE))
-# Do not enable SVE
-ENABLE_SVE_FOR_NS := 0
+# Later QEMU versions support SME and SVE.
+ENABLE_SVE_FOR_NS := 1
+ENABLE_SME_FOR_NS := 1
diff --git a/plat/qti/common/src/qti_pm.c b/plat/qti/common/src/qti_pm.c
index 5f1b7aa..ae361e9 100644
--- a/plat/qti/common/src/qti_pm.c
+++ b/plat/qti/common/src/qti_pm.c
@@ -47,8 +47,7 @@
#define QTI_CORE_PWRDN_EN_MASK 1
/* cpu power control happens to be same across all CPUs */
-_DEFINE_SYSREG_WRITE_FUNC(cpu_pwrctrl_val, S3_0_C15_C2_7)
-_DEFINE_SYSREG_READ_FUNC(cpu_pwrctrl_val, S3_0_C15_C2_7)
+DEFINE_RENAME_SYSREG_RW_FUNCS(cpu_pwrctrl_val, S3_0_C15_C2_7)
const unsigned int qti_pm_idle_states[] = {
qti_make_pwrstate_lvl0(QTI_LOCAL_STATE_OFF,
diff --git a/plat/st/common/bl2_io_storage.c b/plat/st/common/bl2_io_storage.c
index b271ed6..c935b7d 100644
--- a/plat/st/common/bl2_io_storage.c
+++ b/plat/st/common/bl2_io_storage.c
@@ -25,7 +25,6 @@
#include <drivers/raw_nand.h>
#include <drivers/spi_nand.h>
#include <drivers/spi_nor.h>
-#include <drivers/st/io_mmc.h>
#include <drivers/st/stm32_fmc2_nand.h>
#include <drivers/st/stm32_qspi.h>
#include <drivers/st/stm32_sdmmc2.h>
@@ -607,7 +606,7 @@
* - we already boot FWU_MAX_TRIAL_REBOOT times in trial mode.
* we select the previous_active_index.
*/
-#define INVALID_BOOT_IDX 0xFFFFFFFF
+#define INVALID_BOOT_IDX 0xFFFFFFFFU
uint32_t plat_fwu_get_boot_idx(void)
{
diff --git a/plat/st/common/include/stm32mp_common.h b/plat/st/common/include/stm32mp_common.h
index a5316b6..bb3401f 100644
--- a/plat/st/common/include/stm32mp_common.h
+++ b/plat/st/common/include/stm32mp_common.h
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2018-2022, STMicroelectronics - All Rights Reserved
+ * Copyright (C) 2018-2023, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -35,6 +35,9 @@
/* Return the base address of the RCC peripheral */
uintptr_t stm32mp_rcc_base(void);
+void stm32mp_gic_pcpu_init(void);
+void stm32mp_gic_init(void);
+
/* Check MMU status to allow spinlock use */
bool stm32mp_lock_available(void);
@@ -113,12 +116,15 @@
int stm32mp_map_ddr_non_cacheable(void);
int stm32mp_unmap_ddr(void);
-/* Functions to save and get boot peripheral info */
-void stm32_save_boot_interface(uint32_t interface, uint32_t instance);
+/* Function to save boot info */
+void stm32_save_boot_info(boot_api_context_t *boot_context);
+/* Function to get boot peripheral info */
void stm32_get_boot_interface(uint32_t *interface, uint32_t *instance);
+/* Function to get BOOT_MODE backup register address */
+uintptr_t stm32_get_bkpr_boot_mode_addr(void);
-/* Functions to save and get boot authentication status and partition used */
-void stm32_save_boot_auth(uint32_t auth_status, uint32_t boot_partition);
+/* Display board information from the value found in OTP fuse */
+void stm32_display_board_info(uint32_t board_id);
#if PSA_FWU_SUPPORT
void stm32mp1_fwu_set_boot_idx(void);
diff --git a/plat/st/common/include/stm32mp_efi.h b/plat/st/common/include/stm32mp_efi.h
index 490560f..af9165f 100644
--- a/plat/st/common/include/stm32mp_efi.h
+++ b/plat/st/common/include/stm32mp_efi.h
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: BSD-3-Clause */
/*
* Copyright (c) 2021, Linaro Limited
+ * Copyright (c) 2022, STMicroelectronics - All Rights Reserved
*/
#ifndef STM32MP_EFI_H
@@ -9,7 +10,7 @@
#include <drivers/partition/efi.h>
#define STM32MP_FIP_GUID \
- EFI_GUID(0x19d5df83, 0x11b0, 0x457b, \
- 0xbe, 0x2c, 0x75, 0x59, 0xc1, 0x31, 0x42, 0xa5)
+ EFI_GUID(0x19d5df83U, 0x11b0U, 0x457bU, \
+ 0xbeU, 0x2cU, 0x75U, 0x59U, 0xc1U, 0x31U, 0x42U, 0xa5U)
#endif /* STM32MP_EFI_H */
diff --git a/plat/st/common/stm32mp_common.c b/plat/st/common/stm32mp_common.c
index bb56bac..f842e16 100644
--- a/plat/st/common/stm32mp_common.c
+++ b/plat/st/common/stm32mp_common.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -14,6 +14,7 @@
#include <drivers/st/stm32_console.h>
#include <drivers/st/stm32mp_clkfunc.h>
#include <drivers/st/stm32mp_reset.h>
+#include <lib/mmio.h>
#include <lib/smccc.h>
#include <lib/xlat_tables/xlat_tables_v2.h>
#include <plat/common/platform.h>
@@ -24,6 +25,36 @@
#define HEADER_VERSION_MAJOR_MASK GENMASK(23, 16)
#define RESET_TIMEOUT_US_1MS 1000U
+/* Internal layout of the 32bit OTP word board_id */
+#define BOARD_ID_BOARD_NB_MASK GENMASK_32(31, 16)
+#define BOARD_ID_BOARD_NB_SHIFT 16
+#define BOARD_ID_VARCPN_MASK GENMASK_32(15, 12)
+#define BOARD_ID_VARCPN_SHIFT 12
+#define BOARD_ID_REVISION_MASK GENMASK_32(11, 8)
+#define BOARD_ID_REVISION_SHIFT 8
+#define BOARD_ID_VARFG_MASK GENMASK_32(7, 4)
+#define BOARD_ID_VARFG_SHIFT 4
+#define BOARD_ID_BOM_MASK GENMASK_32(3, 0)
+
+#define BOARD_ID2NB(_id) (((_id) & BOARD_ID_BOARD_NB_MASK) >> \
+ BOARD_ID_BOARD_NB_SHIFT)
+#define BOARD_ID2VARCPN(_id) (((_id) & BOARD_ID_VARCPN_MASK) >> \
+ BOARD_ID_VARCPN_SHIFT)
+#define BOARD_ID2REV(_id) (((_id) & BOARD_ID_REVISION_MASK) >> \
+ BOARD_ID_REVISION_SHIFT)
+#define BOARD_ID2VARFG(_id) (((_id) & BOARD_ID_VARFG_MASK) >> \
+ BOARD_ID_VARFG_SHIFT)
+#define BOARD_ID2BOM(_id) ((_id) & BOARD_ID_BOM_MASK)
+
+#define BOOT_AUTH_MASK GENMASK_32(23, 20)
+#define BOOT_AUTH_SHIFT 20
+#define BOOT_PART_MASK GENMASK_32(19, 16)
+#define BOOT_PART_SHIFT 16
+#define BOOT_ITF_MASK GENMASK_32(15, 12)
+#define BOOT_ITF_SHIFT 12
+#define BOOT_INST_MASK GENMASK_32(11, 8)
+#define BOOT_INST_SHIFT 8
+
static console_t console;
uintptr_t plat_get_ns_image_entrypoint(void)
@@ -277,3 +308,69 @@
{
return (int32_t)(stm32mp_get_chip_version() & SOC_ID_REV_MASK);
}
+
+void stm32_display_board_info(uint32_t board_id)
+{
+ char rev[2];
+
+ rev[0] = BOARD_ID2REV(board_id) - 1 + 'A';
+ rev[1] = '\0';
+ NOTICE("Board: MB%04x Var%u.%u Rev.%s-%02u\n",
+ BOARD_ID2NB(board_id),
+ BOARD_ID2VARCPN(board_id),
+ BOARD_ID2VARFG(board_id),
+ rev,
+ BOARD_ID2BOM(board_id));
+}
+
+void stm32_save_boot_info(boot_api_context_t *boot_context)
+{
+ uint32_t auth_status;
+
+ assert(boot_context->boot_interface_instance <= (BOOT_INST_MASK >> BOOT_INST_SHIFT));
+ assert(boot_context->boot_interface_selected <= (BOOT_ITF_MASK >> BOOT_ITF_SHIFT));
+ assert(boot_context->boot_partition_used_toboot <= (BOOT_PART_MASK >> BOOT_PART_SHIFT));
+
+ switch (boot_context->auth_status) {
+ case BOOT_API_CTX_AUTH_NO:
+ auth_status = 0x0U;
+ break;
+
+ case BOOT_API_CTX_AUTH_SUCCESS:
+ auth_status = 0x2U;
+ break;
+
+ case BOOT_API_CTX_AUTH_FAILED:
+ default:
+ auth_status = 0x1U;
+ break;
+ }
+
+ clk_enable(TAMP_BKP_REG_CLK);
+
+ mmio_clrsetbits_32(stm32_get_bkpr_boot_mode_addr(),
+ BOOT_ITF_MASK | BOOT_INST_MASK | BOOT_PART_MASK | BOOT_AUTH_MASK,
+ (boot_context->boot_interface_instance << BOOT_INST_SHIFT) |
+ (boot_context->boot_interface_selected << BOOT_ITF_SHIFT) |
+ (boot_context->boot_partition_used_toboot << BOOT_PART_SHIFT) |
+ (auth_status << BOOT_AUTH_SHIFT));
+
+ clk_disable(TAMP_BKP_REG_CLK);
+}
+
+void stm32_get_boot_interface(uint32_t *interface, uint32_t *instance)
+{
+ static uint32_t itf;
+
+ if (itf == 0U) {
+ clk_enable(TAMP_BKP_REG_CLK);
+
+ itf = mmio_read_32(stm32_get_bkpr_boot_mode_addr()) &
+ (BOOT_ITF_MASK | BOOT_INST_MASK);
+
+ clk_disable(TAMP_BKP_REG_CLK);
+ }
+
+ *interface = (itf & BOOT_ITF_MASK) >> BOOT_ITF_SHIFT;
+ *instance = (itf & BOOT_INST_MASK) >> BOOT_INST_SHIFT;
+}
diff --git a/plat/st/common/stm32mp_crypto_lib.c b/plat/st/common/stm32mp_crypto_lib.c
index d644242..0da0019 100644
--- a/plat/st/common/stm32mp_crypto_lib.c
+++ b/plat/st/common/stm32mp_crypto_lib.c
@@ -16,6 +16,7 @@
#include <drivers/st/stm32_pka.h>
#include <drivers/st/stm32_rng.h>
#include <drivers/st/stm32_saes.h>
+#include <lib/utils.h>
#include <lib/xlat_tables/xlat_tables_v2.h>
#include <mbedtls/asn1.h>
#include <mbedtls/md.h>
@@ -78,7 +79,7 @@
}
}
-int get_plain_pk_from_asn1(void *pk_ptr, unsigned int pk_len, void **plain_pk,
+static int get_plain_pk_from_asn1(void *pk_ptr, unsigned int pk_len, void **plain_pk,
unsigned int *len, int *pk_alg)
{
int ret;
diff --git a/plat/st/common/stm32mp_dt.c b/plat/st/common/stm32mp_dt.c
index c9efeb5..34d52e1 100644
--- a/plat/st/common/stm32mp_dt.c
+++ b/plat/st/common/stm32mp_dt.c
@@ -79,11 +79,8 @@
}
cchar = fdt_getprop(fdt, node, "secure-status", NULL);
- if (cchar == NULL) {
- if (status == DT_NON_SECURE) {
- status |= DT_SECURE;
- }
- } else if (strncmp(cchar, "okay", strlen("okay")) == 0) {
+ if (((cchar == NULL) && (status == DT_NON_SECURE)) ||
+ ((cchar != NULL) && (strncmp(cchar, "okay", strlen("okay")) == 0))) {
status |= DT_SECURE;
}
@@ -350,7 +347,7 @@
return -FDT_ERR_BADVALUE;
}
- if (fdt32_to_cpu(*cuint) % sizeof(uint32_t)) {
+ if ((fdt32_to_cpu(*cuint) % sizeof(uint32_t)) != 0U) {
ERROR("Misaligned nvmem %s element: ignored\n", name);
return -FDT_ERR_BADVALUE;
}
@@ -386,7 +383,7 @@
fdt_for_each_subnode(node, fdt, pinctrl_node) {
const fdt32_t *cuint;
- int pin_count;
+ int pin_count = 0;
int len;
int i;
@@ -415,11 +412,9 @@
}
/* Get the last defined gpio line (offset + nb of pins) */
- pin_count = fdt32_to_cpu(*(cuint + 1)) + fdt32_to_cpu(*(cuint + 3));
- for (i = 0; i < len / 4; i++) {
- pin_count = MAX(pin_count, (int)(fdt32_to_cpu(*(cuint + 1)) +
- fdt32_to_cpu(*(cuint + 3))));
- cuint += 4;
+ for (i = 0; i < len; i += 4) {
+ pin_count = MAX(pin_count, (int)(fdt32_to_cpu(cuint[i + 1]) +
+ fdt32_to_cpu(cuint[i + 3])));
}
return pin_count;
diff --git a/plat/st/common/stm32mp_fconf_io.c b/plat/st/common/stm32mp_fconf_io.c
index 0b6cc78..1a59f0b 100644
--- a/plat/st/common/stm32mp_fconf_io.c
+++ b/plat/st/common/stm32mp_fconf_io.c
@@ -28,7 +28,7 @@
#endif
#if (STM32MP_SDMMC || STM32MP_EMMC) && PSA_FWU_SUPPORT
-io_block_spec_t metadata_block_spec = {
+static io_block_spec_t metadata_block_spec = {
.offset = 0, /* To be filled at runtime */
.length = 0, /* To be filled at runtime */
};
diff --git a/plat/st/stm32mp1/stm32mp1_gic.c b/plat/st/common/stm32mp_gic.c
similarity index 75%
rename from plat/st/stm32mp1/stm32mp1_gic.c
rename to plat/st/common/stm32mp_gic.c
index 851a9cf..d02b635 100644
--- a/plat/st/stm32mp1/stm32mp1_gic.c
+++ b/plat/st/common/stm32mp_gic.c
@@ -1,21 +1,20 @@
/*
- * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2023, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
-#include <libfdt.h>
-
-#include <platform_def.h>
-
#include <common/bl_common.h>
#include <common/debug.h>
#include <drivers/arm/gicv2.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <lib/utils.h>
+#include <libfdt.h>
#include <plat/common/platform.h>
+#include <platform_def.h>
+
-struct stm32_gic_instance {
+struct stm32mp_gic_instance {
uint32_t cells;
uint32_t phandle_node;
};
@@ -24,7 +23,7 @@
* On a GICv2 system, the Group 1 secure interrupts are treated as Group 0
* interrupts.
*****************************************************************************/
-static const interrupt_prop_t stm32mp1_interrupt_props[] = {
+static const interrupt_prop_t stm32mp_interrupt_props[] = {
PLATFORM_G1S_PROPS(GICV2_INTR_GROUP0),
PLATFORM_G0_PROPS(GICV2_INTR_GROUP0)
};
@@ -33,15 +32,15 @@
static unsigned int target_mask_array[PLATFORM_CORE_COUNT] = {1, 2};
static gicv2_driver_data_t platform_gic_data = {
- .interrupt_props = stm32mp1_interrupt_props,
- .interrupt_props_num = ARRAY_SIZE(stm32mp1_interrupt_props),
+ .interrupt_props = stm32mp_interrupt_props,
+ .interrupt_props_num = ARRAY_SIZE(stm32mp_interrupt_props),
.target_masks = target_mask_array,
.target_masks_num = ARRAY_SIZE(target_mask_array),
};
-static struct stm32_gic_instance stm32_gic;
+static struct stm32mp_gic_instance stm32mp_gic;
-void stm32mp1_gic_init(void)
+void stm32mp_gic_init(void)
{
int node;
void *fdt;
@@ -71,20 +70,20 @@
panic();
}
- stm32_gic.cells = fdt32_to_cpu(*cuint);
+ stm32mp_gic.cells = fdt32_to_cpu(*cuint);
- stm32_gic.phandle_node = fdt_get_phandle(fdt, node);
- if (stm32_gic.phandle_node == 0U) {
+ stm32mp_gic.phandle_node = fdt_get_phandle(fdt, node);
+ if (stm32mp_gic.phandle_node == 0U) {
panic();
}
gicv2_driver_init(&platform_gic_data);
gicv2_distif_init();
- stm32mp1_gic_pcpu_init();
+ stm32mp_gic_pcpu_init();
}
-void stm32mp1_gic_pcpu_init(void)
+void stm32mp_gic_pcpu_init(void)
{
gicv2_pcpu_distif_init();
gicv2_set_pe_target_mask(plat_my_core_pos());
diff --git a/plat/st/stm32mp1/bl2_plat_setup.c b/plat/st/stm32mp1/bl2_plat_setup.c
index 4f04a6f..eeabd09 100644
--- a/plat/st/stm32mp1/bl2_plat_setup.c
+++ b/plat/st/stm32mp1/bl2_plat_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -290,10 +290,7 @@
panic();
}
- stm32_save_boot_interface(boot_context->boot_interface_selected,
- boot_context->boot_interface_instance);
- stm32_save_boot_auth(boot_context->auth_status,
- boot_context->boot_partition_used_toboot);
+ stm32_save_boot_info(boot_context);
#if STM32MP_USB_PROGRAMMER && STM32MP15
/* Deconfigure all UART RX pins configured by ROM code */
@@ -543,20 +540,15 @@
void bl2_el3_plat_prepare_exit(void)
{
+#if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER
uint16_t boot_itf = stm32mp_get_boot_itf_selected();
- switch (boot_itf) {
-#if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER
- case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART:
- case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB:
+ if ((boot_itf == BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART) ||
+ (boot_itf == BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB)) {
/* Invalidate the downloaded buffer used with io_memmap */
inv_dcache_range(DWL_BUFFER_BASE, DWL_BUFFER_SIZE);
- break;
-#endif /* STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER */
- default:
- /* Do nothing in default case */
- break;
}
+#endif /* STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER */
stm32mp1_security_setup();
}
diff --git a/plat/st/stm32mp1/include/stm32mp1_private.h b/plat/st/stm32mp1/include/stm32mp1_private.h
index 21ef60d..4a52255 100644
--- a/plat/st/stm32mp1/include/stm32mp1_private.h
+++ b/plat/st/stm32mp1/include/stm32mp1_private.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -14,9 +14,6 @@
void stm32mp1_arch_security_setup(void);
void stm32mp1_security_setup(void);
-void stm32mp1_gic_pcpu_init(void);
-void stm32mp1_gic_init(void);
-
void stm32mp1_syscfg_init(void);
void stm32mp1_syscfg_enable_io_compensation_start(void);
void stm32mp1_syscfg_enable_io_compensation_finish(void);
diff --git a/plat/st/stm32mp1/plat_image_load.c b/plat/st/stm32mp1/plat_image_load.c
index c4048fc..c455544 100644
--- a/plat/st/stm32mp1/plat_image_load.c
+++ b/plat/st/stm32mp1/plat_image_load.c
@@ -5,6 +5,7 @@
*/
#include <common/desc_image_load.h>
+#include <plat/common/platform.h>
/*******************************************************************************
* This function flushes the data structures so that they are visible
diff --git a/plat/st/stm32mp1/platform.mk b/plat/st/stm32mp1/platform.mk
index 7eecf30..236296e 100644
--- a/plat/st/stm32mp1/platform.mk
+++ b/plat/st/stm32mp1/platform.mk
@@ -403,7 +403,6 @@
BL2_SOURCES += drivers/mmc/mmc.c \
drivers/partition/gpt.c \
drivers/partition/partition.c \
- drivers/st/io/io_mmc.c \
drivers/st/mmc/stm32_sdmmc2.c
endif
diff --git a/plat/st/stm32mp1/sp_min/sp_min-stm32mp1.mk b/plat/st/stm32mp1/sp_min/sp_min-stm32mp1.mk
index 1d754d9..f5184e7 100644
--- a/plat/st/stm32mp1/sp_min/sp_min-stm32mp1.mk
+++ b/plat/st/stm32mp1/sp_min/sp_min-stm32mp1.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2017-2023, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -32,7 +32,7 @@
BL32_SOURCES += ${GICV2_SOURCES} \
plat/common/plat_gicv2.c \
- plat/st/stm32mp1/stm32mp1_gic.c
+ plat/st/common/stm32mp_gic.c
# Generic PSCI
BL32_SOURCES += plat/common/plat_psci_common.c
diff --git a/plat/st/stm32mp1/sp_min/sp_min_setup.c b/plat/st/stm32mp1/sp_min/sp_min_setup.c
index 50b0794..b46f4af 100644
--- a/plat/st/stm32mp1/sp_min/sp_min_setup.c
+++ b/plat/st/stm32mp1/sp_min/sp_min_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,9 +7,8 @@
#include <assert.h>
#include <string.h>
-#include <platform_def.h>
-
#include <arch_helpers.h>
+#include <bl32/sp_min/platform_sp_min.h>
#include <common/bl_common.h>
#include <common/debug.h>
#include <context.h>
@@ -27,7 +26,7 @@
#include <lib/xlat_tables/xlat_tables_v2.h>
#include <plat/common/platform.h>
-#include <platform_sp_min.h>
+#include <platform_def.h>
/******************************************************************************
* Placeholder variables for copying the arguments that have been passed to
@@ -181,7 +180,7 @@
{
generic_delay_timer_init();
- stm32mp1_gic_init();
+ stm32mp_gic_init();
if (stm32_iwdg_init() < 0) {
panic();
diff --git a/plat/st/stm32mp1/stm32mp1_def.h b/plat/st/stm32mp1/stm32mp1_def.h
index f0d8526..8cac4b5 100644
--- a/plat/st/stm32mp1/stm32mp1_def.h
+++ b/plat/st/stm32mp1/stm32mp1_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -548,6 +548,7 @@
******************************************************************************/
#define TAMP_BASE U(0x5C00A000)
#define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100))
+#define TAMP_BKP_REG_CLK RTCAPB
#define TAMP_COUNTR U(0x40)
#if !(defined(__LINKER__) || defined(__ASSEMBLER__))
diff --git a/plat/st/stm32mp1/stm32mp1_fconf_firewall.c b/plat/st/stm32mp1/stm32mp1_fconf_firewall.c
index f2568ab..7d99564 100644
--- a/plat/st/stm32mp1/stm32mp1_fconf_firewall.c
+++ b/plat/st/stm32mp1/stm32mp1_fconf_firewall.c
@@ -99,15 +99,16 @@
/* Locate the memory cells and read all values */
for (i = 0U; i < (unsigned int)(len / (sizeof(uint32_t) * STM32MP_REGION_PARAMS)); i++) {
+ uint32_t idx = i * STM32MP_REGION_PARAMS;
uint32_t base;
uint32_t size;
uint32_t sec_attr;
uint32_t nsaid;
- base = fdt32_to_cpu(conf_list->id_attr[i * STM32MP_REGION_PARAMS]);
- size = fdt32_to_cpu(conf_list->id_attr[i * STM32MP_REGION_PARAMS + 1]);
- sec_attr = fdt32_to_cpu(conf_list->id_attr[i * STM32MP_REGION_PARAMS + 2]);
- nsaid = fdt32_to_cpu(conf_list->id_attr[i * STM32MP_REGION_PARAMS + 3]);
+ base = fdt32_to_cpu(conf_list->id_attr[idx]);
+ size = fdt32_to_cpu(conf_list->id_attr[idx + 1]);
+ sec_attr = fdt32_to_cpu(conf_list->id_attr[idx + 2]);
+ nsaid = fdt32_to_cpu(conf_list->id_attr[idx + 3]);
VERBOSE("FCONF: stm32mp1-firewall cell found with value = 0x%x 0x%x 0x%x 0x%x\n",
base, size, sec_attr, nsaid);
diff --git a/plat/st/stm32mp1/stm32mp1_pm.c b/plat/st/stm32mp1/stm32mp1_pm.c
index 6e438c4..7439381 100644
--- a/plat/st/stm32mp1/stm32mp1_pm.c
+++ b/plat/st/stm32mp1/stm32mp1_pm.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -118,7 +118,7 @@
******************************************************************************/
static void stm32_pwr_domain_on_finish(const psci_power_state_t *target_state)
{
- stm32mp1_gic_pcpu_init();
+ stm32mp_gic_pcpu_init();
write_cntfrq_el0(cntfrq_core0);
}
diff --git a/plat/st/stm32mp1/stm32mp1_private.c b/plat/st/stm32mp1/stm32mp1_private.c
index 9bdb075..ea35055 100644
--- a/plat/st/stm32mp1/stm32mp1_private.c
+++ b/plat/st/stm32mp1/stm32mp1_private.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -16,37 +16,12 @@
#include <plat/common/platform.h>
#include <platform_def.h>
-/* Internal layout of the 32bit OTP word board_id */
-#define BOARD_ID_BOARD_NB_MASK GENMASK(31, 16)
-#define BOARD_ID_BOARD_NB_SHIFT 16
-#define BOARD_ID_VARCPN_MASK GENMASK(15, 12)
-#define BOARD_ID_VARCPN_SHIFT 12
-#define BOARD_ID_REVISION_MASK GENMASK(11, 8)
-#define BOARD_ID_REVISION_SHIFT 8
-#define BOARD_ID_VARFG_MASK GENMASK(7, 4)
-#define BOARD_ID_VARFG_SHIFT 4
-#define BOARD_ID_BOM_MASK GENMASK(3, 0)
-
-#define BOARD_ID2NB(_id) (((_id) & BOARD_ID_BOARD_NB_MASK) >> \
- BOARD_ID_BOARD_NB_SHIFT)
-#define BOARD_ID2VARCPN(_id) (((_id) & BOARD_ID_VARCPN_MASK) >> \
- BOARD_ID_VARCPN_SHIFT)
-#define BOARD_ID2REV(_id) (((_id) & BOARD_ID_REVISION_MASK) >> \
- BOARD_ID_REVISION_SHIFT)
-#define BOARD_ID2VARFG(_id) (((_id) & BOARD_ID_VARFG_MASK) >> \
- BOARD_ID_VARFG_SHIFT)
-#define BOARD_ID2BOM(_id) ((_id) & BOARD_ID_BOM_MASK)
-
#if STM32MP13
#define TAMP_BOOT_MODE_BACKUP_REG_ID U(30)
#endif
#if STM32MP15
#define TAMP_BOOT_MODE_BACKUP_REG_ID U(20)
#endif
-#define TAMP_BOOT_MODE_ITF_MASK GENMASK(15, 8)
-#define TAMP_BOOT_MODE_ITF_SHIFT 8
-#define TAMP_BOOT_MODE_AUTH_MASK GENMASK(23, 16)
-#define TAMP_BOOT_MODE_AUTH_SHIFT 16
/*
* Backup register to store fwu update information.
@@ -140,14 +115,14 @@
uintptr_t stm32_get_gpio_bank_base(unsigned int bank)
{
#if STM32MP13
- assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_I);
+ assert((GPIO_BANK_A == 0) && (bank <= GPIO_BANK_I));
#endif
#if STM32MP15
if (bank == GPIO_BANK_Z) {
return GPIOZ_BASE;
}
- assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K);
+ assert((GPIO_BANK_A == 0) && (bank <= GPIO_BANK_K));
#endif
return GPIOA_BASE + (bank * GPIO_BANK_OFFSET);
@@ -156,14 +131,14 @@
uint32_t stm32_get_gpio_bank_offset(unsigned int bank)
{
#if STM32MP13
- assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_I);
+ assert((GPIO_BANK_A == 0) && (bank <= GPIO_BANK_I));
#endif
#if STM32MP15
if (bank == GPIO_BANK_Z) {
return 0;
}
- assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K);
+ assert((GPIO_BANK_A == 0) && (bank <= GPIO_BANK_K));
#endif
return bank * GPIO_BANK_OFFSET;
@@ -186,14 +161,14 @@
unsigned long stm32_get_gpio_bank_clock(unsigned int bank)
{
#if STM32MP13
- assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_I);
+ assert((GPIO_BANK_A == 0) && (bank <= GPIO_BANK_I));
#endif
#if STM32MP15
if (bank == GPIO_BANK_Z) {
return GPIOZ;
}
- assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K);
+ assert((GPIO_BANK_A == 0) && (bank <= GPIO_BANK_K));
#endif
return GPIOA + (bank - GPIO_BANK_A);
@@ -378,7 +353,7 @@
void stm32mp_get_soc_name(char name[STM32_SOC_NAME_SIZE])
{
- char *cpu_s, *cpu_r, *pkg;
+ const char *cpu_s, *cpu_r, *pkg;
/* MPUs Part Numbers */
switch (get_part_number()) {
@@ -520,23 +495,14 @@
void stm32mp_print_boardinfo(void)
{
- uint32_t board_id = 0;
+ uint32_t board_id = 0U;
if (stm32_get_otp_value(BOARD_ID_OTP, &board_id) != 0) {
return;
}
if (board_id != 0U) {
- char rev[2];
-
- rev[0] = BOARD_ID2REV(board_id) - 1 + 'A';
- rev[1] = '\0';
- NOTICE("Board: MB%04x Var%u.%u Rev.%s-%02u\n",
- BOARD_ID2NB(board_id),
- BOARD_ID2VARCPN(board_id),
- BOARD_ID2VARFG(board_id),
- rev,
- BOARD_ID2BOM(board_id));
+ stm32_display_board_info(board_id);
}
}
@@ -697,51 +663,9 @@
}
#endif
-void stm32_save_boot_interface(uint32_t interface, uint32_t instance)
+uintptr_t stm32_get_bkpr_boot_mode_addr(void)
{
- uintptr_t bkpr_itf_idx = tamp_bkpr(TAMP_BOOT_MODE_BACKUP_REG_ID);
-
- clk_enable(RTCAPB);
-
- mmio_clrsetbits_32(bkpr_itf_idx,
- TAMP_BOOT_MODE_ITF_MASK,
- ((interface << 4) | (instance & 0xFU)) <<
- TAMP_BOOT_MODE_ITF_SHIFT);
-
- clk_disable(RTCAPB);
-}
-
-void stm32_get_boot_interface(uint32_t *interface, uint32_t *instance)
-{
- static uint32_t itf;
-
- if (itf == 0U) {
- uintptr_t bkpr = tamp_bkpr(TAMP_BOOT_MODE_BACKUP_REG_ID);
-
- clk_enable(RTCAPB);
-
- itf = (mmio_read_32(bkpr) & TAMP_BOOT_MODE_ITF_MASK) >>
- TAMP_BOOT_MODE_ITF_SHIFT;
-
- clk_disable(RTCAPB);
- }
-
- *interface = itf >> 4;
- *instance = itf & 0xFU;
-}
-
-void stm32_save_boot_auth(uint32_t auth_status, uint32_t boot_partition)
-{
- uint32_t boot_status = tamp_bkpr(TAMP_BOOT_MODE_BACKUP_REG_ID);
-
- clk_enable(RTCAPB);
-
- mmio_clrsetbits_32(boot_status,
- TAMP_BOOT_MODE_AUTH_MASK,
- ((auth_status << 4) | (boot_partition & 0xFU)) <<
- TAMP_BOOT_MODE_AUTH_SHIFT);
-
- clk_disable(RTCAPB);
+ return tamp_bkpr(TAMP_BOOT_MODE_BACKUP_REG_ID);
}
#if PSA_FWU_SUPPORT
diff --git a/plat/st/stm32mp1/stm32mp1_syscfg.c b/plat/st/stm32mp1/stm32mp1_syscfg.c
index ff79428..75dd709 100644
--- a/plat/st/stm32mp1/stm32mp1_syscfg.c
+++ b/plat/st/stm32mp1/stm32mp1_syscfg.c
@@ -235,7 +235,9 @@
}
if (apply_hslv) {
- mmio_write_32(SYSCFG_BASE + SYSCFG_HSLVEN0R + index * sizeof(uint32_t), HSLV_KEY);
+ uint32_t reg_offset = index * sizeof(uint32_t);
+
+ mmio_write_32(SYSCFG_BASE + SYSCFG_HSLVEN0R + reg_offset, HSLV_KEY);
}
}
#endif
diff --git a/plat/ti/k3/board/generic/board.mk b/plat/ti/k3/board/generic/board.mk
index ef74cd6..58c966a 100644
--- a/plat/ti/k3/board/generic/board.mk
+++ b/plat/ti/k3/board/generic/board.mk
@@ -4,21 +4,9 @@
# SPDX-License-Identifier: BSD-3-Clause
#
-BL32_BASE ?= 0x9e800000
-$(eval $(call add_define,BL32_BASE))
-
-PRELOADED_BL33_BASE ?= 0x80080000
-$(eval $(call add_define,PRELOADED_BL33_BASE))
-
-K3_HW_CONFIG_BASE ?= 0x82000000
-$(eval $(call add_define,K3_HW_CONFIG_BASE))
-
# Define sec_proxy usage as the full prioritized communication scheme
K3_SEC_PROXY_LITE := 0
$(eval $(call add_define,K3_SEC_PROXY_LITE))
# System coherency is managed in hardware
USE_COHERENT_MEM := 1
-
-PLAT_INCLUDES += \
- -Iplat/ti/k3/board/generic/include \
diff --git a/plat/ti/k3/board/generic/include/board_def.h b/plat/ti/k3/board/generic/include/board_def.h
index 4ff687c..edfa73f 100644
--- a/plat/ti/k3/board/generic/include/board_def.h
+++ b/plat/ti/k3/board/generic/include/board_def.h
@@ -15,29 +15,9 @@
#define K3_CLUSTER2_CORE_COUNT U(2)
#define K3_CLUSTER3_CORE_COUNT U(2)
-/*
- * This RAM will be used for the bootloader including code, bss, and stacks.
- * It may need to be increased if BL31 grows in size.
- *
- * The link addresses are determined by SEC_SRAM_BASE + offset.
- * When ENABLE_PIE is set, the TF images can be loaded anywhere, so
- * SEC_SRAM_BASE is really arbitrary.
- *
- * When ENABLE_PIE is unset, SEC_SRAM_BASE should be chosen so that
- * it matches to the physical address where BL31 is loaded, that is,
- * SEC_SRAM_BASE should be the base address of the RAM region.
- *
- * Lets make things explicit by mapping SRAM_BASE to 0x0 since ENABLE_PIE is
- * defined as default for our platform.
- */
-#define SEC_SRAM_BASE UL(0x00000000) /* PIE remapped on fly */
-#define SEC_SRAM_SIZE UL(0x00020000) /* 128k */
-
-#define PLAT_MAX_OFF_STATE U(2)
-#define PLAT_MAX_RET_STATE U(1)
-
#define PLAT_PROC_START_ID U(32)
#define PLAT_PROC_DEVICE_START_ID U(202)
#define PLAT_CLUSTER_DEVICE_START_ID U(198)
+#define PLAT_BOARD_DEVICE_ID U(157)
#endif /* BOARD_DEF_H */
diff --git a/plat/ti/k3/board/j784s4/board.mk b/plat/ti/k3/board/j784s4/board.mk
index 92433ab..21d4151 100644
--- a/plat/ti/k3/board/j784s4/board.mk
+++ b/plat/ti/k3/board/j784s4/board.mk
@@ -4,21 +4,17 @@
# SPDX-License-Identifier: BSD-3-Clause
#
-BL32_BASE ?= 0x9e800000
-$(eval $(call add_define,BL32_BASE))
-
-PRELOADED_BL33_BASE ?= 0x80080000
-$(eval $(call add_define,PRELOADED_BL33_BASE))
-
-K3_HW_CONFIG_BASE ?= 0x82000000
-$(eval $(call add_define,K3_HW_CONFIG_BASE))
-
# Define sec_proxy usage as the full prioritized communication scheme
K3_SEC_PROXY_LITE := 0
$(eval $(call add_define,K3_SEC_PROXY_LITE))
+# Use a 4 cycle data RAM latency for J784s4
+K3_DATA_RAM_4_LATENCY := 1
+$(eval $(call add_define,K3_DATA_RAM_4_LATENCY))
+
+# Delay snoop exclusive handling for J784s4
+K3_EXCLUSIVE_SNOOP_DELAY := 1
+$(eval $(call add_define,K3_EXCLUSIVE_SNOOP_DELAY))
+
# System coherency is managed in hardware
USE_COHERENT_MEM := 1
-
-PLAT_INCLUDES += \
- -Iplat/ti/k3/board/j784s4/include \
diff --git a/plat/ti/k3/board/j784s4/include/board_def.h b/plat/ti/k3/board/j784s4/include/board_def.h
index c2debc7..c817999 100644
--- a/plat/ti/k3/board/j784s4/include/board_def.h
+++ b/plat/ti/k3/board/j784s4/include/board_def.h
@@ -14,30 +14,10 @@
#define K3_CLUSTER1_CORE_COUNT U(4)
#define K3_CLUSTER2_CORE_COUNT U(0)
#define K3_CLUSTER3_CORE_COUNT U(0)
-/*
- * This RAM will be used for the bootloader including code, bss, and stacks.
- * It may need to be increased if BL31 grows in size.
- *
- * The link addresses are determined by SEC_SRAM_BASE + offset.
- * When ENABLE_PIE is set, the TF images can be loaded anywhere, so
- * SEC_SRAM_BASE is really arbitrary.
- *
- * When ENABLE_PIE is unset, SEC_SRAM_BASE should be chosen so that
- * it matches to the physical address where BL31 is loaded, that is,
- * SEC_SRAM_BASE should be the base address of the RAM region.
- *
- * Lets make things explicit by mapping SRAM_BASE to 0x0 since ENABLE_PIE is
- * defined as default for our platform.
- */
-#define SEC_SRAM_BASE UL(0x00000000) /* PIE remapped on fly */
-#define SEC_SRAM_SIZE UL(0x00020000) /* 128k */
-
-#define PLAT_MAX_OFF_STATE U(2)
-#define PLAT_MAX_RET_STATE U(1)
#define PLAT_PROC_START_ID U(32)
-
#define PLAT_PROC_DEVICE_START_ID U(202)
#define PLAT_CLUSTER_DEVICE_START_ID U(198)
+#define PLAT_BOARD_DEVICE_ID U(157)
#endif /* BOARD_DEF_H */
diff --git a/plat/ti/k3/board/lite/board.mk b/plat/ti/k3/board/lite/board.mk
index 76246be..2fa09ad 100644
--- a/plat/ti/k3/board/lite/board.mk
+++ b/plat/ti/k3/board/lite/board.mk
@@ -4,21 +4,9 @@
# SPDX-License-Identifier: BSD-3-Clause
#
-BL32_BASE ?= 0x9e800000
-$(eval $(call add_define,BL32_BASE))
-
-PRELOADED_BL33_BASE ?= 0x80080000
-$(eval $(call add_define,PRELOADED_BL33_BASE))
-
-K3_HW_CONFIG_BASE ?= 0x82000000
-$(eval $(call add_define,K3_HW_CONFIG_BASE))
-
# Define sec_proxy usage as the lite version
K3_SEC_PROXY_LITE := 1
$(eval $(call add_define,K3_SEC_PROXY_LITE))
# We dont have system level coherency capability
USE_COHERENT_MEM := 0
-
-PLAT_INCLUDES += \
- -Iplat/ti/k3/board/lite/include \
diff --git a/plat/ti/k3/board/lite/include/board_def.h b/plat/ti/k3/board/lite/include/board_def.h
index fd4e5b1..f523198 100644
--- a/plat/ti/k3/board/lite/include/board_def.h
+++ b/plat/ti/k3/board/lite/include/board_def.h
@@ -15,31 +15,9 @@
#define K3_CLUSTER2_CORE_COUNT U(0)
#define K3_CLUSTER3_CORE_COUNT U(0)
-/*
- * This RAM will be used for the bootloader including code, bss, and stacks.
- * It may need to be increased if BL31 grows in size.
- * Current computation assumes data structures necessary for GIC and ARM for
- * a single cluster of 4 processor.
- *
- * The link addresses are determined by SEC_SRAM_BASE + offset.
- * When ENABLE_PIE is set, the TF images can be loaded anywhere, so
- * SEC_SRAM_BASE is really arbitrary.
- *
- * When ENABLE_PIE is unset, SEC_SRAM_BASE should be chosen so that
- * it matches to the physical address where BL31 is loaded, that is,
- * SEC_SRAM_BASE should be the base address of the RAM region.
- *
- * Lets make things explicit by mapping SRAM_BASE to 0x0 since ENABLE_PIE is
- * defined as default for our platform.
- */
-#define SEC_SRAM_BASE UL(0x00000000) /* PIE remapped on fly */
-#define SEC_SRAM_SIZE UL(0x00020000) /* 128k */
-
-#define PLAT_MAX_OFF_STATE U(2)
-#define PLAT_MAX_RET_STATE U(1)
-
#define PLAT_PROC_START_ID U(32)
#define PLAT_PROC_DEVICE_START_ID U(135)
#define PLAT_CLUSTER_DEVICE_START_ID U(134)
+#define PLAT_BOARD_DEVICE_ID U(157)
#endif /* BOARD_DEF_H */
diff --git a/plat/ti/k3/common/drivers/ti_sci/ti_sci.c b/plat/ti/k3/common/drivers/ti_sci/ti_sci.c
index 2cbfa3d..569e60c 100644
--- a/plat/ti/k3/common/drivers/ti_sci/ti_sci.c
+++ b/plat/ti/k3/common/drivers/ti_sci/ti_sci.c
@@ -1432,7 +1432,7 @@
struct ti_sci_xfer xfer;
int ret;
- ret = ti_sci_setup_one_xfer(TISCI_MSG_PROC_AUTH_BOOT_IMIAGE, 0,
+ ret = ti_sci_setup_one_xfer(TISCI_MSG_PROC_AUTH_BOOT_IMAGE, 0,
&req, sizeof(req),
&resp, sizeof(resp),
&xfer);
diff --git a/plat/ti/k3/common/drivers/ti_sci/ti_sci_protocol.h b/plat/ti/k3/common/drivers/ti_sci/ti_sci_protocol.h
index d220612..1b1a910 100644
--- a/plat/ti/k3/common/drivers/ti_sci/ti_sci_protocol.h
+++ b/plat/ti/k3/common/drivers/ti_sci/ti_sci_protocol.h
@@ -47,7 +47,7 @@
#define TISCI_MSG_PROC_HANDOVER 0xc005
#define TISCI_MSG_SET_PROC_BOOT_CONFIG 0xc100
#define TISCI_MSG_SET_PROC_BOOT_CTRL 0xc101
-#define TISCI_MSG_PROC_AUTH_BOOT_IMIAGE 0xc120
+#define TISCI_MSG_PROC_AUTH_BOOT_IMAGE 0xc120
#define TISCI_MSG_GET_PROC_BOOT_STATUS 0xc400
#define TISCI_MSG_WAIT_PROC_BOOT_STATUS 0xc401
diff --git a/plat/ti/k3/common/k3_bl31_setup.c b/plat/ti/k3/common/k3_bl31_setup.c
index 457c95d..9a1fd94 100644
--- a/plat/ti/k3/common/k3_bl31_setup.c
+++ b/plat/ti/k3/common/k3_bl31_setup.c
@@ -67,7 +67,8 @@
assert(arg0 == 0U);
assert(arg1 == 0U);
- bl31_console_setup();
+ /* Initialize the console to provide early debug support */
+ k3_console_setup();
#ifdef BL32_BASE
/* Populate entry point information for BL32 */
@@ -120,6 +121,10 @@
k3_gic_init();
ti_sci_init();
+
+ if (ti_sci_device_get(PLAT_BOARD_DEVICE_ID)) {
+ WARN("Unable to take system power reference\n");
+ }
}
void platform_mem_init(void)
@@ -164,14 +169,6 @@
return SYS_COUNTER_FREQ_IN_TICKS;
}
-/*
- * Empty function to prevent the console from being uninitialized after BL33 is
- * started and allow us to see messages from BL31.
- */
-void bl31_plat_runtime_setup(void)
-{
-}
-
/*******************************************************************************
* Return a pointer to the 'entry_point_info' structure of the next image
* for the security state specified. BL3-3 corresponds to the non-secure
diff --git a/plat/ti/k3/common/k3_console.c b/plat/ti/k3/common/k3_console.c
index 8c44c17..1b01c9b 100644
--- a/plat/ti/k3/common/k3_console.c
+++ b/plat/ti/k3/common/k3_console.c
@@ -11,11 +11,14 @@
#include <k3_console.h>
-void bl31_console_setup(void)
+void k3_console_setup(void)
{
static console_t console;
- /* Initialize the console to provide early debug support */
console_16550_register(K3_USART_BASE, K3_USART_CLK_SPEED,
K3_USART_BAUD, &console);
+
+ console_set_scope(&console, CONSOLE_FLAG_BOOT |
+ CONSOLE_FLAG_RUNTIME |
+ CONSOLE_FLAG_CRASH);
}
diff --git a/plat/ti/k3/common/k3_helpers.S b/plat/ti/k3/common/k3_helpers.S
index f4f7d18..f997b46 100644
--- a/plat/ti/k3/common/k3_helpers.S
+++ b/plat/ti/k3/common/k3_helpers.S
@@ -105,8 +105,32 @@
/* Cortex-A72 specific settings */
a72:
mrs x0, CORTEX_A72_L2CTLR_EL1
- orr x0, x0, #(CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES << CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT)
+#if K3_DATA_RAM_4_LATENCY
+ /* Set L2 cache data RAM latency to 4 cycles */
+ orr x0, x0, #(CORTEX_A72_L2_DATA_RAM_LATENCY_4_CYCLES << \
+ CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT)
+#else
+ /* Set L2 cache data RAM latency to 3 cycles */
+ orr x0, x0, #(CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES << \
+ CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT)
+#endif
+ /* Enable L2 ECC and parity with inline data */
+ orr x0, x0, #CORTEX_A72_L2CTLR_EL1_ECC_AND_PARITY_ENABLE
+ orr x0, x0, #CORTEX_A72_L2CTLR_EL1_DATA_INLINE_ECC_ENABLE
msr CORTEX_A72_L2CTLR_EL1, x0
+
+ mrs x0, CORTEX_A72_L2ACTLR_EL1
+ /* Enable L2 UniqueClean evictions with data */
+ orr x0, x0, #CORTEX_A72_L2ACTLR_ENABLE_UNIQUE_CLEAN
+ msr CORTEX_A72_L2ACTLR_EL1, x0
+
+#if K3_EXCLUSIVE_SNOOP_DELAY
+ mrs x0, CORTEX_A72_CPUACTLR_EL1
+ /* Set Snoop-delayed exclusive handling */
+ orr x0, x0, #CORTEX_A72_CPUACTLR_EL1_DELAY_EXCLUSIVE_SNOOP
+ msr CORTEX_A72_CPUACTLR_EL1, x0
+#endif
+
isb
ret
endfunc plat_reset_handler
diff --git a/plat/ti/k3/common/k3_psci.c b/plat/ti/k3/common/k3_psci.c
index 6febbc6..d846495 100644
--- a/plat/ti/k3/common/k3_psci.c
+++ b/plat/ti/k3/common/k3_psci.c
@@ -205,7 +205,14 @@
static void __dead2 k3_system_off(void)
{
- ERROR("System Off: operation not handled.\n");
+ int ret;
+
+ /* Queue up the system shutdown request */
+ ret = ti_sci_device_put_no_wait(PLAT_BOARD_DEVICE_ID);
+ if (ret != 0) {
+ ERROR("Sending system shutdown message failed (%d)\n", ret);
+ }
+
while (true)
wfi();
}
@@ -227,13 +234,6 @@
return PSCI_E_SUCCESS;
}
-static int k3_validate_ns_entrypoint(uintptr_t entrypoint)
-{
- /* TODO: perform the proper validation */
-
- return PSCI_E_SUCCESS;
-}
-
#if K3_PM_SYSTEM_SUSPEND
static void k3_pwr_domain_suspend(const psci_power_state_t *target_state)
{
@@ -281,7 +281,6 @@
.system_off = k3_system_off,
.system_reset = k3_system_reset,
.validate_power_state = k3_validate_power_state,
- .validate_ns_entrypoint = k3_validate_ns_entrypoint
};
int plat_setup_psci_ops(uintptr_t sec_entrypoint,
diff --git a/plat/ti/k3/common/plat_common.mk b/plat/ti/k3/common/plat_common.mk
index 026d6a3..fb633a8 100644
--- a/plat/ti/k3/common/plat_common.mk
+++ b/plat/ti/k3/common/plat_common.mk
@@ -27,7 +27,6 @@
ERRATA_A72_1319367 := 1
CRASH_REPORTING := 1
-HANDLE_EA_EL3_FIRST_NS := 1
# Split out RO data into a non-executable section
SEPARATE_CODE_AND_RODATA := 1
diff --git a/plat/ti/k3/include/k3_console.h b/plat/ti/k3/include/k3_console.h
index 6376ab3..51b322c 100644
--- a/plat/ti/k3/include/k3_console.h
+++ b/plat/ti/k3/include/k3_console.h
@@ -7,6 +7,6 @@
#ifndef K3_CONSOLE_H
#define K3_CONSOLE_H
-void bl31_console_setup(void);
+void k3_console_setup(void);
#endif /* K3_CONSOLE_H */
diff --git a/plat/ti/k3/include/platform_def.h b/plat/ti/k3/include/platform_def.h
index 81a383a..ae3775a 100644
--- a/plat/ti/k3/include/platform_def.h
+++ b/plat/ti/k3/include/platform_def.h
@@ -38,21 +38,31 @@
PLATFORM_CLUSTER_COUNT + \
PLATFORM_CORE_COUNT)
#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
+#define PLAT_MAX_OFF_STATE U(2)
+#define PLAT_MAX_RET_STATE U(1)
/*******************************************************************************
* Memory layout constants
******************************************************************************/
/*
- * ARM-TF lives in SRAM, partition it here
+ * This RAM will be used for the bootloader including code, bss, and stacks.
+ * It may need to be increased if BL31 grows in size.
*
- * BL3-1 specific defines.
+ * The link addresses are determined by BL31_BASE + offset.
+ * When ENABLE_PIE is set, the TF images can be loaded anywhere, so
+ * BL31_BASE is really arbitrary.
*
- * Put BL3-1 at the base of the Trusted SRAM.
+ * When ENABLE_PIE is unset, BL31_BASE should be chosen so that
+ * it matches to the physical address where BL31 is loaded, that is,
+ * BL31_BASE should be the base address of the RAM region.
+ *
+ * Lets make things explicit by mapping BL31_BASE to 0x0 since ENABLE_PIE is
+ * defined as default for our platform.
*/
-#define BL31_BASE SEC_SRAM_BASE
-#define BL31_SIZE SEC_SRAM_SIZE
-#define BL31_LIMIT (BL31_BASE + BL31_SIZE)
+#define BL31_BASE UL(0x00000000) /* PIE remapped on fly */
+#define BL31_SIZE UL(0x00020000) /* 128k */
+#define BL31_LIMIT (BL31_BASE + BL31_SIZE)
/*
* Defines the maximum number of translation tables that are allocated by the
diff --git a/plat/ti/k3/platform.mk b/plat/ti/k3/platform.mk
index 2de21aa..bce9ef1 100644
--- a/plat/ti/k3/platform.mk
+++ b/plat/ti/k3/platform.mk
@@ -10,5 +10,16 @@
include ${PLAT_PATH}/common/plat_common.mk
include ${PLAT_PATH}/board/${TARGET_BOARD}/board.mk
+BL32_BASE ?= 0x9e800000
+$(eval $(call add_define,BL32_BASE))
+
+PRELOADED_BL33_BASE ?= 0x80080000
+$(eval $(call add_define,PRELOADED_BL33_BASE))
+
+K3_HW_CONFIG_BASE ?= 0x82000000
+$(eval $(call add_define,K3_HW_CONFIG_BASE))
+
+PLAT_INCLUDES += -Iplat/ti/k3/board/${TARGET_BOARD}/include
+
# modify BUILD_PLAT to point to board specific build directory
BUILD_PLAT := $(abspath ${BUILD_BASE})/${PLAT}/${TARGET_BOARD}/${BUILD_TYPE}
diff --git a/plat/xilinx/common/ipi.c b/plat/xilinx/common/ipi.c
index 6438896..8fa7bc5 100644
--- a/plat/xilinx/common/ipi.c
+++ b/plat/xilinx/common/ipi.c
@@ -39,7 +39,7 @@
#define IPI_BIT_MASK(I) (ipi_table[(I)].ipi_bit_mask)
/* IPI configuration table */
-const static struct ipi_config *ipi_table;
+static const struct ipi_config *ipi_table;
/* Total number of IPI */
static uint32_t ipi_total;
diff --git a/plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c b/plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c
index cb6aaa5..8438aba 100644
--- a/plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c
+++ b/plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c
@@ -21,7 +21,6 @@
#include <plat_private.h>
#include "ipi_mailbox_svc.h"
-#include "../../../services/spd/trusty/smcall.h"
/*********************************************************************
* Macros definitions
@@ -75,17 +74,23 @@
ipi_local_id = x1 & UNSIGNED32_MASK;
ipi_remote_id = x2 & UNSIGNED32_MASK;
- if (SMC_ENTITY(smc_fid) >= SMC_ENTITY_TRUSTED_APP)
+ /* OEN Number 48 to 63 is for Trusted App and OS
+ * GET_SMC_OEN limits the return value of OEN number to 63 by bitwise
+ * AND operation with 0x3F.
+ * Upper limit check for OEN value is not required.
+ */
+ if (GET_SMC_OEN(smc_fid) >= OEN_TAP_START) {
is_secure = 1;
- else
+ } else {
is_secure = 0;
+ }
/* Validate IPI mailbox access */
ret = ipi_mb_validate(ipi_local_id, ipi_remote_id, is_secure);
if (ret)
SMC_RET1(handle, ret);
- switch (SMC_FUNCTION(smc_fid)) {
+ switch (GET_SMC_NUM(smc_fid)) {
case IPI_MAILBOX_OPEN:
ipi_mb_open(ipi_local_id, ipi_remote_id);
SMC_RET1(handle, 0);
diff --git a/plat/xilinx/versal/bl31_versal_setup.c b/plat/xilinx/versal/bl31_versal_setup.c
index 9b36208..995c852 100644
--- a/plat/xilinx/versal/bl31_versal_setup.c
+++ b/plat/xilinx/versal/bl31_versal_setup.c
@@ -135,7 +135,7 @@
} else if (ret != FSBL_HANDOFF_SUCCESS) {
panic();
} else {
- INFO("BL31: fsbl-atf handover success %u\n", ret);
+ INFO("BL31: PLM to TF-A handover success %u\n", ret);
}
NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc);
diff --git a/plat/xilinx/versal/versal_ipi.c b/plat/xilinx/versal/versal_ipi.c
index f99af82..d821929 100644
--- a/plat/xilinx/versal/versal_ipi.c
+++ b/plat/xilinx/versal/versal_ipi.c
@@ -19,7 +19,7 @@
#include <lib/mmio.h>
/* versal ipi configuration table */
-const static struct ipi_config versal_ipi_table[] = {
+static const struct ipi_config versal_ipi_table[] = {
/* A72 IPI */
[IPI_ID_APU] = {
.ipi_bit_mask = IPI0_TRIG_BIT,
diff --git a/plat/xilinx/versal_net/include/versal_net_def.h b/plat/xilinx/versal_net/include/versal_net_def.h
index 8cb5bf3..14e63d5 100644
--- a/plat/xilinx/versal_net/include/versal_net_def.h
+++ b/plat/xilinx/versal_net/include/versal_net_def.h
@@ -53,9 +53,9 @@
#define PSX_CRF_RST_TIMESTAMP_OFFSET U(0x33C)
-#define APU_PCLI U(0xECB10000)
-#define APU_PCLI_CPU_STEP U(0x30)
-#define APU_PCLI_CLUSTER_CPU_STEP (4U * APU_PCLI_CPU_STEP)
+#define APU_PCLI (0xECB10000ULL)
+#define APU_PCLI_CPU_STEP (0x30ULL)
+#define APU_PCLI_CLUSTER_CPU_STEP (4ULL * APU_PCLI_CPU_STEP)
#define APU_PCLI_CLUSTER_OFFSET U(0x8000)
#define APU_PCLI_CLUSTER_STEP U(0x1000)
#define PCLI_PREQ_OFFSET U(0x4)
@@ -67,13 +67,29 @@
/* Firmware Image Package */
#define VERSAL_NET_PRIMARY_CPU U(0)
-#define CORE_0_IEN_POWER_OFFSET (0x00000018U)
+#define CORE_0_ISR_WAKE_OFFSET (0x00000020ULL)
+#define APU_PCIL_CORE_X_ISR_WAKE_REG(cpu_id) (APU_PCLI + (CORE_0_ISR_WAKE_OFFSET + \
+ (APU_PCLI_CPU_STEP * (cpu_id))))
+#define APU_PCIL_CORE_X_ISR_WAKE_MASK (0x00000001U)
+#define CORE_0_IEN_WAKE_OFFSET (0x00000028ULL)
+#define APU_PCIL_CORE_X_IEN_WAKE_REG(cpu_id) (APU_PCLI + (CORE_0_IEN_WAKE_OFFSET + \
+ (APU_PCLI_CPU_STEP * (cpu_id))))
+#define APU_PCIL_CORE_X_IEN_WAKE_MASK (0x00000001U)
+#define CORE_0_IDS_WAKE_OFFSET (0x0000002CULL)
+#define APU_PCIL_CORE_X_IDS_WAKE_REG(cpu_id) (APU_PCLI + (CORE_0_IDS_WAKE_OFFSET + \
+ (APU_PCLI_CPU_STEP * (cpu_id))))
+#define APU_PCIL_CORE_X_IDS_WAKE_MASK (0x00000001U)
+#define CORE_0_ISR_POWER_OFFSET (0x00000010ULL)
+#define APU_PCIL_CORE_X_ISR_POWER_REG(cpu_id) (APU_PCLI + (CORE_0_ISR_POWER_OFFSET + \
+ (APU_PCLI_CPU_STEP * (cpu_id))))
+#define APU_PCIL_CORE_X_ISR_POWER_MASK U(0x00000001)
+#define CORE_0_IEN_POWER_OFFSET (0x00000018ULL)
#define APU_PCIL_CORE_X_IEN_POWER_REG(cpu_id) (APU_PCLI + (CORE_0_IEN_POWER_OFFSET + \
- (0x30 * cpu_id)))
+ (APU_PCLI_CPU_STEP * (cpu_id))))
#define APU_PCIL_CORE_X_IEN_POWER_MASK (0x00000001U)
-#define CORE_0_IDS_POWER_OFFSET (0x0000001CU)
+#define CORE_0_IDS_POWER_OFFSET (0x0000001CULL)
#define APU_PCIL_CORE_X_IDS_POWER_REG(cpu_id) (APU_PCLI + (CORE_0_IDS_POWER_OFFSET + \
- (0x30 * cpu_id)))
+ (APU_PCLI_CPU_STEP * (cpu_id))))
#define APU_PCIL_CORE_X_IDS_POWER_MASK (0x00000001U)
#define CORE_PWRDN_EN_BIT_MASK (0x1U)
@@ -122,9 +138,17 @@
* UART related constants
******************************************************************************/
#define VERSAL_NET_UART0_BASE U(0xF1920000)
+#define VERSAL_NET_UART1_BASE U(0xF1930000)
+
#define VERSAL_NET_UART_BAUDRATE 115200
+#if VERSAL_NET_CONSOLE_IS(pl011) || VERSAL_NET_CONSOLE_IS(pl011_0)
#define VERSAL_NET_UART_BASE VERSAL_NET_UART0_BASE
+#elif VERSAL_NET_CONSOLE_IS(pl011_1)
+#define VERSAL_NET_UART_BASE VERSAL_NET_UART1_BASE
+#else
+# error "invalid VERSAL_NET_CONSOLE"
+#endif
#define PLAT_VERSAL_NET_CRASH_UART_BASE VERSAL_NET_UART_BASE
#define PLAT_VERSAL_NET_CRASH_UART_CLK_IN_HZ VERSAL_NET_UART_CLOCK
diff --git a/plat/xilinx/versal_net/plat_psci_pm.c b/plat/xilinx/versal_net/plat_psci_pm.c
index 8beaa9a..c713061 100644
--- a/plat/xilinx/versal_net/plat_psci_pm.c
+++ b/plat/xilinx/versal_net/plat_psci_pm.c
@@ -196,6 +196,7 @@
VERBOSE("%s: power_state: 0x%x\n", __func__, power_state);
int32_t pstate = psci_get_pstate_type(power_state);
+ uint64_t i;
assert(req_state);
@@ -203,7 +204,8 @@
if (pstate == PSTATE_TYPE_STANDBY) {
req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE;
} else {
- req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE;
+ for (i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++)
+ req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE;
}
/* We expect the 'state id' to be zero */
@@ -221,8 +223,10 @@
*/
static void versal_net_get_sys_suspend_power_state(psci_power_state_t *req_state)
{
- req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE;
- req_state->pwr_domain_state[1] = PLAT_MAX_OFF_STATE;
+ uint64_t i;
+
+ for (i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++)
+ req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE;
}
static const struct plat_psci_ops versal_net_nopmc_psci_ops = {
diff --git a/plat/xilinx/versal_net/platform.mk b/plat/xilinx/versal_net/platform.mk
index b3d56bc..622ae98 100644
--- a/plat/xilinx/versal_net/platform.mk
+++ b/plat/xilinx/versal_net/platform.mk
@@ -53,6 +53,11 @@
HW_ASSISTED_COHERENCY := 1
VERSAL_NET_CONSOLE ?= pl011
+ifeq (${VERSAL_NET_CONSOLE}, $(filter ${VERSAL_NET_CONSOLE},pl011 pl011_0 pl011_1))
+else
+ $(error Please define VERSAL_NET_CONSOLE)
+endif
+
$(eval $(call add_define_val,VERSAL_NET_CONSOLE,VERSAL_NET_CONSOLE_ID_${VERSAL_NET_CONSOLE}))
PLAT_INCLUDES := -Iinclude/plat/arm/common/ \
diff --git a/plat/xilinx/versal_net/pm_service/pm_client.c b/plat/xilinx/versal_net/pm_service/pm_client.c
index 6487324..f543193 100644
--- a/plat/xilinx/versal_net/pm_service/pm_client.c
+++ b/plat/xilinx/versal_net/pm_service/pm_client.c
@@ -164,8 +164,18 @@
isb();
+ /* Clear power down interrupt status before enabling */
+ mmio_write_32(APU_PCIL_CORE_X_ISR_POWER_REG(cpu_id),
+ APU_PCIL_CORE_X_ISR_POWER_MASK);
+ /* Enable power down interrupt */
mmio_write_32(APU_PCIL_CORE_X_IEN_POWER_REG(cpu_id),
APU_PCIL_CORE_X_IEN_POWER_MASK);
+ /* Clear wakeup interrupt status before enabling */
+ mmio_write_32(APU_PCIL_CORE_X_ISR_WAKE_REG(cpu_id),
+ APU_PCIL_CORE_X_ISR_WAKE_MASK);
+ /* Enable wake interrupt */
+ mmio_write_32(APU_PCIL_CORE_X_IEN_WAKE_REG(cpu_id),
+ APU_PCIL_CORE_X_IEN_WAKE_MASK);
bakery_lock_release(&pm_client_secure_lock);
}
@@ -197,6 +207,7 @@
void pm_client_wakeup(const struct pm_proc *proc)
{
uint32_t cpuid = pm_get_cpuid(proc->node_id);
+ uintptr_t val;
if (cpuid == UNDEFINED_CPUID) {
return;
@@ -204,7 +215,22 @@
bakery_lock_get(&pm_client_secure_lock);
- /* TODO: clear powerdown bit for affected cpu */
+ /* Clear powerdown request */
+ val = read_cpu_pwrctrl_val();
+ val &= ~CORE_PWRDN_EN_BIT_MASK;
+ write_cpu_pwrctrl_val(val);
+
+ isb();
+
+ /* Disabled power down interrupt */
+ mmio_write_32(APU_PCIL_CORE_X_IDS_POWER_REG(cpuid),
+ APU_PCIL_CORE_X_IDS_POWER_MASK);
+ /* Clear wakeup interrupt status before disabling */
+ mmio_write_32(APU_PCIL_CORE_X_ISR_WAKE_REG(cpuid),
+ APU_PCIL_CORE_X_ISR_WAKE_MASK);
+ /* Disable wake interrupt */
+ mmio_write_32(APU_PCIL_CORE_X_IDS_WAKE_REG(cpuid),
+ APU_PCIL_CORE_X_IDS_WAKE_MASK);
bakery_lock_release(&pm_client_secure_lock);
}
diff --git a/plat/xilinx/zynqmp/aarch64/zynqmp_common.c b/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
index 3946e9b..7bdd5bd 100644
--- a/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
+++ b/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
@@ -215,7 +215,7 @@
#define ZYNQMP_PL_STATUS_MASK BIT(ZYNQMP_PL_STATUS_BIT)
#define ZYNQMP_CSU_VERSION_MASK ~(ZYNQMP_PL_STATUS_MASK)
-#define SILICON_ID_XCK24 0x4714093U
+#define SILICON_ID_XCK24 0x4712093U
#define SILICON_ID_XCK26 0x4724093U
static char *zynqmp_get_silicon_idcode_name(void)
diff --git a/plat/xilinx/zynqmp/pm_service/pm_svc_main.c b/plat/xilinx/zynqmp/pm_service/pm_svc_main.c
index b45ce6c..a3f0278 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_svc_main.c
+++ b/plat/xilinx/zynqmp/pm_service/pm_svc_main.c
@@ -334,29 +334,25 @@
SMC_RET1(handle, (uint64_t)ret);
case PM_GET_API_VERSION:
- /* Check is PM API version already verified */
- if (pm_ctx.api_version >= PM_VERSION) {
- if (ipi_irq_flag == 0U) {
- /*
- * Enable IPI IRQ
- * assume the rich OS is OK to handle callback IRQs now.
- * Even if we were wrong, it would not enable the IRQ in
- * the GIC.
- */
- pm_ipi_irq_enable(primary_proc);
- ipi_irq_flag = 1U;
- }
- SMC_RET1(handle, (uint64_t)PM_RET_SUCCESS |
- ((uint64_t)pm_ctx.api_version << 32));
+ if (ipi_irq_flag == 0U) {
+ /*
+ * Enable IPI IRQ
+ * assume the rich OS is OK to handle callback IRQs now.
+ * Even if we were wrong, it would not enable the IRQ in
+ * the GIC.
+ */
+ pm_ipi_irq_enable(primary_proc);
+ ipi_irq_flag = 1U;
}
-
+ SMC_RET1(handle, (uint64_t)PM_RET_SUCCESS |
+ ((uint64_t)pm_ctx.api_version << 32));
case PM_FPGA_LOAD:
ret = pm_fpga_load(pm_arg[0], pm_arg[1], pm_arg[2], pm_arg[3]);
SMC_RET1(handle, (uint64_t)ret);
case PM_FPGA_GET_STATUS:
{
- uint32_t value = 0;
+ uint32_t value = 0U;
ret = pm_fpga_get_status(&value);
SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
@@ -374,7 +370,7 @@
(uint64_t)result[2] | ((uint64_t)result[3] << 32));
case PM_IOCTL:
{
- uint32_t value = 0;
+ uint32_t value = 0U;
ret = pm_ioctl(pm_arg[0], pm_arg[1], pm_arg[2],
pm_arg[3], &value);
@@ -401,7 +397,7 @@
case PM_CLOCK_GETSTATE:
{
- uint32_t value = 0;
+ uint32_t value = 0U;
ret = pm_clock_getstate(pm_arg[0], &value);
SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
@@ -413,7 +409,7 @@
case PM_CLOCK_GETDIVIDER:
{
- uint32_t value = 0;
+ uint32_t value = 0U;
ret = pm_clock_getdivider(pm_arg[0], &value);
SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
@@ -442,7 +438,7 @@
case PM_CLOCK_GETPARENT:
{
- uint32_t value = 0;
+ uint32_t value = 0U;
ret = pm_clock_getparent(pm_arg[0], &value);
SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32U);
@@ -476,7 +472,7 @@
case PM_FPGA_READ:
{
- uint32_t value = 0;
+ uint32_t value = 0U;
ret = pm_fpga_read(pm_arg[0], pm_arg[1], pm_arg[2], pm_arg[3],
&value);
@@ -485,7 +481,7 @@
case PM_SECURE_AES:
{
- uint32_t value = 0;
+ uint32_t value = 0U;
ret = pm_aes_engine(pm_arg[0], pm_arg[1], &value);
SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32U);
@@ -497,7 +493,7 @@
case PM_PLL_GET_PARAMETER:
{
- uint32_t value = 0;
+ uint32_t value = 0U;
ret = pm_pll_get_parameter(pm_arg[0], pm_arg[1], &value);
SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value << 32U));
@@ -509,7 +505,7 @@
case PM_PLL_GET_MODE:
{
- uint32_t mode = 0;
+ uint32_t mode = 0U;
ret = pm_pll_get_mode(pm_arg[0], &mode);
SMC_RET1(handle, (uint64_t)ret | ((uint64_t)mode << 32U));
@@ -517,7 +513,7 @@
case PM_REGISTER_ACCESS:
{
- uint32_t value = 0;
+ uint32_t value = 0U;
ret = pm_register_access(pm_arg[0], pm_arg[1], pm_arg[2],
pm_arg[3], &value);
@@ -526,7 +522,7 @@
case PM_EFUSE_ACCESS:
{
- uint32_t value = 0;
+ uint32_t value = 0U;
#if defined(ZYNQMP_SECURE_EFUSES)
if (is_caller_non_secure(flags)) {
diff --git a/plat/xilinx/zynqmp/zynqmp_ipi.c b/plat/xilinx/zynqmp/zynqmp_ipi.c
index 4ea3c6a..acd31df 100644
--- a/plat/xilinx/zynqmp/zynqmp_ipi.c
+++ b/plat/xilinx/zynqmp/zynqmp_ipi.c
@@ -21,7 +21,7 @@
#include <plat_private.h>
/* Zynqmp ipi configuration table */
-const static struct ipi_config zynqmp_ipi_table[] = {
+static const struct ipi_config zynqmp_ipi_table[] = {
/* APU IPI */
{
.ipi_bit_mask = 0x1,
diff --git a/services/std_svc/rmmd/trp/trp_entry.S b/services/std_svc/rmmd/trp/trp_entry.S
index 47c1df1..3e1d8c9 100644
--- a/services/std_svc/rmmd/trp/trp_entry.S
+++ b/services/std_svc/rmmd/trp/trp_entry.S
@@ -83,7 +83,17 @@
mov x3, x23
bl trp_setup
bl trp_main
+ b 1f
+
warm_boot:
+ mov x0, x20
+ mov x1, x21
+ mov x2, x22
+ mov x3, x23
+ bl trp_validate_warmboot_args
+ cbnz x0, trp_panic /* Failed to validate warmboot args */
+
+1:
mov_imm x0, RMM_BOOT_COMPLETE
mov x1, xzr /* RMM_BOOT_SUCCESS */
smc #0
@@ -115,7 +125,29 @@
* ---------------------------------------------
*/
func trp_handler
+ /*
+ * Save Link Register and X4, as per SMCCC v1.2 its value
+ * must be preserved unless it contains result, as specified
+ * in the function definition.
+ */
+ stp x4, lr, [sp, #-16]!
+
+ /*
+ * Zero the space for X0-X3 in trp_smc_result structure
+ * and pass its address as the last argument.
+ */
+ stp xzr, xzr, [sp, #-16]!
+ stp xzr, xzr, [sp, #-16]!
+ mov x7, sp
+
bl trp_rmi_handler
- restore_args_call_smc
+
+ ldp x1, x2, [sp], #16
+ ldp x3, x4, [sp], #16
+ ldp x5, lr, [sp], #16
+
+ ldr x0, =RMM_RMI_REQ_COMPLETE
+ smc #0
+
b trp_handler
endfunc trp_handler
diff --git a/services/std_svc/rmmd/trp/trp_main.c b/services/std_svc/rmmd/trp/trp_main.c
index 5a56af0..196bc11 100644
--- a/services/std_svc/rmmd/trp/trp_main.c
+++ b/services/std_svc/rmmd/trp/trp_main.c
@@ -4,7 +4,6 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
-
#include <common/debug.h>
#include <plat/common/platform.h>
#include <services/rmm_core_manifest.h>
@@ -31,11 +30,11 @@
uint64_t x3)
{
/*
- * Validate boot parameters.
+ * Validate boot parameters
*
- * According to the Boot Interface ABI v.0.1, the
- * parameters recived from EL3 are:
- * x0: CPUID (verified earlier so not used)
+ * According to the Boot Interface ABI v.0.1,
+ * the parameters received from EL3 are:
+ * x0: CPUID (verified earlier, so not used)
* x1: Boot Interface version
* x2: PLATFORM_CORE_COUNT
* x3: Pointer to the shared memory area.
@@ -66,6 +65,24 @@
trp_early_platform_setup((rmm_manifest_t *)trp_shared_region_start);
}
+int trp_validate_warmboot_args(uint64_t x0, uint64_t x1,
+ uint64_t x2, uint64_t x3)
+{
+ /*
+ * Validate boot parameters for warm boot
+ *
+ * According to the Boot Interface ABI v.0.1, the parameters
+ * received from EL3 during warm boot are:
+ *
+ * x0: CPUID (verified earlier so not used here)
+ * [x1:x3]: RES0
+ */
+
+ (void)x0;
+
+ return ((x1 | x2 | x3) == 0UL) ? 0 : E_RMM_BOOT_UNKNOWN;
+}
+
/* Main function for TRP */
void trp_main(void)
{
@@ -73,14 +90,14 @@
NOTICE("TRP: %s\n", build_message);
NOTICE("TRP: Supported RMM-EL3 Interface ABI: v.%u.%u\n",
TRP_RMM_EL3_ABI_VERS_MAJOR, TRP_RMM_EL3_ABI_VERS_MINOR);
- NOTICE("TRP: Boot Manifest Version : v.%u.%u\n",
+ NOTICE("TRP: Boot Manifest Version: v.%u.%u\n",
RMMD_GET_MANIFEST_VERSION_MAJOR(trp_boot_manifest_version),
RMMD_GET_MANIFEST_VERSION_MINOR(trp_boot_manifest_version));
- INFO("TRP: Memory base : 0x%lx\n", (unsigned long)RMM_BASE);
- INFO("TRP: Base address for the shared region : 0x%lx\n",
+ INFO("TRP: Memory base: 0x%lx\n", (unsigned long)RMM_BASE);
+ INFO("TRP: Shared region base address: 0x%lx\n",
(unsigned long)trp_shared_region_start);
- INFO("TRP: Total size : 0x%lx bytes\n", (unsigned long)(RMM_END
- - RMM_BASE));
+ INFO("TRP: Total size: 0x%lx bytes\n",
+ (unsigned long)(RMM_END - RMM_BASE));
INFO("TRP: RMM-EL3 Interface ABI reported by EL3: v.%u.%u\n",
TRP_RMM_EL3_VERSION_GET_MAJOR(trp_boot_abi_version),
TRP_RMM_EL3_VERSION_GET_MINOR(trp_boot_abi_version));
@@ -89,62 +106,73 @@
/*******************************************************************************
* Returning RMI version back to Normal World
******************************************************************************/
-static trp_args_t *trp_ret_rmi_version(void)
+static void trp_ret_rmi_version(struct trp_smc_result *smc_ret)
{
VERBOSE("RMM version is %u.%u\n", RMI_ABI_VERSION_MAJOR,
RMI_ABI_VERSION_MINOR);
- return set_smc_args(RMM_RMI_REQ_COMPLETE, RMI_ABI_VERSION,
- 0, 0, 0, 0, 0, 0);
+ smc_ret->x[0] = RMI_ABI_VERSION;
}
/*******************************************************************************
* Transitioning granule of NON-SECURE type to REALM type
******************************************************************************/
-static trp_args_t *trp_asc_mark_realm(unsigned long long x1)
+static void trp_asc_mark_realm(unsigned long long x1,
+ struct trp_smc_result *smc_ret)
{
- unsigned long long ret;
-
VERBOSE("Delegating granule 0x%llx\n", x1);
- ret = trp_smc(set_smc_args(RMM_GTSI_DELEGATE, x1, 0, 0, 0, 0, 0, 0));
+ smc_ret->x[0] = trp_smc(set_smc_args(RMM_GTSI_DELEGATE, x1,
+ 0UL, 0UL, 0UL, 0UL, 0UL, 0UL));
- if (ret != 0ULL) {
+ if (smc_ret->x[0] != 0ULL) {
ERROR("Granule transition from NON-SECURE type to REALM type "
- "failed 0x%llx\n", ret);
+ "failed 0x%llx\n", smc_ret->x[0]);
}
- return set_smc_args(RMM_RMI_REQ_COMPLETE, ret, 0, 0, 0, 0, 0, 0);
}
/*******************************************************************************
* Transitioning granule of REALM type to NON-SECURE type
******************************************************************************/
-static trp_args_t *trp_asc_mark_nonsecure(unsigned long long x1)
+static void trp_asc_mark_nonsecure(unsigned long long x1,
+ struct trp_smc_result *smc_ret)
{
- unsigned long long ret;
-
VERBOSE("Undelegating granule 0x%llx\n", x1);
- ret = trp_smc(set_smc_args(RMM_GTSI_UNDELEGATE, x1, 0, 0, 0, 0, 0, 0));
+ smc_ret->x[0] = trp_smc(set_smc_args(RMM_GTSI_UNDELEGATE, x1,
+ 0UL, 0UL, 0UL, 0UL, 0UL, 0UL));
- if (ret != 0ULL) {
+ if (smc_ret->x[0] != 0ULL) {
ERROR("Granule transition from REALM type to NON-SECURE type "
- "failed 0x%llx\n", ret);
+ "failed 0x%llx\n", smc_ret->x[0]);
}
- return set_smc_args(RMM_RMI_REQ_COMPLETE, ret, 0, 0, 0, 0, 0, 0);
}
/*******************************************************************************
* Main RMI SMC handler function
******************************************************************************/
-trp_args_t *trp_rmi_handler(unsigned long fid, unsigned long long x1)
+void trp_rmi_handler(unsigned long fid,
+ unsigned long long x1, unsigned long long x2,
+ unsigned long long x3, unsigned long long x4,
+ unsigned long long x5, unsigned long long x6,
+ struct trp_smc_result *smc_ret)
{
+ /* Not used in the current implementation */
+ (void)x2;
+ (void)x3;
+ (void)x4;
+ (void)x5;
+ (void)x6;
+
switch (fid) {
case RMI_RMM_REQ_VERSION:
- return trp_ret_rmi_version();
+ trp_ret_rmi_version(smc_ret);
+ break;
case RMI_RMM_GRANULE_DELEGATE:
- return trp_asc_mark_realm(x1);
+ trp_asc_mark_realm(x1, smc_ret);
+ break;
case RMI_RMM_GRANULE_UNDELEGATE:
- return trp_asc_mark_nonsecure(x1);
+ trp_asc_mark_nonsecure(x1, smc_ret);
+ break;
default:
- ERROR("Invalid SMC code to %s, FID %lu\n", __func__, fid);
+ ERROR("Invalid SMC code to %s, FID %lx\n", __func__, fid);
+ smc_ret->x[0] = SMC_UNK;
}
- return set_smc_args(SMC_UNK, 0, 0, 0, 0, 0, 0, 0);
}
diff --git a/services/std_svc/rmmd/trp/trp_private.h b/services/std_svc/rmmd/trp/trp_private.h
index 945ae1c..d8c6960 100644
--- a/services/std_svc/rmmd/trp/trp_private.h
+++ b/services/std_svc/rmmd/trp/trp_private.h
@@ -53,5 +53,9 @@
uint64_t x2,
uint64_t x3);
+/* Validate arguments for warm boot only */
+int trp_validate_warmboot_args(uint64_t x0, uint64_t x1,
+ uint64_t x2, uint64_t x3);
+
#endif /* __ASSEMBLER__ */
#endif /* TRP_PRIVATE_H */
diff --git a/services/std_svc/spm/el3_spmc/spmc.h b/services/std_svc/spm/el3_spmc/spmc.h
index 5233650..61afee3 100644
--- a/services/std_svc/spm/el3_spmc/spmc.h
+++ b/services/std_svc/spm/el3_spmc/spmc.h
@@ -228,6 +228,12 @@
uint32_t uuid[4];
};
+/* FF-A Partition Info Get related macros. */
+#define FFA_PARTITION_INFO_GET_PROPERTIES_V1_0_MASK U(0x7)
+#define FFA_PARTITION_INFO_GET_EXEC_STATE_SHIFT U(8)
+#define FFA_PARTITION_INFO_GET_AARCH32_STATE U(0)
+#define FFA_PARTITION_INFO_GET_AARCH64_STATE U(1)
+
/* Reference to power management hooks */
extern const spd_pm_ops_t spmc_pm;
diff --git a/services/std_svc/spm/el3_spmc/spmc.mk b/services/std_svc/spm/el3_spmc/spmc.mk
index c674e71..6442af0 100644
--- a/services/std_svc/spm/el3_spmc/spmc.mk
+++ b/services/std_svc/spm/el3_spmc/spmc.mk
@@ -20,7 +20,9 @@
${PLAT}_el3_spmc_logical_sp.c)
+ifneq ($(wildcard $(SPMC_LP_SOURCES)),)
SPMC_SOURCES += $(SPMC_LP_SOURCES)
+endif
# Let the top-level Makefile know that we intend to include a BL32 image
NEED_BL32 := yes
diff --git a/services/std_svc/spm/el3_spmc/spmc_main.c b/services/std_svc/spm/el3_spmc/spmc_main.c
index 9b8621a..08e7218 100644
--- a/services/std_svc/spm/el3_spmc/spmc_main.c
+++ b/services/std_svc/spm/el3_spmc/spmc_main.c
@@ -746,6 +746,27 @@
}
/*
+ * Helper function to populate the properties field of a Partition Info Get
+ * descriptor.
+ */
+static uint32_t
+partition_info_get_populate_properties(uint32_t sp_properties,
+ enum sp_execution_state sp_ec_state)
+{
+ uint32_t properties = sp_properties;
+ uint32_t ec_state;
+
+ /* Determine the execution state of the SP. */
+ ec_state = sp_ec_state == SP_STATE_AARCH64 ?
+ FFA_PARTITION_INFO_GET_AARCH64_STATE :
+ FFA_PARTITION_INFO_GET_AARCH32_STATE;
+
+ properties |= ec_state << FFA_PARTITION_INFO_GET_EXEC_STATE_SHIFT;
+
+ return properties;
+}
+
+/*
* Collate the partition information in a v1.1 partition information
* descriptor format, this will be converter later if required.
*/
@@ -771,7 +792,12 @@
desc = &partitions[*partition_count];
desc->ep_id = el3_lp_descs[index].sp_id;
desc->execution_ctx_count = PLATFORM_CORE_COUNT;
- desc->properties = el3_lp_descs[index].properties;
+ /* LSPs must be AArch64. */
+ desc->properties =
+ partition_info_get_populate_properties(
+ el3_lp_descs[index].properties,
+ SP_STATE_AARCH64);
+
if (null_uuid) {
copy_uuid(desc->uuid, el3_lp_descs[index].uuid);
}
@@ -794,7 +820,11 @@
* S-EL1 SPs.
*/
desc->execution_ctx_count = PLATFORM_CORE_COUNT;
- desc->properties = sp_desc[index].properties;
+ desc->properties =
+ partition_info_get_populate_properties(
+ sp_desc[index].properties,
+ sp_desc[index].execution_state);
+
if (null_uuid) {
copy_uuid(desc->uuid, sp_desc[index].uuid);
}
@@ -835,7 +865,7 @@
/*
* If the caller of the PARTITION_INFO_GET ABI was a v1.0 caller, populate
- * the coresponding descriptor format from the v1.1 descriptor array.
+ * the corresponding descriptor format from the v1.1 descriptor array.
*/
static uint64_t partition_info_populate_v1_0(struct ffa_partition_info_v1_1
*partitions,
@@ -860,8 +890,10 @@
v1_0_partitions[index].ep_id = partitions[index].ep_id;
v1_0_partitions[index].execution_ctx_count =
partitions[index].execution_ctx_count;
+ /* Only report v1.0 properties. */
v1_0_partitions[index].properties =
- partitions[index].properties;
+ (partitions[index].properties &
+ FFA_PARTITION_INFO_GET_PROPERTIES_V1_0_MASK);
}
return 0;
}
diff --git a/services/std_svc/spm/el3_spmc/spmc_shared_mem.c b/services/std_svc/spm/el3_spmc/spmc_shared_mem.c
index 89d7b31..c039350 100644
--- a/services/std_svc/spm/el3_spmc/spmc_shared_mem.c
+++ b/services/std_svc/spm/el3_spmc/spmc_shared_mem.c
@@ -274,13 +274,15 @@
* spmc_shmem_obj_validate_id - Validate a partition ID is participating in
* a given memory transaction.
* @sp_id: Partition ID to validate.
- * @desc: Descriptor of the memory transaction.
- *
+ * @obj: The shared memory object containing the descriptor
+ * of the memory transaction.
* Return: true if ID is valid, else false.
*/
-bool spmc_shmem_obj_validate_id(const struct ffa_mtd *desc, uint16_t sp_id)
+bool spmc_shmem_obj_validate_id(struct spmc_shmem_obj *obj, uint16_t sp_id)
{
bool found = false;
+ struct ffa_mtd *desc = &obj->desc;
+ size_t desc_size = obj->desc_size;
/* Validate the partition is a valid participant. */
for (unsigned int i = 0U; i < desc->emad_count; i++) {
@@ -290,6 +292,15 @@
emad = spmc_shmem_obj_get_emad(desc, i,
MAKE_FFA_VERSION(1, 1),
&emad_size);
+ /*
+ * Validate the calculated emad address resides within the
+ * descriptor.
+ */
+ if ((emad == NULL) || (uintptr_t) emad >=
+ (uintptr_t)((uint8_t *) desc + desc_size)) {
+ VERBOSE("Invalid emad.\n");
+ break;
+ }
if (sp_id == emad->mapd.endpoint_id) {
found = true;
break;
@@ -385,7 +396,8 @@
emad_array[0].comp_mrd_offset);
/* Check the calculated address is within the memory descriptor. */
- if ((uintptr_t) mrd >= (uintptr_t)((uint8_t *) orig + desc_size)) {
+ if (((uintptr_t) mrd + sizeof(struct ffa_comp_mrd)) >
+ (uintptr_t)((uint8_t *) orig + desc_size)) {
return 0;
}
size += mrd->address_range_count * sizeof(struct ffa_cons_mrd);
@@ -424,7 +436,8 @@
emad_array[0].comp_mrd_offset);
/* Check the calculated address is within the memory descriptor. */
- if ((uintptr_t) mrd >= (uintptr_t)((uint8_t *) orig + desc_size)) {
+ if (((uintptr_t) mrd + sizeof(struct ffa_comp_mrd)) >
+ (uintptr_t)((uint8_t *) orig + desc_size)) {
return 0;
}
size += mrd->address_range_count * sizeof(struct ffa_cons_mrd);
@@ -475,6 +488,12 @@
/* Copy across the emad structs. */
for (unsigned int i = 0U; i < out->emad_count; i++) {
+ /* Bound check for emad array. */
+ if (((uint8_t *)emad_array_in + sizeof(struct ffa_emad_v1_0)) >
+ ((uint8_t *) mtd_orig + orig->desc_size)) {
+ VERBOSE("%s: Invalid mtd structure.\n", __func__);
+ return false;
+ }
memcpy(&emad_array_out[i], &emad_array_in[i],
sizeof(struct ffa_emad_v1_0));
}
@@ -542,6 +561,7 @@
size_t mrd_out_offset;
size_t emad_out_array_size;
size_t mrd_size = 0;
+ size_t orig_desc_size = orig->desc_size;
/* Populate the v1.0 descriptor format from the v1.1 struct. */
out->sender_id = mtd_orig->sender_id;
@@ -559,6 +579,12 @@
/* Copy across the emad structs. */
emad_in = emad_array_in;
for (unsigned int i = 0U; i < out->emad_count; i++) {
+ /* Bound check for emad array. */
+ if (((uint8_t *)emad_in + sizeof(struct ffa_emad_v1_0)) >
+ ((uint8_t *) mtd_orig + orig_desc_size)) {
+ VERBOSE("%s: Invalid mtd structure.\n", __func__);
+ return false;
+ }
memcpy(&emad_array_out[i], emad_in,
sizeof(struct ffa_emad_v1_0));
@@ -1442,7 +1468,7 @@
}
/* Validate the caller is a valid participant. */
- if (!spmc_shmem_obj_validate_id(&obj->desc, sp_ctx->sp_id)) {
+ if (!spmc_shmem_obj_validate_id(obj, sp_ctx->sp_id)) {
WARN("%s: Invalid endpoint ID (0x%x).\n",
__func__, sp_ctx->sp_id);
ret = FFA_ERROR_INVALID_PARAMETER;
@@ -1761,7 +1787,7 @@
}
/* Validate the caller is a valid participant. */
- if (!spmc_shmem_obj_validate_id(&obj->desc, sp_ctx->sp_id)) {
+ if (!spmc_shmem_obj_validate_id(obj, sp_ctx->sp_id)) {
WARN("%s: Invalid endpoint ID (0x%x).\n",
__func__, req->endpoint_array[0]);
ret = FFA_ERROR_INVALID_PARAMETER;
diff --git a/services/std_svc/spmd/spmd_main.c b/services/std_svc/spmd/spmd_main.c
index 7e6c89d..afd0f2e 100644
--- a/services/std_svc/spmd/spmd_main.c
+++ b/services/std_svc/spmd/spmd_main.c
@@ -868,7 +868,8 @@
FFA_ERROR_NOT_SUPPORTED);
}
- /* Fall through to forward the call to the other world */
+ /* Forward the call to the other world */
+ /* fallthrough */
case FFA_MSG_SEND:
case FFA_MSG_SEND_DIRECT_RESP_SMC64:
case FFA_MEM_DONATE_SMC32:
@@ -908,7 +909,8 @@
spmd_spm_core_sync_exit(0ULL);
}
- /* Fall through to forward the call to the other world */
+ /* Forward the call to the other world */
+ /* fallthrough */
case FFA_INTERRUPT:
case FFA_MSG_YIELD:
/* This interface must be invoked only by the Secure world */
diff --git a/services/std_svc/trng/trng_entropy_pool.c b/services/std_svc/trng/trng_entropy_pool.c
index 30105b3..dd08c5e 100644
--- a/services/std_svc/trng/trng_entropy_pool.c
+++ b/services/std_svc/trng/trng_entropy_pool.c
@@ -66,7 +66,7 @@
bool trng_pack_entropy(uint32_t nbits, uint64_t *out)
{
bool ret = true;
-
+ uint32_t bits_to_discard = nbits;
spin_lock(&trng_pool_lock);
if (!trng_fill_entropy(nbits)) {
@@ -111,9 +111,66 @@
* 5 4 3 2 1 0 7 6
* [e,e,e,e,e,e,e,e]
*/
- out[word_i] = 0;
out[word_i] |= entropy[ENTROPY_WORD_INDEX(word_i)] >> rshift;
+ /**
+ * Discarding the used/packed entropy bits from the respective
+ * words, (word_i) and (word_i+1) as applicable.
+ * In each iteration of the loop, we pack 64bits of entropy to
+ * the output buffer. The bits are picked linearly starting from
+ * 1st word (entropy[0]) till 4th word (entropy[3]) and then
+ * rolls back (entropy[0]). Discarding of bits is managed
+ * similarly.
+ *
+ * The following diagram illustrates the logic:
+ *
+ * |---------entropy pool----------|
+ * C var |--(word_i + 1)-|----word_i-----|
+ * bit idx |7 6 5 4 3 2 1 0|7 6 5 4 3 2 1 0|
+ * [e,e,e,e,e,e,e,e|e,e,0,0,0,0,0,0]
+ * | [e,e,e,e,e,e,e,e] |
+ * | |--out[word_i]--| |
+ * lshift|---| |--rshift---|
+ * |e,e|0,0,0,0,0,0,0,0|0,0,0,0,0,0|
+ * |<== || ==>|
+ * bits_to_discard (from these bytes)
+ *
+ * variable(bits_to_discard): Tracks the amount of bits to be
+ * discarded and is updated accordingly in each iteration.
+ *
+ * It monitors these packed bits from respective word_i and
+ * word_i+1 and overwrites them with zeros accordingly.
+ * It discards linearly from the lowest index and moves upwards
+ * until bits_to_discard variable becomes zero.
+ *
+ * In the above diagram,for example, we pack 2bytes(7th and 6th
+ * from word_i) and 6bytes(0th till 5th from word_i+1), combine
+ * and pack them as 64bit to output buffer out[i].
+ * Depending on the number of bits requested, we discard the
+ * bits from these packed bytes by overwriting them with zeros.
+ */
+
+ /*
+ * If the bits to be discarded is lesser than the amount of bits
+ * copied to the output buffer from word_i, we discard that much
+ * amount of bits only.
+ */
+ if (bits_to_discard < (BITS_PER_WORD - rshift)) {
+ entropy[ENTROPY_WORD_INDEX(word_i)] &=
+ (~0ULL << ((bits_to_discard+rshift) % BITS_PER_WORD));
+ bits_to_discard = 0;
+ } else {
+ /*
+ * If the bits to be discarded is more than the amount of valid
+ * upper bits from word_i, which has been copied to the output
+ * buffer, we just set the entire word_i to 0, as the lower bits
+ * will be already zeros from previous operations, and the
+ * bits_to_discard is updated precisely.
+ */
+ entropy[ENTROPY_WORD_INDEX(word_i)] = 0;
+ bits_to_discard -= (BITS_PER_WORD - rshift);
+ }
+
/*
* Note that a shift of 64 bits is treated as a shift of 0 bits.
* When the shift amount is the same as the BITS_PER_WORD, we
@@ -123,6 +180,35 @@
if (lshift != BITS_PER_WORD) {
out[word_i] |= entropy[ENTROPY_WORD_INDEX(word_i + 1)]
<< lshift;
+ /**
+ * Discarding the remaining packed bits from upperword
+ * (word[i+1]) which was copied to output buffer by
+ * overwriting with zeros.
+ *
+ * If the remaining bits to be discarded is lesser than
+ * the amount of bits from [word_i+1], which has been
+ * copied to the output buffer, we overwrite that much
+ * amount of bits only.
+ */
+ if (bits_to_discard < (BITS_PER_WORD - lshift)) {
+ entropy[ENTROPY_WORD_INDEX(word_i+1)] &=
+ (~0ULL << ((bits_to_discard) % BITS_PER_WORD));
+ bits_to_discard = 0;
+ } else {
+ /*
+ * If bits to discard is more than the bits from word_i+1
+ * which got packed into the output, then we discard all
+ * those copied bits.
+ *
+ * Note: we cannot set the entire word_i+1 to 0, as
+ * there are still some unused valid entropy bits at the
+ * upper end for future use.
+ */
+ entropy[ENTROPY_WORD_INDEX(word_i+1)] &=
+ (~0ULL << ((BITS_PER_WORD - lshift) % BITS_PER_WORD));
+ bits_to_discard -= (BITS_PER_WORD - lshift);
+ }
+
}
}
const uint64_t mask = ~0ULL >> (BITS_PER_WORD - (nbits % BITS_PER_WORD));
diff --git a/tools/nxp/create_pbl/create_pbl.c b/tools/nxp/create_pbl/create_pbl.c
index 9457a00..792747f 100644
--- a/tools/nxp/create_pbl/create_pbl.c
+++ b/tools/nxp/create_pbl/create_pbl.c
@@ -823,7 +823,9 @@
}
}
- if ((args & MAND_ARG_MASK) != MAND_ARG_MASK) {
+ if ((args & MAND_ARG_MASK) != MAND_ARG_MASK
+ || pblimg.rcw_nm == NULL
+ || pblimg.imagefile == NULL) {
print_usage();
}
diff --git a/tools/sptool/sp_mk_generator.py b/tools/sptool/sp_mk_generator.py
index f3af584..4067331 100644
--- a/tools/sptool/sp_mk_generator.py
+++ b/tools/sptool/sp_mk_generator.py
@@ -132,20 +132,21 @@
sp_pkg = get_sp_pkg(sp, args)
sp_dtb_name = os.path.basename(get_file_from_layout(sp_layout[sp]["pm"]))[:-1] + "b"
sp_dtb = os.path.join(args["out_dir"], f"fdts/{sp_dtb_name}")
+ sp_img = get_sp_img_full_path(sp_layout[sp], args)
# Do not generate rule if already there.
if is_line_in_sp_gen(f'{sp_pkg}:', args):
return args
write_to_sp_mk_gen(f"SP_PKGS += {sp_pkg}\n", args)
- sptool_args = f" -i {get_sp_img_full_path(sp_layout[sp], args)}:{sp_dtb}"
+ sptool_args = f" -i {sp_img}:{sp_dtb}"
pm_offset = get_pm_offset(sp_layout[sp])
sptool_args += f" --pm-offset {pm_offset}" if pm_offset is not None else ""
image_offset = get_image_offset(sp_layout[sp])
sptool_args += f" --img-offset {image_offset}" if image_offset is not None else ""
sptool_args += f" -o {sp_pkg}"
sppkg_rule = f'''
-{sp_pkg}: {sp_dtb}
+{sp_pkg}: {sp_dtb} {sp_img}
\t$(Q)echo Generating {sp_pkg}
\t$(Q)$(PYTHON) $(SPTOOL) {sptool_args}
'''