Merge "refactor(st-pmic): use LOG_LEVEL for regulator debug output" into integration
diff --git a/bl1/bl1_fwu.c b/bl1/bl1_fwu.c
index 6d4dc7e..167a22e 100644
--- a/bl1/bl1_fwu.c
+++ b/bl1/bl1_fwu.c
@@ -170,6 +170,9 @@
uintptr_t checked_image_base, checked_image_end;
checked_desc = bl1_plat_get_image_desc(image_id);
+
+ assert(checked_desc != NULL);
+
checked_info = &checked_desc->image_info;
/* Image being checked mustn't be empty. */
diff --git a/common/tf_log.c b/common/tf_log.c
index 2d976f6..bef1739 100644
--- a/common/tf_log.c
+++ b/common/tf_log.c
@@ -61,7 +61,7 @@
return;
}
- putchar('\n');
+ (void)putchar((int32_t)'\n');
}
/*
diff --git a/fdts/fvp-base-psci-common.dtsi b/fdts/fvp-base-psci-common.dtsi
index 95ea2a1..bdb0229 100644
--- a/fdts/fvp-base-psci-common.dtsi
+++ b/fdts/fvp-base-psci-common.dtsi
@@ -29,7 +29,8 @@
chosen {
stdout-path = "serial0:115200n8";
-#if (ENABLE_RME == 1)
+/* SPM_MM doesn't like this */
+#if SPM_MM == 0
bootargs = "console=ttyAMA0 earlycon=pl011,0x1c090000 root=/dev/vda ip=on";
#endif
};
diff --git a/fdts/stm32mp25-ddr4-2x8Gbits-2x16bits-1200MHz.dtsi b/fdts/stm32mp25-ddr4-2x8Gbits-2x16bits-1200MHz.dtsi
index 674cb3d..223761f 100644
--- a/fdts/stm32mp25-ddr4-2x8Gbits-2x16bits-1200MHz.dtsi
+++ b/fdts/stm32mp25-ddr4-2x8Gbits-2x16bits-1200MHz.dtsi
@@ -1,21 +1,21 @@
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
- * Copyright (C) 2022-2024, STMicroelectronics - All Rights Reserved
+ * Copyright (C) 2022-2025, STMicroelectronics - All Rights Reserved
*/
/*
* STM32MP25 DDR4 board configuration
* DDR4 2x8Gbits 2x16bits 1200MHz
*
- * version 1
- * package 1 Package selection (14x14 and 18x18)
- * memclk 1200MHz (2x DFI clock) + range check
- * Speed_Bin Worse from JEDEC
- * width 32 32: full width / 16: half width
- * ranks 1 Single or Dual rank
- * density 8Gbits (per 16bit device)
- * Addressing RBC row/bank interleaving
- * RDBI No Read DBI
+ * version 2
+ * package 1 Package selection (14x14 and 18x18)
+ * memclk 1200MHz (2x DFI clock) + range check
+ * Speed_Bin Worse from JEDEC
+ * device_width 16 x16 by default
+ * width 32 32: full width / 16: half width
+ * density 8Gbits (per device)
+ * Addressing RBC row/bank interleaving
+ * RDBI No Read DBI
*/
#define DDR_MEM_NAME "DDR4 2x8Gbits 2x16bits 1200MHz"
@@ -49,6 +49,7 @@
#define DDR_INIT7 0x00000C16
#define DDR_DIMMCTL 0x00000000
#define DDR_RANKCTL 0x0000066F
+#define DDR_RANKCTL1 0x0000000D
#define DDR_DRAMTMG0 0x11152815
#define DDR_DRAMTMG1 0x0004051E
#define DDR_DRAMTMG2 0x0609060D
@@ -94,31 +95,34 @@
#define DDR_ADDRMAP11 0x00000007
#define DDR_ODTCFG 0x06000618
#define DDR_ODTMAP 0x00000001
-#define DDR_SCHED 0x00000F00
+#define DDR_SCHED 0x80001B00
#define DDR_SCHED1 0x00000000
-#define DDR_PERFHPR1 0x0F000001
-#define DDR_PERFLPR1 0x0F000080
-#define DDR_PERFWR1 0x01000200
+#define DDR_PERFHPR1 0x04000200
+#define DDR_PERFLPR1 0x08000080
+#define DDR_PERFWR1 0x08000400
+#define DDR_SCHED3 0x04040208
+#define DDR_SCHED4 0x08400810
#define DDR_DBG0 0x00000000
#define DDR_DBG1 0x00000000
#define DDR_DBGCMD 0x00000000
#define DDR_SWCTL 0x00000000
+#define DDR_SWCTLSTATIC 0x00000000
#define DDR_POISONCFG 0x00000000
#define DDR_PCCFG 0x00000000
-#define DDR_PCFGR_0 0x00004100
+#define DDR_PCFGR_0 0x00704100
#define DDR_PCFGW_0 0x00004100
#define DDR_PCTRL_0 0x00000000
-#define DDR_PCFGQOS0_0 0x00200007
-#define DDR_PCFGQOS1_0 0x01000100
-#define DDR_PCFGWQOS0_0 0x00000C07
-#define DDR_PCFGWQOS1_0 0x02000200
-#define DDR_PCFGR_1 0x00004100
+#define DDR_PCFGQOS0_0 0x0021000C
+#define DDR_PCFGQOS1_0 0x01000080
+#define DDR_PCFGWQOS0_0 0x01100C07
+#define DDR_PCFGWQOS1_0 0x04000200
+#define DDR_PCFGR_1 0x00704100
#define DDR_PCFGW_1 0x00004100
#define DDR_PCTRL_1 0x00000000
-#define DDR_PCFGQOS0_1 0x00200007
-#define DDR_PCFGQOS1_1 0x01000180
-#define DDR_PCFGWQOS0_1 0x00000C07
-#define DDR_PCFGWQOS1_1 0x04000400
+#define DDR_PCFGQOS0_1 0x00100007
+#define DDR_PCFGQOS1_1 0x01000080
+#define DDR_PCFGWQOS0_1 0x01100C07
+#define DDR_PCFGWQOS1_1 0x04000200
#define DDR_UIB_DRAMTYPE 0x00000000
#define DDR_UIB_DIMMTYPE 0x00000004
diff --git a/fdts/stm32mp25-lpddr4-1x16Gbits-1x32bits-1200MHz.dtsi b/fdts/stm32mp25-lpddr4-1x16Gbits-1x32bits-1200MHz.dtsi
index 3917dc6..32424d0 100644
--- a/fdts/stm32mp25-lpddr4-1x16Gbits-1x32bits-1200MHz.dtsi
+++ b/fdts/stm32mp25-lpddr4-1x16Gbits-1x32bits-1200MHz.dtsi
@@ -7,7 +7,7 @@
* STM32MP25 LPDDR4 board configuration
* LPDDR4 1x16Gbits 1x32bits 1200MHz
*
- * version 1
+ * version 2
* memclk 1200MHz (2x DFI clock)
* width 32 32: full width / 16: half width
* ranks 1 Single or Dual rank
@@ -46,10 +46,11 @@
#define DDR_INIT3 0x00C40024
#define DDR_INIT4 0x00310008
#define DDR_INIT5 0x00100004
-#define DDR_INIT6 0x00660050
-#define DDR_INIT7 0x00050019
+#define DDR_INIT6 0x00660047
+#define DDR_INIT7 0x00050047
#define DDR_DIMMCTL 0x00000000
#define DDR_RANKCTL 0x0000066F
+#define DDR_RANKCTL1 0x00000011
#define DDR_DRAMTMG0 0x1718141A
#define DDR_DRAMTMG1 0x00050524
#define DDR_DRAMTMG2 0x060C1111
@@ -95,25 +96,28 @@
#define DDR_ADDRMAP11 0x00000007
#define DDR_ODTCFG 0x04000400
#define DDR_ODTMAP 0x00000000
-#define DDR_SCHED 0x00001B00
+#define DDR_SCHED 0x80001B00
#define DDR_SCHED1 0x00000000
#define DDR_PERFHPR1 0x04000200
#define DDR_PERFLPR1 0x08000080
#define DDR_PERFWR1 0x08000400
+#define DDR_SCHED3 0x04040208
+#define DDR_SCHED4 0x08400810
#define DDR_DBG0 0x00000000
#define DDR_DBG1 0x00000000
#define DDR_DBGCMD 0x00000000
#define DDR_SWCTL 0x00000000
+#define DDR_SWCTLSTATIC 0x00000000
#define DDR_POISONCFG 0x00000000
#define DDR_PCCFG 0x00000000
-#define DDR_PCFGR_0 0x00004100
+#define DDR_PCFGR_0 0x00704100
#define DDR_PCFGW_0 0x00004100
#define DDR_PCTRL_0 0x00000000
#define DDR_PCFGQOS0_0 0x0021000C
#define DDR_PCFGQOS1_0 0x01000080
#define DDR_PCFGWQOS0_0 0x01100C07
#define DDR_PCFGWQOS1_0 0x04000200
-#define DDR_PCFGR_1 0x00004100
+#define DDR_PCFGR_1 0x00704100
#define DDR_PCFGW_1 0x00004100
#define DDR_PCTRL_1 0x00000000
#define DDR_PCFGQOS0_1 0x00100007
@@ -148,8 +152,8 @@
#define DDR_UIA_EXTCALRESVAL 0x00000000
#define DDR_UIA_IS2TTIMING_0 0x00000000
#define DDR_UIA_ODTIMPEDANCE_0 0x00000035
-#define DDR_UIA_TXIMPEDANCE_0 0x0000003C
-#define DDR_UIA_ATXIMPEDANCE 0x0000001E
+#define DDR_UIA_TXIMPEDANCE_0 0x00000028
+#define DDR_UIA_ATXIMPEDANCE 0x00000028
#define DDR_UIA_MEMALERTEN 0x00000000
#define DDR_UIA_MEMALERTPUIMP 0x00000000
#define DDR_UIA_MEMALERTVREFLEVEL 0x00000000
@@ -157,7 +161,7 @@
#define DDR_UIA_DISDYNADRTRI_0 0x00000001
#define DDR_UIA_PHYMSTRTRAININTERVAL_0 0x0000000A
#define DDR_UIA_PHYMSTRMAXREQTOACK_0 0x00000005
-#define DDR_UIA_WDQSEXT 0x00000000
+#define DDR_UIA_WDQSEXT 0x00000001
#define DDR_UIA_CALINTERVAL 0x00000009
#define DDR_UIA_CALONCE 0x00000000
#define DDR_UIA_LP4RL_0 0x00000004
@@ -193,9 +197,9 @@
#define DDR_UIM_MR5_0 0x00000000
#define DDR_UIM_MR6_0 0x00000000
#define DDR_UIM_MR11_0 0x00000066
-#define DDR_UIM_MR12_0 0x00000050
+#define DDR_UIM_MR12_0 0x00000047
#define DDR_UIM_MR13_0 0x00000008
-#define DDR_UIM_MR14_0 0x00000019
+#define DDR_UIM_MR14_0 0x00000047
#define DDR_UIM_MR22_0 0x00000005
#define DDR_UIS_SWIZZLE_0 0x00000003
diff --git a/fdts/stm32mp25-lpddr4-1x32Gbits-1x32bits-1200MHz.dtsi b/fdts/stm32mp25-lpddr4-1x32Gbits-1x32bits-1200MHz.dtsi
index 53d6b7d..0df2a4d 100644
--- a/fdts/stm32mp25-lpddr4-1x32Gbits-1x32bits-1200MHz.dtsi
+++ b/fdts/stm32mp25-lpddr4-1x32Gbits-1x32bits-1200MHz.dtsi
@@ -161,7 +161,7 @@
#define DDR_UIA_DISDYNADRTRI_0 0x00000001
#define DDR_UIA_PHYMSTRTRAININTERVAL_0 0x0000000A
#define DDR_UIA_PHYMSTRMAXREQTOACK_0 0x00000005
-#define DDR_UIA_WDQSEXT 0x00000000
+#define DDR_UIA_WDQSEXT 0x00000001
#define DDR_UIA_CALINTERVAL 0x00000009
#define DDR_UIA_CALONCE 0x00000000
#define DDR_UIA_LP4RL_0 0x00000004
diff --git a/include/drivers/arm/css/css_scp.h b/include/drivers/arm/css/css_scp.h
index 5395546..c3ce1d6 100644
--- a/include/drivers/arm/css/css_scp.h
+++ b/include/drivers/arm/css/css_scp.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2025, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -45,8 +45,11 @@
CASSERT(SCP_BL2_LIMIT <= BL2_BASE, assert_scp_bl2_overwrite_bl2);
CASSERT(SCP_BL2U_LIMIT <= BL2_BASE, assert_scp_bl2u_overwrite_bl2);
+#if !TRANSFER_LIST
CASSERT(SCP_BL2_BASE >= ARM_FW_CONFIG_LIMIT, assert_scp_bl2_overflow);
CASSERT(SCP_BL2U_BASE >= ARM_FW_CONFIG_LIMIT, assert_scp_bl2u_overflow);
+#endif /* !TRANSFER_LIST */
+
#endif
#endif /* CSS_SCP_H */
diff --git a/include/drivers/delay_timer.h b/include/drivers/delay_timer.h
index e9fdfb7..0ef6831 100644
--- a/include/drivers/delay_timer.h
+++ b/include/drivers/delay_timer.h
@@ -21,7 +21,7 @@
* the clock period in microseconds.
********************************************************************/
-typedef struct timer_ops {
+typedef struct timer_operation {
uint32_t (*get_timer_value)(void);
uint32_t clk_mult;
uint32_t clk_div;
diff --git a/include/drivers/st/stpmic2.h b/include/drivers/st/stpmic2.h
index edb56e0..b2aadfb 100644
--- a/include/drivers/st/stpmic2.h
+++ b/include/drivers/st/stpmic2.h
@@ -146,6 +146,51 @@
#define INT_DBG_LATCH_R3 0x82
#define INT_DBG_LATCH_R4 0x83
+/* NVM user control registers */
+#define NVM_SR 0x8E
+#define NVM_CR 0x8F
+
+/* NVM user shadow registers */
+#define NVM_MAIN_CTRL_SHR1 0x90
+#define NVM_MAIN_CTRL_SHR2 0x91
+#define NVM_RANK_SHR1 0x92
+#define NVM_RANK_SHR2 0x93
+#define NVM_RANK_SHR3 0x94
+#define NVM_RANK_SHR4 0x95
+#define NVM_RANK_SHR5 0x96
+#define NVM_RANK_SHR6 0x97
+#define NVM_RANK_SHR7 0x98
+#define NVM_RANK_SHR8 0x99
+#define NVM_BUCK_MODE_SHR1 0x9A
+#define NVM_BUCK_MODE_SHR2 0x9B
+#define NVM_BUCK1_VOUT_SHR 0x9C
+#define NVM_BUCK2_VOUT_SHR 0x9D
+#define NVM_BUCK3_VOUT_SHR 0x9E
+#define NVM_BUCK4_VOUT_SHR 0x9F
+#define NVM_BUCK5_VOUT_SHR 0xA0
+#define NVM_BUCK6_VOUT_SHR 0xA1
+#define NVM_BUCK7_VOUT_SHR 0xA2
+#define NVM_LDO2_SHR 0xA3
+#define NVM_LDO3_SHR 0xA4
+#define NVM_LDO5_SHR 0xA5
+#define NVM_LDO6_SHR 0xA6
+#define NVM_LDO7_SHR 0xA7
+#define NVM_LDO8_SHR 0xA8
+#define NVM_PD_SHR1 0xA9
+#define NVM_PD_SHR2 0xAA
+#define NVM_PD_SHR3 0xAB
+#define NVM_BUCKS_IOUT_SHR1 0xAC
+#define NVM_BUCKS_IOUT_SHR2 0xAD
+#define NVM_LDOS_IOUT_SHR 0xAE
+#define NVM_FS_OCP_SHR1 0xAF
+#define NVM_FS_OCP_SHR2 0xB0
+#define NVM_FS_SHR1 0xB1
+#define NVM_FS_SHR2 0xB2
+#define NVM_FS_SHR3 0xB3
+#define NVM_I2C_ADDR_SHR 0xB5
+#define NVM_USER_SHR1 0xB6
+#define NVM_USER_SHR2 0xB7
+
/* BUCKS_MRST_CR bits definition */
#define BUCK1_MRST BIT(0)
#define BUCK2_MRST BIT(1)
@@ -237,6 +282,16 @@
#define FS_OCP_LDO7 BIT(6)
#define FS_OCP_LDO8 BIT(7)
+/* NVM_CR */
+#define NVM_CMD_MASK GENMASK_32(1, 0)
+
+#define NVM_CMD_PROGRAM 1
+#define NVM_CMD_READ 2
+
+/* NVM_SR */
+#define NVM_BUSY BIT(0)
+#define NVM_WRITE_FAIL BIT(1)
+
/* IRQ definitions */
#define IT_PONKEY_F 0
#define IT_PONKEY_R 1
diff --git a/include/services/ffa_svc.h b/include/services/ffa_svc.h
index f5a9a2d..0010d2b 100644
--- a/include/services/ffa_svc.h
+++ b/include/services/ffa_svc.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020-2024, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2025, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -57,8 +57,8 @@
<< FFA_MSG_SEND_ATTRS_BLK_SHIFT)
/* Defines for FF-A framework messages exchanged using direct messages. */
-#define FFA_FWK_MSG_BIT BIT(31)
-#define FFA_FWK_MSG_MASK 0xFF
+#define FFA_FWK_MSG_BIT BIT_32(31)
+#define FFA_FWK_MSG_MASK U(0xFF)
#define FFA_FWK_MSG_PSCI U(0x0)
/* Defines for FF-A power management messages framework messages. */
diff --git a/lib/el3_runtime/aarch64/context.S b/lib/el3_runtime/aarch64/context.S
index 1e6a42e..243a372 100644
--- a/lib/el3_runtime/aarch64/context.S
+++ b/lib/el3_runtime/aarch64/context.S
@@ -75,6 +75,9 @@
*/
#if CTX_INCLUDE_FPREGS
func fpregs_context_save
+.arch_extension fp
+ /* Temporarily enable floating point */
+
/* Save x0 and pass its original value to fpregs_state_save */
mov x1, x0
@@ -97,6 +100,7 @@
fpregs_state_save x1, x9
+.arch_extension nofp
ret
endfunc fpregs_context_save
@@ -115,6 +119,9 @@
* ------------------------------------------------------------------
*/
func fpregs_context_restore
+.arch_extension fp
+ /* Temporarily enable floating point */
+
/* Save x0 and pass its original value to fpregs_state_restore */
mov x1, x0
@@ -137,6 +144,7 @@
fpregs_state_restore x1, x9
+.arch_extension nofp
ret
endfunc fpregs_context_restore
#endif /* CTX_INCLUDE_FPREGS */
diff --git a/lib/psci/psci_common.c b/lib/psci/psci_common.c
index 2d33350..17ecab8 100644
--- a/lib/psci/psci_common.c
+++ b/lib/psci/psci_common.c
@@ -1299,7 +1299,8 @@
/* Need to wait for other cores to shutdown */
if (wait_ms != 0U) {
- while ((wait_ms-- != 0U) && (!psci_is_last_on_cpu(this_cpu_idx))) {
+ for (uint32_t delay_ms = wait_ms; ((delay_ms != 0U) &&
+ (!psci_is_last_on_cpu(this_cpu_idx))); delay_ms--) {
mdelay(1U);
}
diff --git a/lib/psci/psci_off.c b/lib/psci/psci_off.c
index 577fdd7..932a039 100644
--- a/lib/psci/psci_off.c
+++ b/lib/psci/psci_off.c
@@ -94,7 +94,7 @@
if ((psci_spd_pm != NULL) && (psci_spd_pm->svc_off != NULL)) {
rc = psci_spd_pm->svc_off(0);
if (rc != PSCI_E_SUCCESS)
- goto exit;
+ goto off_exit;
}
/*
@@ -127,7 +127,7 @@
plat_psci_stat_accounting_start(&state_info);
#endif
-exit:
+off_exit:
/*
* Release the locks corresponding to each power level in the
* reverse order to which they were acquired.
diff --git a/lib/psci/psci_on.c b/lib/psci/psci_on.c
index 7e161dd..3eacb9c 100644
--- a/lib/psci/psci_on.c
+++ b/lib/psci/psci_on.c
@@ -93,7 +93,7 @@
psci_svc_cpu_data.aff_info_state);
rc = cpu_on_validate_state(psci_get_aff_info_state_by_idx(target_idx));
if (rc != PSCI_E_SUCCESS)
- goto exit;
+ goto on_exit;
/*
* Call the cpu on handler registered by the Secure Payload Dispatcher
@@ -151,7 +151,7 @@
psci_svc_cpu_data.aff_info_state);
}
-exit:
+on_exit:
psci_spin_unlock_cpu(target_idx);
return rc;
}
diff --git a/lib/psci/psci_suspend.c b/lib/psci/psci_suspend.c
index 0fb1ed3..f690e49 100644
--- a/lib/psci/psci_suspend.c
+++ b/lib/psci/psci_suspend.c
@@ -152,7 +152,7 @@
* detection that a wake-up interrupt has fired.
*/
if (read_isr_el1() != 0U) {
- goto exit;
+ goto suspend_exit;
}
#if PSCI_OS_INIT_MODE
@@ -163,7 +163,7 @@
*/
rc = psci_validate_state_coordination(idx, end_pwrlvl, state_info);
if (rc != PSCI_E_SUCCESS) {
- goto exit;
+ goto suspend_exit;
}
} else {
#endif
@@ -181,7 +181,7 @@
if (psci_plat_pm_ops->pwr_domain_validate_suspend != NULL) {
rc = psci_plat_pm_ops->pwr_domain_validate_suspend(state_info);
if (rc != PSCI_E_SUCCESS) {
- goto exit;
+ goto suspend_exit;
}
}
#endif
@@ -327,7 +327,7 @@
*/
psci_set_pwr_domains_to_run(idx, end_pwrlvl);
-exit:
+suspend_exit:
psci_release_pwr_domain_locks(end_pwrlvl, parent_nodes);
return rc;
diff --git a/plat/amd/versal2/bl31_setup.c b/plat/amd/versal2/bl31_setup.c
index 3a856cb..77838a9 100644
--- a/plat/amd/versal2/bl31_setup.c
+++ b/plat/amd/versal2/bl31_setup.c
@@ -31,6 +31,8 @@
#include <pm_api_sys.h>
#include <pm_client.h>
+#include <plat_ocm_coherency.h>
+
static entry_point_info_t bl32_image_ep_info;
static entry_point_info_t bl33_image_ep_info;
@@ -120,9 +122,6 @@
cpu_clock = 112203;
break;
case QEMU:
- /* Random values now */
- cpu_clock = 3333333;
- break;
case SILICON:
cpu_clock = 100000000;
break;
@@ -143,6 +142,10 @@
setup_console();
+ if (IS_TFA_IN_OCM(BL31_BASE) && (check_ocm_coherency() < 0)) {
+ NOTICE("OCM coherency check not supported\n");
+ }
+
NOTICE("TF-A running on %s v%d.%d, RTL v%d.%d, PS v%d.%d, PMC v%d.%d\n",
board_name_decode(),
(platform_version >> 1), platform_version % 10U,
diff --git a/plat/amd/versal2/include/plat_ocm_coherency.h b/plat/amd/versal2/include/plat_ocm_coherency.h
new file mode 100644
index 0000000..b88c2eb
--- /dev/null
+++ b/plat/amd/versal2/include/plat_ocm_coherency.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2025, Advanced Micro Devices, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef PLAT_OCM_COHERENCY_H
+#define PLAT_OCM_COHERENCY_H
+
+#define COHERENCY_CHECK_NOT_SUPPORTED -1
+
+#if (DEBUG == 1)
+int32_t check_ocm_coherency(void);
+#else
+static inline int32_t check_ocm_coherency(void)
+{
+ return COHERENCY_CHECK_NOT_SUPPORTED;
+}
+#endif
+
+#endif/*PLAT_OCM_COHERENCY_H*/
diff --git a/plat/amd/versal2/plat_ocm_coherency.c b/plat/amd/versal2/plat_ocm_coherency.c
new file mode 100644
index 0000000..872ee23
--- /dev/null
+++ b/plat/amd/versal2/plat_ocm_coherency.c
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2025, Advanced Micro Devices, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <common/debug.h>
+#include <lib/mmio.h>
+
+#include <plat_ocm_coherency.h>
+#include <platform_def.h>
+
+/*
+ * Register non hash mem regions addresses
+ */
+#define POR_RNSAM_NODE_INFO_U_RNFBESAM_NID12 U(0xF8168000)
+#define NON_HASH_MEM_REGION_REG0 U(POR_RNSAM_NODE_INFO_U_RNFBESAM_NID12 + 0xC08)
+#define NON_HASH_MEM_REGION_REG1 U(POR_RNSAM_NODE_INFO_U_RNFBESAM_NID12 + 0xC0C)
+#define NON_HASH_MEM_REGION_REG2 U(POR_RNSAM_NODE_INFO_U_RNFBESAM_NID12 + 0xC10)
+#define NON_HASH_MEM_REGION_REG3 U(POR_RNSAM_NODE_INFO_U_RNFBESAM_NID12 + 0xC14)
+#define NON_HASH_MEM_REGION_REG4 U(POR_RNSAM_NODE_INFO_U_RNFBESAM_NID12 + 0xC18)
+#define NON_HASH_MEM_REGION_REG5 U(POR_RNSAM_NODE_INFO_U_RNFBESAM_NID12 + 0xC1C)
+#define NON_HASH_MEM_REGION_REG6 U(POR_RNSAM_NODE_INFO_U_RNFBESAM_NID12 + 0xC20)
+#define NON_HASH_MEM_REGION_REG7 U(POR_RNSAM_NODE_INFO_U_RNFBESAM_NID12 + 0xC24)
+
+#define REGION_BASE_ADDR_VALUE U(0x2E)
+#define REGION_BASE_ADDR_SHIFT 9
+
+#define REGION_BASE_ADDRESS_MASK GENMASK(30, REGION_BASE_ADDR_SHIFT)
+#define REGION_VALID_BIT BIT(0)
+
+/*
+ * verify the register configured as non-hashed
+ */
+#define IS_NON_HASHED_REGION(reg) \
+((FIELD_GET(REGION_BASE_ADDRESS_MASK, mmio_read_32(reg)) == REGION_BASE_ADDR_VALUE) && \
+ (mmio_read_32(reg) & REGION_VALID_BIT))
+
+/*
+ * Splitter registers
+ */
+#define FPX_SPLITTER_0 U(0xECC20000)
+#define FPX_SPLITTER_1 U(0xECD20000)
+#define FPX_SPLITTER_2 U(0xECE20000)
+#define FPX_SPLITTER_3 U(0xECF20000)
+#define OCM_ADDR_DIST_MODE BIT(16)
+
+#define OCM_COHERENT 0
+#define OCM_NOT_COHERENT 1
+#define TFA_NOT_IN_OCM 2
+
+/*
+ * Function that verifies the OCM is coherent or not with the following checks:
+ * verify that OCM is in non hashed region or not if not then verify
+ * OCM_ADDR_DIST_MODE bit in splitter registers is set.
+ */
+int32_t check_ocm_coherency(void)
+{
+ int32_t status = OCM_COHERENT;
+ /* isolation should be disabled in order to read these registers */
+ if ((IS_NON_HASHED_REGION(NON_HASH_MEM_REGION_REG0) ||
+ IS_NON_HASHED_REGION(NON_HASH_MEM_REGION_REG1) ||
+ IS_NON_HASHED_REGION(NON_HASH_MEM_REGION_REG2) ||
+ IS_NON_HASHED_REGION(NON_HASH_MEM_REGION_REG3) ||
+ IS_NON_HASHED_REGION(NON_HASH_MEM_REGION_REG4) ||
+ IS_NON_HASHED_REGION(NON_HASH_MEM_REGION_REG5) ||
+ IS_NON_HASHED_REGION(NON_HASH_MEM_REGION_REG6) ||
+ IS_NON_HASHED_REGION(NON_HASH_MEM_REGION_REG7))) {
+ WARN("OCM is not configured as coherent\n");
+ status = OCM_NOT_COHERENT;
+ } else {
+ /* verify OCM_ADDR_DIST_MODE bit in splitter registers is set */
+ if (!((mmio_read_32(FPX_SPLITTER_0) & OCM_ADDR_DIST_MODE) &&
+ (mmio_read_32(FPX_SPLITTER_1) & OCM_ADDR_DIST_MODE) &&
+ (mmio_read_32(FPX_SPLITTER_2) & OCM_ADDR_DIST_MODE) &&
+ (mmio_read_32(FPX_SPLITTER_3) & OCM_ADDR_DIST_MODE))) {
+ WARN("OCM is not configured as coherent\n");
+ status = OCM_NOT_COHERENT;
+ }
+ }
+ return status;
+}
+
diff --git a/plat/amd/versal2/platform.mk b/plat/amd/versal2/platform.mk
index 7cd864e..283ad42 100644
--- a/plat/amd/versal2/platform.mk
+++ b/plat/amd/versal2/platform.mk
@@ -160,6 +160,11 @@
${PLAT_PATH}/sip_svc_setup.c \
${PLAT_PATH}/gicv3.c
+
+ifeq ($(DEBUG),1)
+BL31_SOURCES += ${PLAT_PATH}/plat_ocm_coherency.c
+endif
+
ifeq (${ERRATA_ABI_SUPPORT}, 1)
# enable the cpu macros for errata abi interface
CORTEX_A78_AE_H_INC := 1
diff --git a/plat/arm/board/tc/include/platform_def.h b/plat/arm/board/tc/include/platform_def.h
index 71f7bb3..0216000 100644
--- a/plat/arm/board/tc/include/platform_def.h
+++ b/plat/arm/board/tc/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020-2024, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2025, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -34,6 +34,28 @@
#define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00080000 /* 512 KB */
+#if TRANSFER_LIST
+/*
+ * Summation of data size of all Transfer Entries included in the Transfer list.
+ * Note: Update this field whenever new Transfer Entries are added in future.
+ */
+#define PLAT_ARM_FW_HANDOFF_SIZE U(0x9000)
+#define PLAT_ARM_EL3_FW_HANDOFF_BASE ARM_BL_RAM_BASE
+#define PLAT_ARM_EL3_FW_HANDOFF_LIMIT PLAT_ARM_EL3_FW_HANDOFF_BASE + PLAT_ARM_FW_HANDOFF_SIZE
+#define FW_NS_HANDOFF_BASE (PLAT_ARM_NS_IMAGE_BASE - PLAT_ARM_FW_HANDOFF_SIZE)
+
+/* Mappings for Secure and Non-secure Transfer_list */
+#define TC_MAP_EL3_FW_HANDOFF MAP_REGION_FLAT( \
+ PLAT_ARM_EL3_FW_HANDOFF_BASE, \
+ PLAT_ARM_FW_HANDOFF_SIZE, \
+ MT_MEMORY | MT_RW | EL3_PAS)
+
+#define TC_MAP_FW_NS_HANDOFF MAP_REGION_FLAT( \
+ FW_NS_HANDOFF_BASE, \
+ PLAT_ARM_FW_HANDOFF_SIZE, \
+ MT_MEMORY | MT_RW | MT_NS)
+#endif /* TRANSFER_LIST */
+
/*
* The top 16MB of ARM_DRAM1 is configured as secure access only using the TZC,
* its base is ARM_AP_TZC_DRAM1_BASE.
diff --git a/plat/arm/board/tc/tc_bl2_setup.c b/plat/arm/board/tc/tc_bl2_setup.c
index 74ef569..b5d3a1a 100644
--- a/plat/arm/board/tc/tc_bl2_setup.c
+++ b/plat/arm/board/tc/tc_bl2_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021, ARM Limited. All rights reserved.
+ * Copyright (c) 2021-2025, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -18,17 +18,26 @@
******************************************************************************/
struct bl_params *plat_get_next_bl_params(void)
{
- struct bl_params *arm_bl_params = arm_get_next_bl_params();
-
- const struct dyn_cfg_dtb_info_t *fw_config_info;
+ struct bl_params *arm_bl_params;
bl_mem_params_node_t *param_node;
- uintptr_t fw_config_base = 0U;
- entry_point_info_t *ep_info;
+ const struct dyn_cfg_dtb_info_t *fw_config_info __maybe_unused;
+ uintptr_t fw_config_base __maybe_unused;
+ entry_point_info_t *ep_info __maybe_unused;
+
+ arm_bl_params = arm_get_next_bl_params();
/* Get BL31 image node */
param_node = get_bl_mem_params_node(BL31_IMAGE_ID);
assert(param_node != NULL);
+#if TRANSFER_LIST
+ assert(arm_bl_params != NULL);
+ arm_bl_params->head = ¶m_node->params_node_mem;
+ arm_bl_params->head->ep_info = ¶m_node->ep_info;
+ arm_bl_params->head->image_id = param_node->image_id;
+
+ arm_bl2_setup_next_ep_info(param_node);
+#else
/* Get fw_config load address */
fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, FW_CONFIG_ID);
assert(fw_config_info != NULL);
@@ -42,6 +51,7 @@
*/
ep_info = ¶m_node->ep_info;
ep_info->args.arg1 = (uint32_t)fw_config_base;
+#endif /* TRANSFER_LIST */
return arm_bl_params;
}
diff --git a/plat/arm/board/tc/tc_bl31_setup.c b/plat/arm/board/tc/tc_bl31_setup.c
index 66d921d..a358390 100644
--- a/plat/arm/board/tc/tc_bl31_setup.c
+++ b/plat/arm/board/tc/tc_bl31_setup.c
@@ -159,8 +159,10 @@
arm_bl31_early_platform_setup(arg0, arg1, arg2, arg3);
+#if !TRANSFER_LIST
/* Fill the properties struct with the info from the config dtb */
fconf_populate("FW_CONFIG", arg1);
+#endif
}
#ifdef PLATFORM_TESTS
@@ -205,6 +207,13 @@
{
arm_bl31_plat_arch_setup();
+ /*
+ * When TRANSFER_LIST is enabled, HW_CONFIG is included in Transfer List
+ * as an entry with the tag TL_TAG_FDT. In this case, the configuration
+ * is already available, so the fconf_populate mechanism is not needed.
+ * The code block below is only required when TRANSFER_LIST is not used.
+ */
+#if !TRANSFER_LIST
/* HW_CONFIG was also loaded by BL2 */
const struct dyn_cfg_dtb_info_t *hw_config_info;
@@ -212,6 +221,7 @@
assert(hw_config_info != NULL);
fconf_populate("HW_CONFIG", hw_config_info->config_addr);
+#endif
}
#if defined(SPD_spmd) && (SPMC_AT_EL3 == 0)
diff --git a/plat/arm/board/tc/tc_plat.c b/plat/arm/board/tc/tc_plat.c
index 1ecfdb9..fcee784 100644
--- a/plat/arm/board/tc/tc_plat.c
+++ b/plat/arm/board/tc/tc_plat.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -33,6 +33,9 @@
TC_MAP_NS_DRAM1,
TC_FLASH0_RO,
TC_MAP_DEVICE,
+#if TRANSFER_LIST
+ TC_MAP_EL3_FW_HANDOFF,
+#endif
{0}
};
#endif
@@ -59,6 +62,9 @@
ARM_MAP_OPTEE_CORE_MEM,
ARM_OPTEE_PAGEABLE_LOAD_MEM,
#endif
+#if TRANSFER_LIST
+ TC_MAP_EL3_FW_HANDOFF,
+#endif
{0}
};
#endif
@@ -72,6 +78,10 @@
#if SPM_MM
ARM_SPM_BUF_EL3_MMAP,
#endif
+#if TRANSFER_LIST
+ TC_MAP_FW_NS_HANDOFF,
+ TC_MAP_EL3_FW_HANDOFF,
+#endif
{0}
};
diff --git a/plat/intel/soc/common/include/socfpga_ros.h b/plat/intel/soc/common/include/socfpga_ros.h
index 10cabd3..62a9fe8 100644
--- a/plat/intel/soc/common/include/socfpga_ros.h
+++ b/plat/intel/soc/common/include/socfpga_ros.h
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2024, Intel Corporation. All rights reserved.
+ * Copyright (c) 2025, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -40,8 +41,8 @@
#define SPT_MIN_PARTITIONS (9U)
#define FACTORY_IMAGE "FACTORY_IMAGE"
-#define FACTORY_SSBL "FACTORY_IM.SSBL"
-#define SSBL_SUFFIX ".SSBL"
+#define FACTORY_SSBL "SSBL.FACTORY_IM"
+#define SSBL_PREFIX "SSBL."
typedef struct {
const uint32_t magic_number;
@@ -55,7 +56,7 @@
const uint32_t length;
const uint32_t flags;
} partition[SPT_MAX_PARTITIONS];
-} __packed spt_table_t;
+} __packed __aligned(4) spt_table_t;
uint32_t ros_qspi_get_ssbl_offset(unsigned long *offset);
diff --git a/plat/intel/soc/common/socfpga_ros.c b/plat/intel/soc/common/socfpga_ros.c
index ea37384..62e689c 100644
--- a/plat/intel/soc/common/socfpga_ros.c
+++ b/plat/intel/soc/common/socfpga_ros.c
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2024, Intel Corporation. All rights reserved.
+ * Copyright (c) 2025, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -20,6 +21,8 @@
#include <socfpga_ros.h>
+#define WORD_SIZE (sizeof(uint32_t))
+
static void swap_bits(char *const data, uint32_t len)
{
uint32_t x, y;
@@ -99,7 +102,8 @@
return ROS_IMAGE_PARTNUM_OVFL;
}
- memcpy_s(&spt_data, SPT_SIZE, spt_ptr, SPT_SIZE);
+ memcpy_s(&spt_data, (sizeof(spt_table_t) / WORD_SIZE),
+ spt_ptr, (SPT_SIZE / WORD_SIZE));
spt_data.checksum = 0U;
swap_bits((char *)&spt_data, SPT_SIZE);
@@ -153,6 +157,7 @@
}
uint32_t ret, img_index;
+ size_t len;
char ssbl_name[SPT_PARTITION_NAME_LENGTH];
static spt_table_t spt;
@@ -168,11 +173,12 @@
if (strncmp(spt.partition[img_index].name, FACTORY_IMAGE,
SPT_PARTITION_NAME_LENGTH) == 0U) {
- strlcpy(ssbl_name, FACTORY_SSBL, SPT_PARTITION_NAME_LENGTH);
+ strcpy_secure(ssbl_name, SPT_PARTITION_NAME_LENGTH, FACTORY_SSBL);
} else {
- strlcpy(ssbl_name, spt.partition[img_index].name,
- SPT_PARTITION_NAME_LENGTH);
- strlcat(ssbl_name, SSBL_SUFFIX, SPT_PARTITION_NAME_LENGTH);
+ strcpy_secure(ssbl_name, SPT_PARTITION_NAME_LENGTH, SSBL_PREFIX);
+ len = strnlen_secure(ssbl_name, SPT_PARTITION_NAME_LENGTH);
+ strcpy_secure(ssbl_name + len, SPT_PARTITION_NAME_LENGTH - len,
+ spt.partition[img_index].name);
}
for (uint32_t index = 0U; index < spt.partitions; index++) {
diff --git a/plat/xilinx/zynqmp/aarch64/zynqmp_common.c b/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
index 412238d..822919b 100644
--- a/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
+++ b/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
@@ -406,7 +406,7 @@
uint32_t ret = 0U;
if (ver == ZYNQMP_CSU_VERSION_QEMU) {
- ret = 65000000U;
+ ret = 62500000U;
} else {
ret = mmio_read_32((uint64_t)IOU_SCNTRS_BASEFREQ);
}
diff --git a/services/std_svc/drtm/drtm_main.c b/services/std_svc/drtm/drtm_main.c
index c302863..8f71571 100644
--- a/services/std_svc/drtm/drtm_main.c
+++ b/services/std_svc/drtm/drtm_main.c
@@ -293,8 +293,8 @@
/* Prepare DRTM event log for DLME. */
drtm_serialise_event_log(dlme_data_cursor, &serialised_bytes_actual);
assert(serialised_bytes_actual <= ARM_DRTM_MIN_EVENT_LOG_SIZE);
- dlme_data_hdr->dlme_tpm_log_size = ARM_DRTM_MIN_EVENT_LOG_SIZE;
- dlme_data_cursor += dlme_data_hdr->dlme_tpm_log_size;
+ dlme_data_hdr->dlme_tpm_log_size = serialised_bytes_actual;
+ dlme_data_cursor += serialised_bytes_actual;
/*
* TODO: Prepare the TCB hashes for DLME, currently its size
diff --git a/services/std_svc/spmd/spmd_main.c b/services/std_svc/spmd/spmd_main.c
index 94634f2..310610d 100644
--- a/services/std_svc/spmd/spmd_main.c
+++ b/services/std_svc/spmd/spmd_main.c
@@ -888,11 +888,15 @@
}
/*
- * If there was an SPMD logical partition direct request on-going,
+ * Perform a synchronous exit:
+ * 1. If there was an SPMD logical partition direct request on-going,
* return back to the SPMD logical partition so the error can be
* consumed.
+ * 2. SPMC sent FFA_ERROR in response to a power management
+ * operation sent through direct request.
*/
- if (is_spmd_logical_sp_dir_req_in_progress(ctx)) {
+ if (is_spmd_logical_sp_dir_req_in_progress(ctx) ||
+ ctx->psci_operation_ongoing) {
assert(secure_origin);
spmd_spm_core_sync_exit(0ULL);
}
diff --git a/services/std_svc/spmd/spmd_pm.c b/services/std_svc/spmd/spmd_pm.c
index fd89c81..4ed3e2f 100644
--- a/services/std_svc/spmd/spmd_pm.c
+++ b/services/std_svc/spmd/spmd_pm.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -117,6 +117,8 @@
spmd_spm_core_context_t *ctx = spmd_get_context();
unsigned int linear_id = plat_my_core_pos();
int64_t rc;
+ uint32_t ffa_resp_func_id, msg_flags;
+ int status;
assert(ctx != NULL);
assert(ctx->state != SPMC_STATE_OFF);
@@ -137,24 +139,60 @@
write_ctx_reg(gpregs, CTX_GPREG_X16, 0);
write_ctx_reg(gpregs, CTX_GPREG_X17, 0);
+ /* Mark current core as processing a PSCI operation. */
+ ctx->psci_operation_ongoing = true;
+
rc = spmd_spm_core_sync_entry(ctx);
+
if (rc != 0ULL) {
ERROR("%s failed (%" PRIu64 ") on CPU%u\n", __func__, rc, linear_id);
}
+ ctx->psci_operation_ongoing = false;
+
/* Expect a direct message response from the SPMC. */
- u_register_t ffa_resp_func = read_ctx_reg(get_gpregs_ctx(&ctx->cpu_ctx),
+ ffa_resp_func_id = (uint32_t)read_ctx_reg(get_gpregs_ctx(&ctx->cpu_ctx),
CTX_GPREG_X0);
- if (ffa_resp_func != FFA_MSG_SEND_DIRECT_RESP_SMC32) {
- ERROR("%s invalid SPMC response (%lx).\n",
- __func__, ffa_resp_func);
- return -EINVAL;
+
+ /*
+ * Retrieve flags indicating framework message and power management
+ * response.
+ */
+ msg_flags = (uint32_t)read_ctx_reg(get_gpregs_ctx(&ctx->cpu_ctx),
+ CTX_GPREG_X2);
+
+ /* Retrieve error code indicating status of power management operation. */
+ status = (int)read_ctx_reg(get_gpregs_ctx(&ctx->cpu_ctx),
+ CTX_GPREG_X3);
+
+ if (ffa_resp_func_id == FFA_ERROR) {
+ /*
+ * It is likely that SPMC does not support receiving PSCI
+ * operation through framework message. SPMD takes an
+ * implementation defined choice to not treat it as a fatal
+ * error. Consequently, SPMD ignores the error and continues
+ * with power management operation.
+ */
+ VERBOSE("SPMC ignored PSCI CPU_OFF framework message\n");
+ } else if (ffa_resp_func_id != FFA_MSG_SEND_DIRECT_RESP_SMC32) {
+ ERROR("%s invalid SPMC response (%x).\n",
+ __func__, ffa_resp_func_id);
+ panic();
+ } else if (((msg_flags & FFA_FWK_MSG_BIT) == 0U) ||
+ ((msg_flags & FFA_FWK_MSG_MASK) != FFA_PM_MSG_PM_RESP)) {
+ ERROR("SPMC failed to send framework message response for power"
+ " management operation, message flags = (%x)\n",
+ msg_flags);
+ panic();
+ } else if (status != PSCI_E_SUCCESS) {
+ ERROR("SPMC denied CPU_OFF power management request\n");
+ panic();
+ } else {
+ VERBOSE("CPU %u off!\n", linear_id);
}
ctx->state = SPMC_STATE_OFF;
- VERBOSE("CPU %u off!\n", linear_id);
-
return 0;
}
diff --git a/services/std_svc/spmd/spmd_private.h b/services/std_svc/spmd/spmd_private.h
index 2cd18a2..0dfad02 100644
--- a/services/std_svc/spmd/spmd_private.h
+++ b/services/std_svc/spmd/spmd_private.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2019-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -52,6 +52,7 @@
cpu_context_t cpu_ctx;
spmc_state_t state;
bool secure_interrupt_ongoing;
+ bool psci_operation_ongoing;
#if ENABLE_SPMD_LP
uint8_t spmd_lp_sync_req_ongoing;
#endif
diff --git a/services/std_svc/std_svc_setup.c b/services/std_svc/std_svc_setup.c
index 5cfe5f9..deca1c0 100644
--- a/services/std_svc/std_svc_setup.c
+++ b/services/std_svc/std_svc_setup.c
@@ -94,14 +94,19 @@
* calls to PSCI SMC handler
*/
static uintptr_t std_svc_smc_handler(uint32_t smc_fid,
- u_register_t x1,
- u_register_t x2,
- u_register_t x3,
- u_register_t x4,
+ u_register_t x1_arg,
+ u_register_t x2_arg,
+ u_register_t x3_arg,
+ u_register_t x4_arg,
void *cookie,
void *handle,
u_register_t flags)
{
+ u_register_t x1 = x1_arg;
+ u_register_t x2 = x2_arg;
+ u_register_t x3 = x3_arg;
+ u_register_t x4 = x4_arg;
+
if (((smc_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_32) {
/* 32-bit SMC function, clear top parameter bits */
diff --git a/tools/marvell/doimage/doimage.c b/tools/marvell/doimage/doimage.c
index 1f0985c..12e1327 100644
--- a/tools/marvell/doimage/doimage.c
+++ b/tools/marvell/doimage/doimage.c
@@ -421,7 +421,7 @@
char *ptmp = (char *)&tv;
unsigned char digest[32];
unsigned char IV[AES_BLOCK_SZ];
- int i, k;
+ size_t i, k;
mbedtls_aes_context aes_ctx;
int rval = -1;
uint8_t *test_img = 0;
@@ -516,7 +516,8 @@
for (i = 0; i < blen; i++) {
if (buf[i] != test_img[i]) {
fprintf(stderr, "Failed to compare the image after");
- fprintf(stderr, " decryption! Byte count is %d\n", i);
+ fprintf(stderr, " decryption! Byte count is %lu\n",
+ (unsigned long)i);
rval = -1;
goto encrypt_exit;
}
@@ -614,11 +615,11 @@
int verify_and_copy_file_name_entry(const char *element_name,
const char *element, char *copy_to)
{
- int element_length = strlen(element);
+ size_t element_length = strlen(element);
if (element_length >= MAX_FILENAME) {
- fprintf(stderr, "The file name %s for %s is too long (%d). ",
- element, element_name, element_length);
+ fprintf(stderr, "The file name %s for %s is too long (%lu). ",
+ element, element_name, (unsigned long)element_length);
fprintf(stderr, "Maximum allowed %d characters!\n",
MAX_FILENAME);
return -1;