diff --git a/plat/rockchip/rk3399/drivers/dram/dfs.c b/plat/rockchip/rk3399/drivers/dram/dfs.c
index 816372b..11b0373 100644
--- a/plat/rockchip/rk3399/drivers/dram/dfs.c
+++ b/plat/rockchip/rk3399/drivers/dram/dfs.c
@@ -1696,7 +1696,7 @@
 
 	pll_cnt = ARRAY_SIZE(dpll_rates_table);
 
-	/* Assumming rate_table is in descending order */
+	/* Assuming rate_table is in descending order */
 	for (i = 0; i < pll_cnt; i++) {
 		if (mhz >= dpll_rates_table[i].mhz)
 			break;
diff --git a/plat/rockchip/rk3399/drivers/dram/dram_spec_timing.h b/plat/rockchip/rk3399/drivers/dram/dram_spec_timing.h
index 9cda22c..102ba78 100644
--- a/plat/rockchip/rk3399/drivers/dram/dram_spec_timing.h
+++ b/plat/rockchip/rk3399/drivers/dram/dram_spec_timing.h
@@ -103,7 +103,7 @@
 	uint32_t tcksre;
 	uint32_t tcksrx;
 	uint32_t tdpd;
-	/* mode regiter timing */
+	/* mode register timing */
 	uint32_t tmod;
 	uint32_t tmrd;
 	uint32_t tmrr;
diff --git a/plat/rockchip/rk3399/drivers/dram/suspend.c b/plat/rockchip/rk3399/drivers/dram/suspend.c
index a8b1c32..caa784c 100644
--- a/plat/rockchip/rk3399/drivers/dram/suspend.c
+++ b/plat/rockchip/rk3399/drivers/dram/suspend.c
@@ -561,7 +561,7 @@
 
 	ch_count = sdram_params->num_channels;
 
-	/* LPDDR4 f2 cann't do training, all training will fail */
+	/* LPDDR4 f2 can't do training, all training will fail */
 	for (ch = 0; ch < ch_count; ch++) {
 		/*
 		 * Without this disabled for LPDDR4 we end up writing 0's
diff --git a/plat/rockchip/rk3399/drivers/m0/src/suspend.c b/plat/rockchip/rk3399/drivers/m0/src/suspend.c
index 9ad2fa2..8a0ea32 100644
--- a/plat/rockchip/rk3399/drivers/m0/src/suspend.c
+++ b/plat/rockchip/rk3399/drivers/m0/src/suspend.c
@@ -30,7 +30,7 @@
 	}
 
 	/*
-	 * FSM power secquence is .. -> ST_INPUT_CLAMP(step.17) -> .. ->
+	 * FSM power sequence is .. -> ST_INPUT_CLAMP(step.17) -> .. ->
 	 * ST_WAKEUP_RESET -> ST_EXT_PWRUP-> ST_RELEASE_CLAMP ->
 	 * ST_24M_OSC_EN -> .. -> ST_WAKEUP_RESET_CLR(step.26) -> ..,
 	 * INPUT_CLAMP and WAKEUP_RESET will hold the SOC not affect by
diff --git a/plat/rockchip/rk3399/drivers/secure/secure.h b/plat/rockchip/rk3399/drivers/secure/secure.h
index e31c999..79997b2 100644
--- a/plat/rockchip/rk3399/drivers/secure/secure.h
+++ b/plat/rockchip/rk3399/drivers/secure/secure.h
@@ -32,7 +32,7 @@
 /* security config pmu slave ip */
 /* All of slaves  is ns */
 #define SGRF_PMU_SLV_S_NS		BIT_WITH_WMSK(0)
-/* slaves secure attr is configed */
+/* slaves secure attr is configured */
 #define SGRF_PMU_SLV_S_CFGED		WMSK_BIT(0)
 #define SGRF_PMU_SLV_CRYPTO1_NS		WMSK_BIT(1)
 
diff --git a/plat/rockchip/rk3399/drivers/soc/soc.c b/plat/rockchip/rk3399/drivers/soc/soc.c
index 98b5ad6..e2b2934 100644
--- a/plat/rockchip/rk3399/drivers/soc/soc.c
+++ b/plat/rockchip/rk3399/drivers/soc/soc.c
@@ -343,7 +343,7 @@
 
 	/*
 	 * Maybe the HW needs some times to reset the system,
-	 * so we do not hope the core to excute valid codes.
+	 * so we do not hope the core to execute valid codes.
 	 */
 	while (1)
 		;