Migrate FVP port to use common code
Major update to the FVP platform port to use the common platform code
in (include/)plat/arm/* and (include/)plat/common/*. This mainly
consists of removing duplicated code but also introduces some small
behavioural changes where there was unnecessary variation between the
FVP and Juno ports. See earlier commit titled `Add common ARM and CSS
platform code` for details.
Also add support for Foundation FVP version 9.1 during FVP config
setup to prevent a warning being emitted in the console.
Change-Id: I254ca854987642ce09d1b924c9fd410a6e13e3bc
diff --git a/plat/fvp/include/plat_macros.S b/plat/fvp/include/plat_macros.S
index 6349c11..2feffbe 100644
--- a/plat/fvp/include/plat_macros.S
+++ b/plat/fvp/include/plat_macros.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -30,33 +30,26 @@
#ifndef __PLAT_MACROS_S__
#define __PLAT_MACROS_S__
-#include <cci.h>
-#include <gic_v2.h>
-#include <plat_config.h>
+#include <arm_macros.S>
+#include <v2m_def.h>
#include "../fvp_def.h"
-.section .rodata.gic_reg_name, "aS"
-gicc_regs:
- .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", ""
-gicd_pend_reg:
- .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n"
-newline:
- .asciz "\n"
-spacer:
- .asciz ":\t\t0x"
-
/* ---------------------------------------------
- * The below macro prints out relevant GIC
- * registers whenever an unhandled exception is
- * taken in BL3-1.
+ * The below required platform porting macro
+ * prints out relevant GIC registers whenever an
+ * unhandled exception is taken in BL3-1.
* Clobbers: x0 - x10, x16, x17, sp
* ---------------------------------------------
*/
.macro plat_print_gic_regs
- mov_imm x0, (VE_SYSREGS_BASE + V2M_SYS_ID)
+ /*
+ * Detect if we're using the base memory map or
+ * the legacy VE memory map
+ */
+ mov_imm x0, (V2M_SYSREGS_BASE + V2M_SYS_ID)
ldr w16, [x0]
/* Extract BLD (12th - 15th bits) from the SYS_ID */
- ubfx x16, x16, #SYS_ID_BLD_SHIFT, #4
+ ubfx x16, x16, #V2M_SYS_ID_BLD_SHIFT, #4
/* Check if VE mmap */
cmp w16, #BLD_GIC_VE_MMAP
b.eq use_ve_mmap
@@ -70,55 +63,7 @@
mov_imm x17, VE_GICC_BASE
mov_imm x16, VE_GICD_BASE
print_gicc_regs:
- /* gicc base address is now in x17 */
- adr x6, gicc_regs /* Load the gicc reg list to x6 */
- /* Load the gicc regs to gp regs used by str_in_crash_buf_print */
- ldr w8, [x17, #GICC_HPPIR]
- ldr w9, [x17, #GICC_AHPPIR]
- ldr w10, [x17, #GICC_CTLR]
- /* Store to the crash buf and print to console */
- bl str_in_crash_buf_print
-
- /* Print the GICD_ISPENDR regs */
- add x7, x16, #GICD_ISPENDR
- adr x4, gicd_pend_reg
- bl asm_print_str
-gicd_ispendr_loop:
- sub x4, x7, x16
- cmp x4, #0x280
- b.eq exit_print_gic_regs
- bl asm_print_hex
- adr x4, spacer
- bl asm_print_str
- ldr x4, [x7], #8
- bl asm_print_hex
- adr x4, newline
- bl asm_print_str
- b gicd_ispendr_loop
-exit_print_gic_regs:
- .endm
-
-.section .rodata.cci_reg_name, "aS"
-cci_iface_regs:
- .asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , ""
-
- /* ------------------------------------------------
- * The below macro prints out relevant interconnect
- * registers whenever an unhandled exception is
- * taken in BL3-1.
- * Clobbers: x0 - x9, sp
- * ------------------------------------------------
- */
- .macro plat_print_interconnect_regs
- adr x6, cci_iface_regs
- /* Store in x7 the base address of the first interface */
- mov_imm x7, (CCI400_BASE + SLAVE_IFACE3_OFFSET)
- ldr w8, [x7, #SNOOP_CTRL_REG]
- /* Store in x7 the base address of the second interface */
- mov_imm x7, (CCI400_BASE + SLAVE_IFACE4_OFFSET)
- ldr w9, [x7, #SNOOP_CTRL_REG]
- /* Store to the crash buf and print to console */
- bl str_in_crash_buf_print
+ arm_print_gic_regs
.endm
#endif /* __PLAT_MACROS_S__ */
diff --git a/plat/fvp/include/platform_def.h b/plat/fvp/include/platform_def.h
index 59b242d..c2a7d6a 100644
--- a/plat/fvp/include/platform_def.h
+++ b/plat/fvp/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -31,203 +31,83 @@
#ifndef __PLATFORM_DEF_H__
#define __PLATFORM_DEF_H__
-#include <arch.h>
+#include <arm_def.h>
+#include <board_arm_def.h>
+#include <common_def.h>
+#include <tzc400.h>
+#include <v2m_def.h>
#include "../fvp_def.h"
-/*******************************************************************************
- * Platform binary types for linking
- ******************************************************************************/
-#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
-#define PLATFORM_LINKER_ARCH aarch64
-
-/*******************************************************************************
- * Generic platform constants
- ******************************************************************************/
-
-/* Size of cacheable stacks */
-#if DEBUG_XLAT_TABLE
-#define PLATFORM_STACK_SIZE 0x800
-#elif IMAGE_BL1
-#if TRUSTED_BOARD_BOOT
-#define PLATFORM_STACK_SIZE 0x1000
-#else
-#define PLATFORM_STACK_SIZE 0x440
-#endif
-#elif IMAGE_BL2
-#if TRUSTED_BOARD_BOOT
-#define PLATFORM_STACK_SIZE 0x1000
-#else
-#define PLATFORM_STACK_SIZE 0x400
-#endif
-#elif IMAGE_BL31
-#define PLATFORM_STACK_SIZE 0x400
-#elif IMAGE_BL32
-#define PLATFORM_STACK_SIZE 0x440
-#endif
-
-#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n"
-
-/* Trusted Boot Firmware BL2 */
-#define BL2_IMAGE_NAME "bl2.bin"
-
-/* EL3 Runtime Firmware BL31 */
-#define BL31_IMAGE_NAME "bl31.bin"
+/*
+ * Most platform porting definitions provided by included headers
+ */
-/* Secure Payload BL32 (Trusted OS) */
-#define BL32_IMAGE_NAME "bl32.bin"
+/*
+ * Required ARM standard platform porting definitions
+ */
+#define PLAT_ARM_CLUSTER0_CORE_COUNT 4
+#define PLAT_ARM_CLUSTER1_CORE_COUNT 4
-/* Non-Trusted Firmware BL33 */
-#define BL33_IMAGE_NAME "bl33.bin" /* e.g. UEFI */
+#define PLAT_ARM_TRUSTED_ROM_BASE 0x00000000
+#define PLAT_ARM_TRUSTED_ROM_SIZE 0x04000000 /* 64 MB */
-#if TRUSTED_BOARD_BOOT
-/* Certificates */
-# define BL2_CERT_NAME "bl2.crt"
-# define TRUSTED_KEY_CERT_NAME "trusted_key.crt"
+#define PLAT_ARM_TRUSTED_DRAM_BASE 0x06000000
+#define PLAT_ARM_TRUSTED_DRAM_SIZE 0x02000000 /* 32 MB */
-# define BL30_KEY_CERT_NAME "bl30_key.crt"
-# define BL31_KEY_CERT_NAME "bl31_key.crt"
-# define BL32_KEY_CERT_NAME "bl32_key.crt"
-# define BL33_KEY_CERT_NAME "bl33_key.crt"
+/* No SCP in FVP */
+#define PLAT_ARM_SCP_TZC_DRAM1_SIZE MAKE_ULL(0x0)
-# define BL30_CERT_NAME "bl30.crt"
-# define BL31_CERT_NAME "bl31.crt"
-# define BL32_CERT_NAME "bl32.crt"
-# define BL33_CERT_NAME "bl33.crt"
-#endif /* TRUSTED_BOARD_BOOT */
+#define PLAT_ARM_DRAM2_SIZE MAKE_ULL(0x780000000)
-#define PLATFORM_CLUSTER_COUNT 2ull
-#define PLATFORM_CLUSTER0_CORE_COUNT 4
-#define PLATFORM_CLUSTER1_CORE_COUNT 4
-#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \
- PLATFORM_CLUSTER0_CORE_COUNT)
-#define PLATFORM_MAX_CPUS_PER_CLUSTER 4
-#define PLATFORM_NUM_AFFS (PLATFORM_CLUSTER_COUNT + \
- PLATFORM_CORE_COUNT)
-#define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL1
-#define MAX_IO_DEVICES 3
-#define MAX_IO_HANDLES 4
+#define PLAT_ARM_SHARED_RAM_CACHED 1
-/*******************************************************************************
- * BL1 specific defines.
- * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of
- * addresses.
- ******************************************************************************/
-#define BL1_RO_BASE FVP_TRUSTED_ROM_BASE
-#define BL1_RO_LIMIT (FVP_TRUSTED_ROM_BASE \
- + FVP_TRUSTED_ROM_SIZE)
/*
- * Put BL1 RW at the top of the Trusted SRAM. BL1_RW_BASE is calculated using
- * the current BL1 RW debug size plus a little space for growth.
+ * Load address of BL3-3 for this platform port
*/
-#if TRUSTED_BOARD_BOOT
-#define BL1_RW_BASE (FVP_TRUSTED_SRAM_BASE \
- + FVP_TRUSTED_SRAM_SIZE - 0x8000)
-#else
-#define BL1_RW_BASE (FVP_TRUSTED_SRAM_BASE \
- + FVP_TRUSTED_SRAM_SIZE - 0x6000)
-#endif
-#define BL1_RW_LIMIT (FVP_TRUSTED_SRAM_BASE \
- + FVP_TRUSTED_SRAM_SIZE)
+#define PLAT_ARM_NS_IMAGE_OFFSET (ARM_DRAM1_BASE + 0x8000000)
-/*******************************************************************************
- * BL2 specific defines.
- ******************************************************************************/
-/*
- * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug
- * size plus a little space for growth.
- */
-#if TRUSTED_BOARD_BOOT
-#define BL2_BASE (BL31_BASE - 0x1C000)
-#else
-#define BL2_BASE (BL31_BASE - 0xC000)
-#endif
-#define BL2_LIMIT BL31_BASE
-/*******************************************************************************
- * BL31 specific defines.
- ******************************************************************************/
/*
- * Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the
- * current BL3-1 debug size plus a little space for growth.
+ * PL011 related constants
*/
-#define BL31_BASE (FVP_TRUSTED_SRAM_BASE \
- + FVP_TRUSTED_SRAM_SIZE - 0x1D000)
-#define BL31_PROGBITS_LIMIT BL1_RW_BASE
-#define BL31_LIMIT (FVP_TRUSTED_SRAM_BASE \
- + FVP_TRUSTED_SRAM_SIZE)
+#define PLAT_ARM_BOOT_UART_BASE V2M_IOFPGA_UART0_BASE
+#define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ
-/*******************************************************************************
- * BL32 specific defines.
- ******************************************************************************/
-/*
- * On FVP, the TSP can execute from Trusted SRAM, Trusted DRAM or the DRAM
- * region secured by the TrustZone controller.
- */
-#if FVP_TSP_RAM_LOCATION_ID == FVP_TRUSTED_SRAM_ID
-# define TSP_SEC_MEM_BASE FVP_TRUSTED_SRAM_BASE
-# define TSP_SEC_MEM_SIZE FVP_TRUSTED_SRAM_SIZE
-# define TSP_PROGBITS_LIMIT BL2_BASE
-# define BL32_BASE FVP_TRUSTED_SRAM_BASE
-# define BL32_LIMIT BL31_BASE
-#elif FVP_TSP_RAM_LOCATION_ID == FVP_TRUSTED_DRAM_ID
-# define TSP_SEC_MEM_BASE FVP_TRUSTED_DRAM_BASE
-# define TSP_SEC_MEM_SIZE FVP_TRUSTED_DRAM_SIZE
-# define BL32_BASE FVP_TRUSTED_DRAM_BASE
-# define BL32_LIMIT (FVP_TRUSTED_DRAM_BASE + (1 << 21))
-#elif FVP_TSP_RAM_LOCATION_ID == FVP_DRAM_ID
-# define TSP_SEC_MEM_BASE DRAM1_SEC_BASE
-# define TSP_SEC_MEM_SIZE DRAM1_SEC_SIZE
-# define BL32_BASE DRAM1_SEC_BASE
-# define BL32_LIMIT (DRAM1_SEC_BASE + DRAM1_SEC_SIZE)
-#else
-# error "Unsupported FVP_TSP_RAM_LOCATION_ID value"
-#endif
+#define PLAT_ARM_CRASH_UART_BASE V2M_IOFPGA_UART1_BASE
+#define PLAT_ARM_CRASH_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ
-/*
- * ID of the secure physical generic timer interrupt used by the TSP.
- */
-#define TSP_IRQ_SEC_PHY_TIMER IRQ_SEC_PHY_TIMER
+#define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART2_BASE
+#define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART2_CLK_IN_HZ
-/*******************************************************************************
- * Platform specific page table and MMU setup constants
- ******************************************************************************/
-#define ADDR_SPACE_SIZE (1ull << 32)
+/* CCI related constants */
+#define PLAT_ARM_CCI_BASE 0x2c090000
+#define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 3
+#define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 4
-#if IMAGE_BL1
-# define MAX_XLAT_TABLES 2
-#elif IMAGE_BL2
-# define MAX_XLAT_TABLES 3
-#elif IMAGE_BL31
-# define MAX_XLAT_TABLES 2
-#elif IMAGE_BL32
-# if FVP_TSP_RAM_LOCATION_ID == FVP_DRAM_ID
-# define MAX_XLAT_TABLES 3
-# else
-# define MAX_XLAT_TABLES 2
-# endif
-#endif
-
-#define MAX_MMAP_REGIONS (FVP_MMAP_ENTRIES + FVP_BL_REGIONS)
+/* TrustZone controller related constants
+ *
+ * Currently only filters 0 and 2 are connected on Base FVP.
+ * Filter 0 : CPU clusters (no access to DRAM by default)
+ * Filter 1 : not connected
+ * Filter 2 : LCDs (access to VRAM allowed by default)
+ * Filter 3 : not connected
+ * Programming unconnected filters will have no effect at the
+ * moment. These filter could, however, be connected in future.
+ * So care should be taken not to configure the unused filters.
+ *
+ * Allow only non-secure access to all DRAM to supported devices.
+ * Give access to the CPUs and Virtio. Some devices
+ * would normally use the default ID so allow that too.
+ */
+#define PLAT_ARM_TZC_FILTERS REG_ATTR_FILTER_BIT(0)
-/*******************************************************************************
- * Declarations and constants to access the mailboxes safely. Each mailbox is
- * aligned on the biggest cache line size in the platform. This is known only
- * to the platform as it might have a combination of integrated and external
- * caches. Such alignment ensures that two maiboxes do not sit on the same cache
- * line at any cache level. They could belong to different cpus/clusters &
- * get written while being protected by different locks causing corruption of
- * a valid mailbox address.
- ******************************************************************************/
-#define CACHE_WRITEBACK_SHIFT 6
-#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
+#define PLAT_ARM_TZC_NS_DEV_ACCESS ( \
+ TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) | \
+ TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI) | \
+ TZC_REGION_ACCESS_RDWR(FVP_NSAID_AP) | \
+ TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO) | \
+ TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO_OLD))
-#if !USE_COHERENT_MEM
-/*******************************************************************************
- * Size of the per-cpu data in bytes that should be reserved in the generic
- * per-cpu data structure for the FVP port.
- ******************************************************************************/
-#define PLAT_PCPU_DATA_SIZE 2
-#endif
#endif /* __PLATFORM_DEF_H__ */
diff --git a/plat/fvp/include/platform_oid.h b/plat/fvp/include/platform_oid.h
index 38aca12..1e44cf7 100644
--- a/plat/fvp/include/platform_oid.h
+++ b/plat/fvp/include/platform_oid.h
@@ -27,43 +27,9 @@
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
-
-#ifndef PLATFORM_OID_H_
-#define PLATFORM_OID_H_
+#include "../../../../../include/plat/arm/board/common/board_arm_oid.h"
/*
- * This is the list of the different extensions containing relevant information
- * to establish the chain of trust.
- *
- * The OIDs shown here are just an example. Real OIDs should be obtained from
- * the ITU-T.
+ * Required platform OIDs
+ * (Provided by included header)
*/
-
-/* Non-volatile counter extensions */
-#define TZ_FW_NVCOUNTER_OID "1.2.3.1"
-#define NTZ_FW_NVCOUNTER_OID "1.2.3.2"
-
-/* BL2 extensions */
-#define BL2_HASH_OID "1.2.3.3"
-
-/* Trusted Key extensions */
-#define TZ_WORLD_PK_OID "1.2.3.4"
-#define NTZ_WORLD_PK_OID "1.2.3.5"
-
-/* BL3-1 extensions */
-#define BL31_CONTENT_CERT_PK_OID "1.2.3.6"
-#define BL31_HASH_OID "1.2.3.7"
-
-/* BL3-0 extensions */
-#define BL30_CONTENT_CERT_PK_OID "1.2.3.8"
-#define BL30_HASH_OID "1.2.3.9"
-
-/* BL3-2 extensions */
-#define BL32_CONTENT_CERT_PK_OID "1.2.3.10"
-#define BL32_HASH_OID "1.2.3.11"
-
-/* BL3-3 extensions */
-#define BL33_CONTENT_CERT_PK_OID "1.2.3.12"
-#define BL33_HASH_OID "1.2.3.13"
-
-#endif /* PLATFORM_OID_H_ */