diff --git a/plat/arm/board/common/rotpk/arm_dev_rotpk.S b/plat/arm/board/common/rotpk/arm_dev_rotpk.S
index 38f91fe..06e2a06 100644
--- a/plat/arm/board/common/rotpk/arm_dev_rotpk.S
+++ b/plat/arm/board/common/rotpk/arm_dev_rotpk.S
@@ -1,10 +1,10 @@
 /*
- * Copyright (c) 2021, ARM Limited. All rights reserved.
+ * Copyright (c) 2021-2022, ARM Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-/* diphda platform provides custom values for the macros defined in
+/* corstone1000 platform provides custom values for the macros defined in
  * arm_def.h , so only platform_def.h needs to be included
  */
 #if !defined(TARGET_PLATFORM_FVP) && !defined(TARGET_PLATFORM_FPGA)
diff --git a/plat/arm/board/diphda/common/diphda_bl2_mem_params_desc.c b/plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c
similarity index 89%
rename from plat/arm/board/diphda/common/diphda_bl2_mem_params_desc.c
rename to plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c
index 916c868..c3c60e5 100644
--- a/plat/arm/board/diphda/common/diphda_bl2_mem_params_desc.c
+++ b/plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -44,7 +44,7 @@
 		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
 			VERSION_2, entry_point_info_t, SECURE | EXECUTABLE),
 		.ep_info.pc = BL32_BASE,
-			.ep_info.args.arg0 = DIPHDA_TOS_FW_CONFIG_BASE,
+			.ep_info.args.arg0 = CORSTONE1000_TOS_FW_CONFIG_BASE,
 		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
 			VERSION_2, image_info_t, 0),
 		.image_info.image_base = BL32_BASE,
@@ -56,9 +56,9 @@
 	/* Fill TOS_FW_CONFIG related information */
 	{
 		.image_id = TOS_FW_CONFIG_ID,
-		.image_info.image_base = DIPHDA_TOS_FW_CONFIG_BASE,
-		.image_info.image_max_size = DIPHDA_TOS_FW_CONFIG_LIMIT - \
-			DIPHDA_TOS_FW_CONFIG_BASE,
+		.image_info.image_base = CORSTONE1000_TOS_FW_CONFIG_BASE,
+		.image_info.image_max_size = CORSTONE1000_TOS_FW_CONFIG_LIMIT - \
+			CORSTONE1000_TOS_FW_CONFIG_BASE,
 		SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
 			VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
 		SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
diff --git a/plat/arm/board/diphda/common/diphda_err.c b/plat/arm/board/corstone1000/common/corstone1000_err.c
similarity index 60%
rename from plat/arm/board/diphda/common/diphda_err.c
rename to plat/arm/board/corstone1000/common/corstone1000_err.c
index 89a3b82..376799f 100644
--- a/plat/arm/board/diphda/common/diphda_err.c
+++ b/plat/arm/board/corstone1000/common/corstone1000_err.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -7,7 +7,7 @@
 #include <plat/arm/common/plat_arm.h>
 
 /*
- * diphda error handler
+ * corstone1000 error handler
  */
 void __dead2 plat_arm_error_handler(int err)
 {
diff --git a/plat/arm/board/diphda/common/diphda_helpers.S b/plat/arm/board/corstone1000/common/corstone1000_helpers.S
similarity index 90%
rename from plat/arm/board/diphda/common/diphda_helpers.S
rename to plat/arm/board/corstone1000/common/corstone1000_helpers.S
index c9d2a88..cbe27c3 100644
--- a/plat/arm/board/diphda/common/diphda_helpers.S
+++ b/plat/arm/board/corstone1000/common/corstone1000_helpers.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -29,7 +29,7 @@
 	 * unsigned long plat_get_my_entrypoint (void);
 	 *
 	 * Main job of this routine is to distinguish between a cold and warm
-	 * boot. On diphda, this information can be queried from the power
+	 * boot. On corstone1000, this information can be queried from the power
 	 * controller. The Power Control SYS Status Register (PSYSR) indicates
 	 * the wake-up reason for the CPU.
 	 *
@@ -61,7 +61,7 @@
 	mrs	x0, mpidr_el1
 	mov_imm	x1, MPIDR_AFFINITY_MASK
 	and	x0, x0, x1
-	cmp	x0, #DIPHDA_PRIMARY_CPU
+	cmp	x0, #CORSTONE1000_PRIMARY_CPU
 	cset	w0, eq
 	ret
 endfunc plat_is_my_cpu_primary
diff --git a/plat/arm/board/diphda/common/diphda_plat.c b/plat/arm/board/corstone1000/common/corstone1000_plat.c
similarity index 86%
rename from plat/arm/board/diphda/common/diphda_plat.c
rename to plat/arm/board/corstone1000/common/corstone1000_plat.c
index 28d15a5..ffe60b1 100644
--- a/plat/arm/board/diphda/common/diphda_plat.c
+++ b/plat/arm/board/corstone1000/common/corstone1000_plat.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -21,12 +21,12 @@
 	ARM_MAP_SHARED_RAM,
 	ARM_MAP_NS_SHARED_RAM,
 	ARM_MAP_NS_DRAM1,
-	DIPHDA_MAP_DEVICE,
-	DIPHDA_EXTERNAL_FLASH,
+	CORSTONE1000_MAP_DEVICE,
+	CORSTONE1000_EXTERNAL_FLASH,
 	{0}
 };
 
-/* diphda only has one always-on power domain and there
+/* corstone1000 only has one always-on power domain and there
  * is no power control present
  */
 void __init plat_arm_pwrc_setup(void)
diff --git a/plat/arm/board/diphda/common/diphda_pm.c b/plat/arm/board/corstone1000/common/corstone1000_pm.c
similarity index 100%
rename from plat/arm/board/diphda/common/diphda_pm.c
rename to plat/arm/board/corstone1000/common/corstone1000_pm.c
diff --git a/plat/arm/board/diphda/common/diphda_security.c b/plat/arm/board/corstone1000/common/corstone1000_security.c
similarity index 78%
rename from plat/arm/board/diphda/common/diphda_security.c
rename to plat/arm/board/corstone1000/common/corstone1000_security.c
index bf172af..c88201b 100644
--- a/plat/arm/board/diphda/common/diphda_security.c
+++ b/plat/arm/board/corstone1000/common/corstone1000_security.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/plat/arm/board/diphda/common/diphda_stack_protector.c b/plat/arm/board/corstone1000/common/corstone1000_stack_protector.c
similarity index 90%
rename from plat/arm/board/diphda/common/diphda_stack_protector.c
rename to plat/arm/board/corstone1000/common/corstone1000_stack_protector.c
index 6228b63..393235e 100644
--- a/plat/arm/board/diphda/common/diphda_stack_protector.c
+++ b/plat/arm/board/corstone1000/common/corstone1000_stack_protector.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/plat/arm/board/diphda/common/diphda_topology.c b/plat/arm/board/corstone1000/common/corstone1000_topology.c
similarity index 72%
rename from plat/arm/board/diphda/common/diphda_topology.c
rename to plat/arm/board/corstone1000/common/corstone1000_topology.c
index 9dfd05d..5351896 100644
--- a/plat/arm/board/diphda/common/diphda_topology.c
+++ b/plat/arm/board/corstone1000/common/corstone1000_topology.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -7,8 +7,8 @@
 #include <plat/arm/common/plat_arm.h>
 #include <plat/common/platform.h>
 
-/* The diphda power domain tree descriptor */
-static unsigned char diphda_power_domain_tree_desc[PLAT_ARM_CLUSTER_COUNT
+/* The corstone1000 power domain tree descriptor */
+static unsigned char corstone1000_power_domain_tree_desc[PLAT_ARM_CLUSTER_COUNT
 							+ 2];
 /*******************************************************************************
  * This function dynamically constructs the topology according to
@@ -22,13 +22,13 @@
 	 * The highest level is the system level. The next level is constituted
 	 * by clusters and then cores in clusters.
 	 */
-	diphda_power_domain_tree_desc[0] = 1;
-	diphda_power_domain_tree_desc[1] = PLAT_ARM_CLUSTER_COUNT;
+	corstone1000_power_domain_tree_desc[0] = 1;
+	corstone1000_power_domain_tree_desc[1] = PLAT_ARM_CLUSTER_COUNT;
 
 	for (i = 0; i < PLAT_ARM_CLUSTER_COUNT; i++)
-		diphda_power_domain_tree_desc[i + 2] = PLATFORM_CORE_COUNT;
+		corstone1000_power_domain_tree_desc[i + 2] = PLATFORM_CORE_COUNT;
 
-	return diphda_power_domain_tree_desc;
+	return corstone1000_power_domain_tree_desc;
 }
 
 /******************************************************************************
diff --git a/plat/arm/board/diphda/common/diphda_trusted_boot.c b/plat/arm/board/corstone1000/common/corstone1000_trusted_boot.c
similarity index 91%
rename from plat/arm/board/diphda/common/diphda_trusted_boot.c
rename to plat/arm/board/corstone1000/common/corstone1000_trusted_boot.c
index ddb41fa..cec7332 100644
--- a/plat/arm/board/diphda/common/diphda_trusted_boot.c
+++ b/plat/arm/board/corstone1000/common/corstone1000_trusted_boot.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -38,7 +38,7 @@
  */
 int plat_get_nv_ctr(void *cookie, unsigned int *nv_ctr)
 {
-    *nv_ctr = DIPHDA_FW_NVCTR_VAL;
+    *nv_ctr = CORSTONE1000_FW_NVCTR_VAL;
     return 0;
 }
 
diff --git a/plat/arm/board/diphda/common/fdts/diphda_spmc_manifest.dts b/plat/arm/board/corstone1000/common/fdts/corstone1000_spmc_manifest.dts
similarity index 87%
rename from plat/arm/board/diphda/common/fdts/diphda_spmc_manifest.dts
rename to plat/arm/board/corstone1000/common/fdts/corstone1000_spmc_manifest.dts
index 536bdc3..8e49ab8 100644
--- a/plat/arm/board/diphda/common/fdts/diphda_spmc_manifest.dts
+++ b/plat/arm/board/corstone1000/common/fdts/corstone1000_spmc_manifest.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2022, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/plat/arm/board/diphda/common/include/platform_def.h b/plat/arm/board/corstone1000/common/include/platform_def.h
similarity index 88%
rename from plat/arm/board/diphda/common/include/platform_def.h
rename to plat/arm/board/corstone1000/common/include/platform_def.h
index 37fd71b..f14e5e6 100644
--- a/plat/arm/board/diphda/common/include/platform_def.h
+++ b/plat/arm/board/corstone1000/common/include/platform_def.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -34,17 +34,17 @@
 #define V2M_IOFPGA_UART0_CLK_IN_HZ		50000000
 #define V2M_IOFPGA_UART1_CLK_IN_HZ		50000000
 
-/* Core/Cluster/Thread counts for diphda */
-#define DIPHDA_CLUSTER_COUNT			U(1)
-#define DIPHDA_MAX_CPUS_PER_CLUSTER		U(4)
-#define DIPHDA_MAX_PE_PER_CPU			U(1)
-#define DIPHDA_PRIMARY_CPU			U(0)
+/* Core/Cluster/Thread counts for corstone1000 */
+#define CORSTONE1000_CLUSTER_COUNT			U(1)
+#define CORSTONE1000_MAX_CPUS_PER_CLUSTER		U(4)
+#define CORSTONE1000_MAX_PE_PER_CPU			U(1)
+#define CORSTONE1000_PRIMARY_CPU			U(0)
 
-#define PLAT_ARM_CLUSTER_COUNT		DIPHDA_CLUSTER_COUNT
+#define PLAT_ARM_CLUSTER_COUNT		CORSTONE1000_CLUSTER_COUNT
 
 #define PLATFORM_CORE_COUNT			(PLAT_ARM_CLUSTER_COUNT *      \
-						DIPHDA_MAX_CPUS_PER_CLUSTER *  \
-						DIPHDA_MAX_PE_PER_CPU)
+						CORSTONE1000_MAX_CPUS_PER_CLUSTER *  \
+						CORSTONE1000_MAX_PE_PER_CPU)
 
 /* UART related constants */
 #define PLAT_ARM_BOOT_UART_BASE		0x1a510000
@@ -85,7 +85,7 @@
  *
  *             BL32 (optee-os)
  *
- * <DIPHDA_TOS_FW_CONFIG_BASE> = 0x20ae000
+ * <CORSTONE1000_TOS_FW_CONFIG_BASE> = 0x20ae000
  *
  *         partition size: 8 KB
  *
@@ -132,7 +132,7 @@
 #define ARM_DRAM1_END				(ARM_DRAM1_BASE +	\
 						ARM_DRAM1_SIZE - 1)
 
-/* DRAM1 and DRAM2 are the same for diphda */
+/* DRAM1 and DRAM2 are the same for corstone1000 */
 #define ARM_DRAM2_BASE			ARM_DRAM1_BASE
 #define ARM_DRAM2_SIZE			ARM_DRAM1_SIZE
 #define ARM_DRAM2_END				ARM_DRAM1_END
@@ -173,13 +173,13 @@
 						PLAT_ARM_MAX_BL31_SIZE)
 #define BL31_LIMIT				BL2_SIGNATURE_BASE
 
-#define DIPHDA_TOS_FW_CONFIG_BASE		(BL31_BASE - \
-						DIPHDA_TOS_FW_CONFIG_SIZE)
-#define DIPHDA_TOS_FW_CONFIG_SIZE		UL(0x00002000)  /* 8 KB */
-#define DIPHDA_TOS_FW_CONFIG_LIMIT		BL31_BASE
+#define CORSTONE1000_TOS_FW_CONFIG_BASE		(BL31_BASE - \
+						CORSTONE1000_TOS_FW_CONFIG_SIZE)
+#define CORSTONE1000_TOS_FW_CONFIG_SIZE		UL(0x00002000)  /* 8 KB */
+#define CORSTONE1000_TOS_FW_CONFIG_LIMIT		BL31_BASE
 
 #define BL32_BASE				ARM_BL_RAM_BASE
-#define PLAT_ARM_MAX_BL32_SIZE		(DIPHDA_TOS_FW_CONFIG_BASE - \
+#define PLAT_ARM_MAX_BL32_SIZE		(CORSTONE1000_TOS_FW_CONFIG_BASE - \
 						BL32_BASE)     /* 688 KB */
 #define BL32_LIMIT				(BL32_BASE + \
 						PLAT_ARM_MAX_BL32_SIZE)
@@ -220,7 +220,7 @@
 /*
  * Define FW_CONFIG area base and limit. Leave enough space for BL2 meminfo.
  * FW_CONFIG is intended to host the device tree. Currently, This area is not
- * used because diphda platform doesn't use a device tree at TF-A level.
+ * used because corstone1000 platform doesn't use a device tree at TF-A level.
  */
 #define ARM_FW_CONFIG_BASE			(ARM_SHARED_RAM_BASE \
 						+ sizeof(meminfo_t))
@@ -261,8 +261,8 @@
 
 #define SYS_COUNTER_FREQ_IN_TICKS	UL(50000000) /* 50MHz */
 
-#define DIPHDA_IRQ_TZ_WDOG			32
-#define DIPHDA_IRQ_SEC_SYS_TIMER		34
+#define CORSTONE1000_IRQ_TZ_WDOG			32
+#define CORSTONE1000_IRQ_SEC_SYS_TIMER		34
 
 #define PLAT_MAX_PWR_LVL			2
 /*
@@ -308,7 +308,7 @@
 
 #define PLATFORM_STACK_SIZE			UL(0x440)
 
-#define DIPHDA_EXTERNAL_FLASH			MAP_REGION_FLAT(	\
+#define CORSTONE1000_EXTERNAL_FLASH			MAP_REGION_FLAT(	\
 						PLAT_ARM_NVM_BASE,	\
 						PLAT_ARM_NVM_SIZE,	\
 						MT_DEVICE | MT_RO | MT_SECURE)
@@ -356,11 +356,11 @@
 						ARM_FW_CONFIG_BASE),   \
 						MT_MEMORY | MT_RW | MT_SECURE)
 
-#define DIPHDA_DEVICE_BASE			(0x1A000000)
-#define DIPHDA_DEVICE_SIZE			(0x26000000)
-#define DIPHDA_MAP_DEVICE			MAP_REGION_FLAT(	\
-						DIPHDA_DEVICE_BASE,	\
-						DIPHDA_DEVICE_SIZE,	\
+#define CORSTONE1000_DEVICE_BASE			(0x1A000000)
+#define CORSTONE1000_DEVICE_SIZE			(0x26000000)
+#define CORSTONE1000_MAP_DEVICE			MAP_REGION_FLAT(	\
+						CORSTONE1000_DEVICE_BASE,	\
+						CORSTONE1000_DEVICE_SIZE,	\
 						MT_DEVICE | MT_RW | MT_SECURE)
 
 #define ARM_IRQ_SEC_PHY_TIMER			29
@@ -406,9 +406,9 @@
  */
 #define PLAT_ARM_G1S_IRQ_PROPS(grp)	\
 	ARM_G1S_IRQ_PROPS(grp), \
-	INTR_PROP_DESC(DIPHDA_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, \
+	INTR_PROP_DESC(CORSTONE1000_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, \
 		(grp), GIC_INTR_CFG_LEVEL), \
-	INTR_PROP_DESC(DIPHDA_IRQ_SEC_SYS_TIMER, \
+	INTR_PROP_DESC(CORSTONE1000_IRQ_SEC_SYS_TIMER, \
 		GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_LEVEL)
 
 #define PLAT_ARM_G0_IRQ_PROPS(grp)	ARM_G0_IRQ_PROPS(grp)
diff --git a/plat/arm/board/diphda/include/plat_macros.S b/plat/arm/board/corstone1000/include/plat_macros.S
similarity index 84%
rename from plat/arm/board/diphda/include/plat_macros.S
rename to plat/arm/board/corstone1000/include/plat_macros.S
index 4de8f95..9334201 100644
--- a/plat/arm/board/diphda/include/plat_macros.S
+++ b/plat/arm/board/corstone1000/include/plat_macros.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/plat/arm/board/corstone1000/platform.mk b/plat/arm/board/corstone1000/platform.mk
new file mode 100644
index 0000000..d891691
--- /dev/null
+++ b/plat/arm/board/corstone1000/platform.mk
@@ -0,0 +1,83 @@
+#
+# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# Making sure the corstone1000 platform type is specified
+ifeq ($(filter ${TARGET_PLATFORM}, fpga fvp),)
+	$(error TARGET_PLATFORM must be fpga or fvp)
+endif
+
+CORSTONE1000_CPU_LIBS	+=lib/cpus/aarch64/cortex_a35.S
+
+PLAT_INCLUDES		:=	-Iplat/arm/board/corstone1000/common/include	\
+				-Iplat/arm/board/corstone1000/include		\
+				-Iinclude/plat/arm/common			\
+				-Iinclude/plat/arm/css/common/aarch64
+
+
+CORSTONE1000_FW_NVCTR_VAL	:=	255
+TFW_NVCTR_VAL		:=	${CORSTONE1000_FW_NVCTR_VAL}
+NTFW_NVCTR_VAL		:=	${CORSTONE1000_FW_NVCTR_VAL}
+
+override NEED_BL1	:=	no
+
+override NEED_BL2	:=	yes
+FIP_BL2_ARGS := tb-fw
+
+override NEED_BL2U	:=	no
+override NEED_BL31	:=	yes
+NEED_BL32		:=	yes
+override NEED_BL33	:=	yes
+
+# Include GICv2 driver files
+include drivers/arm/gic/v2/gicv2.mk
+
+CORSTONE1000_GIC_SOURCES	:=	${GICV2_SOURCES}			\
+				plat/common/plat_gicv2.c		\
+				plat/arm/common/arm_gicv2.c
+
+
+BL2_SOURCES		+=	plat/arm/board/corstone1000/common/corstone1000_security.c		\
+				plat/arm/board/corstone1000/common/corstone1000_err.c		\
+				plat/arm/board/corstone1000/common/corstone1000_trusted_boot.c	\
+				lib/utils/mem_region.c					\
+				plat/arm/board/corstone1000/common/corstone1000_helpers.S		\
+				plat/arm/board/corstone1000/common/corstone1000_plat.c		\
+				plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c \
+				${CORSTONE1000_CPU_LIBS}					\
+
+
+BL31_SOURCES	+=	drivers/cfi/v2m/v2m_flash.c				\
+			lib/utils/mem_region.c					\
+			plat/arm/board/corstone1000/common/corstone1000_helpers.S		\
+			plat/arm/board/corstone1000/common/corstone1000_topology.c		\
+			plat/arm/board/corstone1000/common/corstone1000_security.c		\
+			plat/arm/board/corstone1000/common/corstone1000_plat.c		\
+			plat/arm/board/corstone1000/common/corstone1000_pm.c		\
+			${CORSTONE1000_CPU_LIBS}					\
+			${CORSTONE1000_GIC_SOURCES}
+
+ifneq (${ENABLE_STACK_PROTECTOR},0)
+	ifneq (${ENABLE_STACK_PROTECTOR},none)
+		CORSTONE1000_SECURITY_SOURCES := plat/arm/board/corstone1000/common/corstone1000_stack_protector.c
+		BL2_SOURCES += ${CORSTONE1000_SECURITY_SOURCES}
+		BL31_SOURCES += ${CORSTONE1000_SECURITY_SOURCES}
+	endif
+endif
+
+FDT_SOURCES		+=	plat/arm/board/corstone1000/common/fdts/corstone1000_spmc_manifest.dts
+CORSTONE1000_TOS_FW_CONFIG	:=	${BUILD_PLAT}/fdts/corstone1000_spmc_manifest.dtb
+
+# Add the SPMC manifest to FIP and specify the same to certtool
+$(eval $(call TOOL_ADD_PAYLOAD,${CORSTONE1000_TOS_FW_CONFIG},--tos-fw-config,${CORSTONE1000_TOS_FW_CONFIG}))
+
+# Adding TARGET_PLATFORM as a GCC define (-D option)
+$(eval $(call add_define,TARGET_PLATFORM_$(call uppercase,${TARGET_PLATFORM})))
+
+# Adding CORSTONE1000_FW_NVCTR_VAL as a GCC define (-D option)
+$(eval $(call add_define,CORSTONE1000_FW_NVCTR_VAL))
+
+include plat/arm/common/arm_common.mk
+include plat/arm/board/common/board_common.mk
diff --git a/plat/arm/board/diphda/platform.mk b/plat/arm/board/diphda/platform.mk
deleted file mode 100644
index 8b89cee..0000000
--- a/plat/arm/board/diphda/platform.mk
+++ /dev/null
@@ -1,83 +0,0 @@
-#
-# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-# Making sure the diphda platform type is specified
-ifeq ($(filter ${TARGET_PLATFORM}, fpga fvp),)
-	$(error TARGET_PLATFORM must be fpga or fvp)
-endif
-
-DIPHDA_CPU_LIBS	+=lib/cpus/aarch64/cortex_a35.S
-
-PLAT_INCLUDES		:=	-Iplat/arm/board/diphda/common/include	\
-				-Iplat/arm/board/diphda/include		\
-				-Iinclude/plat/arm/common			\
-				-Iinclude/plat/arm/css/common/aarch64
-
-
-DIPHDA_FW_NVCTR_VAL	:=	255
-TFW_NVCTR_VAL		:=	${DIPHDA_FW_NVCTR_VAL}
-NTFW_NVCTR_VAL		:=	${DIPHDA_FW_NVCTR_VAL}
-
-override NEED_BL1	:=	no
-
-override NEED_BL2	:=	yes
-FIP_BL2_ARGS := tb-fw
-
-override NEED_BL2U	:=	no
-override NEED_BL31	:=	yes
-NEED_BL32		:=	yes
-override NEED_BL33	:=	yes
-
-# Include GICv2 driver files
-include drivers/arm/gic/v2/gicv2.mk
-
-DIPHDA_GIC_SOURCES	:=	${GICV2_SOURCES}			\
-				plat/common/plat_gicv2.c		\
-				plat/arm/common/arm_gicv2.c
-
-
-BL2_SOURCES		+=	plat/arm/board/diphda/common/diphda_security.c		\
-				plat/arm/board/diphda/common/diphda_err.c		\
-				plat/arm/board/diphda/common/diphda_trusted_boot.c	\
-				lib/utils/mem_region.c					\
-				plat/arm/board/diphda/common/diphda_helpers.S		\
-				plat/arm/board/diphda/common/diphda_plat.c		\
-				plat/arm/board/diphda/common/diphda_bl2_mem_params_desc.c \
-				${DIPHDA_CPU_LIBS}					\
-
-
-BL31_SOURCES	+=	drivers/cfi/v2m/v2m_flash.c				\
-			lib/utils/mem_region.c					\
-			plat/arm/board/diphda/common/diphda_helpers.S		\
-			plat/arm/board/diphda/common/diphda_topology.c		\
-			plat/arm/board/diphda/common/diphda_security.c		\
-			plat/arm/board/diphda/common/diphda_plat.c		\
-			plat/arm/board/diphda/common/diphda_pm.c		\
-			${DIPHDA_CPU_LIBS}					\
-			${DIPHDA_GIC_SOURCES}
-
-ifneq (${ENABLE_STACK_PROTECTOR},0)
-	ifneq (${ENABLE_STACK_PROTECTOR},none)
-		DIPHDA_SECURITY_SOURCES := plat/arm/board/diphda/common/diphda_stack_protector.c
-		BL2_SOURCES += ${DIPHDA_SECURITY_SOURCES}
-		BL31_SOURCES += ${DIPHDA_SECURITY_SOURCES}
-	endif
-endif
-
-FDT_SOURCES		+=	plat/arm/board/diphda/common/fdts/diphda_spmc_manifest.dts
-DIPHDA_TOS_FW_CONFIG	:=	${BUILD_PLAT}/fdts/diphda_spmc_manifest.dtb
-
-# Add the SPMC manifest to FIP and specify the same to certtool
-$(eval $(call TOOL_ADD_PAYLOAD,${DIPHDA_TOS_FW_CONFIG},--tos-fw-config,${DIPHDA_TOS_FW_CONFIG}))
-
-# Adding TARGET_PLATFORM as a GCC define (-D option)
-$(eval $(call add_define,TARGET_PLATFORM_$(call uppercase,${TARGET_PLATFORM})))
-
-# Adding DIPHDA_FW_NVCTR_VAL as a GCC define (-D option)
-$(eval $(call add_define,DIPHDA_FW_NVCTR_VAL))
-
-include plat/arm/common/arm_common.mk
-include plat/arm/board/common/board_common.mk
diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk
index c45e045..6d7aa2d 100644
--- a/plat/arm/common/arm_common.mk
+++ b/plat/arm/common/arm_common.mk
@@ -282,7 +282,7 @@
 ifeq (${JUNO_AARCH32_EL3_RUNTIME},1)
 BL2_SOURCES		+=	plat/arm/common/aarch32/arm_bl2_mem_params_desc.c
 else
-ifneq (${PLAT}, diphda)
+ifneq (${PLAT}, corstone1000)
 BL2_SOURCES		+=	plat/arm/common/${ARCH}/arm_bl2_mem_params_desc.c
 endif
 endif