commit 2b3ac0b5e5d1c6a6ca73c099694ed87822c682ef
author Sieu Mun Tang <sieu.mun.tang@intel.com> Sat Jul 08 02:30:08 2023 +0800
committer Sieu Mun Tang <sieu.mun.tang@intel.com> Tue Jul 11 00:06:19 2023 +0800
tree 5b1e32fdb2337f4a3611d0f06ef65a613c08deab
parent 8bc3e33edb9927cb54107f66f9ea990223121585

fix(intel): resolved coverity checking

Coverity checking fix. Resolved unused value, deadcode and uninit.

	1. CID: 395326
	2. CID: 395327
	3. CID: 395328
	4. CID: 395329
	5. CID: 395330

Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I86b8af28dc345542b142ce53e1935bb855888238

plat/intel/soc/agilex5/bl2_plat_setup.c

diff --git a/plat/intel/soc/agilex5/bl2_plat_setup.c b/plat/intel/soc/agilex5/bl2_plat_setup.c
index 88f9880..a2fafd2 100644
--- a/plat/intel/soc/agilex5/bl2_plat_setup.c
+++ b/plat/intel/soc/agilex5/bl2_plat_setup.c
@@ -68,7 +68,7 @@
 {
 	static console_t console;
 
-	handoff reverse_handoff_ptr;
+	handoff reverse_handoff_ptr = { 0 };
 
 	generic_delay_timer_init();
 	config_clkmgr_handoff(&reverse_handoff_ptr);

plat/intel/soc/agilex5/soc/agilex5_clock_manager.c

diff --git a/plat/intel/soc/agilex5/soc/agilex5_clock_manager.c b/plat/intel/soc/agilex5/soc/agilex5_clock_manager.c
index 522bf5d..cc68153 100644
--- a/plat/intel/soc/agilex5/soc/agilex5_clock_manager.c
+++ b/plat/intel/soc/agilex5/soc/agilex5_clock_manager.c
@@ -178,17 +178,7 @@
 		pllc_reg = CLKMGR_MAINPLL + main_pllc;
 		pllglob_reg = CLKMGR_MAINPLL + CLKMGR_MAINPLL_PLLGLOB;
 		break;
-	case CLKMGR_PSRC_PER:
-		pllm_reg = CLKMGR_PERPLL + CLKMGR_PERPLL_PLLM;
-		pllc_reg = CLKMGR_PERPLL + per_pllc;
-		pllglob_reg = CLKMGR_PERPLL + CLKMGR_PERPLL_PLLGLOB;
-		break;
-	default:
-		return 0;
 	}
-	pllm_reg = CLKMGR_MAINPLL + CLKMGR_MAINPLL_PLLM;
-			pllc_reg = CLKMGR_MAINPLL + main_pllc;
-			pllglob_reg = CLKMGR_MAINPLL + CLKMGR_MAINPLL_PLLGLOB;
 
 	ref_clk = get_ref_clk(mmio_read_32(pllglob_reg));
 	mdiv = CLKMGR_PLLM_MDIV(mmio_read_32(pllm_reg));