diff --git a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20.c b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20.c
index c4f8701..c7137de 100644
--- a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20.c
+++ b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -13,7 +13,7 @@
 #include "qos_init_h3_v20.h"
 
 
-#define	RCAR_QOS_VERSION		"rev.0.20"
+#define	RCAR_QOS_VERSION		"rev.0.21"
 
 #define QOSWT_TIME_BANK0				(20000000U)	/* unit:ns */
 
diff --git a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.c b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.c
index 95f4810..ffc9025 100644
--- a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.c
+++ b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2018-2019, Renesas Electronics Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -13,7 +13,7 @@
 #include "qos_init_h3_v30.h"
 
 
-#define	RCAR_QOS_VERSION		"rev.0.10"
+#define	RCAR_QOS_VERSION		"rev.0.11"
 
 #define QOSCTRL_FSS			(QOS_BASE1 + 0x0048U)
 
diff --git a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30.c b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30.c
index 71e0396..6503b43 100644
--- a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30.c
+++ b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2018-2019, Renesas Electronics Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -13,7 +13,7 @@
 #include "qos_init_h3n_v30.h"
 
 
-#define	RCAR_QOS_VERSION		"rev.0.06"
+#define	RCAR_QOS_VERSION		"rev.0.07"
 
 #define QOSCTRL_FSS			(QOS_BASE1 + 0x0048U)
 
diff --git a/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c b/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c
index 10fa6b4..cee9dd0 100644
--- a/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c
+++ b/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2017-2019, Renesas Electronics Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -12,7 +12,7 @@
 #include "../qos_reg.h"
 #include "qos_init_m3_v11.h"
 
-#define	RCAR_QOS_VERSION		"rev.0.18"
+#define	RCAR_QOS_VERSION		"rev.0.19"
 
 
 #define QOSWT_TIME_BANK0				(20000000U)	/* unit:ns */
diff --git a/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v30.c b/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v30.c
index 319e393..e5a31c4 100644
--- a/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v30.c
+++ b/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v30.c
@@ -12,7 +12,7 @@
 #include "../qos_reg.h"
 #include "qos_init_m3_v30.h"
 
-#define	RCAR_QOS_VERSION		"rev.0.1"
+#define	RCAR_QOS_VERSION		"rev.0.02"
 
 #define QOSCTRL_EARLYR			(QOS_BASE1 + 0x0060U)
 #define QOSCTRL_FSS			(QOS_BASE1 + 0x0048U)
diff --git a/drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.c b/drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
index 52a3ca2..bd023e2 100644
--- a/drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
+++ b/drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2017-2019, Renesas Electronics Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -12,7 +12,7 @@
 #include "../qos_reg.h"
 #include "qos_init_m3n_v10.h"
 
-#define	RCAR_QOS_VERSION		"rev.0.08"
+#define	RCAR_QOS_VERSION		"rev.0.09"
 
 #define QOSCTRL_EARLYR			(QOS_BASE1 + 0x0060U)
 #define QOSCTRL_FSS			(QOS_BASE1 + 0x0048U)
diff --git a/drivers/staging/renesas/rcar/qos/qos_common.h b/drivers/staging/renesas/rcar/qos/qos_common.h
index 89dcf06..c3a83ac 100644
--- a/drivers/staging/renesas/rcar/qos/qos_common.h
+++ b/drivers/staging/renesas/rcar/qos/qos_common.h
@@ -34,9 +34,9 @@
 #if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N)
 /* define used for M3N */
 #if (RCAR_REF_INT == RCAR_REF_DEFAULT)	/* REF 1.95usec */
-#define SUB_SLOT_CYCLE_M3N		(0x84U)	/* 132 */
+#define SUB_SLOT_CYCLE_M3N		(0x7EU)	/* 126 */
 #else /* REF 3.9usec */
-#define SUB_SLOT_CYCLE_M3N		(0x108U)	/* 264 */
+#define SUB_SLOT_CYCLE_M3N		(0xFCU)	/* 252 */
 #endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
 
 #define SL_INIT_SSLOTCLK_M3N		(SUB_SLOT_CYCLE_M3N -1U)
@@ -46,9 +46,9 @@
 #if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3)
 /* define used for H3 */
 #if (RCAR_REF_INT == RCAR_REF_DEFAULT)	/* REF 1.95usec */
-#define SUB_SLOT_CYCLE_H3_20		(0x84U)	/* 132 */
+#define SUB_SLOT_CYCLE_H3_20		(0x7EU)	/* 126 */
 #else /* REF 3.9usec */
-#define SUB_SLOT_CYCLE_H3_20		(0x108U)	/* 264 */
+#define SUB_SLOT_CYCLE_H3_20		(0xFCU)	/* 252 */
 #endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
 
 #define SL_INIT_SSLOTCLK_H3_20		(SUB_SLOT_CYCLE_H3_20 -1U)
@@ -64,9 +64,9 @@
 #if (RCAR_LSI == RCAR_H3N)
 /* define used for H3N */
 #if (RCAR_REF_INT == RCAR_REF_DEFAULT)	/* REF 1.95usec */
-#define SUB_SLOT_CYCLE_H3N		(0x84U)	/* 132 */
+#define SUB_SLOT_CYCLE_H3N		(0x7EU)	/* 126 */
 #else /* REF 3.9usec */
-#define SUB_SLOT_CYCLE_H3N		(0x108U)	/* 264 */
+#define SUB_SLOT_CYCLE_H3N		(0xFCU)	/* 252 */
 #endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
 
 #define SL_INIT_SSLOTCLK_H3N		(SUB_SLOT_CYCLE_H3N -1U)
@@ -77,11 +77,11 @@
 #if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3)
 /* define used for M3 */
 #if (RCAR_REF_INT == RCAR_REF_DEFAULT)	/* REF 1.95usec */
-#define SUB_SLOT_CYCLE_M3_11		(0x84U)	/* 132 */
-#define SUB_SLOT_CYCLE_M3_30		(0x84U)	/* 132 */
+#define SUB_SLOT_CYCLE_M3_11		(0x7EU)	/* 126 */
+#define SUB_SLOT_CYCLE_M3_30		(0x7EU)	/* 126 */
 #else /* REF 3.9usec */
-#define SUB_SLOT_CYCLE_M3_11		(0x108U)	/* 264 */
-#define SUB_SLOT_CYCLE_M3_30		(0x108U)	/* 264 */
+#define SUB_SLOT_CYCLE_M3_11		(0xFCU)	/* 252 */
+#define SUB_SLOT_CYCLE_M3_30		(0xFCU)	/* 252 */
 #endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
 
 #define SL_INIT_SSLOTCLK_M3_11		(SUB_SLOT_CYCLE_M3_11 -1U)