Merge "fix(st): manage UART clock and reset only in BL2" into integration
diff --git a/docs/plat/allwinner.rst b/docs/plat/allwinner.rst
index b696989..3e9ce51 100644
--- a/docs/plat/allwinner.rst
+++ b/docs/plat/allwinner.rst
@@ -8,24 +8,67 @@
Building TF-A
-------------
-To build for machines with an A64 or H5 SoC:
+There is one build target per supported SoC:
+
++------+-------------------+
+| SoC | TF-A build target |
++======+===================+
+| A64 | sun50i_a64 |
++------+-------------------+
+| H5 | sun50i_a64 |
++------+-------------------+
+| H6 | sun50i_h6 |
++------+-------------------+
+| H616 | sun50i_h616 |
++------+-------------------+
+| H313 | sun50i_h616 |
++------+-------------------+
+| R329 | sun50i_r329 |
++------+-------------------+
+
+To build with the default settings for a particular SoC:
.. code:: shell
- make CROSS_COMPILE=aarch64-linux-gnu- PLAT=sun50i_a64 DEBUG=1 bl31
+ make CROSS_COMPILE=aarch64-linux-gnu- PLAT=<build target> DEBUG=1
-To build for machines with an H6 SoC:
+So for instance to build for a board with the Allwinner A64 SoC::
-.. code:: shell
+ make CROSS_COMPILE=aarch64-linux-gnu- PLAT=sun50i_a64 DEBUG=1
- make CROSS_COMPILE=aarch64-linux-gnu- PLAT=sun50i_h6 DEBUG=1 bl31
+Platform-specific build options
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-To build for machines with an H616 or H313 SoC:
+The default build options should generate a working firmware image. There are
+some build options that allow to fine-tune the firmware, or to disable support
+for optional features.
-.. code:: shell
+- ``SUNXI_PSCI_USE_NATIVE`` : Support direct control of the CPU cores powerdown
+ and powerup sequence by BL31. This requires either support for a code snippet
+ to be loaded into the ARISC SCP (A64, H5), or the power sequence control
+ registers to be programmed directly (H6, H616). This supports only basic
+ control, like core on/off and system off/reset.
+ This option defaults to 1. If an active SCP supporting the SCPI protocol
+ is detected at runtime, this control scheme will be ignored, and SCPI
+ will be used instead, unless support has been explicitly disabled.
- make CROSS_COMPILE=aarch64-linux-gnu- PLAT=sun50i_h616 DEBUG=1 bl31
+- ``SUNXI_PSCI_USE_SCPI`` : Support control of the CPU cores powerdown and
+ powerup sequence by talking to the SCP processor via the SCPI protocol.
+ This allows more advanced power saving techniques, like suspend to RAM.
+ This option defaults to 1 on SoCs that feature an SCP. If no SCP firmware
+ using the SCPI protocol is detected, the native sequence will be used
+ instead. If both native and SCPI methods are included, SCPI will be favoured
+ if SCP support is detected.
+- ``SUNXI_SETUP_REGULATORS`` : On SoCs that typically ship with a PMIC
+ power management controller, BL31 tries to set up all needed power rails,
+ programming them to their respective voltages. That allows bootloader
+ software like U-Boot to ignore power control via the PMIC.
+ This setting defaults to 1. In some situations that enables too many
+ regulators, or some regulators need to be enabled in a very specific
+ sequence. To avoid problems with those boards, ``SUNXI_SETUP_REGULATORS``
+ can bet set to ``0`` on the build command line, to skip the PMIC setup
+ entirely. Any bootloader or OS would need to setup the PMIC on its own then.
Installation
------------
diff --git a/lib/cpus/aarch64/rainier.S b/lib/cpus/aarch64/rainier.S
index 3017a50..584ab97 100644
--- a/lib/cpus/aarch64/rainier.S
+++ b/lib/cpus/aarch64/rainier.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2022, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -41,6 +41,40 @@
ret
endfunc rainier_disable_speculative_loads
+ /* --------------------------------------------------
+ * Errata Workaround for Neoverse N1 Errata #1868343.
+ * This applies to revision <= r4p0 of Neoverse N1.
+ * This workaround is the same as the workaround for
+ * errata 1262606 and 1275112 but applies to a wider
+ * revision range.
+ * Rainier R0P0 is based on Neoverse N1 R4P0 so the
+ * workaround checks for r0p0 version of Rainier CPU.
+ * Inputs:
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0, x1 & x17
+ * --------------------------------------------------
+ */
+func errata_n1_1868343_wa
+ /*
+ * Compare x0 against revision r4p0
+ */
+ mov x17, x30
+ bl check_errata_1868343
+ cbz x0, 1f
+ mrs x1, RAINIER_CPUACTLR_EL1
+ orr x1, x1, RAINIER_CPUACTLR_EL1_BIT_13
+ msr RAINIER_CPUACTLR_EL1, x1
+ isb
+1:
+ ret x17
+endfunc errata_n1_1868343_wa
+
+func check_errata_1868343
+ /* Applies to r0p0 of Rainier CPU */
+ mov x1, #0x00
+ b cpu_rev_var_ls
+endfunc check_errata_1868343
+
func rainier_reset_func
mov x19, x30
@@ -55,6 +89,11 @@
bl cpu_get_rev_var
mov x18, x0
+#if ERRATA_N1_1868343
+ mov x0, x18
+ bl errata_n1_1868343_wa
+#endif
+
#if ENABLE_AMU
/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
mrs x0, actlr_el3
@@ -101,6 +140,12 @@
bl cpu_get_rev_var
mov x8, x0
+ /*
+ * Report all errata. The revision-variant information is passed to
+ * checking functions of each errata.
+ */
+ report_errata ERRATA_N1_1868343, rainier, 1868343
+
ldp x8, x30, [sp], #16
ret
endfunc rainier_errata_report
diff --git a/plat/arm/board/morello/platform.mk b/plat/arm/board/morello/platform.mk
index 26a1911..86047e3 100644
--- a/plat/arm/board/morello/platform.mk
+++ b/plat/arm/board/morello/platform.mk
@@ -83,6 +83,9 @@
override ARM_PLAT_MT := 1
+# Errata workarounds:
+ERRATA_N1_1868343 := 1
+
# Select SCMI/SDS drivers instead of SCPI/BOM driver for communicating with the
# SCP during power management operations and for SCP RAM Firmware transfer.
CSS_USE_SCMI_SDS_DRIVER := 1