| commit | 29efcbebfd2f32db46e6bfcf208d9111a652c60c | [log] [tgz] |
|---|---|---|
| author | Amit Nagal <amit.nagal@amd.com> | Mon Sep 04 21:54:00 2023 -1200 |
| committer | amit nagal <amit.nagal@amd.com> | Wed Sep 13 18:37:39 2023 +0200 |
| tree | eabca5a678ec3965165c1050d8f0527721352f01 | |
| parent | c1248e8621c0935f7804041b140b711a673d1154 [diff] |
fix(xilinx): dcache flush for dtb region flush dcache region for dtb so that dtb cache entries are first written to disk and are invalidated afterwards to avoid presence of any stale dtb related entry in the dcache. Change-Id: Ide0ed58f799b35b690ed790c7498ecdc334e02f5 Signed-off-by: Amit Nagal <amit.nagal@amd.com>