diff --git a/drivers/arm/gic/arm_gic.c b/drivers/arm/gic/arm_gic.c
deleted file mode 100644
index e040e0a..0000000
--- a/drivers/arm/gic/arm_gic.c
+++ /dev/null
@@ -1,435 +0,0 @@
-/*
- * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch.h>
-#include <arch_helpers.h>
-#include <arm_gic.h>
-#include <assert.h>
-#include <bl_common.h>
-#include <debug.h>
-#include <gic_v2.h>
-#include <gic_v3.h>
-#include <interrupt_mgmt.h>
-#include <platform.h>
-#include <stdint.h>
-
-/* Value used to initialize Non-Secure IRQ priorities four at a time */
-#define GICD_IPRIORITYR_DEF_VAL \
-	(GIC_HIGHEST_NS_PRIORITY | \
-	(GIC_HIGHEST_NS_PRIORITY << 8) | \
-	(GIC_HIGHEST_NS_PRIORITY << 16) | \
-	(GIC_HIGHEST_NS_PRIORITY << 24))
-
-static uintptr_t g_gicc_base;
-static uintptr_t g_gicd_base;
-static uintptr_t g_gicr_base;
-static const unsigned int *g_irq_sec_ptr;
-static unsigned int g_num_irqs;
-
-
-/*******************************************************************************
- * This function does some minimal GICv3 configuration. The Firmware itself does
- * not fully support GICv3 at this time and relies on GICv2 emulation as
- * provided by GICv3. This function allows software (like Linux) in later stages
- * to use full GICv3 features.
- ******************************************************************************/
-static void gicv3_cpuif_setup(void)
-{
-	unsigned int val;
-	uintptr_t base;
-
-	/*
-	 * When CPUs come out of reset they have their GICR_WAKER.ProcessorSleep
-	 * bit set. In order to allow interrupts to get routed to the CPU we
-	 * need to clear this bit if set and wait for GICR_WAKER.ChildrenAsleep
-	 * to clear (GICv3 Architecture specification 5.4.23).
-	 * GICR_WAKER is NOT banked per CPU, compute the correct base address
-	 * per CPU.
-	 */
-	assert(g_gicr_base);
-	base = gicv3_get_rdist(g_gicr_base, read_mpidr());
-	if (base == (uintptr_t)NULL) {
-		/* No re-distributor base address. This interface cannot be
-		 * configured.
-		 */
-		panic();
-	}
-
-	val = gicr_read_waker(base);
-
-	val &= ~WAKER_PS;
-	gicr_write_waker(base, val);
-	dsb();
-
-	/* We need to wait for ChildrenAsleep to clear. */
-	val = gicr_read_waker(base);
-	while (val & WAKER_CA)
-		val = gicr_read_waker(base);
-
-	val = read_icc_sre_el3();
-	write_icc_sre_el3(val | ICC_SRE_EN | ICC_SRE_SRE);
-	isb();
-}
-
-/*******************************************************************************
- * This function does some minimal GICv3 configuration when cores go
- * down.
- ******************************************************************************/
-static void gicv3_cpuif_deactivate(void)
-{
-	unsigned int val;
-	uintptr_t base;
-
-	/*
-	 * When taking CPUs down we need to set GICR_WAKER.ProcessorSleep and
-	 * wait for GICR_WAKER.ChildrenAsleep to get set.
-	 * (GICv3 Architecture specification 5.4.23).
-	 * GICR_WAKER is NOT banked per CPU, compute the correct base address
-	 * per CPU.
-	 */
-	assert(g_gicr_base);
-	base = gicv3_get_rdist(g_gicr_base, read_mpidr());
-	if (base == (uintptr_t)NULL) {
-		/* No re-distributor base address. This interface cannot be
-		 * configured.
-		 */
-		panic();
-	}
-
-	val = gicr_read_waker(base);
-	val |= WAKER_PS;
-	gicr_write_waker(base, val);
-	dsb();
-
-	/* We need to wait for ChildrenAsleep to set. */
-	val = gicr_read_waker(base);
-	while ((val & WAKER_CA) == 0)
-		val = gicr_read_waker(base);
-}
-
-
-/*******************************************************************************
- * Enable secure interrupts and use FIQs to route them. Disable legacy bypass
- * and set the priority mask register to allow all interrupts to trickle in.
- ******************************************************************************/
-void arm_gic_cpuif_setup(void)
-{
-	unsigned int val;
-
-	assert(g_gicc_base);
-	val = gicc_read_iidr(g_gicc_base);
-
-	/*
-	 * If GICv3 we need to do a bit of additional setup. We want to
-	 * allow default GICv2 behaviour but allow the next stage to
-	 * enable full gicv3 features.
-	 */
-	if (((val >> GICC_IIDR_ARCH_SHIFT) & GICC_IIDR_ARCH_MASK) >= 3)
-		gicv3_cpuif_setup();
-
-	val = ENABLE_GRP0 | FIQ_EN | FIQ_BYP_DIS_GRP0;
-	val |= IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP1 | IRQ_BYP_DIS_GRP1;
-
-	gicc_write_pmr(g_gicc_base, GIC_PRI_MASK);
-	gicc_write_ctlr(g_gicc_base, val);
-}
-
-/*******************************************************************************
- * Place the cpu interface in a state where it can never make a cpu exit wfi as
- * as result of an asserted interrupt. This is critical for powering down a cpu
- ******************************************************************************/
-void arm_gic_cpuif_deactivate(void)
-{
-	unsigned int val;
-
-	/* Disable secure, non-secure interrupts and disable their bypass */
-	assert(g_gicc_base);
-	val = gicc_read_ctlr(g_gicc_base);
-	val &= ~(ENABLE_GRP0 | ENABLE_GRP1);
-	val |= FIQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP0;
-	val |= IRQ_BYP_DIS_GRP0 | IRQ_BYP_DIS_GRP1;
-	gicc_write_ctlr(g_gicc_base, val);
-
-	val = gicc_read_iidr(g_gicc_base);
-
-	/*
-	 * If GICv3 we need to do a bit of additional setup. Make sure the
-	 * RDIST is put to sleep.
-	 */
-	if (((val >> GICC_IIDR_ARCH_SHIFT) & GICC_IIDR_ARCH_MASK) >= 3)
-		gicv3_cpuif_deactivate();
-}
-
-/*******************************************************************************
- * Per cpu gic distributor setup which will be done by all cpus after a cold
- * boot/hotplug. This marks out the secure interrupts & enables them.
- ******************************************************************************/
-void arm_gic_pcpu_distif_setup(void)
-{
-	unsigned int index, irq_num, sec_ppi_sgi_mask;
-
-	assert(g_gicd_base);
-
-	/* Setup PPI priorities doing four at a time */
-	for (index = 0; index < 32; index += 4) {
-		gicd_write_ipriorityr(g_gicd_base, index,
-				GICD_IPRIORITYR_DEF_VAL);
-	}
-
-	assert(g_irq_sec_ptr);
-	sec_ppi_sgi_mask = 0;
-
-	/* Ensure all SGIs and PPIs are Group0 to begin with */
-	gicd_write_igroupr(g_gicd_base, 0, 0);
-
-	for (index = 0; index < g_num_irqs; index++) {
-		irq_num = g_irq_sec_ptr[index];
-		if (irq_num < MIN_SPI_ID) {
-			/* We have an SGI or a PPI */
-			sec_ppi_sgi_mask |= 1U << irq_num;
-			gicd_set_ipriorityr(g_gicd_base, irq_num,
-				GIC_HIGHEST_SEC_PRIORITY);
-			gicd_set_isenabler(g_gicd_base, irq_num);
-		}
-	}
-
-	/*
-	 * Invert the bitmask to create a mask for non-secure PPIs and
-	 * SGIs. Program the GICD_IGROUPR0 with this bit mask. This write will
-	 * update the GICR_IGROUPR0 as well in case we are running on a GICv3
-	 * system. This is critical if GICD_CTLR.ARE_NS=1.
-	 */
-	gicd_write_igroupr(g_gicd_base, 0, ~sec_ppi_sgi_mask);
-}
-
-/*******************************************************************************
- * Get the current CPU bit mask from GICD_ITARGETSR0
- ******************************************************************************/
-static unsigned int arm_gic_get_cpuif_id(void)
-{
-	unsigned int val;
-
-	val = gicd_read_itargetsr(g_gicd_base, 0);
-	return val & GIC_TARGET_CPU_MASK;
-}
-
-/*******************************************************************************
- * Global gic distributor setup which will be done by the primary cpu after a
- * cold boot. It marks out the secure SPIs, PPIs & SGIs and enables them. It
- * then enables the secure GIC distributor interface.
- ******************************************************************************/
-static void arm_gic_distif_setup(void)
-{
-	unsigned int num_ints, ctlr, index, irq_num;
-	uint8_t target_cpu;
-
-	/* Disable the distributor before going further */
-	assert(g_gicd_base);
-	ctlr = gicd_read_ctlr(g_gicd_base);
-	ctlr &= ~(ENABLE_GRP0 | ENABLE_GRP1);
-	gicd_write_ctlr(g_gicd_base, ctlr);
-
-	/*
-	 * Mark out non-secure SPI interrupts. The number of interrupts is
-	 * calculated as 32 * (IT_LINES + 1). We do 32 at a time.
-	 */
-	num_ints = gicd_read_typer(g_gicd_base) & IT_LINES_NO_MASK;
-	num_ints = (num_ints + 1) << 5;
-	for (index = MIN_SPI_ID; index < num_ints; index += 32)
-		gicd_write_igroupr(g_gicd_base, index, ~0);
-
-	/* Setup SPI priorities doing four at a time */
-	for (index = MIN_SPI_ID; index < num_ints; index += 4) {
-		gicd_write_ipriorityr(g_gicd_base, index,
-				GICD_IPRIORITYR_DEF_VAL);
-	}
-
-	/* Read the target CPU mask */
-	target_cpu = arm_gic_get_cpuif_id();
-
-	/* Configure SPI secure interrupts now */
-	assert(g_irq_sec_ptr);
-	for (index = 0; index < g_num_irqs; index++) {
-		irq_num = g_irq_sec_ptr[index];
-		if (irq_num >= MIN_SPI_ID) {
-			/* We have an SPI */
-			gicd_clr_igroupr(g_gicd_base, irq_num);
-			gicd_set_ipriorityr(g_gicd_base, irq_num,
-				GIC_HIGHEST_SEC_PRIORITY);
-			gicd_set_itargetsr(g_gicd_base, irq_num, target_cpu);
-			gicd_set_isenabler(g_gicd_base, irq_num);
-		}
-	}
-
-	/*
-	 * Configure the SGI and PPI. This is done in a separated function
-	 * because each CPU is responsible for initializing its own private
-	 * interrupts.
-	 */
-	arm_gic_pcpu_distif_setup();
-
-	gicd_write_ctlr(g_gicd_base, ctlr | ENABLE_GRP0);
-}
-
-/*******************************************************************************
- * Initialize the ARM GIC driver with the provided platform inputs
-******************************************************************************/
-void arm_gic_init(uintptr_t gicc_base,
-		  uintptr_t gicd_base,
-		  uintptr_t gicr_base,
-		  const unsigned int *irq_sec_ptr,
-		  unsigned int num_irqs)
-{
-	unsigned int val;
-
-	assert(gicc_base);
-	assert(gicd_base);
-	assert(irq_sec_ptr);
-
-	g_gicc_base = gicc_base;
-	g_gicd_base = gicd_base;
-
-	val = gicc_read_iidr(g_gicc_base);
-
-	if (((val >> GICC_IIDR_ARCH_SHIFT) & GICC_IIDR_ARCH_MASK) >= 3) {
-		assert(gicr_base);
-		g_gicr_base = gicr_base;
-	}
-
-	g_irq_sec_ptr = irq_sec_ptr;
-	g_num_irqs = num_irqs;
-}
-
-/*******************************************************************************
- * Setup the ARM GIC CPU and distributor interfaces.
-******************************************************************************/
-void arm_gic_setup(void)
-{
-	arm_gic_cpuif_setup();
-	arm_gic_distif_setup();
-}
-
-/*******************************************************************************
- * An ARM processor signals interrupt exceptions through the IRQ and FIQ pins.
- * The interrupt controller knows which pin/line it uses to signal a type of
- * interrupt. This function provides a common implementation of
- * plat_interrupt_type_to_line() in an ARM GIC environment for optional re-use
- * across platforms. It lets the interrupt management framework determine
- * for a type of interrupt and security state, which line should be used in the
- * SCR_EL3 to control its routing to EL3. The interrupt line is represented as
- * the bit position of the IRQ or FIQ bit in the SCR_EL3.
- ******************************************************************************/
-uint32_t arm_gic_interrupt_type_to_line(uint32_t type,
-				uint32_t security_state)
-{
-	assert(type == INTR_TYPE_S_EL1 ||
-	       type == INTR_TYPE_EL3 ||
-	       type == INTR_TYPE_NS);
-
-	assert(sec_state_is_valid(security_state));
-
-	/*
-	 * We ignore the security state parameter under the assumption that
-	 * both normal and secure worlds are using ARM GICv2. This parameter
-	 * will be used when the secure world starts using GICv3.
-	 */
-#if ARM_GIC_ARCH == 2
-	return gicv2_interrupt_type_to_line(g_gicc_base, type);
-#else
-#error "Invalid ARM GIC architecture version specified for platform port"
-#endif /* ARM_GIC_ARCH */
-}
-
-#if ARM_GIC_ARCH == 2
-/*******************************************************************************
- * This function returns the type of the highest priority pending interrupt at
- * the GIC cpu interface. INTR_TYPE_INVAL is returned when there is no
- * interrupt pending.
- ******************************************************************************/
-uint32_t arm_gic_get_pending_interrupt_type(void)
-{
-	uint32_t id;
-
-	assert(g_gicc_base);
-	id = gicc_read_hppir(g_gicc_base) & INT_ID_MASK;
-
-	/* Assume that all secure interrupts are S-EL1 interrupts */
-	if (id < 1022)
-		return INTR_TYPE_S_EL1;
-
-	if (id == GIC_SPURIOUS_INTERRUPT)
-		return INTR_TYPE_INVAL;
-
-	return INTR_TYPE_NS;
-}
-
-/*******************************************************************************
- * This function returns the id of the highest priority pending interrupt at
- * the GIC cpu interface. INTR_ID_UNAVAILABLE is returned when there is no
- * interrupt pending.
- ******************************************************************************/
-uint32_t arm_gic_get_pending_interrupt_id(void)
-{
-	uint32_t id;
-
-	assert(g_gicc_base);
-	id = gicc_read_hppir(g_gicc_base) & INT_ID_MASK;
-
-	if (id < 1022)
-		return id;
-
-	if (id == 1023)
-		return INTR_ID_UNAVAILABLE;
-
-	/*
-	 * Find out which non-secure interrupt it is under the assumption that
-	 * the GICC_CTLR.AckCtl bit is 0.
-	 */
-	return gicc_read_ahppir(g_gicc_base) & INT_ID_MASK;
-}
-
-/*******************************************************************************
- * This functions reads the GIC cpu interface Interrupt Acknowledge register
- * to start handling the pending interrupt. It returns the contents of the IAR.
- ******************************************************************************/
-uint32_t arm_gic_acknowledge_interrupt(void)
-{
-	assert(g_gicc_base);
-	return gicc_read_IAR(g_gicc_base);
-}
-
-/*******************************************************************************
- * This functions writes the GIC cpu interface End Of Interrupt register with
- * the passed value to finish handling the active interrupt
- ******************************************************************************/
-void arm_gic_end_of_interrupt(uint32_t id)
-{
-	assert(g_gicc_base);
-	gicc_write_EOIR(g_gicc_base, id);
-}
-
-/*******************************************************************************
- * This function returns the type of the interrupt id depending upon the group
- * this interrupt has been configured under by the interrupt controller i.e.
- * group0 or group1.
- ******************************************************************************/
-uint32_t arm_gic_get_interrupt_type(uint32_t id)
-{
-	uint32_t group;
-
-	assert(g_gicd_base);
-	group = gicd_get_igroupr(g_gicd_base, id);
-
-	/* Assume that all secure interrupts are S-EL1 interrupts */
-	if (group == GRP0)
-		return INTR_TYPE_S_EL1;
-	else
-		return INTR_TYPE_NS;
-}
-
-#else
-#error "Invalid ARM GIC architecture version specified for platform port"
-#endif /* ARM_GIC_ARCH */
diff --git a/drivers/arm/gic/gic_v2.c b/drivers/arm/gic/gic_v2.c
deleted file mode 100644
index 29c79e0..0000000
--- a/drivers/arm/gic/gic_v2.c
+++ /dev/null
@@ -1,284 +0,0 @@
-/*
- * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch.h>
-#include <assert.h>
-#include <gic_v2.h>
-#include <interrupt_mgmt.h>
-#include <mmio.h>
-
-/*******************************************************************************
- * GIC Distributor interface accessors for reading entire registers
- ******************************************************************************/
-
-unsigned int gicd_read_igroupr(uintptr_t base, unsigned int id)
-{
-	unsigned n = id >> IGROUPR_SHIFT;
-	return mmio_read_32(base + GICD_IGROUPR + (n << 2));
-}
-
-unsigned int gicd_read_isenabler(uintptr_t base, unsigned int id)
-{
-	unsigned n = id >> ISENABLER_SHIFT;
-	return mmio_read_32(base + GICD_ISENABLER + (n << 2));
-}
-
-unsigned int gicd_read_icenabler(uintptr_t base, unsigned int id)
-{
-	unsigned n = id >> ICENABLER_SHIFT;
-	return mmio_read_32(base + GICD_ICENABLER + (n << 2));
-}
-
-unsigned int gicd_read_ispendr(uintptr_t base, unsigned int id)
-{
-	unsigned n = id >> ISPENDR_SHIFT;
-	return mmio_read_32(base + GICD_ISPENDR + (n << 2));
-}
-
-unsigned int gicd_read_icpendr(uintptr_t base, unsigned int id)
-{
-	unsigned n = id >> ICPENDR_SHIFT;
-	return mmio_read_32(base + GICD_ICPENDR + (n << 2));
-}
-
-unsigned int gicd_read_isactiver(uintptr_t base, unsigned int id)
-{
-	unsigned n = id >> ISACTIVER_SHIFT;
-	return mmio_read_32(base + GICD_ISACTIVER + (n << 2));
-}
-
-unsigned int gicd_read_icactiver(uintptr_t base, unsigned int id)
-{
-	unsigned n = id >> ICACTIVER_SHIFT;
-	return mmio_read_32(base + GICD_ICACTIVER + (n << 2));
-}
-
-unsigned int gicd_read_ipriorityr(uintptr_t base, unsigned int id)
-{
-	unsigned n = id >> IPRIORITYR_SHIFT;
-	return mmio_read_32(base + GICD_IPRIORITYR + (n << 2));
-}
-
-unsigned int gicd_read_itargetsr(uintptr_t base, unsigned int id)
-{
-	unsigned n = id >> ITARGETSR_SHIFT;
-	return mmio_read_32(base + GICD_ITARGETSR + (n << 2));
-}
-
-unsigned int gicd_read_icfgr(uintptr_t base, unsigned int id)
-{
-	unsigned n = id >> ICFGR_SHIFT;
-	return mmio_read_32(base + GICD_ICFGR + (n << 2));
-}
-
-unsigned int gicd_read_cpendsgir(uintptr_t base, unsigned int id)
-{
-	unsigned n = id >> CPENDSGIR_SHIFT;
-	return mmio_read_32(base + GICD_CPENDSGIR + (n << 2));
-}
-
-unsigned int gicd_read_spendsgir(uintptr_t base, unsigned int id)
-{
-	unsigned n = id >> SPENDSGIR_SHIFT;
-	return mmio_read_32(base + GICD_SPENDSGIR + (n << 2));
-}
-
-/*******************************************************************************
- * GIC Distributor interface accessors for writing entire registers
- ******************************************************************************/
-
-void gicd_write_igroupr(uintptr_t base, unsigned int id, unsigned int val)
-{
-	unsigned n = id >> IGROUPR_SHIFT;
-	mmio_write_32(base + GICD_IGROUPR + (n << 2), val);
-}
-
-void gicd_write_isenabler(uintptr_t base, unsigned int id, unsigned int val)
-{
-	unsigned n = id >> ISENABLER_SHIFT;
-	mmio_write_32(base + GICD_ISENABLER + (n << 2), val);
-}
-
-void gicd_write_icenabler(uintptr_t base, unsigned int id, unsigned int val)
-{
-	unsigned n = id >> ICENABLER_SHIFT;
-	mmio_write_32(base + GICD_ICENABLER + (n << 2), val);
-}
-
-void gicd_write_ispendr(uintptr_t base, unsigned int id, unsigned int val)
-{
-	unsigned n = id >> ISPENDR_SHIFT;
-	mmio_write_32(base + GICD_ISPENDR + (n << 2), val);
-}
-
-void gicd_write_icpendr(uintptr_t base, unsigned int id, unsigned int val)
-{
-	unsigned n = id >> ICPENDR_SHIFT;
-	mmio_write_32(base + GICD_ICPENDR + (n << 2), val);
-}
-
-void gicd_write_isactiver(uintptr_t base, unsigned int id, unsigned int val)
-{
-	unsigned n = id >> ISACTIVER_SHIFT;
-	mmio_write_32(base + GICD_ISACTIVER + (n << 2), val);
-}
-
-void gicd_write_icactiver(uintptr_t base, unsigned int id, unsigned int val)
-{
-	unsigned n = id >> ICACTIVER_SHIFT;
-	mmio_write_32(base + GICD_ICACTIVER + (n << 2), val);
-}
-
-void gicd_write_ipriorityr(uintptr_t base, unsigned int id, unsigned int val)
-{
-	unsigned n = id >> IPRIORITYR_SHIFT;
-	mmio_write_32(base + GICD_IPRIORITYR + (n << 2), val);
-}
-
-void gicd_write_itargetsr(uintptr_t base, unsigned int id, unsigned int val)
-{
-	unsigned n = id >> ITARGETSR_SHIFT;
-	mmio_write_32(base + GICD_ITARGETSR + (n << 2), val);
-}
-
-void gicd_write_icfgr(uintptr_t base, unsigned int id, unsigned int val)
-{
-	unsigned n = id >> ICFGR_SHIFT;
-	mmio_write_32(base + GICD_ICFGR + (n << 2), val);
-}
-
-void gicd_write_cpendsgir(uintptr_t base, unsigned int id, unsigned int val)
-{
-	unsigned n = id >> CPENDSGIR_SHIFT;
-	mmio_write_32(base + GICD_CPENDSGIR + (n << 2), val);
-}
-
-void gicd_write_spendsgir(uintptr_t base, unsigned int id, unsigned int val)
-{
-	unsigned n = id >> SPENDSGIR_SHIFT;
-	mmio_write_32(base + GICD_SPENDSGIR + (n << 2), val);
-}
-
-/*******************************************************************************
- * GIC Distributor interface accessors for individual interrupt manipulation
- ******************************************************************************/
-unsigned int gicd_get_igroupr(uintptr_t base, unsigned int id)
-{
-	unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1);
-	unsigned int reg_val = gicd_read_igroupr(base, id);
-
-	return (reg_val >> bit_num) & 0x1;
-}
-
-void gicd_set_igroupr(uintptr_t base, unsigned int id)
-{
-	unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1);
-	unsigned int reg_val = gicd_read_igroupr(base, id);
-
-	gicd_write_igroupr(base, id, reg_val | (1 << bit_num));
-}
-
-void gicd_clr_igroupr(uintptr_t base, unsigned int id)
-{
-	unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1);
-	unsigned int reg_val = gicd_read_igroupr(base, id);
-
-	gicd_write_igroupr(base, id, reg_val & ~(1 << bit_num));
-}
-
-void gicd_set_isenabler(uintptr_t base, unsigned int id)
-{
-	unsigned bit_num = id & ((1 << ISENABLER_SHIFT) - 1);
-
-	gicd_write_isenabler(base, id, (1 << bit_num));
-}
-
-void gicd_set_icenabler(uintptr_t base, unsigned int id)
-{
-	unsigned bit_num = id & ((1 << ICENABLER_SHIFT) - 1);
-
-	gicd_write_icenabler(base, id, (1 << bit_num));
-}
-
-void gicd_set_ispendr(uintptr_t base, unsigned int id)
-{
-	unsigned bit_num = id & ((1 << ISPENDR_SHIFT) - 1);
-
-	gicd_write_ispendr(base, id, (1 << bit_num));
-}
-
-void gicd_set_icpendr(uintptr_t base, unsigned int id)
-{
-	unsigned bit_num = id & ((1 << ICPENDR_SHIFT) - 1);
-
-	gicd_write_icpendr(base, id, (1 << bit_num));
-}
-
-void gicd_set_isactiver(uintptr_t base, unsigned int id)
-{
-	unsigned bit_num = id & ((1 << ISACTIVER_SHIFT) - 1);
-
-	gicd_write_isactiver(base, id, (1 << bit_num));
-}
-
-void gicd_set_icactiver(uintptr_t base, unsigned int id)
-{
-	unsigned bit_num = id & ((1 << ICACTIVER_SHIFT) - 1);
-
-	gicd_write_icactiver(base, id, (1 << bit_num));
-}
-
-/*
- * Make sure that the interrupt's group is set before expecting
- * this function to do its job correctly.
- */
-void gicd_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri)
-{
-	/*
-	 * Enforce ARM recommendation to manage priority values such
-	 * that group1 interrupts always have a lower priority than
-	 * group0 interrupts.
-	 * Note, lower numerical values are higher priorities so the comparison
-	 * checks below are reversed from what might be expected.
-	 */
-	assert(gicd_get_igroupr(base, id) == GRP1 ?
-		pri >= GIC_HIGHEST_NS_PRIORITY &&
-			pri <= GIC_LOWEST_NS_PRIORITY :
-		pri >= GIC_HIGHEST_SEC_PRIORITY &&
-			pri <= GIC_LOWEST_SEC_PRIORITY);
-
-	mmio_write_8(base + GICD_IPRIORITYR + id, pri & GIC_PRI_MASK);
-}
-
-void gicd_set_itargetsr(uintptr_t base, unsigned int id, unsigned int target)
-{
-	mmio_write_8(base + GICD_ITARGETSR + id, target & GIC_TARGET_CPU_MASK);
-}
-
-/*******************************************************************************
- * This function allows the interrupt management framework to determine (through
- * the platform) which interrupt line (IRQ/FIQ) to use for an interrupt type to
- * route it to EL3. The interrupt line is represented as the bit position of the
- * IRQ or FIQ bit in the SCR_EL3.
- ******************************************************************************/
-uint32_t gicv2_interrupt_type_to_line(uint32_t cpuif_base, uint32_t type)
-{
-	uint32_t gicc_ctlr;
-
-	/* Non-secure interrupts are signalled on the IRQ line always */
-	if (type == INTR_TYPE_NS)
-		return __builtin_ctz(SCR_IRQ_BIT);
-
-	/*
-	 * Secure interrupts are signalled using the IRQ line if the FIQ_EN
-	 * bit is not set else they are signalled using the FIQ line.
-	 */
-	gicc_ctlr = gicc_read_ctlr(cpuif_base);
-	if (gicc_ctlr & FIQ_EN)
-		return __builtin_ctz(SCR_FIQ_BIT);
-	else
-		return __builtin_ctz(SCR_IRQ_BIT);
-}
diff --git a/drivers/arm/gic/gic_v3.c b/drivers/arm/gic/gic_v3.c
deleted file mode 100644
index 5486817..0000000
--- a/drivers/arm/gic/gic_v3.c
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch.h>
-#include <debug.h>
-#include <gic_v3.h>
-
-uintptr_t gicv3_get_rdist(uintptr_t gicr_base, u_register_t mpidr)
-{
-	uint32_t  cpu_aff, gicr_aff;
-	uint64_t  gicr_typer;
-	uintptr_t addr;
-
-	/* Construct the affinity as used by GICv3. MPIDR and GIC affinity level
-	 * mask is the same.
-	 */
-	cpu_aff  = ((mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) <<
-			GICV3_AFF0_SHIFT;
-	cpu_aff |= ((mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) <<
-			GICV3_AFF1_SHIFT;
-	cpu_aff |= ((mpidr >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) <<
-			GICV3_AFF2_SHIFT;
-	cpu_aff |= ((mpidr >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK) <<
-			GICV3_AFF3_SHIFT;
-
-	addr = gicr_base;
-	do {
-		gicr_typer = gicr_read_typer(addr);
-
-		gicr_aff = (gicr_typer >> GICR_TYPER_AFF_SHIFT) &
-				GICR_TYPER_AFF_MASK;
-		if (cpu_aff == gicr_aff) {
-			/* Disable this print for now as it appears every time
-			 * when using PSCI CPU_SUSPEND.
-			 * TODO: Print this only the first time for each CPU.
-			 * INFO("GICv3 - Found RDIST for MPIDR(0x%lx) at %p\n",
-			 *	mpidr, (void *) addr);
-			 */
-			return addr;
-		}
-
-		/* TODO:
-		 * For GICv4 we need to adjust the Base address based on
-		 * GICR_TYPER.VLPIS
-		 */
-		addr += (1 << GICR_PCPUBASE_SHIFT);
-
-	} while (!(gicr_typer & GICR_TYPER_LAST));
-
-	/* If we get here we did not find a match. */
-	ERROR("GICv3 - Did not find RDIST for CPU with MPIDR 0x%lx\n", mpidr);
-	return (uintptr_t)NULL;
-}
diff --git a/drivers/arm/gic/v2/gicv2_helpers.c b/drivers/arm/gic/v2/gicv2_helpers.c
index 221f1b5..bc4c1d1 100644
--- a/drivers/arm/gic/v2/gicv2_helpers.c
+++ b/drivers/arm/gic/v2/gicv2_helpers.c
@@ -114,43 +114,6 @@
 		gicd_write_icfgr(gicd_base, index, 0U);
 }
 
-#if !ERROR_DEPRECATED
-/*******************************************************************************
- * Helper function to configure secure G0 SPIs.
- ******************************************************************************/
-void gicv2_secure_spis_configure(uintptr_t gicd_base,
-				     unsigned int num_ints,
-				     const unsigned int *sec_intr_list)
-{
-	unsigned int index, irq_num;
-
-	/* If `num_ints` is not 0, ensure that `sec_intr_list` is not NULL */
-	if (num_ints != 0U)
-		assert(sec_intr_list != NULL);
-
-	for (index = 0; index < num_ints; index++) {
-		irq_num = sec_intr_list[index];
-		if (irq_num >= MIN_SPI_ID) {
-			/* Configure this interrupt as a secure interrupt */
-			gicd_clr_igroupr(gicd_base, irq_num);
-
-			/* Set the priority of this interrupt */
-			gicd_set_ipriorityr(gicd_base,
-					      irq_num,
-					      GIC_HIGHEST_SEC_PRIORITY);
-
-			/* Target the secure interrupts to primary CPU */
-			gicd_set_itargetsr(gicd_base, irq_num,
-					gicv2_get_cpuif_id(gicd_base));
-
-			/* Enable this interrupt */
-			gicd_set_isenabler(gicd_base, irq_num);
-		}
-	}
-
-}
-#endif
-
 /*******************************************************************************
  * Helper function to configure properties of secure G0 SPIs.
  ******************************************************************************/
@@ -191,56 +154,6 @@
 		gicd_set_isenabler(gicd_base, prop_desc->intr_num);
 	}
 }
-
-#if !ERROR_DEPRECATED
-/*******************************************************************************
- * Helper function to configure secure G0 SGIs and PPIs.
- ******************************************************************************/
-void gicv2_secure_ppi_sgi_setup(uintptr_t gicd_base,
-					unsigned int num_ints,
-					const unsigned int *sec_intr_list)
-{
-	unsigned int index, irq_num, sec_ppi_sgi_mask = 0;
-
-	/* If `num_ints` is not 0, ensure that `sec_intr_list` is not NULL */
-	assert(num_ints ? (uintptr_t)sec_intr_list : 1);
-
-	/*
-	 * Disable all SGIs (imp. def.)/PPIs before configuring them. This is a
-	 * more scalable approach as it avoids clearing the enable bits in the
-	 * GICD_CTLR.
-	 */
-	gicd_write_icenabler(gicd_base, 0, ~0);
-
-	/* Setup the default PPI/SGI priorities doing four at a time */
-	for (index = 0; index < MIN_SPI_ID; index += 4)
-		gicd_write_ipriorityr(gicd_base,
-				      index,
-				      GICD_IPRIORITYR_DEF_VAL);
-
-	for (index = 0; index < num_ints; index++) {
-		irq_num = sec_intr_list[index];
-		if (irq_num < MIN_SPI_ID) {
-			/* We have an SGI or a PPI. They are Group0 at reset */
-			sec_ppi_sgi_mask |= 1U << irq_num;
-
-			/* Set the priority of this interrupt */
-			gicd_set_ipriorityr(gicd_base,
-					    irq_num,
-					    GIC_HIGHEST_SEC_PRIORITY);
-		}
-	}
-
-	/*
-	 * Invert the bitmask to create a mask for non-secure PPIs and
-	 * SGIs. Program the GICD_IGROUPR0 with this bit mask.
-	 */
-	gicd_write_igroupr(gicd_base, 0, ~sec_ppi_sgi_mask);
-
-	/* Enable the Group 0 SGIs and PPIs */
-	gicd_write_isenabler(gicd_base, 0, sec_ppi_sgi_mask);
-}
-#endif
 
 /*******************************************************************************
  * Helper function to configure properties of secure G0 SGIs and PPIs.
diff --git a/drivers/arm/gic/v2/gicv2_main.c b/drivers/arm/gic/v2/gicv2_main.c
index 55897bf..b872905 100644
--- a/drivers/arm/gic/v2/gicv2_main.c
+++ b/drivers/arm/gic/v2/gicv2_main.c
@@ -79,27 +79,9 @@
 	assert(driver_data != NULL);
 	assert(driver_data->gicd_base != 0U);
 
-#if !ERROR_DEPRECATED
-	if (driver_data->interrupt_props != NULL) {
-#endif
-		gicv2_secure_ppi_sgi_setup_props(driver_data->gicd_base,
-				driver_data->interrupt_props,
-				driver_data->interrupt_props_num);
-#if !ERROR_DEPRECATED
-	} else {
-		/*
-		 * Suppress deprecated declaration warnings in compatibility
-		 * function
-		 */
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wdeprecated-declarations"
-		assert(driver_data->g0_interrupt_array);
-		gicv2_secure_ppi_sgi_setup(driver_data->gicd_base,
-				driver_data->g0_interrupt_num,
-				driver_data->g0_interrupt_array);
-#pragma GCC diagnostic pop
-	}
-#endif
+	gicv2_secure_ppi_sgi_setup_props(driver_data->gicd_base,
+			driver_data->interrupt_props,
+			driver_data->interrupt_props_num);
 
 	/* Enable G0 interrupts if not already */
 	ctlr = gicd_read_ctlr(driver_data->gicd_base);
@@ -129,30 +111,10 @@
 	/* Set the default attribute of all SPIs */
 	gicv2_spis_configure_defaults(driver_data->gicd_base);
 
-#if !ERROR_DEPRECATED
-	if (driver_data->interrupt_props != NULL) {
-#endif
-		gicv2_secure_spis_configure_props(driver_data->gicd_base,
-				driver_data->interrupt_props,
-				driver_data->interrupt_props_num);
-#if !ERROR_DEPRECATED
-	} else {
-		/*
-		 * Suppress deprecated declaration warnings in compatibility
-		 * function
-		 */
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wdeprecated-declarations"
-
-		assert(driver_data->g0_interrupt_array);
+	gicv2_secure_spis_configure_props(driver_data->gicd_base,
+			driver_data->interrupt_props,
+			driver_data->interrupt_props_num);
 
-		/* Configure the G0 SPIs */
-		gicv2_secure_spis_configure(driver_data->gicd_base,
-				driver_data->g0_interrupt_num,
-				driver_data->g0_interrupt_array);
-#pragma GCC diagnostic pop
-	}
-#endif
 
 	/* Re-enable the secure SPIs now that they have been configured */
 	gicd_write_ctlr(driver_data->gicd_base, ctlr | CTLR_ENABLE_G0_BIT);
@@ -169,35 +131,8 @@
 	assert(plat_driver_data->gicd_base != 0U);
 	assert(plat_driver_data->gicc_base != 0U);
 
-#if !ERROR_DEPRECATED
-	if (plat_driver_data->interrupt_props == NULL) {
-		/* Interrupt properties array size must be 0 */
-		assert(plat_driver_data->interrupt_props_num == 0);
-
-		/*
-		 * Suppress deprecated declaration warnings in compatibility
-		 * function
-		 */
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wdeprecated-declarations"
-
-		/*
-		 * If there are no interrupts of a particular type, then the
-		 * number of interrupts of that type should be 0 and vice-versa.
-		 */
-		assert(plat_driver_data->g0_interrupt_array ?
-				plat_driver_data->g0_interrupt_num :
-				plat_driver_data->g0_interrupt_num == 0);
-#pragma GCC diagnostic pop
-
-		WARN("Using deprecated integer interrupt array in "
-		     "gicv2_driver_data_t\n");
-		WARN("Please migrate to using an interrupt_prop_t array\n");
-	}
-#else
 	assert(plat_driver_data->interrupt_props_num > 0 ?
 			plat_driver_data->interrupt_props != NULL : 1);
-#endif
 
 	/* Ensure that this is a GICv2 system */
 	gic_version = gicd_read_pidr2(plat_driver_data->gicd_base);
diff --git a/drivers/arm/gic/v2/gicv2_private.h b/drivers/arm/gic/v2/gicv2_private.h
index fadc960..1eb6d9d 100644
--- a/drivers/arm/gic/v2/gicv2_private.h
+++ b/drivers/arm/gic/v2/gicv2_private.h
@@ -15,14 +15,6 @@
  * Private function prototypes
  ******************************************************************************/
 void gicv2_spis_configure_defaults(uintptr_t gicd_base);
-#if !ERROR_DEPRECATED
-void gicv2_secure_spis_configure(uintptr_t gicd_base,
-				     unsigned int num_ints,
-				     const unsigned int *sec_intr_list);
-void gicv2_secure_ppi_sgi_setup(uintptr_t gicd_base,
-					unsigned int num_ints,
-					const unsigned int *sec_intr_list);
-#endif
 void gicv2_secure_spis_configure_props(uintptr_t gicd_base,
 		const interrupt_prop_t *interrupt_props,
 		unsigned int interrupt_props_num);
diff --git a/drivers/arm/gic/v3/gicv3_helpers.c b/drivers/arm/gic/v3/gicv3_helpers.c
index 1953a37..c12a4b6 100644
--- a/drivers/arm/gic/v3/gicv3_helpers.c
+++ b/drivers/arm/gic/v3/gicv3_helpers.c
@@ -377,56 +377,6 @@
 		gicd_write_icfgr(gicd_base, index, 0U);
 }
 
-#if !ERROR_DEPRECATED
-/*******************************************************************************
- * Helper function to configure secure G0 and G1S SPIs.
- ******************************************************************************/
-void gicv3_secure_spis_config(uintptr_t gicd_base,
-				     unsigned int num_ints,
-				     const unsigned int *sec_intr_list,
-				     unsigned int int_grp)
-{
-	unsigned int index, irq_num;
-	unsigned long long gic_affinity_val;
-
-	assert((int_grp == INTR_GROUP1S) || (int_grp == INTR_GROUP0));
-	/* If `num_ints` is not 0, ensure that `sec_intr_list` is not NULL */
-	if (num_ints != 0U)
-		assert(sec_intr_list != NULL);
-
-	for (index = 0U; index < num_ints; index++) {
-		irq_num = sec_intr_list[index];
-		if (irq_num >= MIN_SPI_ID) {
-
-			/* Configure this interrupt as a secure interrupt */
-			gicd_clr_igroupr(gicd_base, irq_num);
-
-			/* Configure this interrupt as G0 or a G1S interrupt */
-			if (int_grp == INTR_GROUP1S)
-				gicd_set_igrpmodr(gicd_base, irq_num);
-			else
-				gicd_clr_igrpmodr(gicd_base, irq_num);
-
-			/* Set the priority of this interrupt */
-			gicd_set_ipriorityr(gicd_base,
-					      irq_num,
-					      GIC_HIGHEST_SEC_PRIORITY);
-
-			/* Target SPIs to the primary CPU */
-			gic_affinity_val =
-				gicd_irouter_val_from_mpidr(read_mpidr(), 0U);
-			gicd_write_irouter(gicd_base,
-					   irq_num,
-					   gic_affinity_val);
-
-			/* Enable this interrupt */
-			gicd_set_isenabler(gicd_base, irq_num);
-		}
-	}
-
-}
-#endif
-
 /*******************************************************************************
  * Helper function to configure properties of secure SPIs
  ******************************************************************************/
@@ -511,47 +461,6 @@
 	/* Configure all PPIs as level triggered by default */
 	gicr_write_icfgr1(gicr_base, 0U);
 }
-
-#if !ERROR_DEPRECATED
-/*******************************************************************************
- * Helper function to configure secure G0 and G1S SPIs.
- ******************************************************************************/
-void gicv3_secure_ppi_sgi_config(uintptr_t gicr_base,
-					unsigned int num_ints,
-					const unsigned int *sec_intr_list,
-					unsigned int int_grp)
-{
-	unsigned int index, irq_num;
-
-	assert((int_grp == INTR_GROUP1S) || (int_grp == INTR_GROUP0));
-	/* If `num_ints` is not 0, ensure that `sec_intr_list` is not NULL */
-	if (num_ints != 0U)
-		assert(sec_intr_list != NULL);
-
-	for (index = 0; index < num_ints; index++) {
-		irq_num = sec_intr_list[index];
-		if (irq_num < MIN_SPI_ID) {
-
-			/* Configure this interrupt as a secure interrupt */
-			gicr_clr_igroupr0(gicr_base, irq_num);
-
-			/* Configure this interrupt as G0 or a G1S interrupt */
-			if (int_grp == INTR_GROUP1S)
-				gicr_set_igrpmodr0(gicr_base, irq_num);
-			else
-				gicr_clr_igrpmodr0(gicr_base, irq_num);
-
-			/* Set the priority of this interrupt */
-			gicr_set_ipriorityr(gicr_base,
-					    irq_num,
-					    GIC_HIGHEST_SEC_PRIORITY);
-
-			/* Enable this interrupt */
-			gicr_set_isenabler0(gicr_base, irq_num);
-		}
-	}
-}
-#endif
 
 /*******************************************************************************
  * Helper function to configure properties of secure G0 and G1S PPIs and SGIs.
diff --git a/drivers/arm/gic/v3/gicv3_main.c b/drivers/arm/gic/v3/gicv3_main.c
index 8da4512..5af7e40 100644
--- a/drivers/arm/gic/v3/gicv3_main.c
+++ b/drivers/arm/gic/v3/gicv3_main.c
@@ -67,45 +67,8 @@
 
 	assert(IS_IN_EL3());
 
-#if !ERROR_DEPRECATED
-	if (plat_driver_data->interrupt_props == NULL) {
-		/* Interrupt properties array size must be 0 */
-		assert(plat_driver_data->interrupt_props_num == 0);
-
-		/*
-		 * Suppress deprecated declaration warnings in compatibility
-		 * function
-		 */
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wdeprecated-declarations"
-
-		/*
-		 * The platform should provide a list of at least one type of
-		 * interrupt.
-		 */
-		assert(plat_driver_data->g0_interrupt_array ||
-				plat_driver_data->g1s_interrupt_array);
-
-		/*
-		 * If there are no interrupts of a particular type, then the
-		 * number of interrupts of that type should be 0 and vice-versa.
-		 */
-		assert(plat_driver_data->g0_interrupt_array ?
-				plat_driver_data->g0_interrupt_num :
-				plat_driver_data->g0_interrupt_num == 0);
-		assert(plat_driver_data->g1s_interrupt_array ?
-				plat_driver_data->g1s_interrupt_num :
-				plat_driver_data->g1s_interrupt_num == 0);
-#pragma GCC diagnostic pop
-
-		WARN("Using deprecated integer interrupt arrays in "
-		     "gicv3_driver_data_t\n");
-		WARN("Please migrate to using interrupt_prop_t arrays\n");
-	}
-#else
 	assert(plat_driver_data->interrupt_props_num > 0 ?
 	       plat_driver_data->interrupt_props != NULL : 1);
-#endif
 
 	/* Check for system register support */
 #ifdef AARCH32
@@ -193,45 +156,10 @@
 	/* Set the default attribute of all SPIs */
 	gicv3_spis_config_defaults(gicv3_driver_data->gicd_base);
 
-#if !ERROR_DEPRECATED
-	if (gicv3_driver_data->interrupt_props != NULL) {
-#endif
-		bitmap = gicv3_secure_spis_config_props(
-				gicv3_driver_data->gicd_base,
-				gicv3_driver_data->interrupt_props,
-				gicv3_driver_data->interrupt_props_num);
-#if !ERROR_DEPRECATED
-	} else {
-		/*
-		 * Suppress deprecated declaration warnings in compatibility
-		 * function
-		 */
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wdeprecated-declarations"
-
-		assert(gicv3_driver_data->g1s_interrupt_array ||
-				gicv3_driver_data->g0_interrupt_array);
-
-		/* Configure the G1S SPIs */
-		if (gicv3_driver_data->g1s_interrupt_array) {
-			gicv3_secure_spis_config(gicv3_driver_data->gicd_base,
-					gicv3_driver_data->g1s_interrupt_num,
-					gicv3_driver_data->g1s_interrupt_array,
-					INTR_GROUP1S);
-			bitmap |= CTLR_ENABLE_G1S_BIT;
-		}
-
-		/* Configure the G0 SPIs */
-		if (gicv3_driver_data->g0_interrupt_array) {
-			gicv3_secure_spis_config(gicv3_driver_data->gicd_base,
-					gicv3_driver_data->g0_interrupt_num,
-					gicv3_driver_data->g0_interrupt_array,
-					INTR_GROUP0);
-			bitmap |= CTLR_ENABLE_G0_BIT;
-		}
-#pragma GCC diagnostic pop
-	}
-#endif
+	bitmap = gicv3_secure_spis_config_props(
+			gicv3_driver_data->gicd_base,
+			gicv3_driver_data->interrupt_props,
+			gicv3_driver_data->interrupt_props_num);
 
 	/* Enable the secure SPIs now that they have been configured */
 	gicd_set_ctlr(gicv3_driver_data->gicd_base, bitmap, RWP_TRUE);
@@ -266,44 +194,9 @@
 	/* Set the default attribute of all SGIs and PPIs */
 	gicv3_ppi_sgi_config_defaults(gicr_base);
 
-#if !ERROR_DEPRECATED
-	if (gicv3_driver_data->interrupt_props != NULL) {
-#endif
-		bitmap = gicv3_secure_ppi_sgi_config_props(gicr_base,
-				gicv3_driver_data->interrupt_props,
-				gicv3_driver_data->interrupt_props_num);
-#if !ERROR_DEPRECATED
-	} else {
-		/*
-		 * Suppress deprecated declaration warnings in compatibility
-		 * function
-		 */
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wdeprecated-declarations"
-
-		assert(gicv3_driver_data->g1s_interrupt_array ||
-		       gicv3_driver_data->g0_interrupt_array);
-
-		/* Configure the G1S SGIs/PPIs */
-		if (gicv3_driver_data->g1s_interrupt_array) {
-			gicv3_secure_ppi_sgi_config(gicr_base,
-					gicv3_driver_data->g1s_interrupt_num,
-					gicv3_driver_data->g1s_interrupt_array,
-					INTR_GROUP1S);
-			bitmap |= CTLR_ENABLE_G1S_BIT;
-		}
-
-		/* Configure the G0 SGIs/PPIs */
-		if (gicv3_driver_data->g0_interrupt_array) {
-			gicv3_secure_ppi_sgi_config(gicr_base,
-					gicv3_driver_data->g0_interrupt_num,
-					gicv3_driver_data->g0_interrupt_array,
-					INTR_GROUP0);
-			bitmap |= CTLR_ENABLE_G0_BIT;
-		}
-#pragma GCC diagnostic pop
-	}
-#endif
+	bitmap = gicv3_secure_ppi_sgi_config_props(gicr_base,
+			gicv3_driver_data->interrupt_props,
+			gicv3_driver_data->interrupt_props_num);
 
 	/* Enable interrupt groups as required, if not already */
 	if ((ctlr & bitmap) != bitmap)
diff --git a/drivers/arm/gic/v3/gicv3_private.h b/drivers/arm/gic/v3/gicv3_private.h
index 36d4b3e..85231ad 100644
--- a/drivers/arm/gic/v3/gicv3_private.h
+++ b/drivers/arm/gic/v3/gicv3_private.h
@@ -95,16 +95,6 @@
  ******************************************************************************/
 void gicv3_spis_config_defaults(uintptr_t gicd_base);
 void gicv3_ppi_sgi_config_defaults(uintptr_t gicr_base);
-#if !ERROR_DEPRECATED
-void gicv3_secure_spis_config(uintptr_t gicd_base,
-				     unsigned int num_ints,
-				     const unsigned int *sec_intr_list,
-				     unsigned int int_grp);
-void gicv3_secure_ppi_sgi_config(uintptr_t gicr_base,
-					unsigned int num_ints,
-					const unsigned int *sec_intr_list,
-					unsigned int int_grp);
-#endif
 unsigned int gicv3_secure_ppi_sgi_config_props(uintptr_t gicr_base,
 		const interrupt_prop_t *interrupt_props,
 		unsigned int interrupt_props_num);