Merge changes from topic "marvell-a3k-separate-flash-and-uart" into integration
* changes:
plat: marvell: armada: a3k: Do not use 'echo -e' in Makefile
docs: marvell: Update info about BOOTDEV=SATA
diff --git a/Makefile b/Makefile
index ceb5a11..1501f46 100644
--- a/Makefile
+++ b/Makefile
@@ -242,6 +242,9 @@
$(info Arm Architecture Features specified: $(subst +, ,$(arch-features)))
endif # arch-features
+# Determine if FEAT_RNG is supported
+ENABLE_FEAT_RNG = $(if $(findstring rng,${arch-features}),1,0)
+
ifneq ($(findstring armclang,$(notdir $(CC))),)
TF_CFLAGS_aarch32 = -target arm-arm-none-eabi $(march32-directive)
TF_CFLAGS_aarch64 = -target aarch64-arm-none-eabi $(march64-directive)
@@ -940,6 +943,7 @@
RAS_TRAP_LOWER_EL_ERR_ACCESS \
COT_DESC_IN_DTB \
USE_SP804_TIMER \
+ ENABLE_FEAT_RNG \
)))
$(eval $(call assert_numerics,\
@@ -1030,6 +1034,7 @@
RAS_TRAP_LOWER_EL_ERR_ACCESS \
COT_DESC_IN_DTB \
USE_SP804_TIMER \
+ ENABLE_FEAT_RNG \
)))
ifeq (${SANITIZE_UB},trap)
diff --git a/docs/about/maintainers.rst b/docs/about/maintainers.rst
index 90aed50..14a3b45 100644
--- a/docs/about/maintainers.rst
+++ b/docs/about/maintainers.rst
@@ -295,6 +295,15 @@
:F: include/drivers/measured_boot
:F: plat/arm/board/fvp/fvp_measured_boot.c
+System Control and Management Interface (SCMI) Server
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+:M: Etienne Carriere <etienne.carriere@st.com>
+:G: `etienne-lms`_
+:M: Peng Fan <peng.fan@nxp.com>
+:G: `MrVan`_
+:F: drivers/scmi-msg
+:F: include/drivers/scmi\*
+
Platform Ports
~~~~~~~~~~~~~~
@@ -636,6 +645,7 @@
.. _masahir0y: https://github.com/masahir0y
.. _michalsimek: https://github.com/michalsimek
.. _mmind: https://github.com/mmind
+.. _MrVan: https://github.com/MrVan
.. _mtk09422: https://github.com/mtk09422
.. _niej: https://github.com/niej
.. _npoushin: https://github.com/npoushin
diff --git a/docs/change-log.rst b/docs/change-log.rst
index 3b8f836..ec88df9 100644
--- a/docs/change-log.rst
+++ b/docs/change-log.rst
@@ -689,10 +689,10 @@
- arm/common: Allow boards to specify second DRAM Base address
and to define PLAT_ARM_TZC_FILTERS
- - arm/cornstone700: Add support for mhuv2 and stack protector
+ - arm/corstone700: Add support for mhuv2 and stack protector
- arm/fvp: Add support for fconf in BL31 and SP_MIN. Populate power
- domain desciptor dynamically by leveraging fconf APIs.
+ domain descriptor dynamically by leveraging fconf APIs.
- arm/fvp: Add Cactus/Ivy Secure Partition information and use two
instances of Cactus at S-EL1
- arm/fvp: Add support to run BL32 in TDRAM and BL31 in secure DRAM
@@ -967,7 +967,7 @@
cpu clock, Move versal_def.h and versal_private to include directory
- Tools
- - sptool: Updated sptool to accomodate building secure partition packages.
+ - sptool: Updated sptool to accommodate building secure partition packages.
Resolved Issues
^^^^^^^^^^^^^^^
diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst
index 16de410..c520e0c 100644
--- a/docs/getting_started/build-options.rst
+++ b/docs/getting_started/build-options.rst
@@ -403,7 +403,7 @@
library is not supported.
- ``INVERTED_MEMMAP``: memmap tool print by default lower addresses at the
- bottom, higher addresses at the top. This buid flag can be set to '1' to
+ bottom, higher addresses at the top. This build flag can be set to '1' to
invert this behavior. Lower addresses will be printed at the top and higher
addresses at the bottom.
@@ -570,7 +570,7 @@
- ``SEPARATE_NOBITS_REGION``: Setting this option to ``1`` allows the NOBITS
sections of BL31 (.bss, stacks, page tables, and coherent memory) to be
allocated in RAM discontiguous from the loaded firmware image. When set, the
- platform is expected to provide definitons for ``BL31_NOBITS_BASE`` and
+ platform is expected to provide definitions for ``BL31_NOBITS_BASE`` and
``BL31_NOBITS_LIMIT``. When the option is ``0`` (the default), NOBITS
sections are placed in RAM immediately following the loaded firmware image.
diff --git a/docs/plat/marvell/armada/misc/mvebu-ccu.rst b/docs/plat/marvell/armada/misc/mvebu-ccu.rst
index 5bac11f..12118e9 100644
--- a/docs/plat/marvell/armada/misc/mvebu-ccu.rst
+++ b/docs/plat/marvell/armada/misc/mvebu-ccu.rst
@@ -1,7 +1,7 @@
Marvell CCU address decoding bindings
=====================================
-CCU configration driver (1st stage address translation) for Marvell Armada 8K and 8K+ SoCs.
+CCU configuration driver (1st stage address translation) for Marvell Armada 8K and 8K+ SoCs.
The CCU node includes a description of the address decoding configuration.
diff --git a/docs/plat/marvell/armada/misc/mvebu-io-win.rst b/docs/plat/marvell/armada/misc/mvebu-io-win.rst
index 52845ca..7498291 100644
--- a/docs/plat/marvell/armada/misc/mvebu-io-win.rst
+++ b/docs/plat/marvell/armada/misc/mvebu-io-win.rst
@@ -1,7 +1,7 @@
Marvell IO WIN address decoding bindings
========================================
-IO Window configration driver (2nd stage address translation) for Marvell Armada 8K and 8K+ SoCs.
+IO Window configuration driver (2nd stage address translation) for Marvell Armada 8K and 8K+ SoCs.
The IO WIN includes a description of the address decoding configuration.
diff --git a/docs/plat/marvell/armada/misc/mvebu-iob.rst b/docs/plat/marvell/armada/misc/mvebu-iob.rst
index d02a7e8..aa41822 100644
--- a/docs/plat/marvell/armada/misc/mvebu-iob.rst
+++ b/docs/plat/marvell/armada/misc/mvebu-iob.rst
@@ -1,7 +1,7 @@
Marvell IOB address decoding bindings
=====================================
-IO bridge configration driver (3rd stage address translation) for Marvell Armada 8K and 8K+ SoCs.
+IO bridge configuration driver (3rd stage address translation) for Marvell Armada 8K and 8K+ SoCs.
The IOB includes a description of the address decoding configuration.
diff --git a/docs/plat/rpi4.rst b/docs/plat/rpi4.rst
index beb0227..6e83fd7 100644
--- a/docs/plat/rpi4.rst
+++ b/docs/plat/rpi4.rst
@@ -60,7 +60,7 @@
run after the SoC gets its power. The on-chip Boot ROM loads the next stage
(bootcode.bin) from flash (EEPROM), which is again GPU code.
This part knows how to access the MMC controller and how to parse a FAT
-filesystem, so it will load further compononents and configuration files
+filesystem, so it will load further components and configuration files
from the first FAT partition on the SD card.
To accommodate this existing way of configuring and setting up the board,
diff --git a/drivers/st/scmi-msg/base.c b/drivers/scmi-msg/base.c
similarity index 98%
rename from drivers/st/scmi-msg/base.c
rename to drivers/scmi-msg/base.c
index e44bc52..2d72034 100644
--- a/drivers/st/scmi-msg/base.c
+++ b/drivers/scmi-msg/base.c
@@ -6,8 +6,8 @@
#include <assert.h>
#include <string.h>
-#include <drivers/st/scmi-msg.h>
-#include <drivers/st/scmi.h>
+#include <drivers/scmi-msg.h>
+#include <drivers/scmi.h>
#include <lib/utils.h>
#include <lib/utils_def.h>
diff --git a/drivers/st/scmi-msg/base.h b/drivers/scmi-msg/base.h
similarity index 100%
rename from drivers/st/scmi-msg/base.h
rename to drivers/scmi-msg/base.h
diff --git a/drivers/st/scmi-msg/clock.c b/drivers/scmi-msg/clock.c
similarity index 99%
rename from drivers/st/scmi-msg/clock.c
rename to drivers/scmi-msg/clock.c
index 319557c..e96cede 100644
--- a/drivers/st/scmi-msg/clock.c
+++ b/drivers/scmi-msg/clock.c
@@ -6,8 +6,8 @@
#include <cdefs.h>
#include <string.h>
-#include <drivers/st/scmi-msg.h>
-#include <drivers/st/scmi.h>
+#include <drivers/scmi-msg.h>
+#include <drivers/scmi.h>
#include <lib/utils_def.h>
#include "common.h"
diff --git a/drivers/st/scmi-msg/clock.h b/drivers/scmi-msg/clock.h
similarity index 100%
rename from drivers/st/scmi-msg/clock.h
rename to drivers/scmi-msg/clock.h
diff --git a/drivers/st/scmi-msg/common.h b/drivers/scmi-msg/common.h
similarity index 100%
rename from drivers/st/scmi-msg/common.h
rename to drivers/scmi-msg/common.h
diff --git a/drivers/st/scmi-msg/entry.c b/drivers/scmi-msg/entry.c
similarity index 95%
rename from drivers/st/scmi-msg/entry.c
rename to drivers/scmi-msg/entry.c
index eefcb31..ea3efa2 100644
--- a/drivers/st/scmi-msg/entry.c
+++ b/drivers/scmi-msg/entry.c
@@ -6,8 +6,8 @@
#include <assert.h>
-#include <drivers/st/scmi-msg.h>
-#include <drivers/st/scmi.h>
+#include <drivers/scmi-msg.h>
+#include <drivers/scmi.h>
#include "common.h"
diff --git a/drivers/st/scmi-msg/reset_domain.c b/drivers/scmi-msg/reset_domain.c
similarity index 98%
rename from drivers/st/scmi-msg/reset_domain.c
rename to drivers/scmi-msg/reset_domain.c
index b477302..76ac47e 100644
--- a/drivers/st/scmi-msg/reset_domain.c
+++ b/drivers/scmi-msg/reset_domain.c
@@ -6,8 +6,8 @@
#include <cdefs.h>
#include <string.h>
-#include <drivers/st/scmi-msg.h>
-#include <drivers/st/scmi.h>
+#include <drivers/scmi-msg.h>
+#include <drivers/scmi.h>
#include <lib/utils.h>
#include <lib/utils_def.h>
diff --git a/drivers/st/scmi-msg/reset_domain.h b/drivers/scmi-msg/reset_domain.h
similarity index 100%
rename from drivers/st/scmi-msg/reset_domain.h
rename to drivers/scmi-msg/reset_domain.h
diff --git a/drivers/st/scmi-msg/smt.c b/drivers/scmi-msg/smt.c
similarity index 98%
rename from drivers/st/scmi-msg/smt.c
rename to drivers/scmi-msg/smt.c
index 2d5cd73..b08ee06 100644
--- a/drivers/st/scmi-msg/smt.c
+++ b/drivers/scmi-msg/smt.c
@@ -8,8 +8,8 @@
#include <stdint.h>
#include <string.h>
-#include <drivers/st/scmi-msg.h>
-#include <drivers/st/scmi.h>
+#include <drivers/scmi-msg.h>
+#include <drivers/scmi.h>
#include <lib/cassert.h>
#include <lib/mmio.h>
#include <lib/spinlock.h>
diff --git a/fdts/morello-fvp.dts b/fdts/morello-fvp.dts
index 699dc23..dda73f1 100644
--- a/fdts/morello-fvp.dts
+++ b/fdts/morello-fvp.dts
@@ -10,7 +10,7 @@
/ {
chosen {
- stdout-path = "soc_uart0:115200n8";
+ stdout-path = "serial0:115200n8";
};
reserved-memory {
diff --git a/fdts/n1sdp-single-chip.dts b/fdts/n1sdp-single-chip.dts
index bd48273..3c091ac 100644
--- a/fdts/n1sdp-single-chip.dts
+++ b/fdts/n1sdp-single-chip.dts
@@ -16,7 +16,7 @@
};
chosen {
- stdout-path = "soc_uart0:115200n8";
+ stdout-path = "serial0:115200n8";
};
/* This configuration assumes that standard setup with two DIMM modules.
diff --git a/fdts/tc0.dts b/fdts/tc0.dts
index 5438474..f1ade19 100644
--- a/fdts/tc0.dts
+++ b/fdts/tc0.dts
@@ -17,7 +17,7 @@
};
chosen {
- stdout-path = "soc_uart0:115200n8";
+ stdout-path = "serial0:115200n8";
};
cpus {
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h
index 09e598a..2cdc7b2 100644
--- a/include/arch/aarch64/arch.h
+++ b/include/arch/aarch64/arch.h
@@ -193,6 +193,10 @@
#define ID_AA64DFR0_MTPMU_MASK ULL(0xf)
#define ID_AA64DFR0_MTPMU_SUPPORTED ULL(1)
+/* ID_AA64ISAR0_EL1 definitions */
+#define ID_AA64ISAR0_RNDR_SHIFT U(60)
+#define ID_AA64ISAR0_RNDR_MASK ULL(0xf)
+
/* ID_AA64ISAR1_EL1 definitions */
#define ID_AA64ISAR1_EL1 S3_0_C0_C6_1
#define ID_AA64ISAR1_GPI_SHIFT U(28)
diff --git a/include/arch/aarch64/arch_features.h b/include/arch/aarch64/arch_features.h
index 6b5d326..671b3dc 100644
--- a/include/arch/aarch64/arch_features.h
+++ b/include/arch/aarch64/arch_features.h
@@ -76,6 +76,12 @@
ID_AA64MMFR0_EL1_ECV_MASK);
}
+static inline bool is_armv8_5_rng_present(void)
+{
+ return ((read_id_aa64isar0_el1() >> ID_AA64ISAR0_RNDR_SHIFT) &
+ ID_AA64ISAR0_RNDR_MASK);
+}
+
/*
* Return MPAM version:
*
diff --git a/include/arch/aarch64/arch_helpers.h b/include/arch/aarch64/arch_helpers.h
index 5d1bc94..7fafafc 100644
--- a/include/arch/aarch64/arch_helpers.h
+++ b/include/arch/aarch64/arch_helpers.h
@@ -245,6 +245,7 @@
DEFINE_SYSREG_RW_FUNCS(par_el1)
DEFINE_SYSREG_READ_FUNC(id_pfr1_el1)
+DEFINE_SYSREG_READ_FUNC(id_aa64isar0_el1)
DEFINE_SYSREG_READ_FUNC(id_aa64isar1_el1)
DEFINE_SYSREG_READ_FUNC(id_aa64pfr0_el1)
DEFINE_SYSREG_READ_FUNC(id_aa64pfr1_el1)
@@ -522,6 +523,10 @@
DEFINE_RENAME_SYSREG_RW_FUNCS(rgsr_el1, RGSR_EL1)
DEFINE_RENAME_SYSREG_RW_FUNCS(gcr_el1, GCR_EL1)
+/* Armv8.5 FEAT_RNG Registers */
+DEFINE_SYSREG_READ_FUNC(rndr)
+DEFINE_SYSREG_READ_FUNC(rndrrs)
+
/* DynamIQ Shared Unit power management */
DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpwrdn_el1, CLUSTERPWRDN_EL1)
diff --git a/include/drivers/st/scmi-msg.h b/include/drivers/scmi-msg.h
similarity index 100%
rename from include/drivers/st/scmi-msg.h
rename to include/drivers/scmi-msg.h
diff --git a/include/drivers/st/scmi.h b/include/drivers/scmi.h
similarity index 100%
rename from include/drivers/st/scmi.h
rename to include/drivers/scmi.h
diff --git a/plat/allwinner/common/sunxi_bl31_setup.c b/plat/allwinner/common/sunxi_bl31_setup.c
index 9c8eaa4..b619b18 100644
--- a/plat/allwinner/common/sunxi_bl31_setup.c
+++ b/plat/allwinner/common/sunxi_bl31_setup.c
@@ -100,9 +100,6 @@
bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX,
DISABLE_ALL_EXCEPTIONS);
SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
-
- /* Turn off all secondary CPUs */
- sunxi_disable_secondary_cpus(read_mpidr());
}
void bl31_plat_arch_setup(void)
diff --git a/plat/allwinner/common/sunxi_pm.c b/plat/allwinner/common/sunxi_pm.c
index e0fa5b3..aa80c52 100644
--- a/plat/allwinner/common/sunxi_pm.c
+++ b/plat/allwinner/common/sunxi_pm.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -37,8 +37,6 @@
#define SYSTEM_PWR_STATE(state) \
((state)->pwr_domain_state[SYSTEM_PWR_LVL])
-#define mpidr_is_valid(mpidr) (plat_core_pos_by_mpidr(mpidr) >= 0)
-
/*
* The addresses for the SCP exception vectors are defined in the or1k
* architecture specification.
@@ -78,9 +76,6 @@
static int sunxi_pwr_domain_on(u_register_t mpidr)
{
- if (mpidr_is_valid(mpidr) == 0)
- return PSCI_E_INTERN_FAIL;
-
if (scpi_available) {
scpi_set_css_power_state(mpidr,
scpi_power_on,
@@ -212,10 +207,11 @@
static int sunxi_validate_ns_entrypoint(uintptr_t ns_entrypoint)
{
/* The non-secure entry point must be in DRAM */
- if (ns_entrypoint >= SUNXI_DRAM_BASE)
- return PSCI_E_SUCCESS;
+ if (ns_entrypoint < SUNXI_DRAM_BASE) {
+ return PSCI_E_INVALID_ADDRESS;
+ }
- return PSCI_E_INVALID_ADDRESS;
+ return PSCI_E_SUCCESS;
}
static void sunxi_get_sys_suspend_power_state(psci_power_state_t *req_state)
@@ -226,29 +222,6 @@
req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE;
}
-static int sunxi_get_node_hw_state(u_register_t mpidr,
- unsigned int power_level)
-{
- unsigned int cluster_state, cpu_state;
- unsigned int cpu = MPIDR_AFFLVL0_VAL(mpidr);
-
- /* SoC power level (always on if PSCI works). */
- if (power_level == SYSTEM_PWR_LVL)
- return HW_ON;
- if (scpi_get_css_power_state(mpidr, &cpu_state, &cluster_state))
- return PSCI_E_NOT_SUPPORTED;
- /* Cluster power level (full power state available). */
- if (power_level == CLUSTER_PWR_LVL) {
- if (cluster_state == scpi_power_on)
- return HW_ON;
- if (cluster_state == scpi_power_retention)
- return HW_STANDBY;
- return HW_OFF;
- }
- /* CPU power level (one bit boolean for on or off). */
- return ((cpu_state & BIT(cpu)) != 0) ? HW_ON : HW_OFF;
-}
-
static plat_psci_ops_t sunxi_psci_ops = {
.cpu_standby = sunxi_cpu_standby,
.pwr_domain_on = sunxi_pwr_domain_on,
@@ -297,7 +270,6 @@
sunxi_psci_ops.pwr_domain_suspend = sunxi_pwr_domain_off;
sunxi_psci_ops.pwr_domain_suspend_finish = sunxi_pwr_domain_on_finish;
sunxi_psci_ops.get_sys_suspend_power_state = sunxi_get_sys_suspend_power_state;
- sunxi_psci_ops.get_node_hw_state = sunxi_get_node_hw_state;
} else {
/* This is only needed when SCPI is unavailable. */
sunxi_psci_ops.pwr_domain_pwr_down_wfi = sunxi_pwr_down_wfi;
diff --git a/plat/qemu/common/qemu_stack_protector.c b/plat/qemu/common/qemu_stack_protector.c
index c226158..15ce3d6 100644
--- a/plat/qemu/common/qemu_stack_protector.c
+++ b/plat/qemu/common/qemu_stack_protector.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,17 +7,25 @@
#include <stdint.h>
#include <arch_helpers.h>
+#include <arch_features.h>
#include <plat/common/platform.h>
#define RANDOM_CANARY_VALUE ((u_register_t) 3288484550995823360ULL)
u_register_t plat_get_stack_protector_canary(void)
{
+#if ENABLE_FEAT_RNG
+ /* Use the RNDR instruction if the CPU supports it */
+ if (is_armv8_5_rng_present()) {
+ return read_rndr();
+ }
+#endif
+
/*
- * Ideally, a random number should be returned instead of the
+ * Ideally, a random number should be returned above. If a random
+ * number generator is not supported, return instead a
* combination of a timer's value and a compile-time constant.
- * As the virt platform does not have any random number generator,
- * this is better than nothing but not necessarily really secure.
+ * This is better than nothing but not necessarily really secure.
*/
return RANDOM_CANARY_VALUE ^ read_cntpct_el0();
}
diff --git a/plat/st/stm32mp1/services/stm32mp1_svc_setup.c b/plat/st/stm32mp1/services/stm32mp1_svc_setup.c
index 49375a6..d4ed445 100644
--- a/plat/st/stm32mp1/services/stm32mp1_svc_setup.c
+++ b/plat/st/stm32mp1/services/stm32mp1_svc_setup.c
@@ -9,7 +9,7 @@
#include <common/debug.h>
#include <common/runtime_svc.h>
-#include <drivers/st/scmi-msg.h>
+#include <drivers/scmi-msg.h>
#include <lib/psci/psci.h>
#include <tools_share/uuid.h>
diff --git a/plat/st/stm32mp1/sp_min/sp_min-stm32mp1.mk b/plat/st/stm32mp1/sp_min/sp_min-stm32mp1.mk
index 8866fb5..4d4820a 100644
--- a/plat/st/stm32mp1/sp_min/sp_min-stm32mp1.mk
+++ b/plat/st/stm32mp1/sp_min/sp_min-stm32mp1.mk
@@ -26,11 +26,11 @@
BL32_SOURCES += plat/common/plat_psci_common.c
# SCMI server drivers
-BL32_SOURCES += drivers/st/scmi-msg/base.c \
- drivers/st/scmi-msg/clock.c \
- drivers/st/scmi-msg/entry.c \
- drivers/st/scmi-msg/reset_domain.c \
- drivers/st/scmi-msg/smt.c
+BL32_SOURCES += drivers/scmi-msg/base.c \
+ drivers/scmi-msg/clock.c \
+ drivers/scmi-msg/entry.c \
+ drivers/scmi-msg/reset_domain.c \
+ drivers/scmi-msg/smt.c
# stm32mp1 specific services
BL32_SOURCES += plat/st/stm32mp1/services/bsec_svc.c \
diff --git a/plat/st/stm32mp1/stm32mp1_scmi.c b/plat/st/stm32mp1/stm32mp1_scmi.c
index 80faf0c..6d60bd4 100644
--- a/plat/st/stm32mp1/stm32mp1_scmi.c
+++ b/plat/st/stm32mp1/stm32mp1_scmi.c
@@ -8,8 +8,8 @@
#include <platform_def.h>
-#include <drivers/st/scmi-msg.h>
-#include <drivers/st/scmi.h>
+#include <drivers/scmi-msg.h>
+#include <drivers/scmi.h>
#include <drivers/st/stm32mp1_clk.h>
#include <drivers/st/stm32mp_reset.h>
#include <dt-bindings/clock/stm32mp1-clks.h>
diff --git a/tools/cert_create/src/main.c b/tools/cert_create/src/main.c
index d5abe49..b39378c 100644
--- a/tools/cert_create/src/main.c
+++ b/tools/cert_create/src/main.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -473,6 +473,11 @@
cert = &certs[i];
+ if (cert->fn == NULL) {
+ /* Certificate not requested. Skip to the next one */
+ continue;
+ }
+
/* Create a new stack of extensions. This stack will be used
* to create the certificate */
CHECK_NULL(sk, sk_X509_EXTENSION_new_null());
@@ -492,7 +497,12 @@
*/
switch (ext->type) {
case EXT_TYPE_NVCOUNTER:
- if (ext->arg) {
+ if (ext->optional && ext->arg == NULL) {
+ /* Skip this NVCounter */
+ continue;
+ } else {
+ /* Checked by `check_cmd_params` */
+ assert(ext->arg != NULL);
nvctr = atoi(ext->arg);
CHECK_NULL(cert_ext, ext_new_nvcounter(ext_nid,
EXT_CRIT, nvctr));
@@ -505,7 +515,7 @@
memset(md, 0x0, SHA512_DIGEST_LENGTH);
} else {
/* Do not include this hash in the certificate */
- break;
+ continue;
}
} else {
/* Calculate the hash of the file */
@@ -534,7 +544,7 @@
}
/* Create certificate. Signed with corresponding key */
- if (cert->fn && !cert_new(hash_alg, cert, VAL_DAYS, 0, sk)) {
+ if (!cert_new(hash_alg, cert, VAL_DAYS, 0, sk)) {
ERROR("Cannot create %s\n", cert->cn);
exit(1);
}