diff --git a/plat/mediatek/mt8183/drivers/spm/spm.c b/plat/mediatek/mt8183/drivers/spm/spm.c
index dcafd55..547af57 100644
--- a/plat/mediatek/mt8183/drivers/spm/spm.c
+++ b/plat/mediatek/mt8183/drivers/spm/spm.c
@@ -12,6 +12,21 @@
 
 DEFINE_BAKERY_LOCK(spm_lock);
 
+/* CLK_SCP_CFG_0 */
+#define SPM_CK_OFF_CONTROL	(0x3FF)
+
+/* CLK_SCP_CFG_1 */
+#define SPM_AXI_26M_SEL		(0x1)
+
+/* AP_PLL_CON3 */
+#define SPM_PLL_CONTROL		(0x7FAAAAF)
+
+/* AP_PLL_CON4 */
+#define SPM_PLL_OUT_OFF_CONTROL	(0xFA0A)
+
+/* AP_PLL_CON6 */
+#define PLL_DLY			(0x20000)
+
 const char *wakeup_src_str[32] = {
 	[0] = "R12_PCM_TIMER",
 	[1] = "R12_SSPM_WDT_EVENT_B",
@@ -324,5 +339,14 @@
 	spm_lock_init();
 	mt_spm_pmic_wrap_set_phase(PMIC_WRAP_PHASE_ALLINONE);
 
+	/* switch ck_off/axi_26m control to SPM */
+	mmio_setbits_32(CLK_SCP_CFG_0, SPM_CK_OFF_CONTROL);
+	mmio_setbits_32(CLK_SCP_CFG_1, SPM_AXI_26M_SEL);
+
+	/* switch PLL/CLKSQ control to SPM */
+	mmio_clrbits_32(AP_PLL_CON3, SPM_PLL_CONTROL);
+	mmio_clrbits_32(AP_PLL_CON4, SPM_PLL_OUT_OFF_CONTROL);
+	mmio_clrbits_32(AP_PLL_CON6, PLL_DLY);
+
 	NOTICE("%s() end\n", __func__);
 }