commit 273a68389b19fe60b1009a589cab4a74eb93f558
author Madhukar Pappireddy <madhukar.pappireddy@arm.com> Thu May 19 21:11:55 2022 +0200
committer TrustedFirmware Code Review <review@review.trustedfirmware.org> Thu May 19 21:11:55 2022 +0200
tree 2dbc7dfc6a86b74289981a5ab0915adb99621956
parent ea3ef9faef61331c1938ca5127f9e3794e13e7ae
parent ea465c12e9be177475eed4683410976a7c71318c

Merge "fix(bl1): invalidate SP in data cache during secure SMC" into integration

bl1/aarch32/bl1_exceptions.S

diff --git a/bl1/aarch32/bl1_exceptions.S b/bl1/aarch32/bl1_exceptions.S
index 493d2ca..4a6815f 100644
--- a/bl1/aarch32/bl1_exceptions.S
+++ b/bl1/aarch32/bl1_exceptions.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -118,6 +118,14 @@
 	mov	r0, #DISABLE_DCACHE
 	bl	enable_mmu_svc_mon
 
+	/*
+	 * Invalidate `smc_ctx_t` in data cache to prevent dirty data being
+	 * used.
+	 */
+	mov	r0, r6
+	mov	r1, #SMC_CTX_SIZE
+	bl	inv_dcache_range
+
 	/* Enable the data cache. */
 	ldcopr	r9, SCTLR
 	orr	r9, r9, #SCTLR_C_BIT