commit | 266e07b504d12954b351a607e4f62abc0218d273 | [log] [tgz] |
---|---|---|
author | Michal Simek <michal.simek@amd.com> | Sat Nov 05 15:39:47 2022 -0700 |
committer | Akshay Belsare <Akshay.Belsare@amd.com> | Wed Nov 09 15:11:30 2022 +0530 |
tree | 7d8fdb1acbd56b9cb477b7c84259fde46d497e21 | |
parent | 51781570ea459476abb121542f18feaceebb892b [diff] |
fix(versal-net): add default values for silicon Add missing default value for silicon. Signed-off-by: Michal Simek <michal.simek@amd.com> Change-Id: Iac7d4db17a29a148298e9e3bd3eb3f74cafe7bc1
diff --git a/plat/xilinx/versal_net/bl31_versal_net_setup.c b/plat/xilinx/versal_net/bl31_versal_net_setup.c index 97080e9..c9942d6 100644 --- a/plat/xilinx/versal_net/bl31_versal_net_setup.c +++ b/plat/xilinx/versal_net/bl31_versal_net_setup.c
@@ -88,6 +88,9 @@ uart_clock = 25000000; break; case VERSAL_NET_SILICON: + cpu_clock = 100000000; + uart_clock = 100000000; + break; default: panic(); }