Merge "fix(nuvoton): fix typo in platform.mk" into integration
diff --git a/Makefile b/Makefile
index 0c35120..8e2fd81 100644
--- a/Makefile
+++ b/Makefile
@@ -768,8 +768,8 @@
ifeq (${AARCH32_SP_MAKE},)
$(error Error: No bl32/${AARCH32_SP}/${AARCH32_SP}.mk located)
endif
- $(info Including ${AARCH32_SP_MAKE})
- include ${AARCH32_SP_MAKE}
+ $(info Including ${AARCH32_SP_MAKE})
+ include ${AARCH32_SP_MAKE}
endif
endif #(ARCH=aarch32)
diff --git a/common/feat_detect.c b/common/feat_detect.c
index 2aa0c5c..a1ffc39 100644
--- a/common/feat_detect.c
+++ b/common/feat_detect.c
@@ -203,7 +203,7 @@
check_feature(ENABLE_FEAT_HCX, read_feat_hcx_id_field(), "HCX", 1, 1);
/* v8.9 features */
- check_feature(ENABLE_FEAT_TCR2, read_feat_tcrx_id_field(),
+ check_feature(ENABLE_FEAT_TCR2, read_feat_tcr2_id_field(),
"TCR2", 1, 1);
check_feature(ENABLE_FEAT_S2PIE, read_feat_s2pie_id_field(),
"S2PIE", 1, 1);
diff --git a/docs/design_documents/rss.rst b/docs/design_documents/rss.rst
index 2ad2ee7..18d5436 100644
--- a/docs/design_documents/rss.rst
+++ b/docs/design_documents/rss.rst
@@ -134,12 +134,10 @@
- ``Delegated attestation``: Query the platform attestation token and derive a
delegated attestation key. More info on the delegated attestation service
in RSS can be found in the ``delegated_attestation_integration_guide`` [4]_ .
-- ``OTP assets management``: RSS provides access for AP to assets in OTP.
- These are keys for image signature verification and non-volatile counters
- for anti-rollback protection. Only RSS has direct access to the OTP. Public
- keys used by AP during the trusted boot process can be requested from RSS.
- Furthermore, AP can request RSS to increase a non-volatile counter. Please
- refer to the ``RSS key management`` [5]_ document for more details.
+- ``OTP assets management``: Public keys used by AP during the trusted boot
+ process can be requested from RSS. Furthermore, AP can request RSS to
+ increase a non-volatile counter. Please refer to the
+ ``RSS key management`` [5]_ document for more details.
Runtime service API
^^^^^^^^^^^^^^^^^^^
@@ -625,6 +623,57 @@
"CCA_PLATFORM_VERIFICATION_SERVICE": "www.trustedfirmware.org"
}
+RSS OTP Assets Management
+-------------------------
+
+RSS provides access for AP to assets in OTP, which include keys for image
+signature verification and non-volatile counters for anti-rollback protection.
+
+Non-Volatile Counter API
+^^^^^^^^^^^^^^^^^^^^^^^^
+
+AP/RSS interface for retrieving and incrementing non-volatile counters API is
+as follows.
+
+Defined here:
+
+- ``include/lib/psa/rss_platform_api.h``
+
+.. code-block:: c
+
+ psa_status_t rss_platform_nv_counter_increment(uint32_t counter_id)
+
+ psa_status_t rss_platform_nv_counter_read(uint32_t counter_id,
+ uint32_t size, uint8_t *val)
+
+Through this service, we can read/increment any of the 3 non-volatile
+counters used on an Arm CCA platform:
+
+- ``Non-volatile counter for CCA firmware (BL2, BL31, RMM).``
+- ``Non-volatile counter for secure firmware.``
+- ``Non-volatile counter for non-secure firmware.``
+
+Public Key API
+^^^^^^^^^^^^^^
+
+AP/RSS interface for reading the ROTPK is as follows.
+
+Defined here:
+
+- ``include/lib/psa/rss_platform_api.h``
+
+.. code-block:: c
+
+ psa_status_t rss_platform_key_read(enum rss_key_id_builtin_t key,
+ uint8_t *data, size_t data_size, size_t *data_length)
+
+Through this service, we can read any of the 3 ROTPKs used on an
+Arm CCA platform:
+
+- ``ROTPK for CCA firmware (BL2, BL31, RMM).``
+- ``ROTPK for secure firmware.``
+- ``ROTPK for non-secure firmware.``
+
References
----------
diff --git a/fdts/morello-soc.dts b/fdts/morello-soc.dts
index 9f996bd..f207c06 100644
--- a/fdts/morello-soc.dts
+++ b/fdts/morello-soc.dts
@@ -35,6 +35,15 @@
device_type = "cpu";
enable-method = "psci";
clocks = <&scmi_dvfs 0>;
+ operating-points = <
+ /* kHz uV */
+ 2600000 925000
+ 2400000 875000
+ 2200000 825000
+ 2000000 775000
+ 1800000 750000
+ >;
+ #cooling-cells = <2>;
};
cpu1: cpu1@100 {
compatible = "arm,armv8";
@@ -42,6 +51,15 @@
device_type = "cpu";
enable-method = "psci";
clocks = <&scmi_dvfs 0>;
+ operating-points = <
+ /* kHz uV */
+ 2600000 925000
+ 2400000 875000
+ 2200000 825000
+ 2000000 775000
+ 1800000 750000
+ >;
+ #cooling-cells = <2>;
};
cpu2: cpu2@10000 {
compatible = "arm,armv8";
@@ -49,6 +67,15 @@
device_type = "cpu";
enable-method = "psci";
clocks = <&scmi_dvfs 1>;
+ operating-points = <
+ /* kHz uV */
+ 2600000 925000
+ 2400000 875000
+ 2200000 825000
+ 2000000 775000
+ 1800000 750000
+ >;
+ #cooling-cells = <2>;
};
cpu3: cpu3@10100 {
compatible = "arm,armv8";
@@ -56,6 +83,15 @@
device_type = "cpu";
enable-method = "psci";
clocks = <&scmi_dvfs 1>;
+ operating-points = <
+ /* kHz uV */
+ 2600000 925000
+ 2400000 875000
+ 2200000 825000
+ 2000000 775000
+ 1800000 750000
+ >;
+ #cooling-cells = <2>;
};
};
@@ -255,6 +291,92 @@
reg = <0x14>;
#clock-cells = <1>;
};
+ scmi_sensor: protocol@15 {
+ reg = <0x15>;
+ #thermal-sensor-cells = <1>;
+ };
+ };
+ };
+
+ thermal-zones {
+ clus0-thermal {
+ polling-delay-passive = <200>; /* ms */
+ polling-delay = <1000>; /* ms */
+
+ thermal-sensors = <&scmi_sensor 0>;
+
+ trips {
+ clus0_alarm: clus0-alarm {
+ temperature = <85000>; /* millicelsius */
+ hysteresis = <1000>; /* millicelsius */
+ type = "passive";
+ };
+ clus0_shutdown: clus0-shutdown {
+ temperature = <90000>; /* millicelsius */
+ hysteresis = <0>; /* millicelsius */
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&clus0_alarm>;
+ cooling-device = <&cpu0 4 4>, <&cpu1 4 4>;
+ };
+ };
+ };
+ clus1-thermal {
+ polling-delay-passive = <200>; /* ms */
+ polling-delay = <1000>; /* ms */
+
+ thermal-sensors = <&scmi_sensor 1>;
+ trips {
+ clus1_alarm: clus1-alarm {
+ temperature = <85000>; /* millicelsius */
+ hysteresis = <1000>; /* millicelsius */
+ type = "passive";
+ };
+ clus1_shutdown: clus1-shutdown {
+ temperature = <90000>; /* millicelsius */
+ hysteresis = <0>; /* millicelsius */
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&clus1_alarm>;
+ cooling-device = <&cpu2 4 4>, <&cpu3 4 4>;
+ };
+ };
+ };
+ sys-thermal {
+ polling-delay-passive = <200>; /* ms */
+ polling-delay = <1000>; /* ms */
+
+ thermal-sensors = <&scmi_sensor 2>;
+ trips {
+ sys_alarm: sys-alarm {
+ temperature = <85000>; /* millicelsius */
+ hysteresis = <1000>; /* millicelsius */
+ type = "passive";
+ };
+ sys_shutdown: sys-shutdown {
+ temperature = <90000>; /* millicelsius */
+ hysteresis = <0>; /* millicelsius */
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&sys_alarm>;
+ cooling-device = <&cpu0 4 4>,
+ <&cpu1 4 4>,
+ <&cpu2 4 4>,
+ <&cpu3 4 4>;
+ };
+ };
};
};
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h
index b19e8af..951f023 100644
--- a/include/arch/aarch64/arch.h
+++ b/include/arch/aarch64/arch.h
@@ -157,6 +157,8 @@
#define DCCSW U(0x2)
#endif
+#define ID_REG_FIELD_MASK ULL(0xf)
+
/* ID_AA64PFR0_EL1 definitions */
#define ID_AA64PFR0_EL0_SHIFT U(0)
#define ID_AA64PFR0_EL1_SHIFT U(4)
@@ -435,6 +437,7 @@
#define ID_AA64PFR1_EL1_SME_SHIFT U(24)
#define ID_AA64PFR1_EL1_SME_MASK ULL(0xf)
+#define ID_AA64PFR1_EL1_SME_WIDTH U(4)
#define ID_AA64PFR1_EL1_SME_NOT_SUPPORTED ULL(0x0)
#define ID_AA64PFR1_EL1_SME_SUPPORTED ULL(0x1)
#define ID_AA64PFR1_EL1_SME2_SUPPORTED ULL(0x2)
diff --git a/include/arch/aarch64/arch_features.h b/include/arch/aarch64/arch_features.h
index 9f11f15..bd41fef 100644
--- a/include/arch/aarch64/arch_features.h
+++ b/include/arch/aarch64/arch_features.h
@@ -13,49 +13,37 @@
#include <common/feat_detect.h>
#define ISOLATE_FIELD(reg, feat) \
- ((unsigned int)(((reg) >> (feat ## _SHIFT)) & (feat ## _MASK)))
+ ((unsigned int)(((reg) >> (feat)) & ID_REG_FIELD_MASK))
-static inline bool is_armv7_gentimer_present(void)
-{
- /* The Generic Timer is always present in an ARMv8-A implementation */
- return true;
+#define CREATE_FEATURE_FUNCS_VER(name, read_func, idvalue, guard) \
+static inline bool is_ ## name ## _supported(void) \
+{ \
+ if ((guard) == FEAT_STATE_DISABLED) { \
+ return false; \
+ } \
+ if ((guard) == FEAT_STATE_ALWAYS) { \
+ return true; \
+ } \
+ return read_func() >= (idvalue); \
}
-static inline unsigned int read_feat_pan_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_PAN);
-}
-
-static inline bool is_feat_pan_supported(void)
-{
- if (ENABLE_FEAT_PAN == FEAT_STATE_DISABLED) {
- return false;
- }
+#define CREATE_FEATURE_FUNCS(name, idreg, idfield, guard) \
+static unsigned int read_ ## name ## _id_field(void) \
+{ \
+ return ISOLATE_FIELD(read_ ## idreg(), idfield); \
+} \
+CREATE_FEATURE_FUNCS_VER(name, read_ ## name ## _id_field, 1U, guard)
- if (ENABLE_FEAT_PAN == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_pan_id_field() != 0U;
-}
-
-static inline unsigned int read_feat_vhe_id_field(void)
+static inline bool is_armv7_gentimer_present(void)
{
- return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_VHE);
+ /* The Generic Timer is always present in an ARMv8-A implementation */
+ return true;
}
-static inline bool is_feat_vhe_supported(void)
-{
- if (ENABLE_FEAT_VHE == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_FEAT_VHE == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_vhe_id_field() != 0U;
-}
+CREATE_FEATURE_FUNCS(feat_pan, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_PAN_SHIFT,
+ ENABLE_FEAT_PAN)
+CREATE_FEATURE_FUNCS(feat_vhe, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_VHE_SHIFT,
+ ENABLE_FEAT_VHE)
static inline bool is_armv8_2_ttcnp_present(void)
{
@@ -107,278 +95,51 @@
ID_AA64PFR1_EL1_MTE_MASK);
}
-static inline unsigned int read_feat_sel2_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_SEL2);
-}
-
-static inline bool is_feat_sel2_supported(void)
-{
- if (ENABLE_FEAT_SEL2 == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_FEAT_SEL2 == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_sel2_id_field() != 0U;
-}
-
-static inline unsigned int read_feat_twed_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_TWED);
-}
-
-static inline bool is_feat_twed_supported(void)
-{
- if (ENABLE_FEAT_TWED == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_FEAT_TWED == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_twed_id_field() != 0U;
-}
-
-static unsigned int read_feat_fgt_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64mmfr0_el1(), ID_AA64MMFR0_EL1_FGT);
-}
-
-static unsigned int read_feat_mte_perm_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64pfr2_el1(), ID_AA64PFR2_EL1_MTEPERM);
-}
-
-static inline bool is_feat_fgt_supported(void)
-{
- if (ENABLE_FEAT_FGT == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_FEAT_FGT == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_fgt_id_field() != 0U;
-}
-
-static inline bool is_feat_mte_perm_supported(void)
-{
- if (ENABLE_FEAT_MTE_PERM == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_FEAT_MTE_PERM == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_mte_perm_id_field() != 0U;
-}
-
-static unsigned int read_feat_ecv_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64mmfr0_el1(), ID_AA64MMFR0_EL1_ECV);
-}
-
-static inline bool is_feat_ecv_supported(void)
-{
- if (ENABLE_FEAT_ECV == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_FEAT_ECV == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_ecv_id_field() != 0U;
-}
-
-static inline bool is_feat_ecv_v2_supported(void)
-{
- if (ENABLE_FEAT_ECV == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_FEAT_ECV == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_ecv_id_field() >= ID_AA64MMFR0_EL1_ECV_SELF_SYNCH;
-}
-
-static unsigned int read_feat_rng_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64isar0_el1(), ID_AA64ISAR0_RNDR);
-}
-
-static inline bool is_feat_rng_supported(void)
-{
- if (ENABLE_FEAT_RNG == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_FEAT_RNG == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_rng_id_field() != 0U;
-}
-
-static unsigned int read_feat_tcrx_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_TCRX);
-}
-
-static inline bool is_feat_tcr2_supported(void)
-{
- if (ENABLE_FEAT_TCR2 == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_FEAT_TCR2 == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_tcrx_id_field() != 0U;
-}
+CREATE_FEATURE_FUNCS(feat_sel2, id_aa64pfr0_el1, ID_AA64PFR0_SEL2_SHIFT,
+ ENABLE_FEAT_SEL2)
+CREATE_FEATURE_FUNCS(feat_twed, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_TWED_SHIFT,
+ ENABLE_FEAT_TWED)
+CREATE_FEATURE_FUNCS(feat_fgt, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_FGT_SHIFT,
+ ENABLE_FEAT_FGT)
+CREATE_FEATURE_FUNCS(feat_mte_perm, id_aa64pfr2_el1,
+ ID_AA64PFR2_EL1_MTEPERM_SHIFT, ENABLE_FEAT_MTE_PERM)
+CREATE_FEATURE_FUNCS(feat_ecv, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_ECV_SHIFT,
+ ENABLE_FEAT_ECV)
+CREATE_FEATURE_FUNCS_VER(feat_ecv_v2, read_feat_ecv_id_field,
+ ID_AA64MMFR0_EL1_ECV_SELF_SYNCH, ENABLE_FEAT_ECV)
-static unsigned int read_feat_s2poe_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_S2POE);
-}
-
-static inline bool is_feat_s2poe_supported(void)
-{
- if (ENABLE_FEAT_S2POE == FEAT_STATE_DISABLED) {
- return false;
- }
+CREATE_FEATURE_FUNCS(feat_rng, id_aa64isar0_el1, ID_AA64ISAR0_RNDR_SHIFT,
+ ENABLE_FEAT_RNG)
+CREATE_FEATURE_FUNCS(feat_tcr2, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_TCRX_SHIFT,
+ ENABLE_FEAT_TCR2)
- if (ENABLE_FEAT_S2POE == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_s2poe_id_field() != 0U;
-}
-
-static unsigned int read_feat_s1poe_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_S1POE);
-}
-
-static inline bool is_feat_s1poe_supported(void)
-{
- if (ENABLE_FEAT_S1POE == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_FEAT_S1POE == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_s1poe_id_field() != 0U;
-}
-
+CREATE_FEATURE_FUNCS(feat_s2poe, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S2POE_SHIFT,
+ ENABLE_FEAT_S2POE)
+CREATE_FEATURE_FUNCS(feat_s1poe, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S1POE_SHIFT,
+ ENABLE_FEAT_S1POE)
static inline bool is_feat_sxpoe_supported(void)
{
return is_feat_s1poe_supported() || is_feat_s2poe_supported();
}
-static unsigned int read_feat_s2pie_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_S2PIE);
-}
-
-static inline bool is_feat_s2pie_supported(void)
-{
- if (ENABLE_FEAT_S2PIE == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_FEAT_S2PIE == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_s2pie_id_field() != 0U;
-}
-
-static unsigned int read_feat_s1pie_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_S1PIE);
-}
-
-static inline bool is_feat_s1pie_supported(void)
-{
- if (ENABLE_FEAT_S1PIE == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_FEAT_S1PIE == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_s1pie_id_field() != 0U;
-}
-
+CREATE_FEATURE_FUNCS(feat_s2pie, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S2PIE_SHIFT,
+ ENABLE_FEAT_S2PIE)
+CREATE_FEATURE_FUNCS(feat_s1pie, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S1PIE_SHIFT,
+ ENABLE_FEAT_S1PIE)
static inline bool is_feat_sxpie_supported(void)
{
return is_feat_s1pie_supported() || is_feat_s2pie_supported();
}
-static unsigned int read_feat_gcs_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_GCS);
-}
-
-static inline bool is_feat_gcs_supported(void)
-{
- if (ENABLE_FEAT_GCS == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_FEAT_GCS == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_gcs_id_field() != 0U;
-}
-
-/*******************************************************************************
- * Functions to identify the presence of the Activity Monitors Extension
- ******************************************************************************/
-static unsigned int read_feat_amu_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_AMU);
-}
-
-static inline bool is_feat_amu_supported(void)
-{
- if (ENABLE_FEAT_AMU == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_FEAT_AMU == FEAT_STATE_ALWAYS) {
- return true;
- }
+/* FEAT_GCS: Guarded Control Stack */
+CREATE_FEATURE_FUNCS(feat_gcs, id_aa64pfr1_el1, ID_AA64PFR1_EL1_GCS_SHIFT,
+ ENABLE_FEAT_GCS)
- return read_feat_amu_id_field() >= ID_AA64PFR0_AMU_V1;
-}
-
-static inline bool is_feat_amuv1p1_supported(void)
-{
- if (ENABLE_FEAT_AMUv1p1 == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_FEAT_AMUv1p1 == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_amu_id_field() >= ID_AA64PFR0_AMU_V1P1;
-}
+/* FEAT_AMU: Activity Monitors Extension */
+CREATE_FEATURE_FUNCS(feat_amu, id_aa64pfr0_el1, ID_AA64PFR0_AMU_SHIFT,
+ ENABLE_FEAT_AMU)
+CREATE_FEATURE_FUNCS_VER(feat_amuv1p1, read_feat_amu_id_field,
+ ID_AA64PFR0_AMU_V1P1, ENABLE_FEAT_AMUv1p1)
/*
* Return MPAM version:
@@ -397,36 +158,12 @@
ID_AA64PFR1_MPAM_FRAC_SHIFT) & ID_AA64PFR1_MPAM_FRAC_MASK));
}
-static inline bool is_feat_mpam_supported(void)
-{
- if (ENABLE_MPAM_FOR_LOWER_ELS == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_MPAM_FOR_LOWER_ELS == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_mpam_version() != 0U;
-}
-
-static inline unsigned int read_feat_hcx_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_HCX);
-}
-
-static inline bool is_feat_hcx_supported(void)
-{
- if (ENABLE_FEAT_HCX == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_FEAT_HCX == FEAT_STATE_ALWAYS) {
- return true;
- }
+CREATE_FEATURE_FUNCS_VER(feat_mpam, read_feat_mpam_version, 1U,
+ ENABLE_MPAM_FOR_LOWER_ELS)
- return read_feat_hcx_id_field() != 0U;
-}
+/* FEAT_HCX: Extended Hypervisor Configuration Register */
+CREATE_FEATURE_FUNCS(feat_hcx, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_HCX_SHIFT,
+ ENABLE_FEAT_HCX)
static inline bool is_feat_rng_trap_present(void)
{
@@ -451,251 +188,60 @@
********************************************************************************/
static inline unsigned int read_feat_sb_id_field(void)
{
- return ISOLATE_FIELD(read_id_aa64isar1_el1(), ID_AA64ISAR1_SB);
-}
-
-/*********************************************************************************
- * Function to identify the presence of FEAT_CSV2_2 (Cache Speculation Variant 2)
- ********************************************************************************/
-static inline unsigned int read_feat_csv2_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_CSV2);
-}
-
-static inline bool is_feat_csv2_2_supported(void)
-{
- if (ENABLE_FEAT_CSV2_2 == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_FEAT_CSV2_2 == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_csv2_id_field() >= ID_AA64PFR0_CSV2_2_SUPPORTED;
-}
-
-/**********************************************************************************
- * Function to identify the presence of FEAT_SPE (Statistical Profiling Extension)
- *********************************************************************************/
-static inline unsigned int read_feat_spe_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_PMS);
-}
-
-static inline bool is_feat_spe_supported(void)
-{
- if (ENABLE_SPE_FOR_NS == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_SPE_FOR_NS == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_spe_id_field() != 0U;
-}
-
-/*******************************************************************************
- * Function to identify the presence of FEAT_SVE (Scalable Vector Extension)
- ******************************************************************************/
-static inline unsigned int read_feat_sve_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_SVE);
-}
-
-static inline bool is_feat_sve_supported(void)
-{
- if (ENABLE_SVE_FOR_NS == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_SVE_FOR_NS == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_sve_id_field() >= ID_AA64PFR0_SVE_SUPPORTED;
-}
-
-static unsigned int read_feat_ras_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_RAS);
-}
-
-static inline bool is_feat_ras_supported(void)
-{
- if (ENABLE_FEAT_RAS == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_FEAT_RAS == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_ras_id_field() != 0U;
-}
-
-static unsigned int read_feat_dit_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_DIT);
-}
-
-static inline bool is_feat_dit_supported(void)
-{
- if (ENABLE_FEAT_DIT == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_FEAT_DIT == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_dit_id_field() != 0U;
-}
-
-static inline unsigned int read_feat_tracever_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_TRACEVER);
-}
-
-static inline bool is_feat_sys_reg_trace_supported(void)
-{
- if (ENABLE_SYS_REG_TRACE_FOR_NS == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_SYS_REG_TRACE_FOR_NS == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_tracever_id_field() != 0U;
-}
-
-/*************************************************************************
- * Function to identify the presence of FEAT_TRF (TraceLift)
- ************************************************************************/
-static inline unsigned int read_feat_trf_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_TRACEFILT);
+ return ISOLATE_FIELD(read_id_aa64isar1_el1(), ID_AA64ISAR1_SB_SHIFT);
}
-static inline bool is_feat_trf_supported(void)
-{
- if (ENABLE_TRF_FOR_NS == FEAT_STATE_DISABLED) {
- return false;
- }
+/* FEAT_CSV2_2: Cache Speculation Variant 2 */
+CREATE_FEATURE_FUNCS(feat_csv2, id_aa64pfr0_el1, ID_AA64PFR0_CSV2_SHIFT, 0)
+CREATE_FEATURE_FUNCS_VER(feat_csv2_2, read_feat_csv2_id_field,
+ ID_AA64PFR0_CSV2_2_SUPPORTED, ENABLE_FEAT_CSV2_2)
- if (ENABLE_TRF_FOR_NS == FEAT_STATE_ALWAYS) {
- return true;
- }
+/* FEAT_SPE: Statistical Profiling Extension */
+CREATE_FEATURE_FUNCS(feat_spe, id_aa64dfr0_el1, ID_AA64DFR0_PMS_SHIFT,
+ ENABLE_SPE_FOR_NS)
- return read_feat_trf_id_field() != 0U;
-}
+/* FEAT_SVE: Scalable Vector Extension */
+CREATE_FEATURE_FUNCS(feat_sve, id_aa64pfr0_el1, ID_AA64PFR0_SVE_SHIFT,
+ ENABLE_SVE_FOR_NS)
-/********************************************************************************
- * Function to identify the presence of FEAT_NV2 (Enhanced Nested Virtualization
- * Support)
- *******************************************************************************/
-static inline unsigned int read_feat_nv_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64mmfr2_el1(), ID_AA64MMFR2_EL1_NV);
-}
+/* FEAT_RAS: Reliability, Accessibility, Serviceability */
+CREATE_FEATURE_FUNCS(feat_ras, id_aa64pfr0_el1,
+ ID_AA64PFR0_RAS_SHIFT, ENABLE_FEAT_RAS)
-static inline bool is_feat_nv2_supported(void)
-{
- if (CTX_INCLUDE_NEVE_REGS == FEAT_STATE_DISABLED) {
- return false;
- }
+/* FEAT_DIT: Data Independent Timing instructions */
+CREATE_FEATURE_FUNCS(feat_dit, id_aa64pfr0_el1,
+ ID_AA64PFR0_DIT_SHIFT, ENABLE_FEAT_DIT)
- if (CTX_INCLUDE_NEVE_REGS == FEAT_STATE_ALWAYS) {
- return true;
- }
+CREATE_FEATURE_FUNCS(feat_sys_reg_trace, id_aa64dfr0_el1,
+ ID_AA64DFR0_TRACEVER_SHIFT, ENABLE_SYS_REG_TRACE_FOR_NS)
- return read_feat_nv_id_field() >= ID_AA64MMFR2_EL1_NV2_SUPPORTED;
-}
+/* FEAT_TRF: TraceFilter */
+CREATE_FEATURE_FUNCS(feat_trf, id_aa64dfr0_el1, ID_AA64DFR0_TRACEFILT_SHIFT,
+ ENABLE_TRF_FOR_NS)
-/*******************************************************************************
- * Function to identify the presence of FEAT_BRBE (Branch Record Buffer
- * Extension)
- ******************************************************************************/
-static inline unsigned int read_feat_brbe_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_BRBE);
-}
+/* FEAT_NV2: Enhanced Nested Virtualization */
+CREATE_FEATURE_FUNCS(feat_nv, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_NV_SHIFT, 0)
+CREATE_FEATURE_FUNCS_VER(feat_nv2, read_feat_nv_id_field,
+ ID_AA64MMFR2_EL1_NV2_SUPPORTED, CTX_INCLUDE_NEVE_REGS)
-static inline bool is_feat_brbe_supported(void)
-{
- if (ENABLE_BRBE_FOR_NS == FEAT_STATE_DISABLED) {
- return false;
- }
+/* FEAT_BRBE: Branch Record Buffer Extension */
+CREATE_FEATURE_FUNCS(feat_brbe, id_aa64dfr0_el1, ID_AA64DFR0_BRBE_SHIFT,
+ ENABLE_BRBE_FOR_NS)
- if (ENABLE_BRBE_FOR_NS == FEAT_STATE_ALWAYS) {
- return true;
- }
+/* FEAT_TRBE: Trace Buffer Extension */
+CREATE_FEATURE_FUNCS(feat_trbe, id_aa64dfr0_el1, ID_AA64DFR0_TRACEBUFFER_SHIFT,
+ ENABLE_TRBE_FOR_NS)
- return read_feat_brbe_id_field() != 0U;
-}
-
-/*******************************************************************************
- * Function to identify the presence of FEAT_TRBE (Trace Buffer Extension)
- ******************************************************************************/
-static inline unsigned int read_feat_trbe_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_TRACEBUFFER);
-}
-
-static inline bool is_feat_trbe_supported(void)
-{
- if (ENABLE_TRBE_FOR_NS == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_TRBE_FOR_NS == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_trbe_id_field() != 0U;
-
-}
-
-/*******************************************************************************
- * Function to identify the presence of FEAT_SMEx (Scalar Matrix Extension)
- ******************************************************************************/
static inline unsigned int read_feat_sme_fa64_id_field(void)
{
- return ISOLATE_FIELD(read_id_aa64smfr0_el1(), ID_AA64SMFR0_EL1_SME_FA64);
+ return ISOLATE_FIELD(read_id_aa64smfr0_el1(),
+ ID_AA64SMFR0_EL1_SME_FA64_SHIFT);
}
-
-static inline unsigned int read_feat_sme_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_SME);
-}
-
-static inline bool is_feat_sme_supported(void)
-{
- if (ENABLE_SME_FOR_NS == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_SME_FOR_NS == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_sme_id_field() >= ID_AA64PFR1_EL1_SME_SUPPORTED;
-}
-
-static inline bool is_feat_sme2_supported(void)
-{
- if (ENABLE_SME2_FOR_NS == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_SME2_FOR_NS == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_sme_id_field() >= ID_AA64PFR1_EL1_SME2_SUPPORTED;
-}
+/* FEAT_SMEx: Scalar Matrix Extension */
+CREATE_FEATURE_FUNCS(feat_sme, id_aa64pfr1_el1, ID_AA64PFR1_EL1_SME_SHIFT,
+ ENABLE_SME_FOR_NS)
+CREATE_FEATURE_FUNCS_VER(feat_sme2, read_feat_sme_id_field,
+ ID_AA64PFR1_EL1_SME2_SUPPORTED, ENABLE_SME2_FOR_NS)
/*******************************************************************************
* Function to get hardware granularity support
@@ -703,29 +249,30 @@
static inline unsigned int read_id_aa64mmfr0_el0_tgran4_field(void)
{
- return ISOLATE_FIELD(read_id_aa64mmfr0_el1(), ID_AA64MMFR0_EL1_TGRAN4);
+ return ISOLATE_FIELD(read_id_aa64mmfr0_el1(),
+ ID_AA64MMFR0_EL1_TGRAN4_SHIFT);
}
static inline unsigned int read_id_aa64mmfr0_el0_tgran16_field(void)
{
return ISOLATE_FIELD(read_id_aa64mmfr0_el1(),
- ID_AA64MMFR0_EL1_TGRAN16);
+ ID_AA64MMFR0_EL1_TGRAN16_SHIFT);
}
static inline unsigned int read_id_aa64mmfr0_el0_tgran64_field(void)
{
return ISOLATE_FIELD(read_id_aa64mmfr0_el1(),
- ID_AA64MMFR0_EL1_TGRAN64);
+ ID_AA64MMFR0_EL1_TGRAN64_SHIFT);
}
static inline unsigned int read_feat_pmuv3_id_field(void)
{
- return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_PMUVER);
+ return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_PMUVER_SHIFT);
}
static inline unsigned int read_feat_mtpmu_id_field(void)
{
- return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_MTPMU);
+ return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_MTPMU_SHIFT);
}
static inline bool is_feat_mtpmu_supported(void)
diff --git a/include/arch/aarch64/arch_helpers.h b/include/arch/aarch64/arch_helpers.h
index 3121079..6fdc7e8 100644
--- a/include/arch/aarch64/arch_helpers.h
+++ b/include/arch/aarch64/arch_helpers.h
@@ -487,6 +487,13 @@
DEFINE_SYSREG_RW_FUNCS(vpidr_el2)
DEFINE_SYSREG_RW_FUNCS(vmpidr_el2)
+DEFINE_SYSREG_RW_FUNCS(hacr_el2)
+DEFINE_SYSREG_RW_FUNCS(hpfar_el2)
+DEFINE_SYSREG_RW_FUNCS(tpidr_el2)
+DEFINE_SYSREG_RW_FUNCS(dbgvcr32_el2)
+DEFINE_RENAME_SYSREG_RW_FUNCS(ich_hcr_el2, ICH_HCR_EL2)
+DEFINE_RENAME_SYSREG_RW_FUNCS(ich_vmcr_el2, ICH_VMCR_EL2)
+
DEFINE_SYSREG_READ_FUNC(isr_el1)
DEFINE_SYSREG_RW_FUNCS(mdcr_el2)
@@ -585,6 +592,7 @@
DEFINE_RENAME_SYSREG_RW_FUNCS(tfsr_el1, TFSR_EL1)
DEFINE_RENAME_SYSREG_RW_FUNCS(rgsr_el1, RGSR_EL1)
DEFINE_RENAME_SYSREG_RW_FUNCS(gcr_el1, GCR_EL1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(tfsr_el2, TFSR_EL2)
/* Armv8.5 FEAT_RNG Registers */
DEFINE_RENAME_SYSREG_READ_FUNC(rndr, RNDR)
diff --git a/include/lib/el3_runtime/aarch64/context.h b/include/lib/el3_runtime/aarch64/context.h
index e6af43e..ebd0e30 100644
--- a/include/lib/el3_runtime/aarch64/context.h
+++ b/include/lib/el3_runtime/aarch64/context.h
@@ -516,15 +516,6 @@
void el1_sysregs_context_save(el1_sysregs_t *regs);
void el1_sysregs_context_restore(el1_sysregs_t *regs);
-#if CTX_INCLUDE_EL2_REGS
-void el2_sysregs_context_save_common(el2_sysregs_t *regs);
-void el2_sysregs_context_restore_common(el2_sysregs_t *regs);
-#if CTX_INCLUDE_MTE_REGS
-void el2_sysregs_context_save_mte(el2_sysregs_t *regs);
-void el2_sysregs_context_restore_mte(el2_sysregs_t *regs);
-#endif /* CTX_INCLUDE_MTE_REGS */
-#endif /* CTX_INCLUDE_EL2_REGS */
-
#if CTX_INCLUDE_FPREGS
void fpregs_context_save(fp_regs_t *regs);
void fpregs_context_restore(fp_regs_t *regs);
diff --git a/lib/cpus/aarch64/cortex_gelas.S b/lib/cpus/aarch64/cortex_gelas.S
index e0d20a9..dc704f2 100644
--- a/lib/cpus/aarch64/cortex_gelas.S
+++ b/lib/cpus/aarch64/cortex_gelas.S
@@ -34,13 +34,20 @@
* ----------------------------------------------------
*/
func cortex_gelas_core_pwr_dwn
+#if ENABLE_SME_FOR_NS
/* ---------------------------------------------------
- * Disable SME
+ * Disable SME if enabled and supported
* ---------------------------------------------------
*/
+ mrs x0, ID_AA64PFR1_EL1
+ ubfx x0, x0, #ID_AA64PFR1_EL1_SME_SHIFT, \
+ #ID_AA64PFR1_EL1_SME_WIDTH
+ cmp x0, #ID_AA64PFR1_EL1_SME_NOT_SUPPORTED
+ b.eq 1f
msr CORTEX_GELAS_SVCRSM, xzr
msr CORTEX_GELAS_SVCRZA, xzr
-
+1:
+#endif
/* ---------------------------------------------------
* Enable CPU power down bit in power control register
* ---------------------------------------------------
diff --git a/lib/el3_runtime/aarch64/context.S b/lib/el3_runtime/aarch64/context.S
index 771fcdc..f47e779 100644
--- a/lib/el3_runtime/aarch64/context.S
+++ b/lib/el3_runtime/aarch64/context.S
@@ -10,15 +10,6 @@
#include <context.h>
#include <el3_common_macros.S>
-#if CTX_INCLUDE_EL2_REGS
- .global el2_sysregs_context_save_common
- .global el2_sysregs_context_restore_common
-#if CTX_INCLUDE_MTE_REGS
- .global el2_sysregs_context_save_mte
- .global el2_sysregs_context_restore_mte
-#endif /* CTX_INCLUDE_MTE_REGS */
-#endif /* CTX_INCLUDE_EL2_REGS */
-
.global el1_sysregs_context_save
.global el1_sysregs_context_restore
#if CTX_INCLUDE_FPREGS
@@ -30,183 +21,6 @@
.global save_and_update_ptw_el1_sys_regs
.global el3_exit
-#if CTX_INCLUDE_EL2_REGS
-
-/* -----------------------------------------------------
- * The following functions strictly follow the AArch64
- * PCS to use x9-x16 (temporary caller-saved registers)
- * to save/restore EL2 system register context.
- * el2_sysregs_context_save/restore_common functions
- * save and restore registers that are common to all
- * configurations. The rest of the functions save and
- * restore EL2 system registers that are present when a
- * particular feature is enabled. All functions assume
- * that 'x0' is pointing to a 'el2_sys_regs' structure
- * where the register context will be saved/restored.
- *
- * The following registers are not added.
- * AMEVCNTVOFF0<n>_EL2
- * AMEVCNTVOFF1<n>_EL2
- * ICH_AP0R<n>_EL2
- * ICH_AP1R<n>_EL2
- * ICH_LR<n>_EL2
- * -----------------------------------------------------
- */
-func el2_sysregs_context_save_common
- mrs x9, actlr_el2
- mrs x10, afsr0_el2
- stp x9, x10, [x0, #CTX_ACTLR_EL2]
-
- mrs x11, afsr1_el2
- mrs x12, amair_el2
- stp x11, x12, [x0, #CTX_AFSR1_EL2]
-
- mrs x13, cnthctl_el2
- mrs x14, cntvoff_el2
- stp x13, x14, [x0, #CTX_CNTHCTL_EL2]
-
- mrs x15, cptr_el2
- str x15, [x0, #CTX_CPTR_EL2]
-
-#if CTX_INCLUDE_AARCH32_REGS
- mrs x16, dbgvcr32_el2
- str x16, [x0, #CTX_DBGVCR32_EL2]
-#endif /* CTX_INCLUDE_AARCH32_REGS */
-
- mrs x9, elr_el2
- mrs x10, esr_el2
- stp x9, x10, [x0, #CTX_ELR_EL2]
-
- mrs x11, far_el2
- mrs x12, hacr_el2
- stp x11, x12, [x0, #CTX_FAR_EL2]
-
- mrs x13, hcr_el2
- mrs x14, hpfar_el2
- stp x13, x14, [x0, #CTX_HCR_EL2]
-
- mrs x15, hstr_el2
- mrs x16, ICC_SRE_EL2
- stp x15, x16, [x0, #CTX_HSTR_EL2]
-
- mrs x9, ICH_HCR_EL2
- mrs x10, ICH_VMCR_EL2
- stp x9, x10, [x0, #CTX_ICH_HCR_EL2]
-
- mrs x11, mair_el2
- mrs x12, mdcr_el2
- stp x11, x12, [x0, #CTX_MAIR_EL2]
-
- mrs x14, sctlr_el2
- str x14, [x0, #CTX_SCTLR_EL2]
-
- mrs x15, spsr_el2
- mrs x16, sp_el2
- stp x15, x16, [x0, #CTX_SPSR_EL2]
-
- mrs x9, tcr_el2
- mrs x10, tpidr_el2
- stp x9, x10, [x0, #CTX_TCR_EL2]
-
- mrs x11, ttbr0_el2
- mrs x12, vbar_el2
- stp x11, x12, [x0, #CTX_TTBR0_EL2]
-
- mrs x13, vmpidr_el2
- mrs x14, vpidr_el2
- stp x13, x14, [x0, #CTX_VMPIDR_EL2]
-
- mrs x15, vtcr_el2
- mrs x16, vttbr_el2
- stp x15, x16, [x0, #CTX_VTCR_EL2]
- ret
-endfunc el2_sysregs_context_save_common
-
-func el2_sysregs_context_restore_common
- ldp x9, x10, [x0, #CTX_ACTLR_EL2]
- msr actlr_el2, x9
- msr afsr0_el2, x10
-
- ldp x11, x12, [x0, #CTX_AFSR1_EL2]
- msr afsr1_el2, x11
- msr amair_el2, x12
-
- ldp x13, x14, [x0, #CTX_CNTHCTL_EL2]
- msr cnthctl_el2, x13
- msr cntvoff_el2, x14
-
- ldr x15, [x0, #CTX_CPTR_EL2]
- msr cptr_el2, x15
-
-#if CTX_INCLUDE_AARCH32_REGS
- ldr x16, [x0, #CTX_DBGVCR32_EL2]
- msr dbgvcr32_el2, x16
-#endif /* CTX_INCLUDE_AARCH32_REGS */
-
- ldp x9, x10, [x0, #CTX_ELR_EL2]
- msr elr_el2, x9
- msr esr_el2, x10
-
- ldp x11, x12, [x0, #CTX_FAR_EL2]
- msr far_el2, x11
- msr hacr_el2, x12
-
- ldp x13, x14, [x0, #CTX_HCR_EL2]
- msr hcr_el2, x13
- msr hpfar_el2, x14
-
- ldp x15, x16, [x0, #CTX_HSTR_EL2]
- msr hstr_el2, x15
- msr ICC_SRE_EL2, x16
-
- ldp x9, x10, [x0, #CTX_ICH_HCR_EL2]
- msr ICH_HCR_EL2, x9
- msr ICH_VMCR_EL2, x10
-
- ldp x11, x12, [x0, #CTX_MAIR_EL2]
- msr mair_el2, x11
- msr mdcr_el2, x12
-
- ldr x14, [x0, #CTX_SCTLR_EL2]
- msr sctlr_el2, x14
-
- ldp x15, x16, [x0, #CTX_SPSR_EL2]
- msr spsr_el2, x15
- msr sp_el2, x16
-
- ldp x9, x10, [x0, #CTX_TCR_EL2]
- msr tcr_el2, x9
- msr tpidr_el2, x10
-
- ldp x11, x12, [x0, #CTX_TTBR0_EL2]
- msr ttbr0_el2, x11
- msr vbar_el2, x12
-
- ldp x13, x14, [x0, #CTX_VMPIDR_EL2]
- msr vmpidr_el2, x13
- msr vpidr_el2, x14
-
- ldp x15, x16, [x0, #CTX_VTCR_EL2]
- msr vtcr_el2, x15
- msr vttbr_el2, x16
- ret
-endfunc el2_sysregs_context_restore_common
-
-#if CTX_INCLUDE_MTE_REGS
-func el2_sysregs_context_save_mte
- mrs x9, TFSR_EL2
- str x9, [x0, #CTX_TFSR_EL2]
- ret
-endfunc el2_sysregs_context_save_mte
-
-func el2_sysregs_context_restore_mte
- ldr x9, [x0, #CTX_TFSR_EL2]
- msr TFSR_EL2, x9
- ret
-endfunc el2_sysregs_context_restore_mte
-#endif /* CTX_INCLUDE_MTE_REGS */
-
-#endif /* CTX_INCLUDE_EL2_REGS */
/* ------------------------------------------------------------------
* The following function strictly follows the AArch64 PCS to use
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index 9d717bb..0ac2d6e 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -971,6 +971,89 @@
}
}
+/* -----------------------------------------------------
+ * The following registers are not added:
+ * AMEVCNTVOFF0<n>_EL2
+ * AMEVCNTVOFF1<n>_EL2
+ * ICH_AP0R<n>_EL2
+ * ICH_AP1R<n>_EL2
+ * ICH_LR<n>_EL2
+ * -----------------------------------------------------
+ */
+static void el2_sysregs_context_save_common(el2_sysregs_t *ctx)
+{
+ write_ctx_reg(ctx, CTX_ACTLR_EL2, read_actlr_el2());
+ write_ctx_reg(ctx, CTX_AFSR0_EL2, read_afsr0_el2());
+ write_ctx_reg(ctx, CTX_AFSR1_EL2, read_afsr1_el2());
+ write_ctx_reg(ctx, CTX_AMAIR_EL2, read_amair_el2());
+ write_ctx_reg(ctx, CTX_CNTHCTL_EL2, read_cnthctl_el2());
+ write_ctx_reg(ctx, CTX_CNTVOFF_EL2, read_cntvoff_el2());
+ write_ctx_reg(ctx, CTX_CPTR_EL2, read_cptr_el2());
+ if (CTX_INCLUDE_AARCH32_REGS) {
+ write_ctx_reg(ctx, CTX_DBGVCR32_EL2, read_dbgvcr32_el2());
+ }
+ write_ctx_reg(ctx, CTX_ELR_EL2, read_elr_el2());
+ write_ctx_reg(ctx, CTX_ESR_EL2, read_esr_el2());
+ write_ctx_reg(ctx, CTX_FAR_EL2, read_far_el2());
+ write_ctx_reg(ctx, CTX_HACR_EL2, read_hacr_el2());
+ write_ctx_reg(ctx, CTX_HCR_EL2, read_hcr_el2());
+ write_ctx_reg(ctx, CTX_HPFAR_EL2, read_hpfar_el2());
+ write_ctx_reg(ctx, CTX_HSTR_EL2, read_hstr_el2());
+ write_ctx_reg(ctx, CTX_ICC_SRE_EL2, read_icc_sre_el2());
+ write_ctx_reg(ctx, CTX_ICH_HCR_EL2, read_ich_hcr_el2());
+ write_ctx_reg(ctx, CTX_ICH_VMCR_EL2, read_ich_vmcr_el2());
+ write_ctx_reg(ctx, CTX_MAIR_EL2, read_mair_el2());
+ write_ctx_reg(ctx, CTX_MDCR_EL2, read_mdcr_el2());
+ write_ctx_reg(ctx, CTX_SCTLR_EL2, read_sctlr_el2());
+ write_ctx_reg(ctx, CTX_SPSR_EL2, read_spsr_el2());
+ write_ctx_reg(ctx, CTX_SP_EL2, read_sp_el2());
+ write_ctx_reg(ctx, CTX_TCR_EL2, read_tcr_el2());
+ write_ctx_reg(ctx, CTX_TPIDR_EL2, read_tpidr_el2());
+ write_ctx_reg(ctx, CTX_TTBR0_EL2, read_ttbr0_el2());
+ write_ctx_reg(ctx, CTX_VBAR_EL2, read_vbar_el2());
+ write_ctx_reg(ctx, CTX_VMPIDR_EL2, read_vmpidr_el2());
+ write_ctx_reg(ctx, CTX_VPIDR_EL2, read_vpidr_el2());
+ write_ctx_reg(ctx, CTX_VTCR_EL2, read_vtcr_el2());
+ write_ctx_reg(ctx, CTX_VTTBR_EL2, read_vttbr_el2());
+}
+
+static void el2_sysregs_context_restore_common(el2_sysregs_t *ctx)
+{
+ write_actlr_el2(read_ctx_reg(ctx, CTX_ACTLR_EL2));
+ write_afsr0_el2(read_ctx_reg(ctx, CTX_AFSR0_EL2));
+ write_afsr1_el2(read_ctx_reg(ctx, CTX_AFSR1_EL2));
+ write_amair_el2(read_ctx_reg(ctx, CTX_AMAIR_EL2));
+ write_cnthctl_el2(read_ctx_reg(ctx, CTX_CNTHCTL_EL2));
+ write_cntvoff_el2(read_ctx_reg(ctx, CTX_CNTVOFF_EL2));
+ write_cptr_el2(read_ctx_reg(ctx, CTX_CPTR_EL2));
+ if (CTX_INCLUDE_AARCH32_REGS) {
+ write_dbgvcr32_el2(read_ctx_reg(ctx, CTX_DBGVCR32_EL2));
+ }
+ write_elr_el2(read_ctx_reg(ctx, CTX_ELR_EL2));
+ write_esr_el2(read_ctx_reg(ctx, CTX_ESR_EL2));
+ write_far_el2(read_ctx_reg(ctx, CTX_FAR_EL2));
+ write_hacr_el2(read_ctx_reg(ctx, CTX_HACR_EL2));
+ write_hcr_el2(read_ctx_reg(ctx, CTX_HCR_EL2));
+ write_hpfar_el2(read_ctx_reg(ctx, CTX_HPFAR_EL2));
+ write_hstr_el2(read_ctx_reg(ctx, CTX_HSTR_EL2));
+ write_icc_sre_el2(read_ctx_reg(ctx, CTX_ICC_SRE_EL2));
+ write_ich_hcr_el2(read_ctx_reg(ctx, CTX_ICH_HCR_EL2));
+ write_ich_vmcr_el2(read_ctx_reg(ctx, CTX_ICH_VMCR_EL2));
+ write_mair_el2(read_ctx_reg(ctx, CTX_MAIR_EL2));
+ write_mdcr_el2(read_ctx_reg(ctx, CTX_MDCR_EL2));
+ write_sctlr_el2(read_ctx_reg(ctx, CTX_SCTLR_EL2));
+ write_spsr_el2(read_ctx_reg(ctx, CTX_SPSR_EL2));
+ write_sp_el2(read_ctx_reg(ctx, CTX_SP_EL2));
+ write_tcr_el2(read_ctx_reg(ctx, CTX_TCR_EL2));
+ write_tpidr_el2(read_ctx_reg(ctx, CTX_TPIDR_EL2));
+ write_ttbr0_el2(read_ctx_reg(ctx, CTX_TTBR0_EL2));
+ write_vbar_el2(read_ctx_reg(ctx, CTX_VBAR_EL2));
+ write_vmpidr_el2(read_ctx_reg(ctx, CTX_VMPIDR_EL2));
+ write_vpidr_el2(read_ctx_reg(ctx, CTX_VPIDR_EL2));
+ write_vtcr_el2(read_ctx_reg(ctx, CTX_VTCR_EL2));
+ write_vttbr_el2(read_ctx_reg(ctx, CTX_VTTBR_EL2));
+}
+
/*******************************************************************************
* Save EL2 sysreg context
******************************************************************************/
@@ -994,7 +1077,7 @@
el2_sysregs_context_save_common(el2_sysregs_ctx);
#if CTX_INCLUDE_MTE_REGS
- el2_sysregs_context_save_mte(el2_sysregs_ctx);
+ write_ctx_reg(el2_sysregs_ctx, CTX_TFSR_EL2, read_tfsr_el2());
#endif
if (is_feat_mpam_supported()) {
el2_sysregs_context_save_mpam(el2_sysregs_ctx);
@@ -1083,7 +1166,7 @@
el2_sysregs_context_restore_common(el2_sysregs_ctx);
#if CTX_INCLUDE_MTE_REGS
- el2_sysregs_context_restore_mte(el2_sysregs_ctx);
+ write_tfsr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TFSR_EL2));
#endif
if (is_feat_mpam_supported()) {
el2_sysregs_context_restore_mpam(el2_sysregs_ctx);
diff --git a/plat/arm/board/a5ds/platform.mk b/plat/arm/board/a5ds/platform.mk
index 6fcf080..3ed7a63 100644
--- a/plat/arm/board/a5ds/platform.mk
+++ b/plat/arm/board/a5ds/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2019-2021, Arm Limited. All rights reserved.
+# Copyright (c) 2019-2023, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -98,6 +98,10 @@
NEED_BL32 := yes
+ifeq (${AARCH32_SP},none)
+ $(error Variable AARCH32_SP has to be set for AArch32)
+endif
+
MULTI_CONSOLE_API := 1
ARM_DISABLE_TRUSTED_WDOG := 1
diff --git a/plat/arm/board/corstone700/platform.mk b/plat/arm/board/corstone700/platform.mk
index 75833f6..d6d3bef 100644
--- a/plat/arm/board/corstone700/platform.mk
+++ b/plat/arm/board/corstone700/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2019-2022, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2019-2023, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -25,6 +25,10 @@
NEED_BL32 := yes
+ifeq (${AARCH32_SP},none)
+ $(error Variable AARCH32_SP has to be set for AArch32)
+endif
+
# Include GICv2 driver files
include drivers/arm/gic/v2/gicv2.mk
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index 6ac4e09..9104838 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -407,10 +407,6 @@
PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_stack_protector.c
endif
-ifeq (${ARCH},aarch32)
- NEED_BL32 := yes
-endif
-
# Enable the dynamic translation tables library.
ifeq ($(filter 1,${RESET_TO_BL2} ${ARM_XLAT_TABLES_LIB_V1}),)
ifeq (${ARCH},aarch32)
diff --git a/plat/arm/board/fvp_ve/platform.mk b/plat/arm/board/fvp_ve/platform.mk
index f7eace8..79cf356 100644
--- a/plat/arm/board/fvp_ve/platform.mk
+++ b/plat/arm/board/fvp_ve/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2019-2021, Arm Limited. All rights reserved.
+# Copyright (c) 2019-2023, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -96,6 +96,10 @@
NEED_BL32 := yes
+ifeq (${AARCH32_SP},none)
+ $(error Variable AARCH32_SP has to be set for AArch32)
+endif
+
# Modification of arm_common.mk
# Process ARM_DISABLE_TRUSTED_WDOG flag
diff --git a/plat/arm/board/juno/platform.mk b/plat/arm/board/juno/platform.mk
index 19091f3..a00bf26 100644
--- a/plat/arm/board/juno/platform.mk
+++ b/plat/arm/board/juno/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2013-2023, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -63,6 +63,10 @@
ifneq (${ARCH}, aarch32)
override BL32_SOURCES =
endif
+else
+ ifeq (${ARCH}, aarch32)
+ $(error JUNO_AARCH32_EL3_RUNTIME has to be enabled to build BL32 for AArch32)
+ endif
endif
ifeq (${ARCH},aarch64)
diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk
index 4914553..41d1b66 100644
--- a/plat/arm/common/arm_common.mk
+++ b/plat/arm/common/arm_common.mk
@@ -6,6 +6,12 @@
include common/fdt_wrappers.mk
+ifeq (${ARCH},aarch32)
+ ifeq (${AARCH32_SP},none)
+ $(error Variable AARCH32_SP has to be set for AArch32)
+ endif
+endif
+
ifeq (${ARCH}, aarch64)
# On ARM standard platorms, the TSP can execute from Trusted SRAM, Trusted
# DRAM (if available) or the TZC secured area of DRAM.
diff --git a/plat/imx/imx7/common/imx7.mk b/plat/imx/imx7/common/imx7.mk
index f4f5bfc..156c55d 100644
--- a/plat/imx/imx7/common/imx7.mk
+++ b/plat/imx/imx7/common/imx7.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -110,3 +110,7 @@
ifeq (${ARCH},aarch64)
$(error Error: AArch64 not supported on i.mx7)
endif
+
+ifeq (${AARCH32_SP}, none)
+ $(error Variable AARCH32_SP has to be set for AArch32)
+endif
diff --git a/plat/mediatek/drivers/emi_mpu/emi_mpu.h b/plat/mediatek/drivers/emi_mpu/emi_mpu.h
index 9c1ebb5..ef7134c 100644
--- a/plat/mediatek/drivers/emi_mpu/emi_mpu.h
+++ b/plat/mediatek/drivers/emi_mpu/emi_mpu.h
@@ -57,9 +57,18 @@
unsigned int apc[EMI_MPU_DGROUP_NUM];
};
+enum MPU_REQ_ORIGIN_ZONE_ID {
+ MPU_REQ_ORIGIN_TEE_ZONE_SVP = 0,
+ MPU_REQ_ORIGIN_TEE_ZONE_TUI = 1,
+ MPU_REQ_ORIGIN_TEE_ZONE_WFD = 2,
+ MPU_REQ_ORIGIN_TEE_ZONE_MAX = 3,
+ MPU_REQ_ORIGIN_ZONE_INVALID = 0x7FFFFFFF,
+};
+
int emi_mpu_init(void);
+int emi_mpu_optee_handler(uint64_t encoded_addr, uint64_t zone_size,
+ uint64_t zone_info);
int emi_mpu_set_protection(struct emi_region_info_t *region_info);
void set_emi_mpu_regions(void);
int set_apu_emi_mpu_region(void);
-
#endif
diff --git a/plat/mediatek/drivers/emi_mpu/emi_mpu_common.c b/plat/mediatek/drivers/emi_mpu/emi_mpu_common.c
index bf77791..7eeadec 100644
--- a/plat/mediatek/drivers/emi_mpu/emi_mpu_common.c
+++ b/plat/mediatek/drivers/emi_mpu/emi_mpu_common.c
@@ -7,6 +7,8 @@
#include <string.h>
#include <common/debug.h>
#include <lib/mmio.h>
+#include <smccc_helpers.h>
+
#include <emi_mpu.h>
#include <lib/mtk_init/mtk_init.h>
#include <mtk_sip_svc.h>
@@ -116,7 +118,10 @@
u_register_t x3, u_register_t x4,
void *handle, struct smccc_res *smccc_ret)
{
- /* TODO: implement emi mpu handler */
+ int ret;
+
+ ret = emi_mpu_optee_handler(x1, x2, x3);
+ SMC_RET2(handle, ret, 0U);
return 0;
}
diff --git a/plat/mediatek/drivers/emi_mpu/mt8188/emi_mpu.c b/plat/mediatek/drivers/emi_mpu/mt8188/emi_mpu.c
index 59ab315..ae1b7ef 100644
--- a/plat/mediatek/drivers/emi_mpu/mt8188/emi_mpu.c
+++ b/plat/mediatek/drivers/emi_mpu/mt8188/emi_mpu.c
@@ -6,6 +6,9 @@
#include <common/debug.h>
#include <emi_mpu.h>
+#include <mtk_sip_svc.h>
+
+#define MPU_PHYSICAL_ADDR_SHIFT_BITS (16)
void set_emi_mpu_regions(void)
{
@@ -29,3 +32,43 @@
return emi_mpu_set_protection(®ion_info);
}
+
+static inline uint64_t get_decoded_phys_addr(uint64_t addr)
+{
+ return (addr << MPU_PHYSICAL_ADDR_SHIFT_BITS);
+}
+
+static inline uint32_t get_decoded_zone_id(uint32_t info)
+{
+ return ((info & 0xFFFF0000) >> MPU_PHYSICAL_ADDR_SHIFT_BITS);
+}
+
+int emi_mpu_optee_handler(uint64_t encoded_addr, uint64_t zone_size,
+ uint64_t zone_info)
+{
+ uint64_t phys_addr = get_decoded_phys_addr(encoded_addr);
+ struct emi_region_info_t region_info;
+ enum MPU_REQ_ORIGIN_ZONE_ID zone_id = get_decoded_zone_id(zone_info);
+
+ INFO("encoded_addr = 0x%lx, zone_size = 0x%lx, zone_info = 0x%lx\n",
+ encoded_addr, zone_size, zone_info);
+
+ if (zone_id != MPU_REQ_ORIGIN_TEE_ZONE_SVP) {
+ ERROR("Invalid param %s, %d\n", __func__, __LINE__);
+ return MTK_SIP_E_INVALID_PARAM;
+ }
+
+ /* SVP DRAM */
+ region_info.start = phys_addr;
+ region_info.end = phys_addr + zone_size;
+ region_info.region = 4;
+ SET_ACCESS_PERMISSION(region_info.apc, 1,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, SEC_RW);
+
+ emi_mpu_set_protection(®ion_info);
+
+ return 0;
+}
\ No newline at end of file
diff --git a/plat/qemu/common/common.mk b/plat/qemu/common/common.mk
new file mode 100644
index 0000000..b8b57d2
--- /dev/null
+++ b/plat/qemu/common/common.mk
@@ -0,0 +1,112 @@
+#
+# Copyright (c) 2023, Linaro Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+include lib/libfdt/libfdt.mk
+include common/fdt_wrappers.mk
+
+PLAT_INCLUDES := -Iinclude/plat/arm/common/ \
+ -I${PLAT_QEMU_COMMON_PATH}/include \
+ -I${PLAT_QEMU_PATH}/include \
+ -Iinclude/common/tbbr
+
+ifeq (${ARCH},aarch32)
+QEMU_CPU_LIBS := lib/cpus/${ARCH}/cortex_a15.S
+else
+QEMU_CPU_LIBS := lib/cpus/aarch64/aem_generic.S \
+ lib/cpus/aarch64/cortex_a53.S \
+ lib/cpus/aarch64/cortex_a57.S \
+ lib/cpus/aarch64/cortex_a72.S \
+ lib/cpus/aarch64/cortex_a76.S \
+ lib/cpus/aarch64/neoverse_n_common.S \
+ lib/cpus/aarch64/neoverse_n1.S \
+ lib/cpus/aarch64/neoverse_v1.S \
+ lib/cpus/aarch64/qemu_max.S
+
+PLAT_INCLUDES += -Iinclude/plat/arm/common/${ARCH}
+endif
+
+PLAT_BL_COMMON_SOURCES := ${PLAT_QEMU_COMMON_PATH}/qemu_common.c \
+ ${PLAT_QEMU_COMMON_PATH}/qemu_console.c \
+ drivers/arm/pl011/${ARCH}/pl011_console.S
+
+include lib/xlat_tables_v2/xlat_tables.mk
+PLAT_BL_COMMON_SOURCES += ${XLAT_TABLES_LIB_SRCS}
+
+ifneq ($(ENABLE_STACK_PROTECTOR), 0)
+ PLAT_BL_COMMON_SOURCES += ${PLAT_QEMU_COMMON_PATH}/qemu_stack_protector.c
+endif
+
+BL1_SOURCES += drivers/io/io_semihosting.c \
+ drivers/io/io_storage.c \
+ drivers/io/io_fip.c \
+ drivers/io/io_memmap.c \
+ lib/semihosting/semihosting.c \
+ lib/semihosting/${ARCH}/semihosting_call.S \
+ ${PLAT_QEMU_COMMON_PATH}/qemu_io_storage.c \
+ ${PLAT_QEMU_COMMON_PATH}/${ARCH}/plat_helpers.S \
+ ${PLAT_QEMU_COMMON_PATH}/qemu_bl1_setup.c \
+ ${QEMU_CPU_LIBS}
+
+BL2_SOURCES += drivers/io/io_semihosting.c \
+ drivers/io/io_storage.c \
+ drivers/io/io_fip.c \
+ drivers/io/io_memmap.c \
+ lib/semihosting/semihosting.c \
+ lib/semihosting/${ARCH}/semihosting_call.S \
+ ${PLAT_QEMU_COMMON_PATH}/qemu_io_storage.c \
+ ${PLAT_QEMU_COMMON_PATH}/${ARCH}/plat_helpers.S \
+ ${PLAT_QEMU_COMMON_PATH}/qemu_bl2_setup.c \
+ ${PLAT_QEMU_COMMON_PATH}/qemu_bl2_mem_params_desc.c \
+ ${PLAT_QEMU_COMMON_PATH}/qemu_image_load.c \
+ common/desc_image_load.c \
+ common/fdt_fixup.c
+
+BL31_SOURCES += ${QEMU_CPU_LIBS} \
+ lib/semihosting/semihosting.c \
+ lib/semihosting/${ARCH}/semihosting_call.S \
+ plat/common/plat_psci_common.c \
+ ${PLAT_QEMU_COMMON_PATH}/aarch64/plat_helpers.S \
+ ${PLAT_QEMU_COMMON_PATH}/qemu_bl31_setup.c \
+ common/fdt_fixup.c \
+ ${QEMU_GIC_SOURCES}
+
+# CPU flag enablement
+ifeq (${ARCH},aarch64)
+
+# Later QEMU versions support SME and SVE.
+# SPM_MM is not compatible with ENABLE_SVE_FOR_NS (build breaks)
+ifeq (${SPM_MM},1)
+ ENABLE_SVE_FOR_NS := 0
+ ENABLE_SME_FOR_NS := 0
+else
+ ENABLE_SVE_FOR_NS := 2
+ ENABLE_SME_FOR_NS := 2
+endif
+
+# QEMU will use the RNDR instruction for the stack protector canary.
+ENABLE_FEAT_RNG := 2
+
+# QEMU 7.2+ has support for FGT and Linux needs it enabled to boot on max
+ENABLE_FEAT_FGT := 2
+
+# Treating this as a memory-constrained port for now
+USE_COHERENT_MEM := 0
+
+# This can be overridden depending on CPU(s) used in the QEMU image
+HW_ASSISTED_COHERENCY := 1
+
+CTX_INCLUDE_AARCH32_REGS := 0
+ifeq (${CTX_INCLUDE_AARCH32_REGS}, 1)
+$(error "This is an AArch64-only port; CTX_INCLUDE_AARCH32_REGS must be disabled")
+endif
+
+# Pointer Authentication sources
+ifeq (${ENABLE_PAUTH}, 1)
+PLAT_BL_COMMON_SOURCES += plat/arm/common/aarch64/arm_pauth.c
+CTX_INCLUDE_PAUTH_REGS := 1
+endif
+
+endif
diff --git a/plat/qemu/qemu/platform.mk b/plat/qemu/qemu/platform.mk
index a10ab65..16e89c1 100644
--- a/plat/qemu/qemu/platform.mk
+++ b/plat/qemu/qemu/platform.mk
@@ -4,6 +4,14 @@
# SPDX-License-Identifier: BSD-3-Clause
#
+PLAT_QEMU_PATH := plat/qemu/qemu
+PLAT_QEMU_COMMON_PATH := plat/qemu/common
+
+SEPARATE_CODE_AND_RODATA := 1
+ENABLE_STACK_PROTECTOR := 0
+
+include plat/qemu/common/common.mk
+
# Use the GICv2 driver on QEMU by default
QEMU_USE_GIC_DRIVER := QEMU_GICV2
@@ -18,17 +26,6 @@
$(eval $(call add_define,ARMV7_SUPPORTS_VFP))
# Qemu expects a BL32 boot stage.
NEED_BL32 := yes
-else
-CTX_INCLUDE_AARCH32_REGS := 0
-ifeq (${CTX_INCLUDE_AARCH32_REGS}, 1)
-$(error "This is an AArch64-only port; CTX_INCLUDE_AARCH32_REGS must be disabled")
-endif
-
-# Treating this as a memory-constrained port for now
-USE_COHERENT_MEM := 0
-
-# This can be overridden depending on CPU(s) used in the QEMU image
-HW_ASSISTED_COHERENCY := 1
endif # ARMv7
ifeq (${SPD},opteed)
@@ -42,42 +39,10 @@
add-lib-optee := yes
endif
-include lib/libfdt/libfdt.mk
-
ifeq ($(NEED_BL32),yes)
$(eval $(call add_define,QEMU_LOAD_BL32))
endif
-PLAT_QEMU_PATH := plat/qemu/qemu
-PLAT_QEMU_COMMON_PATH := plat/qemu/common
-PLAT_INCLUDES := -Iinclude/plat/arm/common/ \
- -I${PLAT_QEMU_COMMON_PATH}/include \
- -I${PLAT_QEMU_PATH}/include \
- -Iinclude/common/tbbr
-
-ifeq (${ARM_ARCH_MAJOR},8)
-PLAT_INCLUDES += -Iinclude/plat/arm/common/${ARCH}
-
-QEMU_CPU_LIBS := lib/cpus/aarch64/aem_generic.S \
- lib/cpus/aarch64/cortex_a53.S \
- lib/cpus/aarch64/cortex_a57.S \
- lib/cpus/aarch64/cortex_a72.S \
- lib/cpus/aarch64/cortex_a76.S \
- lib/cpus/aarch64/neoverse_n_common.S \
- lib/cpus/aarch64/neoverse_n1.S \
- lib/cpus/aarch64/neoverse_v1.S \
- lib/cpus/aarch64/qemu_max.S
-else
-QEMU_CPU_LIBS := lib/cpus/${ARCH}/cortex_a15.S
-endif
-
-PLAT_BL_COMMON_SOURCES := ${PLAT_QEMU_COMMON_PATH}/qemu_common.c \
- ${PLAT_QEMU_COMMON_PATH}/qemu_console.c \
- drivers/arm/pl011/${ARCH}/pl011_console.S
-
-include lib/xlat_tables_v2/xlat_tables.mk
-PLAT_BL_COMMON_SOURCES += ${XLAT_TABLES_LIB_SRCS}
-
ifneq (${TRUSTED_BOARD_BOOT},0)
AUTH_SOURCES := drivers/auth/auth_mod.c \
@@ -150,42 +115,7 @@
include drivers/auth/mbedtls/mbedtls_crypto.mk
endif
-BL1_SOURCES += drivers/io/io_semihosting.c \
- drivers/io/io_storage.c \
- drivers/io/io_fip.c \
- drivers/io/io_memmap.c \
- lib/semihosting/semihosting.c \
- lib/semihosting/${ARCH}/semihosting_call.S \
- ${PLAT_QEMU_COMMON_PATH}/qemu_io_storage.c \
- ${PLAT_QEMU_COMMON_PATH}/${ARCH}/plat_helpers.S \
- ${PLAT_QEMU_COMMON_PATH}/qemu_bl1_setup.c \
- ${QEMU_CPU_LIBS}
-
-ifeq (${ARM_ARCH_MAJOR},8)
-BL1_SOURCES += lib/cpus/${ARCH}/aem_generic.S \
- lib/cpus/${ARCH}/cortex_a53.S \
- lib/cpus/${ARCH}/cortex_a57.S \
- lib/cpus/${ARCH}/cortex_a72.S \
- lib/cpus/${ARCH}/qemu_max.S \
-
-else
-BL1_SOURCES += lib/cpus/${ARCH}/cortex_a15.S
-endif
-
-BL2_SOURCES += drivers/io/io_semihosting.c \
- drivers/io/io_storage.c \
- drivers/io/io_fip.c \
- drivers/io/io_memmap.c \
- lib/semihosting/semihosting.c \
- lib/semihosting/${ARCH}/semihosting_call.S \
- ${PLAT_QEMU_COMMON_PATH}/qemu_io_storage.c \
- ${PLAT_QEMU_COMMON_PATH}/${ARCH}/plat_helpers.S \
- ${PLAT_QEMU_COMMON_PATH}/qemu_bl2_setup.c \
- ${PLAT_QEMU_COMMON_PATH}/qemu_bl2_mem_params_desc.c \
- ${PLAT_QEMU_COMMON_PATH}/qemu_image_load.c \
- common/fdt_fixup.c \
- common/fdt_wrappers.c \
- common/desc_image_load.c \
+BL2_SOURCES += ${FDT_WRAPPERS_SOURCES} \
common/uuid.c
ifeq ($(add-lib-optee),yes)
@@ -218,29 +148,16 @@
$(error "Incorrect GIC driver chosen for QEMU platform")
endif
-ifeq (${ARM_ARCH_MAJOR},8)
-BL31_SOURCES += ${QEMU_CPU_LIBS} \
- lib/semihosting/semihosting.c \
- lib/semihosting/${ARCH}/semihosting_call.S \
- plat/common/plat_psci_common.c \
- drivers/arm/pl061/pl061_gpio.c \
+ifeq (${ARCH},aarch64)
+BL31_SOURCES += drivers/arm/pl061/pl061_gpio.c \
drivers/gpio/gpio.c \
- ${PLAT_QEMU_COMMON_PATH}/qemu_pm.c \
- ${PLAT_QEMU_COMMON_PATH}/topology.c \
- ${PLAT_QEMU_COMMON_PATH}/aarch64/plat_helpers.S \
- ${PLAT_QEMU_COMMON_PATH}/qemu_bl31_setup.c \
- ${QEMU_GIC_SOURCES}
+ ${PLAT_QEMU_COMMON_PATH}/qemu_pm.c \
+ ${PLAT_QEMU_COMMON_PATH}/topology.c
ifeq (${SDEI_SUPPORT}, 1)
BL31_SOURCES += plat/qemu/common/qemu_sdei.c
endif
-# Pointer Authentication sources
-ifeq (${ENABLE_PAUTH}, 1)
-PLAT_BL_COMMON_SOURCES += plat/arm/common/aarch64/arm_pauth.c \
- lib/extensions/pauth/pauth_helpers.S
-endif
-
ifeq (${SPD},spmd)
BL31_SOURCES += plat/common/plat_spmd_manifest.c \
common/uuid.c \
@@ -280,12 +197,6 @@
$(eval $(call TOOL_ADD_PAYLOAD,${QEMU_TOS_FW_CONFIG},--tos-fw-config,${QEMU_TOS_FW_CONFIG}))
endif
-SEPARATE_CODE_AND_RODATA := 1
-ENABLE_STACK_PROTECTOR := 0
-ifneq ($(ENABLE_STACK_PROTECTOR), 0)
- PLAT_BL_COMMON_SOURCES += ${PLAT_QEMU_COMMON_PATH}/qemu_stack_protector.c
-endif
-
BL32_RAM_LOCATION := tdram
ifeq (${BL32_RAM_LOCATION}, tsram)
BL32_RAM_LOCATION_ID = SEC_SRAM_ID
@@ -306,15 +217,6 @@
ARM_PRELOADED_DTB_BASE := PLAT_QEMU_DT_BASE
$(eval $(call add_define,ARM_PRELOADED_DTB_BASE))
-# QEMU will use the RNDR instruction for the stack protector canary.
-ENABLE_FEAT_RNG := 2
-
-# Later QEMU versions support SME and SVE.
-ifneq (${ARCH},aarch32)
- ENABLE_SVE_FOR_NS := 2
- ENABLE_SME_FOR_NS := 2
-endif
-
qemu_fw.bios: bl1 fip
$(ECHO) " DD $@"
$(Q)cp ${BUILD_PLAT}/bl1.bin ${BUILD_PLAT}/$@
diff --git a/plat/qemu/qemu_sbsa/platform.mk b/plat/qemu/qemu_sbsa/platform.mk
index 3dfefd0..4a8df46 100644
--- a/plat/qemu/qemu_sbsa/platform.mk
+++ b/plat/qemu/qemu_sbsa/platform.mk
@@ -4,11 +4,17 @@
# SPDX-License-Identifier: BSD-3-Clause
#
-include common/fdt_wrappers.mk
+PLAT_QEMU_PATH := plat/qemu/qemu_sbsa
+PLAT_QEMU_COMMON_PATH := plat/qemu/common
+
+MULTI_CONSOLE_API := 1
+CRASH_REPORTING := 1
-CRASH_REPORTING := 1
+# Disable the PSCI platform compatibility layer
+ENABLE_PLAT_COMPAT := 0
-include lib/libfdt/libfdt.mk
+SEPARATE_CODE_AND_RODATA := 1
+ENABLE_STACK_PROTECTOR := 0
ifeq (${SPM_MM},1)
NEED_BL32 := yes
@@ -16,75 +22,16 @@
GICV2_G0_FOR_EL3 := 1
endif
+include plat/qemu/common/common.mk
+
# Enable new version of image loading on QEMU platforms
LOAD_IMAGE_V2 := 1
-CTX_INCLUDE_AARCH32_REGS := 0
-ifeq (${CTX_INCLUDE_AARCH32_REGS}, 1)
-$(error "This is an AArch64-only port; CTX_INCLUDE_AARCH32_REGS must be disabled")
-endif
-
ifeq ($(NEED_BL32),yes)
$(eval $(call add_define,QEMU_LOAD_BL32))
endif
-PLAT_QEMU_PATH := plat/qemu/qemu_sbsa
-PLAT_QEMU_COMMON_PATH := plat/qemu/common
-PLAT_INCLUDES := -Iinclude/plat/arm/common/ \
- -I${PLAT_QEMU_COMMON_PATH}/include \
- -I${PLAT_QEMU_PATH}/include \
- -Iinclude/common/tbbr
-
-PLAT_INCLUDES += -Iinclude/plat/arm/common/${ARCH}
-
-PLAT_BL_COMMON_SOURCES := ${PLAT_QEMU_COMMON_PATH}/qemu_common.c \
- ${PLAT_QEMU_COMMON_PATH}/qemu_console.c \
- drivers/arm/pl011/${ARCH}/pl011_console.S
-
-# Treating this as a memory-constrained port for now
-USE_COHERENT_MEM := 0
-
-# This can be overridden depending on CPU(s) used in the QEMU image
-HW_ASSISTED_COHERENCY := 1
-
-QEMU_CPU_LIBS := lib/cpus/aarch64/cortex_a57.S \
- lib/cpus/aarch64/cortex_a72.S \
- lib/cpus/aarch64/neoverse_n_common.S \
- lib/cpus/aarch64/neoverse_n1.S \
- lib/cpus/aarch64/neoverse_v1.S \
- lib/cpus/aarch64/qemu_max.S
-
-include lib/xlat_tables_v2/xlat_tables.mk
-PLAT_BL_COMMON_SOURCES += ${XLAT_TABLES_LIB_SRCS}
-
-BL1_SOURCES += drivers/io/io_semihosting.c \
- drivers/io/io_storage.c \
- drivers/io/io_fip.c \
- drivers/io/io_memmap.c \
- lib/semihosting/semihosting.c \
- lib/semihosting/${ARCH}/semihosting_call.S \
- ${PLAT_QEMU_COMMON_PATH}/qemu_io_storage.c \
- ${PLAT_QEMU_COMMON_PATH}/${ARCH}/plat_helpers.S \
- ${PLAT_QEMU_COMMON_PATH}/qemu_bl1_setup.c
-
-BL1_SOURCES += ${QEMU_CPU_LIBS}
-
-BL2_SOURCES += drivers/io/io_semihosting.c \
- drivers/io/io_storage.c \
- drivers/io/io_fip.c \
- drivers/io/io_memmap.c \
- lib/semihosting/semihosting.c \
- lib/semihosting/${ARCH}/semihosting_call.S \
- ${PLAT_QEMU_COMMON_PATH}/qemu_io_storage.c \
- ${PLAT_QEMU_COMMON_PATH}/${ARCH}/plat_helpers.S \
- ${PLAT_QEMU_COMMON_PATH}/qemu_bl2_setup.c \
- common/fdt_fixup.c \
- $(LIBFDT_SRCS)
-ifeq (${LOAD_IMAGE_V2},1)
-BL2_SOURCES += ${PLAT_QEMU_COMMON_PATH}/qemu_bl2_mem_params_desc.c \
- ${PLAT_QEMU_COMMON_PATH}/qemu_image_load.c \
- common/desc_image_load.c
-endif
+BL2_SOURCES += $(LIBFDT_SRCS)
# Include GICv3 driver files
include drivers/arm/gic/v3/gicv3.mk
@@ -92,18 +39,10 @@
QEMU_GIC_SOURCES := ${GICV3_SOURCES} \
plat/common/plat_gicv3.c
-BL31_SOURCES += ${QEMU_CPU_LIBS} \
- lib/semihosting/semihosting.c \
- lib/semihosting/${ARCH}/semihosting_call.S \
- plat/common/plat_psci_common.c \
- ${PLAT_QEMU_PATH}/sbsa_gic.c \
+BL31_SOURCES += ${PLAT_QEMU_PATH}/sbsa_gic.c \
${PLAT_QEMU_PATH}/sbsa_pm.c \
${PLAT_QEMU_PATH}/sbsa_sip_svc.c \
- ${PLAT_QEMU_PATH}/sbsa_topology.c \
- ${PLAT_QEMU_COMMON_PATH}/aarch64/plat_helpers.S \
- ${PLAT_QEMU_COMMON_PATH}/qemu_bl31_setup.c \
- common/fdt_fixup.c \
- ${QEMU_GIC_SOURCES}
+ ${PLAT_QEMU_PATH}/sbsa_topology.c
BL31_SOURCES += ${FDT_WRAPPERS_SOURCES}
@@ -111,17 +50,6 @@
BL31_SOURCES += ${PLAT_QEMU_COMMON_PATH}/qemu_spm.c
endif
-SEPARATE_CODE_AND_RODATA := 1
-ENABLE_STACK_PROTECTOR := 0
-ifneq ($(ENABLE_STACK_PROTECTOR), 0)
- PLAT_BL_COMMON_SOURCES += ${PLAT_QEMU_COMMON_PATH}/qemu_stack_protector.c
-endif
-
-MULTI_CONSOLE_API := 1
-
-# Disable the PSCI platform compatibility layer
-ENABLE_PLAT_COMPAT := 0
-
# Use known base for UEFI if not given from command line
# By default BL33 is at FLASH1 base
PRELOADED_BL33_BASE ?= 0x10000000
@@ -137,10 +65,3 @@
ARM_PRELOADED_DTB_BASE := PLAT_QEMU_DT_BASE
$(eval $(call add_define,ARM_PRELOADED_DTB_BASE))
-
-# Later QEMU versions support SME and SVE.
-ENABLE_SVE_FOR_NS := 2
-ENABLE_SME_FOR_NS := 2
-
-# QEMU 7.2+ has support for FGT and Linux needs it enabled to boot on max
-ENABLE_FEAT_FGT := 2
diff --git a/plat/qti/msm8916/platform.mk b/plat/qti/msm8916/platform.mk
index 4f4dcb4..c71ad94 100644
--- a/plat/qti/msm8916/platform.mk
+++ b/plat/qti/msm8916/platform.mk
@@ -75,11 +75,14 @@
PRELOADED_BL33_BASE ?= 0x8f600000
ifeq (${ARCH},aarch64)
-BL32_BASE ?= BL31_LIMIT
-$(eval $(call add_define,BL31_BASE))
+ BL32_BASE ?= BL31_LIMIT
+ $(eval $(call add_define,BL31_BASE))
else
-# There is no BL31 on aarch32, so reuse its location for BL32
-BL32_BASE ?= $(BL31_BASE)
+ ifeq (${AARCH32_SP},none)
+ $(error Variable AARCH32_SP has to be set for AArch32)
+ endif
+ # There is no BL31 on aarch32, so reuse its location for BL32
+ BL32_BASE ?= $(BL31_BASE)
endif
$(eval $(call add_define,BL32_BASE))
diff --git a/plat/rockchip/rk3288/platform.mk b/plat/rockchip/rk3288/platform.mk
index b8dd195..e6f78cf 100644
--- a/plat/rockchip/rk3288/platform.mk
+++ b/plat/rockchip/rk3288/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -67,3 +67,7 @@
ENABLE_SVE_FOR_NS := 0
WORKAROUND_CVE_2017_5715 := 0
+
+ifeq (${AARCH32_SP}, none)
+ $(error Variable AARCH32_SP has to be set for AArch32)
+endif
diff --git a/plat/xilinx/versal_net/pm_service/pm_client.c b/plat/xilinx/versal_net/pm_service/pm_client.c
index 626611c..cff400c 100644
--- a/plat/xilinx/versal_net/pm_service/pm_client.c
+++ b/plat/xilinx/versal_net/pm_service/pm_client.c
@@ -321,15 +321,9 @@
isb();
- /* Clear power down interrupt status before enabling */
- mmio_write_32(APU_PCIL_CORE_X_ISR_POWER_REG(cpu_id),
- APU_PCIL_CORE_X_ISR_POWER_MASK);
/* Enable power down interrupt */
mmio_write_32(APU_PCIL_CORE_X_IEN_POWER_REG(cpu_id),
APU_PCIL_CORE_X_IEN_POWER_MASK);
- /* Clear wakeup interrupt status before enabling */
- mmio_write_32(APU_PCIL_CORE_X_ISR_WAKE_REG(cpu_id),
- APU_PCIL_CORE_X_ISR_WAKE_MASK);
/* Enable wake interrupt */
mmio_write_32(APU_PCIL_CORE_X_IEN_WAKE_REG(cpu_id),
APU_PCIL_CORE_X_IEN_WAKE_MASK);
@@ -383,9 +377,6 @@
/* Disabled power down interrupt */
mmio_write_32(APU_PCIL_CORE_X_IDS_POWER_REG(cpuid),
APU_PCIL_CORE_X_IDS_POWER_MASK);
- /* Clear wakeup interrupt status before disabling */
- mmio_write_32(APU_PCIL_CORE_X_ISR_WAKE_REG(cpuid),
- APU_PCIL_CORE_X_ISR_WAKE_MASK);
/* Disable wake interrupt */
mmio_write_32(APU_PCIL_CORE_X_IDS_WAKE_REG(cpuid),
APU_PCIL_CORE_X_IDS_WAKE_MASK);
diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_clock.c b/plat/xilinx/zynqmp/pm_service/pm_api_clock.c
index 2041541..9682e59 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_api_clock.c
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_clock.c
@@ -2458,7 +2458,7 @@
if (clock_id == CLK_MAX) {
memcpy(name, END_OF_CLK, sizeof(END_OF_CLK) > CLK_NAME_LEN ?
CLK_NAME_LEN : sizeof(END_OF_CLK));
- } else if (!pm_clock_valid(clock_id)) {
+ } else if ((clock_id > CLK_MAX) || (!pm_clock_valid(clock_id))) {
memset(name, 0, CLK_NAME_LEN);
} else if (clock_id < CLK_MAX_OUTPUT_CLK) {
memcpy(name, clocks[clock_id].name, CLK_NAME_LEN);