diff --git a/drivers/staging/renesas/rcar/pfc/E3/pfc_init_e3.c b/drivers/staging/renesas/rcar/pfc/E3/pfc_init_e3.c
index a81a419..c939c22 100644
--- a/drivers/staging/renesas/rcar/pfc/E3/pfc_init_e3.c
+++ b/drivers/staging/renesas/rcar/pfc/E3/pfc_init_e3.c
@@ -11,140 +11,140 @@
 #include "../pfc_regs.h"
 
 /* PFC */
-#define GPSR0_SDA4		((uint32_t)1U << 17U)
-#define GPSR0_SCL4		((uint32_t)1U << 16U)
-#define GPSR0_D15		((uint32_t)1U << 15U)
-#define GPSR0_D14		((uint32_t)1U << 14U)
-#define GPSR0_D13		((uint32_t)1U << 13U)
-#define GPSR0_D12		((uint32_t)1U << 12U)
-#define GPSR0_D11		((uint32_t)1U << 11U)
-#define GPSR0_D10		((uint32_t)1U << 10U)
-#define GPSR0_D9		((uint32_t)1U << 9U)
-#define GPSR0_D8		((uint32_t)1U << 8U)
-#define GPSR0_D7		((uint32_t)1U << 7U)
-#define GPSR0_D6		((uint32_t)1U << 6U)
-#define GPSR0_D5		((uint32_t)1U << 5U)
-#define GPSR0_D4		((uint32_t)1U << 4U)
-#define GPSR0_D3		((uint32_t)1U << 3U)
-#define GPSR0_D2		((uint32_t)1U << 2U)
-#define GPSR0_D1		((uint32_t)1U << 1U)
-#define GPSR0_D0		((uint32_t)1U << 0U)
-#define GPSR1_WE0		((uint32_t)1U << 22U)
-#define GPSR1_CS0		((uint32_t)1U << 21U)
-#define GPSR1_CLKOUT		((uint32_t)1U << 20U)
-#define GPSR1_A19		((uint32_t)1U << 19U)
-#define GPSR1_A18		((uint32_t)1U << 18U)
-#define GPSR1_A17		((uint32_t)1U << 17U)
-#define GPSR1_A16		((uint32_t)1U << 16U)
-#define GPSR1_A15		((uint32_t)1U << 15U)
-#define GPSR1_A14		((uint32_t)1U << 14U)
-#define GPSR1_A13		((uint32_t)1U << 13U)
-#define GPSR1_A12		((uint32_t)1U << 12U)
-#define GPSR1_A11		((uint32_t)1U << 11U)
-#define GPSR1_A10		((uint32_t)1U << 10U)
-#define GPSR1_A9		((uint32_t)1U << 9U)
-#define GPSR1_A8		((uint32_t)1U << 8U)
-#define GPSR1_A7		((uint32_t)1U << 7U)
-#define GPSR1_A6		((uint32_t)1U << 6U)
-#define GPSR1_A5		((uint32_t)1U << 5U)
-#define GPSR1_A4		((uint32_t)1U << 4U)
-#define GPSR1_A3		((uint32_t)1U << 3U)
-#define GPSR1_A2		((uint32_t)1U << 2U)
-#define GPSR1_A1		((uint32_t)1U << 1U)
-#define GPSR1_A0		((uint32_t)1U << 0U)
-#define GPSR2_BIT27_REVERCED 	((uint32_t)1U << 27U)
-#define GPSR2_BIT26_REVERCED 	((uint32_t)1U << 26U)
-#define GPSR2_EX_WAIT0		((uint32_t)1U << 25U)
-#define GPSR2_RD_WR		((uint32_t)1U << 24U)
-#define GPSR2_RD		((uint32_t)1U << 23U)
-#define GPSR2_BS		((uint32_t)1U << 22U)
-#define GPSR2_AVB_PHY_INT	((uint32_t)1U << 21U)
-#define GPSR2_AVB_TXCREFCLK	((uint32_t)1U << 20U)
-#define GPSR2_AVB_RD3		((uint32_t)1U << 19U)
-#define GPSR2_AVB_RD2		((uint32_t)1U << 18U)
-#define GPSR2_AVB_RD1		((uint32_t)1U << 17U)
-#define GPSR2_AVB_RD0		((uint32_t)1U << 16U)
-#define GPSR2_AVB_RXC		((uint32_t)1U << 15U)
-#define GPSR2_AVB_RX_CTL	((uint32_t)1U << 14U)
-#define GPSR2_RPC_RESET		((uint32_t)1U << 13U)
-#define GPSR2_RPC_RPC_INT	((uint32_t)1U << 12U)
-#define GPSR2_QSPI1_SSL		((uint32_t)1U << 11U)
-#define GPSR2_QSPI1_IO3		((uint32_t)1U << 10U)
-#define GPSR2_QSPI1_IO2		((uint32_t)1U << 9U)
-#define GPSR2_QSPI1_MISO_IO1	((uint32_t)1U << 8U)
-#define GPSR2_QSPI1_MOSI_IO0	((uint32_t)1U << 7U)
-#define GPSR2_QSPI1_SPCLK	((uint32_t)1U << 6U)
-#define GPSR2_QSPI0_SSL		((uint32_t)1U << 5U)
-#define GPSR2_QSPI0_IO3		((uint32_t)1U << 4U)
-#define GPSR2_QSPI0_IO2		((uint32_t)1U << 3U)
-#define GPSR2_QSPI0_MISO_IO1	((uint32_t)1U << 2U)
-#define GPSR2_QSPI0_MOSI_IO0	((uint32_t)1U << 1U)
-#define GPSR2_QSPI0_SPCLK	((uint32_t)1U << 0U)
-#define GPSR3_SD1_WP		((uint32_t)1U << 15U)
-#define GPSR3_SD1_CD		((uint32_t)1U << 14U)
-#define GPSR3_SD0_WP		((uint32_t)1U << 13U)
-#define GPSR3_SD0_CD		((uint32_t)1U << 12U)
-#define GPSR3_SD1_DAT3		((uint32_t)1U << 11U)
-#define GPSR3_SD1_DAT2		((uint32_t)1U << 10U)
-#define GPSR3_SD1_DAT1		((uint32_t)1U << 9U)
-#define GPSR3_SD1_DAT0		((uint32_t)1U << 8U)
-#define GPSR3_SD1_CMD		((uint32_t)1U << 7U)
-#define GPSR3_SD1_CLK		((uint32_t)1U << 6U)
-#define GPSR3_SD0_DAT3		((uint32_t)1U << 5U)
-#define GPSR3_SD0_DAT2		((uint32_t)1U << 4U)
-#define GPSR3_SD0_DAT1		((uint32_t)1U << 3U)
-#define GPSR3_SD0_DAT0		((uint32_t)1U << 2U)
-#define GPSR3_SD0_CMD		((uint32_t)1U << 1U)
-#define GPSR3_SD0_CLK		((uint32_t)1U << 0U)
-#define GPSR4_SD3_DS		((uint32_t)1U << 10U)
-#define GPSR4_SD3_DAT7		((uint32_t)1U << 9U)
-#define GPSR4_SD3_DAT6		((uint32_t)1U << 8U)
-#define GPSR4_SD3_DAT5		((uint32_t)1U << 7U)
-#define GPSR4_SD3_DAT4		((uint32_t)1U << 6U)
-#define GPSR4_SD3_DAT3		((uint32_t)1U << 5U)
-#define GPSR4_SD3_DAT2		((uint32_t)1U << 4U)
-#define GPSR4_SD3_DAT1		((uint32_t)1U << 3U)
-#define GPSR4_SD3_DAT0		((uint32_t)1U << 2U)
-#define GPSR4_SD3_CMD		((uint32_t)1U << 1U)
-#define GPSR4_SD3_CLK		((uint32_t)1U << 0U)
-#define GPSR5_MLB_DAT		((uint32_t)1U << 19U)
-#define GPSR5_MLB_SIG		((uint32_t)1U << 18U)
-#define GPSR5_MLB_CLK		((uint32_t)1U << 17U)
-#define GPSR5_SSI_SDATA9	((uint32_t)1U << 16U)
-#define GPSR5_MSIOF0_SS2	((uint32_t)1U << 15U)
-#define GPSR5_MSIOF0_SS1	((uint32_t)1U << 14U)
-#define GPSR5_MSIOF0_SYNC	((uint32_t)1U << 13U)
-#define GPSR5_MSIOF0_TXD	((uint32_t)1U << 12U)
-#define GPSR5_MSIOF0_RXD	((uint32_t)1U << 11U)
-#define GPSR5_MSIOF0_SCK	((uint32_t)1U << 10U)
-#define GPSR5_RX2_A		((uint32_t)1U << 9U)
-#define GPSR5_TX2_A		((uint32_t)1U << 8U)
-#define GPSR5_SCK2_A		((uint32_t)1U << 7U)
-#define GPSR5_TX1		((uint32_t)1U << 6U)
-#define GPSR5_RX1		((uint32_t)1U << 5U)
-#define GPSR5_RTS0_TANS_A	((uint32_t)1U << 4U)
-#define GPSR5_CTS0_A		((uint32_t)1U << 3U)
-#define GPSR5_TX0_A		((uint32_t)1U << 2U)
-#define GPSR5_RX0_A		((uint32_t)1U << 1U)
-#define GPSR5_SCK0_A		((uint32_t)1U << 0U)
-#define GPSR6_USB30_PWEN	((uint32_t)1U << 17U)
-#define GPSR6_SSI_SDATA6	((uint32_t)1U << 16U)
-#define GPSR6_SSI_WS6		((uint32_t)1U << 15U)
-#define GPSR6_SSI_SCK6		((uint32_t)1U << 14U)
-#define GPSR6_SSI_SDATA5	((uint32_t)1U << 13U)
-#define GPSR6_SSI_WS5		((uint32_t)1U << 12U)
-#define GPSR6_SSI_SCK5		((uint32_t)1U << 11U)
-#define GPSR6_SSI_SDATA4	((uint32_t)1U << 10U)
-#define GPSR6_USB30_OVC		((uint32_t)1U << 9U)
-#define GPSR6_AUDIO_CLKA	((uint32_t)1U << 8U)
-#define GPSR6_SSI_SDATA3	((uint32_t)1U << 7U)
-#define GPSR6_SSI_WS349		((uint32_t)1U << 6U)
-#define GPSR6_SSI_SCK349	((uint32_t)1U << 5U)
-#define GPSR6_SSI_SDATA2	((uint32_t)1U << 4U)
-#define GPSR6_SSI_SDATA1	((uint32_t)1U << 3U)
-#define GPSR6_SSI_SDATA0	((uint32_t)1U << 2U)
-#define GPSR6_SSI_WS01239	((uint32_t)1U << 1U)
-#define GPSR6_SSI_SCK01239	((uint32_t)1U << 0U)
+#define GPSR0_SDA4		BIT(17)
+#define GPSR0_SCL4		BIT(16)
+#define GPSR0_D15		BIT(15)
+#define GPSR0_D14		BIT(14)
+#define GPSR0_D13		BIT(13)
+#define GPSR0_D12		BIT(12)
+#define GPSR0_D11		BIT(11)
+#define GPSR0_D10		BIT(10)
+#define GPSR0_D9		BIT(9)
+#define GPSR0_D8		BIT(8)
+#define GPSR0_D7		BIT(7)
+#define GPSR0_D6		BIT(6)
+#define GPSR0_D5		BIT(5)
+#define GPSR0_D4		BIT(4)
+#define GPSR0_D3		BIT(3)
+#define GPSR0_D2		BIT(2)
+#define GPSR0_D1		BIT(1)
+#define GPSR0_D0		BIT(0)
+#define GPSR1_WE0		BIT(22)
+#define GPSR1_CS0		BIT(21)
+#define GPSR1_CLKOUT		BIT(20)
+#define GPSR1_A19		BIT(19)
+#define GPSR1_A18		BIT(18)
+#define GPSR1_A17		BIT(17)
+#define GPSR1_A16		BIT(16)
+#define GPSR1_A15		BIT(15)
+#define GPSR1_A14		BIT(14)
+#define GPSR1_A13		BIT(13)
+#define GPSR1_A12		BIT(12)
+#define GPSR1_A11		BIT(11)
+#define GPSR1_A10		BIT(10)
+#define GPSR1_A9		BIT(9)
+#define GPSR1_A8		BIT(8)
+#define GPSR1_A7		BIT(7)
+#define GPSR1_A6		BIT(6)
+#define GPSR1_A5		BIT(5)
+#define GPSR1_A4		BIT(4)
+#define GPSR1_A3		BIT(3)
+#define GPSR1_A2		BIT(2)
+#define GPSR1_A1		BIT(1)
+#define GPSR1_A0		BIT(0)
+#define GPSR2_BIT27_REVERCED	BIT(27)
+#define GPSR2_BIT26_REVERCED	BIT(26)
+#define GPSR2_EX_WAIT0		BIT(25)
+#define GPSR2_RD_WR		BIT(24)
+#define GPSR2_RD		BIT(23)
+#define GPSR2_BS		BIT(22)
+#define GPSR2_AVB_PHY_INT	BIT(21)
+#define GPSR2_AVB_TXCREFCLK	BIT(20)
+#define GPSR2_AVB_RD3		BIT(19)
+#define GPSR2_AVB_RD2		BIT(18)
+#define GPSR2_AVB_RD1		BIT(17)
+#define GPSR2_AVB_RD0		BIT(16)
+#define GPSR2_AVB_RXC		BIT(15)
+#define GPSR2_AVB_RX_CTL	BIT(14)
+#define GPSR2_RPC_RESET		BIT(13)
+#define GPSR2_RPC_RPC_INT	BIT(12)
+#define GPSR2_QSPI1_SSL		BIT(11)
+#define GPSR2_QSPI1_IO3		BIT(10)
+#define GPSR2_QSPI1_IO2		BIT(9)
+#define GPSR2_QSPI1_MISO_IO1	BIT(8)
+#define GPSR2_QSPI1_MOSI_IO0	BIT(7)
+#define GPSR2_QSPI1_SPCLK	BIT(6)
+#define GPSR2_QSPI0_SSL		BIT(5)
+#define GPSR2_QSPI0_IO3		BIT(4)
+#define GPSR2_QSPI0_IO2		BIT(3)
+#define GPSR2_QSPI0_MISO_IO1	BIT(2)
+#define GPSR2_QSPI0_MOSI_IO0	BIT(1)
+#define GPSR2_QSPI0_SPCLK	BIT(0)
+#define GPSR3_SD1_WP		BIT(15)
+#define GPSR3_SD1_CD		BIT(14)
+#define GPSR3_SD0_WP		BIT(13)
+#define GPSR3_SD0_CD		BIT(12)
+#define GPSR3_SD1_DAT3		BIT(11)
+#define GPSR3_SD1_DAT2		BIT(10)
+#define GPSR3_SD1_DAT1		BIT(9)
+#define GPSR3_SD1_DAT0		BIT(8)
+#define GPSR3_SD1_CMD		BIT(7)
+#define GPSR3_SD1_CLK		BIT(6)
+#define GPSR3_SD0_DAT3		BIT(5)
+#define GPSR3_SD0_DAT2		BIT(4)
+#define GPSR3_SD0_DAT1		BIT(3)
+#define GPSR3_SD0_DAT0		BIT(2)
+#define GPSR3_SD0_CMD		BIT(1)
+#define GPSR3_SD0_CLK		BIT(0)
+#define GPSR4_SD3_DS		BIT(10)
+#define GPSR4_SD3_DAT7		BIT(9)
+#define GPSR4_SD3_DAT6		BIT(8)
+#define GPSR4_SD3_DAT5		BIT(7)
+#define GPSR4_SD3_DAT4		BIT(6)
+#define GPSR4_SD3_DAT3		BIT(5)
+#define GPSR4_SD3_DAT2		BIT(4)
+#define GPSR4_SD3_DAT1		BIT(3)
+#define GPSR4_SD3_DAT0		BIT(2)
+#define GPSR4_SD3_CMD		BIT(1)
+#define GPSR4_SD3_CLK		BIT(0)
+#define GPSR5_MLB_DAT		BIT(19)
+#define GPSR5_MLB_SIG		BIT(18)
+#define GPSR5_MLB_CLK		BIT(17)
+#define GPSR5_SSI_SDATA9	BIT(16)
+#define GPSR5_MSIOF0_SS2	BIT(15)
+#define GPSR5_MSIOF0_SS1	BIT(14)
+#define GPSR5_MSIOF0_SYNC	BIT(13)
+#define GPSR5_MSIOF0_TXD	BIT(12)
+#define GPSR5_MSIOF0_RXD	BIT(11)
+#define GPSR5_MSIOF0_SCK	BIT(10)
+#define GPSR5_RX2_A		BIT(9)
+#define GPSR5_TX2_A		BIT(8)
+#define GPSR5_SCK2_A		BIT(7)
+#define GPSR5_TX1		BIT(6)
+#define GPSR5_RX1		BIT(5)
+#define GPSR5_RTS0_TANS_A	BIT(4)
+#define GPSR5_CTS0_A		BIT(3)
+#define GPSR5_TX0_A		BIT(2)
+#define GPSR5_RX0_A		BIT(1)
+#define GPSR5_SCK0_A		BIT(0)
+#define GPSR6_USB30_PWEN	BIT(17)
+#define GPSR6_SSI_SDATA6	BIT(16)
+#define GPSR6_SSI_WS6		BIT(15)
+#define GPSR6_SSI_SCK6		BIT(14)
+#define GPSR6_SSI_SDATA5	BIT(13)
+#define GPSR6_SSI_WS5		BIT(12)
+#define GPSR6_SSI_SCK5		BIT(11)
+#define GPSR6_SSI_SDATA4	BIT(10)
+#define GPSR6_USB30_OVC		BIT(9)
+#define GPSR6_AUDIO_CLKA	BIT(8)
+#define GPSR6_SSI_SDATA3	BIT(7)
+#define GPSR6_SSI_WS349		BIT(6)
+#define GPSR6_SSI_SCK349	BIT(5)
+#define GPSR6_SSI_SDATA2	BIT(4)
+#define GPSR6_SSI_SDATA1	BIT(3)
+#define GPSR6_SSI_SDATA0	BIT(2)
+#define GPSR6_SSI_WS01239	BIT(1)
+#define GPSR6_SSI_SCK01239	BIT(0)
 
 #define IPSR_28_FUNC(x)		((uint32_t)(x) << 28U)
 #define IPSR_24_FUNC(x)		((uint32_t)(x) << 24U)
@@ -156,32 +156,32 @@
 #define IPSR_0_FUNC(x)		((uint32_t)(x) << 0U)
 
 #define IOCTRL30_MASK		(0x0007F000U)
-#define POC_SD3_DS_33V		((uint32_t)1U << 29U)
-#define POC_SD3_DAT7_33V	((uint32_t)1U << 28U)
-#define POC_SD3_DAT6_33V	((uint32_t)1U << 27U)
-#define POC_SD3_DAT5_33V	((uint32_t)1U << 26U)
-#define POC_SD3_DAT4_33V	((uint32_t)1U << 25U)
-#define POC_SD3_DAT3_33V	((uint32_t)1U << 24U)
-#define POC_SD3_DAT2_33V	((uint32_t)1U << 23U)
-#define POC_SD3_DAT1_33V	((uint32_t)1U << 22U)
-#define POC_SD3_DAT0_33V	((uint32_t)1U << 21U)
-#define POC_SD3_CMD_33V		((uint32_t)1U << 20U)
-#define POC_SD3_CLK_33V		((uint32_t)1U << 19U)
-#define POC_SD1_DAT3_33V	((uint32_t)1U << 11U)
-#define POC_SD1_DAT2_33V	((uint32_t)1U << 10U)
-#define POC_SD1_DAT1_33V	((uint32_t)1U << 9U)
-#define POC_SD1_DAT0_33V	((uint32_t)1U << 8U)
-#define POC_SD1_CMD_33V		((uint32_t)1U << 7U)
-#define POC_SD1_CLK_33V		((uint32_t)1U << 6U)
-#define POC_SD0_DAT3_33V	((uint32_t)1U << 5U)
-#define POC_SD0_DAT2_33V	((uint32_t)1U << 4U)
-#define POC_SD0_DAT1_33V	((uint32_t)1U << 3U)
-#define POC_SD0_DAT0_33V	((uint32_t)1U << 2U)
-#define POC_SD0_CMD_33V		((uint32_t)1U << 1U)
-#define POC_SD0_CLK_33V		((uint32_t)1U << 0U)
+#define POC_SD3_DS_33V		BIT(29)
+#define POC_SD3_DAT7_33V	BIT(28)
+#define POC_SD3_DAT6_33V	BIT(27)
+#define POC_SD3_DAT5_33V	BIT(26)
+#define POC_SD3_DAT4_33V	BIT(25)
+#define POC_SD3_DAT3_33V	BIT(24)
+#define POC_SD3_DAT2_33V	BIT(23)
+#define POC_SD3_DAT1_33V	BIT(22)
+#define POC_SD3_DAT0_33V	BIT(21)
+#define POC_SD3_CMD_33V		BIT(20)
+#define POC_SD3_CLK_33V		BIT(19)
+#define POC_SD1_DAT3_33V	BIT(11)
+#define POC_SD1_DAT2_33V	BIT(10)
+#define POC_SD1_DAT1_33V	BIT(9)
+#define POC_SD1_DAT0_33V	BIT(8)
+#define POC_SD1_CMD_33V		BIT(7)
+#define POC_SD1_CLK_33V		BIT(6)
+#define POC_SD0_DAT3_33V	BIT(5)
+#define POC_SD0_DAT2_33V	BIT(4)
+#define POC_SD0_DAT1_33V	BIT(3)
+#define POC_SD0_DAT0_33V	BIT(2)
+#define POC_SD0_CMD_33V		BIT(1)
+#define POC_SD0_CLK_33V		BIT(0)
 
 #define IOCTRL32_MASK		(0xFFFFFFFEU)
-#define POC2_VREF_33V		((uint32_t)1U << 0U)
+#define POC2_VREF_33V		BIT(0)
 
 #define MOD_SEL0_ADGB_A		((uint32_t)0U << 29U)
 #define MOD_SEL0_ADGB_B		((uint32_t)1U << 29U)